Abstract: Vacancies and dopant ions are introduced near the surface of a semiconductor wafer. The dopant ions which diffuse by an interstitialcy mechanism have diffusivity greatly reduced, which leads to a very low resistivity doped region and a very shallow junction.

Abstract: A silicon wafer wherein stacking fault (SF) nuclei are distributed throughout the entire in-plane direction, and the density of the stacking fault nuclei is set to a range of between 0.5×108 cm−3 and 1×1011 cm−3.

Abstract: A method for improving the operating stability of compound semiconductor minority carrier devices and the devices created using this method are described. The method describes intentional introduction of impurities into the layers adjacent to the active region, which impurities act as a barrier to the degradation process, particularly undesired defect formation and propagation. A preferred embodiment of the present invention uses O doping of III-V optoelectronic devices during an epitaxial growth process to improve the operating reliability of the devices.

Abstract: A semiconductor device has a semiconductor substrate of a first conductivity; and a first electrode formation region and a second electrode formation region formed adjacent to an inner surface of the semiconductor substrate. The first electrode formation regions and the second electrode formation regions are isolated from each other via an element isolation region. An upper first-type impurity layer and a lower first-type impurity layer are formed in one of the first electrode formation region and the second electrode formation region, the lower first-type impurity layer has a different first-type impurity concentration from the upper first-type impurity layer and is formed under the upper first-type impurity layer. A second-type impurity layer and a first-type impurity layer are formed in the other electrode formation region and the first-type impurity layer is formed under a part of the second-type impurity layer having second-type impurities.

Abstract: A semiconductor-on-insulator (SOI) wafer. The wafer includes a silicon substrate, a buried oxide (BOX) layer disposed on the substrate, and an active layer disposed on the box layer. The active layer has an upper silicon layer disposed on a silicon-germanium layer. The silicon-germanium layer is disposed on a lower silicon layer. The silicon-germanium of the silicon-germanium layer is strained silicon-germanium and is about 200 Å to about 400 Å thick.

Abstract: A method for forming an integrated circuit is provided. A semiconductor film is formed onto a first substrate. A metal film is formed onto a second substrate. The second substrate is bonded with the metal film onto the thin film of the first substrate. A first layer of transistors is formed onto the film. The second substrate is removed at a temperature within a low temperature range. The semiconductor film is bonded with the first layer of transistors onto a second layer of transistors of a third substrate.

Abstract: An integrated circuit formed in semiconductor-on-insulator format. The integrated circuit includes a layer of semiconductor material disposed on an insulating layer, where the insulating layer disposed on a substrate. A first and a second MOSFET are provided such that one of a source and a drain of the first MOSFET is disposed adjacent one of a source and a drain of the second MOSFET. An amorphous region is formed in the layer of semiconductor material and extending from an upper surface of the layer of semiconductor material to the isolation layer. The amorphous region is formed between a crystalline portion of the one of the source and the drain of the first MOSFET and a crystalline portion of the one of the source and the drain of the second MOSFET.

Abstract: An N-type semiconductor layer with a low impurity concentration is grown by epitaxial growth on top of an N-type semiconductor substrate. An oxide film, with a desired pattern, is formed on the surface of the semiconductor layer. Using the oxide film as a mask, an active region edge and a guard ring region are formed by ion injection. After formation, the portion that forms the active region is exposed, and a paste containing platinum is coated onto the back surface of semiconductor substrate. The platinum is heat diffused into the substrate. Through this process, a region near the surface of the active region of semiconductor layer reverses to a P-type, and a shallow reverse region is formed, thereby producing a fast diode with adequate soft recovery characteristics.

Abstract: In a bonded semiconductor member, microgaps are formed on a substrate side of a bonding interface to thereby constitute a gettering site, and heavy metal elements contaminated in the substrate are captured by the microgaps. The bonded semiconductor member is manufactured by interposing the microgaps between two substrates.

Abstract: To improve the gettering performance by ion implanting boron and improves the production yield of the semiconductor device by using an epitaxial wafer of good quality suppressing the occurrence of dislocations. For this purpose, an epitaxial wafer in which an epitaxial layer of about 1 &mgr;m is formed to a CZ semiconductor substrate implanted with boron ions which are dopant and carbon ions which are not a dopant is provided, and transistors are formed on the surface of the epitaxial layer.

Abstract: A power semiconductor device including first and second assembly units. The first assembly of units includes a first semiconductor region of a second conductivity type selectively formed in a first main surface of the first semiconductor layer, a second semiconductor region of the first conductivity type selectively formed in a surface of the first semiconductor region, a first gate insulation film formed in contact with at least the surface of the first semiconductor region between the second semiconductor region and the first semiconductor layer, and a first trench-type gate electrode formed on the first gate insulation film and arranged in parallel and extending through the first semiconductor region in a direction of depth thereof.

Abstract: The invention provides a technology for reducing the direct contact resistance and for reducing the junction leak while maintaining the punch through margin. A semiconductor integrated circuit device is provided which comprises: a substrate; a transistor formed on the substrate, which comprises a source, a drain and a gate which controls a current flowing from said source to said drain; and a contact plug being electrically connected to at least one of the source and drain and made of a conductive material including a dopant. The contact plug is formed of at least a first layer and a second layer. The first layer contacts with one of the source and drain and is made of said material including the dopant of a first concentration. The second layer is formed of a layer of said material including the dopant of a second concentration, which is lower than the second concentration.

Abstract: A method of fabricating a silicon wafer, which includes the steps of preparing a silicon wafer by slicing, grinding, and cleaning an ingot, inserting the silicon wafer in a diffusion furnace having an ambience of one of Ar, N2 and inert gas including Ar and N2, pre-heating and maintaining the diffusion furnace at about 500° C., changing the ambience into one of H2, Ar and inert gas including H2 and Ar successively, increasing a temperature of the diffusion furnace by a temperature-increasing speed of 50˜70 ° C./min between 500˜800° C., 10˜50° C./min between 800˜900° C., 0.5˜10 ° C./min between 900˜1000° C., and 0.1˜0.5° C./min between 1000˜1250° C., maintaining the diffusion furnace at 1200˜1250° C.

Abstract: The present invention describes a method of manufacturing a semiconductor device, comprising a semiconductor substrate (2) in the shape of a slice, the method comprising the steps of: step 1) selectively applying a pattern of a solids-based dopant source to a first major surface of said semiconducting substrate (2); step 2) diffusing the dopant atoms from said solids-based dopant source into said substrate (2) by a controlled heat treatment step in a gaseous environment surrounding said semi-conducting substrate (2), the dopant from said solids-based dopant source diffusing directly into said substrate (2) to form a first diffusion region (12) and, at the time, diffusing said dopant from said solids-based dopant source indirectly via said gaseous environment into said substrate (2) to form a second diffusion region (15) in at least some areas of said substrate (2) not covered by said pattern; and step 3) forming a metal contact pattern (20) substantially in alignment with said first diffusion region (12) with

Abstract: A silicon semiconductor substrate is obtained by deriving a silicon semiconductor substrate from a silicon single crystal grown by the Czochralski method from a molten silicon containing not less than 1×1016 atoms/cm3 and not more than 1.5×1019 atoms/cm3 of nitrogen and heat-treating the silicon semiconductor substrate at a temperature of not less than 1000° C. and not more than 1300° C. for not less than one hour and is characterized by the fact that the density of crystal defects measuring not less than 0.1 &mgr;m as reduced to diameter is not more than 104 pieces/cm3 at least in the region reaching a depth of 1 &mgr;m from the surface of the substrate and the nitrogen content at the center of thickness of the silicon semiconductor substrate is not less than 1×1013 atoms/cm3 and not more than 1×1016 atoms/cm3.

Abstract: Methods and apparatus are provided for forming ultrashallow junctions in semiconductor wafers. The method includes the step of introducing into a shallow surface layer of a semiconductor wafer a dopant material that is selected to form charge carrier complexes, such as exciton complexes, which produce at least two charge carriers per complex. The semiconductor wafer containing the dopant material may be processed, such as by thermal processing, to form the charge carrier complexes. The charge carrier complexes are interstitial and therefore are not subject to the limitations imposed by the electrical solubility limits resulting from incorporation into substitutional sites. Thus, low sheet resistance can be obtained.

Abstract: The invention provides an improved well structure for electrically separating n-channel and p-channel MOSFETs. The invention first forms a shallow well in a substrate. A buried amorphous layer is then formed below the shallow well. A deep well is then formed below the buried amorphous layer. The substrate is then subjected to a rapid thermal anneal to recrystallize the buried amorphous layer. The well structure is formed by the shallow well and the deep well. A conventional semiconductor device may then be formed above the well structure. The buried amorphous layer suppresses the channeling effect during the forming of the deep well without requiring a tilt angle.

Abstract: The present invention is directed toward the formation of implanted thermally and electrically conductive structures in a dielectric. An electrically conductive structure, such as an interconnect is formed through ion implantation into several levels within a dielectric layer to penetrate into an electrically conductive region beneath the dielectric layer, such as a semiconductor substrate. Ion implantation continues in discreet, overlapping implantations of the ions from the electrical conductive region up to the top of the dielectric layer so as to form a continuous interconnect. Structural qualities achieved by the method of the present invention include a low interconnect-conductive region resistivity and a low thermal-cycle stress between the interconnect and the dielectric layer in which the interconnect has been implanted.

Abstract: In one aspect, the invention includes a method of semiconductive wafer processing comprising forming a silicon nitride layer over a surface of a semiconductive wafer, the silicon nitride layer comprising at least two portions, one of said at least two portions generating a compressive force against the other of the at least two portions, and the other of the at least two portions generating a tensile force against the one of the at least two portions.

Abstract: A compound semiconductor device having improved backgate voltage resistance characteristics. To improve the backgate voltage resistance of a compound semiconductor device having field effect transistors on a main surface of a semi-insulating substrate, boron ions are implanted on the rear surface to form a defect-rich layer having carrier recombination centers.

Abstract: A structure for forming thin film transistor with reduced metal impurities. The structure at least includes the following steps. First of all, an insulation substrate. Then, an insulating gettering layer on the insulation substrate, wherein the amorphous silicon layer defines an active area, and a channel region on the insulating gettering layer, a source region on the insulating gettering layer adjacent to the channel region, a drain region on the insulating gettering layer adjacent to the channel region and opposite to the source region, and a gate on the channel region, wherein the source, drain, insulating gettering layer and channel region are components of a transistor.

Abstract: A MOS IC device and a manufacturing method thereof capable of readily improving the isolation breakdown voltage while achieving a low threshold value and low junction capacitance with sufficient well-region separation breakdown voltage. To this end, a buried oxide film is deposited on a buried oxide film formed in a substrate while an oxide film is formed on the surface of the substrate. An ion decelerator layer of an appropriate material with a specified thickness is selectively disposed only on part of the substrate overlying the well boundary region; then, first ion implantation and second ion implantation steps are carried out. Accordingly, as compared to those regions other than the well boundary region, the resultant well profile in the well boundary region is shifted in position or “offset” towards a shallower part.

Abstract: A p-type MOSFET having very shallow p-junction extensions. The semiconductor device is produced on a substrate by creating a layer of implanted nitrogen ions extending from the substrate surface to a predetermined depth preferably less than about 800 Å. The gate electrode serves as a mask so that the nitrogen implantation does not filly extend under the gate electrode. Boron is also implanted to an extent and depth comparable to the nitrogen implantation thereby forming very shallow p-junction extensions that remain confined substantially within the nitrogen layer even after thermal treatment. There is thus produced a pMOSFET having very shallow p-junction extensions in a containment layer of nitrogen and boron in the semiconductor material.

Abstract: A method for fabricating an integrated circuit is presented wherein a semiconductor substrate is provided having a dielectric layer formed on its upper surface. A groove is formed in the dielectric layer that extends from the upper surface of the semiconductor substrate to the upper surface of the dielectric layer. A silicon epitaxial layer is then grown within the groove. Barrier atoms are incorporated into the silicon epitaxial layer concurrently with the epitaxial growth process.

Abstract: A little amount of nickel is introduced into an amorphous silicon film formed on a glass substrate to crystallize the amorphous silicon film by heating. In this situation, nickel elements remain in a crystallized silicon film. An amorphous silicon film is formed on the surface of the crystallized silicon film and then subjected to a heat treatment. With this heat treatment, the nickel elements are diffused in the amorphous silicon film, thereby being capable of lowering the concentration of nickel in the crystallized silicon film.

Abstract: There are disclosed a method for producing a silicon single crystal wafer for particle monitoring, which comprises growing a silicon single crystal ingot doped with nitrogen by the Czochralski method, and processing the single crystal ingot into wafers to produce the silicon single crystal wafer for particle monitoring; and a silicon single crystal wafer for particle monitoring, which is a silicon single crystal wafer for particle monitoring obtained by processing a silicon single crystal ingot into wafers, which ingot has been produced by the Czochralski method while doped with nitrogen. The method of the present invention can produce silicon single crystal wafers for particle monitoring having few pits on wafer surfaces with high productivity.

Abstract: A lateral PNP transistor (LPNP) (102) having the low resistance base buried N+ region (114) removed from below the emitter region (118). This leaves a high resistance n-well (116) below the emitter. The resistance from the center of the emitter region (118) to the N+ buried region (114) is greater than the resistance at the periphery of the emitter region (118) to the N+ buried region (114). Debiasing will occur in the center of the emitter region (118) where the parasitic base current is generated. Thus, the ratio of parasitic current to active collector current and peak beta will improve.

Abstract: A soft recovery diode is made by first implanting helium into the die to a location below the P/N junction and the implant annealed. An E-beam radiation process then is applied to the entire wafer and is also annealed. The diode then has very soft recovery characteristics without requiring heavy metal doping.

Abstract: The present invention relates to a diode, and has an object to simultaneously implement a high di/dt capability, a low reverse recovery loss and a low forward voltage and to suppress generation of voltage oscillation. In order to achieve the above-mentioned object, life time killers are selectively introduced into a semiconductor substrate (20) comprising a P layer (1), an N− layer (21) and an N+ layer (3). A density of the introduced life time killers is the highest in a first region (6) adjacent to the P layer (1), and is the second highest in a second region (7) in the N− layer (21). The life time killers are not introduced into a third region (2). Accordingly, a life time in the N− layer (21) is expressed by the first region (6)<the second region (7)<the third region (2). The second region (7) and the third region (2) are adjacent to the P layer (1). In addition, the second region (7) annularly surrounds the third region (2).

Abstract: To improve the gettering performance by ion implanting boron and improves the production yield of the semiconductor device by using an epitaxial wafer of good quality suppressing the occurrence of dislocations. For this purpose, an epitaxial wafer in which an epitaxial layer of about 1 &mgr;m is formed to a CZ semiconductor substrate implanted with boron ions which are dopant and carbon ions which are not a dopant is provided, and transistors are formed on the surface of the epitaxial layer.

Abstract: A process for heat-treating a single crystal silicon wafer to influence the precipitation behavior of oxygen in the wafer in a subsequent thermal processing step is disclosed. The wafer has a front surface, a back surface, and a central plane between the front and back surfaces. In the process, the wafer is subjected to a heat-treatment to form crystal lattice vacancies, the vacancies being formed in the bulk of the silicon. The heat-treated wafer is then oxidized by heating in the presence of an oxygen-containing atmosphere in order to establish a vacancy concentration profile within the wafer. The oxidized wafer is then cooled from the temperature of said oxidizing heat treatment at a rate which allows some, but not all, of the crystal lattice vacancies to diffuse to the front surface to produce a wafer having a vacancy concentration profile in which the peak density is at or near the central plane with the concentration generally decreasing in the direction of the front surface of the wafer.

Abstract: A GaAs single crystal substrate and an epitaxial wafer using the same suppress the generation of slips during growth of the epitaxial layer, and improve the breakdown withstanding characteristic of devices fabricated on such substrates. The GaAs single crystal substrate has a mean dislocation density in plane of at most 2×104 cm−2, a carbon concentration of 2.5 to 20.0×1015 cm−3, a boron concentration of 2.0 to 20.0×1016 cm−3, an impurity concentration other than carbon and boron of at most 1×1017 cm−3, an EL2 concentration of 5.0 to 10.0×1015 cm−3, resistivity of 1.0 to 5.0×108 &OHgr;·cm and a mean residual strain measured by photoelastic analysis of at most 1.0×10−5.

Abstract: A nitride-type III-V group compound semiconductor device includes a substrate and a layered structure including at least a channel layer using two-dimensional electron gas formed over a substrate, wherein the channel layer contains InN.

Abstract: A semiconductor device having a carbon-containing region with an advantageous concentration profile is disclosed. The carbon is introduced into a region of the substrate and at a depth below the space-charge layer of the device and at a concentration such that the carbon atoms absorb point defects created in the substrate during device fabrication but do not adversely affect the leakage characteristics of the device.

Abstract: A silicon single-crystal wafer having a diameter of 6 inches or larger and improved in the dielectric breakdown strength of oxide film especially in a peripheral part thereof is provided to thereby heighten the yield of device chips produced per wafer. This wafer has no crystal defects with regard to the dielectric breakdown strength of oxide film in its peripheral region which extends from the circumference and accounts for up to 50% of the total area, in particular which extends from the circumference to a circle 30 mm apart from the circumference. A process for producing a silicon single crystal for easily producing, by the Czochralski method, a silicon single-crystal wafer improved in the dielectric breakdown strength of oxide film especially in a peripheral part thereof without considerably lowering the production efficiency is provided.

Abstract: A semiconductor device having two or more p-n junctions, being in particular a bipolar transistor or a thyristor. The device has an gold ion implant in a region of the device between two of or the two p-n junctions, which region is the base in the case of a bipolar transistor, located away from the current carrying active region of the device. The device has a low resistance and may be turned off rapidly because the implanted gold provides recombination centers which act as a sink for carriers drawing them from the active region.

Abstract: Channel-hot-carrier reliability can be improved by deuterium sintering. However, the benefits obtained by deuterium sintering can be greatly reduced or destroyed by thermal processing steps which break Si--H and Si--D bonds. A solution is to increase the deuterium concentration near the interface to avoid subsequent depletion of deuterium due to diffusion. By using a rapid quench of a sintered wafer, the deuterium concentration near the interface is increased, because the rapid quench impedes the ability of the deuterium to diffuse away from the gate oxide interface.

Abstract: An amorphized implant is performed to retard diffusion of ions in the source and drain regions. By retarding the diffusion of ions in these regions, a shallower junction is advantageously created in the silicon regions of the wafer. A slight degradation in leakage current is obtained if the amorphized implant is performed on both the source and the drain sides of a transistor. However, since the source region is a low voltage region with a very shallow junction, MOSFETs in both n-channel and p-channel regions are formed with improved performance and reliability.A method of fabricating an integrated circuit includes forming a gate electrode over a semiconductor substrate, forming a source mask extending over the drain region of the semiconductor substrate, and implanting an implant species into the source region of the semiconductor substrate to form an amorphous implant layer of the semiconductor substrate.

Abstract: A method for improving the operating stability of compound semiconductor minority carrier devices and the devices created using this method are described. The method describes intentional introduction of impurities into the layers adjacent to the active region, which impurities act as a barrier to the degradation process, particularly undesired defect formation and propagation. A preferred embodiment of the present invention uses O doping of III-V optoelectronic devices during an epitaxial growth process to improve the operating reliability of the devices.

Abstract: A photoconductive switching device is disclosed that has an enhanced speed of response so that its closed (low) and open (high) resistive states are obtained in response to optical illumination in the less than nanosecond regime. The enhanced speed of response is achieved by neutron irradiation of a material preferably comprising GaAs:Si:Cu. An application of the improved photoconductive switching devices is disclosed which allows the realization of a high-power, frequency-agile RF source topology.

Abstract: An electronic switch (80) having a transistor (T) and a diode (D) formed on a substrate (82) is provided. The electronic switch (80) includes a common transistor collector and diode cathode region (81) of a first conductivity type formed in the substrate (82). The switch (80) also includes a transistor base region (83) of a second conductivity type formed in a first section of the collector region (81) and a transistor emitter region (84) of the first conductivity type formed in a section of the base region (83). Additionally, the electronic switch (80) includes a diode anode region (85) formed of the second conductivity type and in a second section of the collector region (81). At least a portion of the anode region (85) is selectively doped with a metallic dopant to provide centers for charge carrier recombination so as to decrease the recovery time of the diode (D).

Abstract: A semiconductor device includes a semiconductor substrate having first and second main surfaces and including a denuded zone, in which an oxygen concentration is lower than that in an inner portion of the semiconductor substrate and which does not include a bulk microdefect, and an intrinsic gettering zone, and element region formed on the first surface of the semiconductor substrate, and an extrinsic gettering layer, made of an amorphous semiconductor material which traps a metal impurity, and formed directly on at least a portion of the intrinsic gettering region or the denuded zone entirely or partially thinned of the second main surface of the semiconductor substrate.

Abstract: A fast power diode with a soft switching-time response for use in a commutating branch containing a switchable semiconductor component is formed by at least three successive diffusions with p and n dopants and the heavy metal platinum, and for final incorporation of the parameters necessary for operation, the diode is irradiated with electrons.

Abstract: A semiconductor structure, in which the concentrations of impurities are in such a ratio that the amount of carriers produced by an impurity of a first type of conductivity compensated by a third impurity is essentially equal to or exceeds by no more than one order of magnitude the amount of carriers produced by an impurity of the second type of conductivity. A method for controlling such a semiconductor structure (1) is provided, in which the value of the current forming a current path or filament (7) is set in a range, in which a periodic variation of the conductivity in the zone of the current filament (7) is produced. The variation leads to a change of the conductivity of the entire semiconductor structure (1) so that a train of pulses is generated at the output of the semiconductor structure (1).

Abstract: A frequency compensator is disposed as a stage preceding an inverter or a source follower constituted by a compound semiconductor FET, and it has a node A, at which an input signal is divided by resistances, and a node B, at which the input signal is divided by capacitances. The two nodes A and B are connected to each other via a diode such that the diode is biased forward when the node A is biased positively with respect to the node B. The node B is connected to the input of the FET. The diode has a barrier height substantially equal to the activation energy in a deep level trap contained in crystal constituting the FET.

Abstract: A semiconductor device includes a semiconductor substrate having first and second main surfaces and including a denuded zone, in which an oxygen concentration is lower than that in an inner portion of the semiconductor substrate and which does not include a bulk microdefect, and an intrinsic gettering zone, an element region formed on the first surface of the semiconductor substrate, and an extrinsic gettering layer, made of an amorphous semiconductor material which traps a metal impurity, and formed directly on at least a portion of the intrinsic gettering region or the denuded zone entirely or partially thinned of the second main surface of the semiconductor substrate.

Abstract: Integrated structure bipolar transistors with controlled storage time are manufactured by forming at least one bipolar transistor occupying a first area on a first surface of the silicon material, covering the first surface of the silicon material with an insulating material layer, and selectively removing the insulating material layer to open a window. The window has a second area much smaller than the first area occupied by the bipolar transistor. Therefore, by implanting into the silicon material a medium dose of platinum ions through the window and diffusing into the silicon material the implanted platinum ions, a uniform distribution of platinum inside the transistor is obtained.

Abstract: A semiconductor fabrication method improves the voltage characteristic of floating-body MOSFETs by creating recombination centers near the source-body junction of the device. A MOSFET is fabricated through the passivation oxidation stage, and a photolithography step is used to expose the source region. Implantation is then performed using one of two types of material. A first type creates electron traps of predetermined energy in the vicinity of the source-body junction. A second type creates defects in the crystalline structure of the semiconductor material. Both implantation types create recombination centers in the material. This allows the discharge through the source-body junction of charges built up in the body region.

Abstract: A semiconductor commutator which is constructed by joining a semiconductor region of the first conductivity type and a semiconductor region of the second conductivity type, wherein there is provided a grain boundary which is located near a junction surface of the semiconductor region of the first conductivity type and the semiconductor region of the second conductivity type so as not to cross said junction surface.

Abstract: A method for growing an epitaxial layer of a group III-V compound semiconductor material that contains oxygen comprises the steps of supplying molecules of an organic compound that contains a group V element and oxygen in the molecule, and decomposing the molecules of the organic compound to release the group V element and oxygen.