Abstract: Provided is a CdTe-based semiconductor substrate for epitaxial growth, which is capable of growing good-quality epitaxial crystals without urging a substrate user to implement etching treatment before the epitaxial growth. A CdTe-based semiconductor substrate, in which tracks of linear polishing damage with a depth of 1 nm or more are not observed within a viewing range of 10 ?m×10 ?m when a surface of the substrate is observed by an atomic force microscope, and orange peel defects are not observed when the surface of the substrate is visually observed under a fluorescent lamp, can grow the good-quality epitaxial crystals.

Abstract: An electronic device having a plurality of electronic components placed on a substrate, each component being constituted by a portion of a layer of active material joined mechanically to the substrate by an electrically conductive joining element pertinent to it, the layer of active material having at least one trench delimiting, at least in part, groups of electronic components each having at least two components and forming successive strips, two successive strips having a common boundary.

Abstract: There is provided a semiconductor wafer including a base wafer, an insulating layer, and a Si crystal layer in the stated order. Here, the semiconductor wafer includes a seed crystal disposed on the Si crystal layer where the seed crystal has been subjected to annealing, and a compound semiconductor that has a lattice match or a pseudo lattice match with the seed crystal. There is provided an electronic device including a substrate, an insulating layer disposed on the substrate, a Si crystal layer disposed on the insulating layer, a seed crystal disposed on the Si crystal layer where the seed crystal has been subjected to annealing, a compound semiconductor that has a lattice match or a pseudo lattice match with the seed crystal, and a semiconductor device formed using the compound semiconductor.

Abstract: There is provided a semiconductor wafer having a base wafer, an insulating layer, and a SixGe1-x crystal layer (0?x<1) in the stated order. Here, at least a partial region of the SixGe1-x crystal layer (0?x<1) has been subjected to annealing, and the semiconductor wafer comprises a compound semiconductor that has a lattice match or a pseudo lattice match with the at least partial region of the SixGe1-x crystal layer (0?x<1). Furthermore, there is provided an electronic device including a substrate, an insulating layer disposed on the substrate, a SixGe1-x crystal layer (0?x<1) disposed on the insulating layer, at least a partial region of the SixGe1-x crystal layer (0?x<1) having been subjected to annealing, a compound semiconductor that has a lattice match or a pseudo lattice match with the at least partial region of the SixGe1-x crystal layer (0?x<1), and a semiconductor device formed using the compound semiconductor.

Abstract: Provided is a method of fabricating a ZnO thin film structure and a ZnO thin film transistor (TFT), and a ZnO thin film structure and a ZnO thin film transistor. The method of fabricating a ZnO thin film structure may include forming a ZnO thin film on a substrate in an oxygen atmosphere, forming oxygen diffusion layers of a metal having an affinity for oxygen on the ZnO thin film and heating the ZnO thin film and the oxygen diffusion layers to diffuse oxygen of the ZnO thin film into the oxygen diffusion layers.

Abstract: Hetero-epitaxial semiconductor materials comprising cubic crystalline semiconductor alloys grown on the basal plane of trigonal and hexagonal substrates, in which misfit dislocations are reduced by approximate lattice matching of the cubic crystal structure to underlying trigonal or hexagonal substrate structure, enabling the development of alloyed semiconductor layers of greater thickness, resulting in a new class of semiconductor materials and corresponding devices, including improved hetero-bipolar and high-electron mobility transistors, and high-mobility thermoelectric devices.

Abstract: Crystalline inorganic-organic hybrid structures having a plurality of layers of a repeating unit characterized by a first organic ligand layer, a second organic ligand layer, and a two-dimensional semiconducting inorganic double layer having two opposing surfaces therebetween, wherein the two-dimentional semiconducting inorganic double layer is characterized by two single atom thick layers of a II-chalcogenide compound; and the first organic ligand layer and the second organic ligand layer are attached to the two opposing surfaces of the two-dimensional semiconducting inorganic double layer through a covalent bond or a coordinate covalent bond between the compounds of the organic ligand layers and the metal cation species of the II-VI chalcogenide compounds, so that the semiconducting inorganic double layer is directed by the compounds of the two opposing organic layers to form ordered crystal lattices. Methods for the preparation of the hybrid structures are also disclosed.

Abstract: This invention relates to the manufacture of Cadmium Mercury Telluride (CMT) on patterned silicon, especially to growth of CMT on silicon substrates bearing integrated circuitry. The method of the invention involves growing CMT in selected growth windows on the silicon substrate by first growing one or more buffer layers by MBE and then growing the CMT by MOVPE. The growth windows may be defined by masking the area outside of the growth windows. Growth within the growth windows is crystalline whereas any growth outside the growth windows is polycrystalline and can be removed by etching. The invention offers a method of growing CMT structures directly on integrated circuits removing the need for hybridisation.

Abstract: A thin film transistor is disclosed comprising comprises a substrate, a dielectric layer, and a semiconductor layer. The semiconductor layer, which is crystalline zinc oxide preferentially oriented with the c-axis perpendicular to the plane of the dielectric layer or substrate, is prepared by liquid depositing a zinc oxide nanodisk composition. The thin film transistor has good mobility and on/off ratio.

Abstract: Expungement ions, preferably including hydrogen ions, are implanted into a face of a first, preferably silicon, substrate such that there will be a maximum concentration of the expungement ions at a predetermined depth from the face. Subsequently a monocrystalline Group II-VI semiconductor layer, or two or more such layers, is/are grown on the face, as by means of molecular beam epitaxy. After this a second, preselected substrate is attached to an upper face of the Group II-VI layer(s). Next, the implanted expungement ions are used to expunge most of the first substrate from a remnant thereof, from the grown II-VI layer, and from the second substrate.

Abstract: A structure including a substrate, an intermediate layer provided and formed directly onto the substrate, a transition region, and a group II-VI bulk crystal material provided and formed as an extension of the transition region. The transition region acts to change the structure from the underlying substrate to that of the bulk crystal. In a method of manufacture, a similar technique can be used for growing the transition region and the bulk crystal layer.

Abstract: Provided is a semiconductor substrate for epitaxial growth which does not require any etching treatment as a pretreatment in the stage of performing an epitaxial growth of HgCdTe film. A CdTe system compound semiconductor substrate for the epitaxial growth of the HgCdTe film is housed in an inactive gas atmosphere, in a predetermined period of time (for example, 10 hours) after mirror finish treatment thereof, to thereby regulate the proportion of Te oxide of the total amount of Te on the substrate surface which is obtained by XPS measurement so as to be not more than 30%.

Abstract: Compound semiconductors capable of emitting light in the green spectrum are provided. The compound semiconductors may display improved quantum efficiencies when applied to various optical devices. Also, light emitting diodes and light emitting diode modules comprising the compound semiconductors are provided.

Abstract: A method of fabricating a micro-electromechanical system microphone structure is disclosed. First, a substrate defining a MEMS region and a logic region is provided, and a surface of the substrate has a dielectric layer thereon. Next, at least one metal interconnect layer is formed on the dielectric layer in the logic region, and at least one micro-machined metal mesh is simultaneously formed in the dielectric layer of the MEMS region. Therefore, the thickness of the MEMS microphone structure can be effectively reduced.

Abstract: An ohmic contact in accordance with the invention includes a layer of p-type GaN-based material. A first layer of a group II-VI compound semiconductor is located adjacent to the layer of p-type GaN-based material. The ohmic contact further includes a metal layer that provides metal contact. A second layer of a different II-VI compound semiconductor is located adjacent to the metal layer.

Abstract: The present invention provides semiconductor structures comprising a substrate and at least three III-V and/or II-VI multi junction building blocks, each comprising a p-n junction having at least two alloy layers, formed over the substrate, provided at least one multi-junction building block comprises II-VI alloy layers. Further described are methods for preparing semiconductor structures utilizing a sacrificial or etch-stop ternary III-V alloy layer over an III-V substrate.

Abstract: A coated nano particle and an electronic device using the composite nano particle as an illuminator are provided. The composite nano particle includes a nano particle receiving light and emitting light; and a coating material formed on a surface of the nano particle and having an index of refraction different from that of the nano particle. The coated nano particle is made by coating a surface of the nano particle with a material having an index of refraction, which has an intermediate value between an index of refraction of a matrix and an index of refraction of the nano particle as an illuminator, with a predetermined thickness. The light emitted from the nano particle is efficiently transferred to the outside as the light reflected from the matrix and absorbed by the nano particle is suppressed. Therefore, a luminous efficiency of the illuminator is improved, and an electronic device using the illuminator is provided.

Abstract: A system and method for variable doping within a semiconductor structure for improved efficiency is described. One embodiment includes a semiconductor structure comprising a first semiconductor layer comprising a first semiconductor material, and a second semiconductor layer comprising a second semiconductor material, wherein the second semiconductor material is an oppositely-typed semiconductor material from the first semiconductor material, and wherein the second semiconductor layer comprises a first region adjacent to the first semiconductor layer, wherein the first region comprises low-doped second semiconductor material, and a second region adjacent to the first region, wherein the second region comprises highly-doped second semiconductor material to increase a built-in potential of the semiconductor structure.

Abstract: An organic thin film transistor substrate includes a gate line formed on a substrate, a data line intersecting the gate line and defining a subpixel area, an organic thin film transistor including a gate electrode connected to the gate line, a source electrode connected to the data line, a drain electrode facing the source electrode, and an organic semiconductor layer forming a channel between the source and drain electrodes, a passivation layer parallel with the gate line, for covering the organic semiconductor layer and peripheral regions of the organic semiconductor layer, and a bank insulating layer for determining the position of the organic semiconductor layer and the passivation layer.

Abstract: The present invention provides methods of forming metal oxide semiconductor nanostructures and, in particular, zinc oxide (ZnO) semiconductor nanostructures, possessing high surface area, plant-like morphologies on a variety of substrates. Optoelectronic devices, such as photovoltaic cells, incorporating the nanostructures are also provided.

Abstract: The invention described herein provides for thin films and methods of making comprising inorganic semiconductor-nanocrystals dispersed in semiconducting-polymers in high loading amounts. The invention also describes photovoltaic devices incorporating the thin films.

Abstract: A compound semiconductor workpiece with reduced defects and greater strength that uses Group II-VI semiconductor nanoislands on a substrate. Additional layers of Group II-VI semiconductor are grown on the nanoislands using MBE until the newly formed layers coalesce to form a uniform layer of a desired thickness. In an alternate embodiment, nanoholes are patterned into a silicon nitride layer to expose an elemental silicon surface of a substrate. Group II-VI semiconductor material is grown in the holes until the layers fill the holes and coalesce to form a uniform layer of a desired thickness. Suitable materials for the substrate include silicon and silicon on insulator materials and cadmium telluride may be used as the Group II-VI semiconductor.

Abstract: The present invention relates to a method for producing an n-type ZnTe system compound semiconductor single crystal having high carrier concentration and low resistivity, the ZnTe system compound semiconductor single crystal, and a semiconductor device produced by using the ZnTe system compound semiconductor as a base member. Concretely, a first dopant and a second dopant are co-doped into the ZnTe system compound semiconductor single crystal so that the number of atoms of the second dopant becomes smaller than the number of atoms of the first dopant, the first dopant being for controlling a conductivity type of the ZnTe system compound semiconductor to a first conductivity type, and the second dopant being for controlling the conductivity type to a second conductivity type different from the first conductivity type. By the present invention, a desired carrier concentration can be achieved with a doping amount smaller than in earlier technology, and crystallinity of the obtained crystal can be improved.

Abstract: A functional perovskite cell formed on a silicon substrate layer and including a functional layer of bismuth ferrite (BiFeO3 or BFO) sandwiched between two electrode layers. An optional intermediate template layer, for example, of strontium titanate allows the bismuth ferrite layer to be crystallographically aligned with the silicon substrate layer. Other barrier layers of platinum or an intermetallic alloy produce a polycrystalline BFO layer. The cell may be configured as a non-volatile memory cell or a MEMS structure respectively depending upon the ferroelectric and piezoelectric character of BFO. Lanthanum substitution in the BFO increases ferroelectric performance. The films may be grown by MOCVD using a heated vaporizer.

Abstract: Low dielectric constant group II-VI compounds, such as zinc oxide, and fabrication methods are disclosed. Low dielectric constant insulator materials are fabricated by doping zinc oxide with at least one mole % p-type dopant ion. Low dielectric constant zinc oxide insulator materials are fabricated by doping zinc oxide with silicon having a concentration of at least 1017 atoms/cm3. Low dielectric zinc oxide insulator materials are fabricated by doping zinc oxide with a dopant ion having a concentration of at least about 1018 atoms/cm3, followed by heating to a temperature which converts the zinc oxide to an insulator. The temperature varies depending upon the choice of dopant. For arsenic, the temperature is at least about 450° C.; for antimony, the temperature is at least about 650° C. The dielectric constant of zinc oxide semiconductor is lowered by doping zinc oxide with a dopant ion at a concentration at least about 1018 to about 1019 atoms/cm3.

Abstract: Phase-changeable memory devices include a lower electrode electrically connected to an impurity region of a transistor in a substrate and a programming layer pattern including a first phase-changeable material on the lower electrode. An adiabatic layer pattern including a material having a lower thermal conductivity than the first phase-changeable material is on the programming layer pattern and an upper electrode is on the adiabatic layer pattern.

Abstract: A persistent p-type group II-VI semiconductor material is disclosed containing atoms of group II elements, atoms of group VI elements, and a p-type dopant which replaces atoms of the group VI element in the semiconductor material. The p-type dopant has a negative oxidation state. The p-type dopant causes formation of vacancies of atoms of the group II element in the semiconductor material. Fabrication methods and solid state devices containing the group II-VI semiconductor material are disclosed.

Abstract: A radiation detector crystal is made from CdxZn1-xTe, where 0?x?1; an element from column III or column VII of the periodic table, desirably in a concentration of about 1 to 10,000 atomic parts per billion; and the element Ruthenium (Ru), the element Osmium (Os) or the combination of Ru and Os, desirably in a concentration of about 1 to 10,000 atomic parts per billion using a conventional crystal growth method, such as, for example, the Bridgman method, the gradient freeze method, the electro-dynamic gradient freeze method, the so-call traveling heater method or by the vapor phase transport method. The crystal can be used as the radiation detecting element of a radiation detection device configured to detect and process, without limitation, X-ray and Gamma ray radiation events.

Abstract: It is an object to provide a p-type ZnS based semiconductor material having a low resistance which can easily form an ohmic contact to a metallic material. Moreover, the invention provides a semiconductor device and a semiconductor light emitting device which include an electrode having a low resistance on a substrate other than a single crystal substrate, for example, a glass substrate. The semiconductor material according to the invention is used as a hole injecting electrode layer of a light emitting device and has a transparent property in a visible region which is expressed in a composition formula of Zn(1-?-?-?)Cu?Mg?Cd?S(1-x-y)SexTey (0.004???0.4, ??0.2, ??0.2, 0?x?1, 0?y?0.2, and x+y?1).

Abstract: The present invention discloses structures to increase carrier mobility using engineered substrate technologies for a solid state device. Structures employing rare-earth compounds enable heteroepitaxy of different semiconductor materials of different orientations.

Abstract: An ohmic contact in accordance with the invention includes a layer of p-type GaN-based material. A first layer of a group II-VI compound semiconductor is located adjacent to the layer of p-type GaN-based material. The ohmic contact further includes a metal layer that provides metal contact. A second layer of a different II-VI compound semiconductor is located adjacent to the metal layer.

Abstract: An intermediate electrode between an ovonic threshold switch and a memory element may be formed in the same pore with the memory element. This may have many advantages including, in some embodiments, reducing leakage.

Abstract: The ternary alloy CdSexTe1-x(2 1 1) and the quaternary alloy Cd1-zZnzSexTe1-x have been grown on Si(2 1 1) substrates using molecular beam epitaxy (MBE). The growth of CdSeTe is facilitated using a compound CdTe effusion source and a Se effusion source while the growth of CdZnSeTe is facilitated using a compound CdTe effusion source, a compound ZnTe effusion source, and an elemental Se source. The alloy compositions (x) and (z) of CdSexTe1-x ternary compound and Cd1-zZnzSexTe1-x are controlled through the Se/CdTe and ZnTe/CdTe flux ratios. The rate of Se incorporation is higher than the rate of Te incorporation as growth temperature increases. As-grown CdSeTe with 4% Se and CdZnSeTe with 4% Zn+Se, which is substantially lattice matched to long-wavelength infrared HgCdTe materials, exhibits excellent surface morphology, low surface defect density (less than 500 cm2), and a narrow X-ray rocking curve (a full-width at half maximum of 103 arcsec).

Abstract: A thin film transistor is disclosed comprising a substrate, a dielectric layer, and a semiconductor layer. The semiconductor layer, which is crystalline zinc oxide preferentially oriented with the c-axis perpendicular to the plane of the dielectric layer or substrate, is prepared by liquid depositing a zinc oxide nanodisk composition. The thin film transistor has good mobility and on/off ratio.

Abstract: A memory cell device, including a memory material element switchable between electrical property states by the application of energy, includes depositing an electrical conductor layer, depositing dielectric material layers and etching to create a first electrode and voids. A memory material is applied into a void to create a memory material element in contact with the first electrode. A second electrode is created to contact the memory material element.

Abstract: A method is provided for forming a Group IBIIIAVIA solar cell absorber layer including indium (In) and gallium (Ga) that are distributed substantially uniformly between the top surface and the bottom surface of the absorber layer. In one embodiment method includes forming a precursor by depositing a metallic layer including copper (Cu), indium (In) and gallium (Ga) on the base, and depositing a film comprising selenium (Se) and tellurium (Te) on the metallic layer. In the precursor, the molar ratio of Te to Ga is equal to or less than 1. In the following step, the precursor is heated to a temperature range of 400-600° C. to form the Group IBIIIAVIA solar cell absorber layer.

Abstract: An ohmic contact in accordance with the invention includes a layer of p-type GaN-based material. A first layer of a group II-VI compound semiconductor is located adjacent to the layer of p-type GaN-based material. The ohmic contact further includes a metal layer that provides metal contact. A second layer of a different II-VI compound semiconductor is located adjacent to the metal layer.

Abstract: A metal oxide nanostructure is formed by oxidizing metallic metal in the presence of a solution containing a liquid ligand to form a metal-ligand complex, and decomposing the metal-ligand complex to form the metal oxide nanostructure. The metal-ligand complex can be a complex of zinc or copper with formamide. In one form, the nanostructure forms ZnO nanorods having a diameter of 10 to 1000 nm, where the nanorods having a hexagonal crystallographic morphology, and the nanorods are oriented perpendicular to a substrate.

Abstract: A memory device, such as a PCRAM, including a chalcogenide glass backbone material with germanium telluride glass and methods of forming such a memory device.

Abstract: An apparatus comprising a substrate, a heater formed on the substrate, and a phase-change layer formed on the heater. The heater comprises a heater layer and first and second electrodes electrically coupled to the heater layer. A process comprising forming a heater on a substrate and forming a phase-change layer on the heater. The heater comprises a heater layer and first and second electrodes electrically coupled to the heater layer.

Abstract: A method for improving the luminescent efficiency of semiconductor nanocrystals by surface treatment with a reducing agent to produce an improvement in luminescent efficiency and quantum efficiency without creating changes in the luminescent characteristics of the nanocrystals such as luminescence wavelengths and the distribution thereof.

Abstract: A field-effect transistor includes source, drain, and gate electrodes; a crystalline or polycrystalline layer of inorganic semiconductor; and a dielectric layer. The layer of inorganic semiconductor has an active channel portion physically extending from the source electrode to the drain electrode. The inorganic semiconductor has a stack of 2-dimensional layers in which intra-layer bonding forces are covalent and/or ionic. Adjacent ones of the layers are bonded together by forces substantially weaker than covalent and ionic bonding forces. The dielectric layer is interposed between the gate electrode and the layer of inorganic semiconductor material. The gate electrode is configured to control a conductivity of an active channel part of the layer of inorganic semiconductor.

Abstract: A III–V group nitride system semiconductor self-standing substrate has: a first III–V group nitride system semiconductor crystal layer that has a region with dislocation lines gathered densely, the dislocation lines being gathered substantially perpendicular to a surface of the substrate, and a region with dislocation lines gathered thinly; and a second III–V group nitride system semiconductor crystal layer that is formed up to 10 ?m from the surface of the substrate on the first III–V group nitride system semiconductor crystal layer and that has a dislocation density distribution that is substantially uniform.

Abstract: An assembly comprising a semiconductor substrate having a first lattice constant, an intermediate layer having a second lattice constant formed on the semiconductor substrate, and a virtual substrate layer having a third lattice constant formed on the intermediate layer. The intermediate layer comprises one of a combination of III–V elements and a combination of II–VI elements. The second lattice constant has a value that is approximately between the values of the first lattice constant and the third lattice constant.

Abstract: A surface of an external electrode 3 of an electronic part 4 is formed with a coating containing resin ingredient. Thereby, adhesion strength and reliability may be significantly improved in mounting an electronic part onto a circuit board 1 through the medium of a conductive adhesive. Further, it will be able to mount an electronic part to an element to be mounted by utilizing a conductive adhesive forming an external electrode 3 as a connecting element. Further, surface roughness (Ra) of an external electrode 3 of an electronic part is set to 0.1 ?m or more and to 10.0 ?m or less and preferably to 1.0 ?m or more and to 5.0 ?m or less. Thereby, adhesion strength with a conductive adhesive may be significantly enhanced in comparison with a conventional electronic part presented.

Abstract: Contact structures having I shapes and L shapes, and methods of fabricating I-shaped and L-shaped contact structures, are employed in semiconductor devices and, in certain instances, phase-change nonvolatile memory devices. The I-shaped and L-shaped contact structures produced by these methods exhibit relatively small active areas. The methods that determine the contact structure dimensions employ conventional semiconductor deposit and etch processing steps that are capable of creating readily reproducible results.

Abstract: A phase change material may be formed within a trench in a first layer to form a damascene memory element and in an overlying layer to form a threshold device. Below the first layer may be a wall heater. The wall heater that heats the overlying phase change material may be formed in a U-shape in some embodiments of the present invention. The phase change material for the memory element may be elongated in one direction to provide greater alignment tolerances with said heater and said threshold device.

Abstract: The problem is to provide a technology to reduce a light leakage current in order to obtain a good display. One kind or plurality kinds of elements chosen from argon, germanium, silicon, helium, neon, krypton, and xenon are implanted in a crystalline semiconductor layer, to distribute crystal defects due to the aforementioned element implantation by uniform and suitable density in the semiconductor film, making recombination centers of carriers, to thereby suppress alight sensitivity without spoiling a high degree of carrier movement included in a crystalline semiconductor layer.

Abstract: In an npn-type transistor, the emitter 42 and the collector 43 are formed of an n-type transparent semiconductor, and the base 41 is formed by a p-type transparent semiconductor. The base electrode 44, the emitter electrode 45 and the collector electrode 46 are formed respectively on the base 41, the emitter 42 and the collector 43. As the n-type transparent semiconductor, for example, n-type ZnO is used. The n-type ZnO is ZnO doped with, for example, group III elements, group VII elements. As the p-type transparent semiconductor, for example, p-type ZnO is used. The p-type ZnO is ZnO doped with, for example, group I elements and group V elements.

Abstract: An ultra-high density data storage device using phase-change diode memory cells, and having a plurality of emitters for directing beams of directed energy, a layer for forming multiple data storage cells and a layered diode structure for detecting a memory or data state of the storage cells, wherein the device comprises a phase-change data storage layer capable of changing states in response to the beams from the emitters, comprising a material containing copper, indium and selenium. A method of forming a diode structure for a phase-change data storage array, having multiple thin film layers adapted to form a plurality of data storage cell diodes, wherein the method comprises depositing a first diode layer of material on a substrate, and depositing a second diode layer of phase-change material on the first diode layer, the phase-change material containing copper, indium and selenium.