Group Ii-vi Compound (e.g., Cdte, Hg X Cd 1-x Te) Patents (Class 257/614)
  • Patent number: 6998697
    Abstract: A chalcogenide comprising material is formed to a first thickness over the first conductive electrode material. The chalcogenide material comprises AxBy. A metal comprising layer is formed to a second thickness over the chalcogenide material. The metal comprising layer defines some metal comprising layer transition thickness for the first thickness of the chalcogenide comprising material such that when said transition thickness is met or exceeded, said metal comprising layer when diffused within said chalcogenide comprising material transforms said chalcogenide comprising material from an amorphous state to a crystalline state. The second thickness being less than but not within 10% of said transition thickness. The metal is irradiated effective to break a chalcogenide bond of the chalcogenide material at an interface of the metal and chalcogenide material and diffuse at least some of the metal into the chalcogenide material.
    Type: Grant
    Filed: December 17, 2003
    Date of Patent: February 14, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Kristy A. Campbell, John T. Moore
  • Patent number: 6975012
    Abstract: Disclosed is a semiconductor radiation detector element of Schottky barrier type, comprising: a compound semiconductor crystal including cadmium and tellurium as main components; and voltage application means for applying voltage to the compound semiconductor crystal. According to the present invention, said voltage application means includes a compound of indium, cadmium and tellurium: InxCdyTez formed on one surface of the compound semiconductor crystal. Preferably, the rate ā€œzā€ of occupation of tellurium in the compound InxCdyTez is in the range of not less than 42.9%, but not greater than 50% by ratio of number of atoms. Furthermore, preferably, the rate ā€œyā€ of occupation of cadmium in the compound InxCdyTez is in the range of not less than 0%, but not greater than 10% by ratio of number of atoms.
    Type: Grant
    Filed: October 29, 2003
    Date of Patent: December 13, 2005
    Assignee: Acrorad Co., Ltd.
    Inventors: Miki Moriyama, Masaki Murakami, Atsushi Kyan, Ryoichi Ohno
  • Patent number: 6878975
    Abstract: A novel tunnel structure is described that enables tunnel diode behavior to be exhibited even in material systems in which extremely heavy doping is impossible and only moderate or light doping levels may be achieved. In one aspect, the tunnel heterostructure includes a first semiconductor layer, a second semiconductor layer, and an intermediate semiconductor layer that is sandwiched between the first and second semiconductor layers and forms first and second heterointerfaces respectively therewith. The first and second heterointerfaces are characterized by respective polarization charge regions that produce a polarization field across the intermediate semiconductor layer that promotes charge carrier tunneling through the intermediate semiconductor layer. In another aspect, the invention features a semiconductor structure having a p-type region, and the above-described heterostructure disposed as a tunnel contact between the p-type region of the semiconductor structure and an adjacent n-type region.
    Type: Grant
    Filed: February 8, 2002
    Date of Patent: April 12, 2005
    Assignee: Agilent Technologies, Inc.
    Inventor: Mark R. Hueschen
  • Patent number: 6653664
    Abstract: Bandgap engineering of thin-film electroluminescent (TFEL) devices increases their efficiency and brightness. An alternating current thin-film electroluminescent display has two stacked dielectrics, a semiconductor active layer therebetween, and metallic cladding electrodes at each side thereof. The semiconductor layer is developed by automated thermal co-evaporation so as to provide a monotonic decrease of the band gap thereof from the respective interfaces with the stacked dielectrics to the middle of the semiconductor active layer so that the dopant concentration thereof is maintained at about 0.7 %.
    Type: Grant
    Filed: May 7, 2002
    Date of Patent: November 25, 2003
    Assignee: Luxell Technologies, Inc.
    Inventor: Alexey N. Krasnov
  • Patent number: 6589447
    Abstract: Provided is a compound semiconductor single crystal and a fabrication process for a compound semiconductor device capable of forming a prescribed pattern without requirement of many steps. A group V element component in a III-V compound semiconductor single crystal or a group VI element component in the II-VI compound semiconductor single crystal is reduced less than a composition ratio expressed by a chemical formula of a corresponding compound semiconductor single crystal in a pattern-shaped portion.
    Type: Grant
    Filed: December 18, 2000
    Date of Patent: July 8, 2003
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Junya Ishizaki, Nobuhiko Noto
  • Patent number: 6566700
    Abstract: A phase-change memory cell may be formed with a carbon-containing interfacial layer that heats a phase-change material. By forming the phase-change material in contact, in one embodiment, with the carbon containing interfacial layer, the amount of heat that may be applied to the phase-change material, at a given current and temperature, may be increased. In some embodiments, the performance of the interfacial layer at high temperatures may be improved by using a wide band gap semiconductor material such as silicon carbide.
    Type: Grant
    Filed: October 11, 2001
    Date of Patent: May 20, 2003
    Assignee: Ovonyx, Inc.
    Inventor: Daniel Xu
  • Patent number: 6541863
    Abstract: There is provided a semiconductor device comprising an insulating layer which is partly formed of porous material, and a method for fabricating the device. A stray capacitance of adjacent wiring lines is significantly reduced by reducing the amount of material, i.e., by using porous material in the insulating layer of a metallization layer. In one embodiment, the porous layer may be fabricated separately on a further substrate and is subsequently transferred to the product wafer while the further substrate and the product wafer are appropriately aligned to each other. In this way, fabrication of complete metallization layers having a reduced dielectric constant in advance or concurrently with the product wafer carrying the MOS structure is possible. Due to the reduced capacitance of the wiring lines of the metallization layer, signal performance and/or power consumption of an integrated circuit is improved.
    Type: Grant
    Filed: January 5, 2000
    Date of Patent: April 1, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Manfred Horstmann, Karsten Wieczorek, Gert Burbach
  • Publication number: 20030030067
    Abstract: The present relates in general to upconversion luminescence (“UCL”) materials and methods of making and using same and more particularly, but not meant to be limiting, to Mn2+ doped semiconductor nanoparticles for use as UCL materials. The present invention also relates in general to upconversion luminescence including two-photon absorption upconversion, and potential applications using UCL materials, including light emitting diodes, upconversion lasers, infrared detectors, chemical sensors, temperature sensors and biological labels, all of which incorporate a UCL material.
    Type: Application
    Filed: June 6, 2002
    Publication date: February 13, 2003
    Inventor: Wei Chen
  • Publication number: 20030011047
    Abstract: This invention is a layered thin film semiconductor device comprising a first transparent layer; a thin, second transparent layer having a conductivity less than the first transparent layer; an n-type layer; and a p-type layer comprising one or more IIB and VIA elements. This invention is also a method for making such semiconductor device. The thin film semiconductor devices of this invention are useful for making photovoltaic devices.
    Type: Application
    Filed: May 7, 2002
    Publication date: January 16, 2003
    Inventors: Daniel W. Cunningham, Marc P. Rubcich
  • Patent number: 6452206
    Abstract: A superlattice structure for thermoelectric power generation includes m monolayers of a first barrier material alternating with n monolayers of a second quantum well material with a pair of monolayers defining a superlattice period and each of the materials having a relatively smooth interface therebetween. Each of the quantum well layers have a thickness which is less than the thickness of the barrier layer by an amount which causes substantial confinement of conduction carriers to the quantum well layer and the alternating layers provide a superlattice structure having a figure of merit which increases with increasing temperature.
    Type: Grant
    Filed: March 16, 1998
    Date of Patent: September 17, 2002
    Assignee: Massachusetts Institute of Technology
    Inventors: Theodore C. Harman, Mildred S. Dresselhaus, David L. Spears, Michael P. Walsh, Stephen B. Cronin, Xiangzhong Sun, Takaaki Koga
  • Patent number: 6420725
    Abstract: A method and an apparatus for manufacturing a memory cell having a non-volatile resistive memory element with a limited size active area. The method comprises a first step of providing a dielectric volume and forming a plug opening within the dielectric volume. A recessed plug of a conductive material is then formed within a lower portion of the opening and a dielectric spacer is formed along the sidewalls of an upper portion of the opening. The spacer is cylindrical and has a central hole. A contact plug is subsequently formed within the central hole, the contact plug electrically coupled to the recessed plug. The contact plug can include a memory element or an additional memory element can be applied over the contact plug.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: July 16, 2002
    Assignee: Micron Technology, Inc.
    Inventor: Steven T. Harshfield
  • Publication number: 20020070426
    Abstract: The invention relates to a method for forming a telescoped multiwall nanotube. Such a telescoped multiwall nanotube may find use as a linear or rotational bearing in microelectromechanical systems or may find use as a constant force nanospring. In the method of the invention, a multiwall nanotube is affixed to a solid, conducting substrate at one end. The tip of the free end of the multiwall nanotube is then removed, revealing the intact end of the inner wall. A nanomanipulator is then attached to the intact end, and the intact, core segments of the multiwall nanotube are partially extracted, thereby telescoping out a segment of nanotube.
    Type: Application
    Filed: July 24, 2001
    Publication date: June 13, 2002
    Inventors: John P. Cumings, Alex K. Zettl, Steven G. Louie, Marvin L. Cohen
  • Patent number: 6376866
    Abstract: A light emitting device employing gallium nitride type compound semiconductor which generates no crystal defect, dislocation and can be separated easily to chips by cleavage and a method for producing the same are provided. As a substrate on which gallium nitride type compound semiconductor layers are stacked, a gallium nitride type compound semiconductor substrate, a single-crystal silicon, a group II-VI compound semiconductor substrate, or a group III-V compound semiconductor substrate is employed.
    Type: Grant
    Filed: May 11, 2000
    Date of Patent: April 23, 2002
    Assignee: Rohm Co., Ltd.
    Inventor: Yukio Shakuda
  • Patent number: 6359290
    Abstract: A method of making a diode and the diode wherein there is provided a substrate of p-type group II-VI semiconductor material and an electrically conductive material capable of forming an ohmic contact with the substrate is forced into the lattice of the substrate to create an n-type region in the substrate in contact with the material and forming an electrical contact to the p-type region of said substrate. The substrate is preferably HgCdTe and the electrically conductive material is preferably tungsten or tin coated tungsten or tungsten coated with a mercury amalgam.
    Type: Grant
    Filed: February 6, 1996
    Date of Patent: March 19, 2002
    Assignee: Raytheon Company
    Inventor: John C. Ehmke
  • Patent number: 6333110
    Abstract: Provided is a method of fluorescence imaging of living tissue using functionalized nanocrystals. The method comprises contacting an effective amount of functionalized nanocrystals with the living tissue; exposing the tissue to a spectrum of light suitable for exciting functionalized nanocrystals, present in fluorescently labeled tissue, to emit a emission spectrum comprising a fluorescence peak; and detecting any fluorescence peak emitted by the tissue exposed to the excitation spectrum of light, and obtaining a fluorescence image of the tissue. Also provided is a composition comprising a functionalized nanocrystal which is bound to a substrate in a living tissue.
    Type: Grant
    Filed: September 13, 1999
    Date of Patent: December 25, 2001
    Assignee: Bio-Pixels Ltd.
    Inventor: Emilio Barbera-Guillem
  • Patent number: 6319607
    Abstract: Provided are methods for purifying functionalized fluorescent nanocrystals having affinity ligand operably bound thereto by using a solid support matrix in a reactor through which solutions are circulated, and by using an immobilized solid phase formed by operably binding functionalized fluorescent nanocrystals to the solid support matrix. Also provided are purified functionalized fluorescent nanocrystals having affinity ligand operably bound thereto which are purified using the methods according to the present invention to be substantially free of free affinity ligand.
    Type: Grant
    Filed: June 8, 2000
    Date of Patent: November 20, 2001
    Assignee: Bio-Pixels Ltd.
    Inventors: Emilio Barbera-Guillem, Stephanie L. Castro
  • Patent number: 6312617
    Abstract: A family of isostructural compounds have been prepared having the general formula AnPbmBinQ2n+m. These compounds possess a NaCl lattice type structure as well as low thermal conductivity and controlled electrical conductivity. Furthermore, the electrical properties can be controlled by varying the values for n and m. These isostructural compounds can be used for semiconductor applications such as detectors, lasers and photovoltaic cells. These compounds also have enhanced thermoelectric properties making them excellent semiconductor materials for fabrication of thermoelectric devices.
    Type: Grant
    Filed: October 11, 1999
    Date of Patent: November 6, 2001
    Assignee: Board of Trustees operating Michigan State University
    Inventors: Mercouri G. Kanatzidis, Duck Young Chung, Stephane DeNardi, Sandrine Sportouch
  • Patent number: 6309701
    Abstract: Provided are a fluorescent microsphere comprised of a plurality of fluorescent nanocrystals operably bound to a polymeric microsphere, and a method of producing the fluorescent microspheres which comprises contacting the polymeric microsphere with a plurality of fluorescent nanocrystals under suitable conditions in which the fluorescent naocrystals become operably bound to the polymeric microsphere. Also provided is a method of using the fluorescent microspheres capable of determining the presence or absence of a predetermined number of analytes in a sample by contacting the sample with the fluorescent microspheres, and detecting the fluorescence signal pattern of excited fluorescent microspheres bound to one or more analytes of the predetermined number of analytes, if present in the sample.
    Type: Grant
    Filed: May 24, 2000
    Date of Patent: October 30, 2001
    Assignee: Bio-Pixels Ltd.
    Inventor: Emilio Barbera-Guillem
  • Patent number: 6281521
    Abstract: Silicon carbide channel semiconductor devices are provided which eliminate the insulator of the gate by utilizing a semiconductor gate layer and buried base regions to create a “pinched off” gate region when no bias is applied to the gate. In particular embodiments of the present invention, the semiconductor devices include a silicon carbide drift layer of a first conductivity type, the silicon carbide drift layer having a first face and having a channel region therein. A buried base region of a second conductivity type semiconductor material is provided in the silicon carbide drift layer so as to define the channel region. A gate layer of a second conductivity type semiconductor material is formed on the first face of the silicon carbide drift layer adjacent the channel region of the silicon carbide drift layer. A gate contact may also be formed on the gate layer. Both transistors and thyristors may be provided.
    Type: Grant
    Filed: July 9, 1998
    Date of Patent: August 28, 2001
    Assignee: Cree Research Inc.
    Inventor: Ranbir Singh
  • Patent number: 6274882
    Abstract: The alloy is for making an infrared transducer. It is constituted by (In1−xTlx) (As1−ySby) in which 0≦x<1 and 0<y<1 (where x and y are less than ½). On a GaSb or AlSb substrate, the transducer comprises an active layer of the alloy having a composition such that its lattice is of a size that is equal to that of the substrate material.
    Type: Grant
    Filed: February 26, 1999
    Date of Patent: August 14, 2001
    Assignee: Sagem SA
    Inventors: Christian Verie, Dominique Lorans, Michel Poirier
  • Patent number: 6208005
    Abstract: A variable bandgap infrared absorbing material, Hg1-x Cdx Te, is manufactured by use of the process termed MOCVD-IMP (Metalorganic Chemical Vapor Deposition-Interdiffused Multilayer Process). A substantial reduction in the dislocation defect density can be achieved through this method by use of CdZnTe layers which have a zinc mole fraction selected to produce a lattice constant which is substantially similar to the lattice constant of HgTe. After the multilayer pairs of HgTe and Cd0.944Zn0.056Te are produced by epitaxial growth, the structure is annealed to interdiffuse the alternating layers to produce a homogeneous alloy of mercury cadmium zinc telluride. The mole fraction x in Hg1-x(Cd0.944Zn0.056)xTe can be varied to produce a structure responsive to multiple wavelength bands of infrared radiation, but without changing the lattice constant. The alloy composition is varied by changing the relative thicknesses of HgTe and Cd0.944Zn0.056Te.
    Type: Grant
    Filed: March 1, 1999
    Date of Patent: March 27, 2001
    Assignee: Lockheed Martin Corporation
    Inventor: Pradip Mitra
  • Patent number: 6114038
    Abstract: Provided are compositions comprising water-soluble, functionalized nanocrystals. The water-soluble functionalized nanocrystals comprise quantum dots capped with a layer of a capping compound, and further comprise, by operably linking and in a successive manner, one or more additional compounds. The one or more additional compounds is comprised of at least a diaminocarboxylic acid which is operatively linked to the capping compound, and may further comprise an amino acid, an affinity ligand, or a combination thereof. Also provided are methods of using the functionalized nanocrystals having an affinity ligand to detect the presence or absence of a target substrate in a sample.
    Type: Grant
    Filed: August 11, 1999
    Date of Patent: September 5, 2000
    Assignee: BioCrystal Ltd.
    Inventors: Stephanie L. Castro, Emilio Barbera-Guillem
  • Patent number: 6081019
    Abstract: A multi-layer Auger suppressed diode having at least two exclusion interfaces and at least two extraction interfaces. A specific embodiment has two composite contacts, each consisting of a heavily doped layer (3, 4) and a buffer layer (8, 9) of lower doped, high bandgap material sandwiched between the heavily doped layer and the active region (2) of the device.
    Type: Grant
    Filed: March 30, 1998
    Date of Patent: June 27, 2000
    Assignee: The Secretary of State for Defence in Her Britannic Majesty's Government of the United Kingdom of Great Britain and Northern Ireland
    Inventor: Anthony M White
  • Patent number: 6072198
    Abstract: A light emitting phosphor having improved luminance is incorporated into an ACTFEL device having front and rear electrode sets, a pair of insulators sandwiched between the front and rear electrode sets, and a thin film electroluminescent laminar stack which includes a phosphor layer having the formula M.sup.II S:D,H where M.sup.II is taken from the group calcium, strontium, barium, and magnesium, S=sulfur, D is taken from the group copper, lead, gold, silver, magnesium, antimony, bismuth and arsenic, and H is taken from the group fluorine, chlorine, bromine, and iodine. Deep blue and green chromaticity phosphors may be obtained through selection of multiple co-dopants and adjusting their relative concentrations.
    Type: Grant
    Filed: September 14, 1998
    Date of Patent: June 6, 2000
    Inventors: Sey-Shing Sun, Jim Kane, P. Niel Yocom
  • Patent number: 6069020
    Abstract: In a method of manufacturing a semiconductor light-emitting device composed of a II-VI compound semiconductor in which at least more than one kind of elements of Zn, Be, Mg, Cd or Hg are used as a II-group element and at least more than one kind of elements of Se, S, Te are used as a VI-group element and which includes first conductivity type and second conductivity type cladding layers and an active layer, a supply ratio VI/II ratio of VI-group element and II-group element required when the active layer is epitaxially deposited is selected to be greater than 1.1 and the active layer is deposited epitaxially. Thus, there may be obtained a highly-reliable semiconductor light-emitting device whose life time is made longer.
    Type: Grant
    Filed: November 13, 1998
    Date of Patent: May 30, 2000
    Assignee: Sony Corporation
    Inventors: Eisaku Kato, Hiroyasu Noguchi, Masaharu Nagai
  • Patent number: 6049116
    Abstract: A structure and the fabrication method of two-color IR detector are disclosed. Disclosed two-color IR detector structure is a n-p-N structure which can be realized using only two-layer HgCdTe. The most important factor in the two-color IR detector structure is the formation of the potential barrier in the conduction band of p-N heterojunction. This potential barrier prevents photogenerated minority carriers in p-HgCdTe region from diffusing to and being collected by N-HgCdTe region (larger band gap diode). The calculated potential barrier heights under the thermal equilibrium at 77 K are 21 kT (141 meV) and 13.4 kT (89 meV) for the cases of p-Hg.sub.0.78 Cd.sub.0.22 Te/N-Hg.sub.0.69 Cd.sub.0.3l Te and p-Hg.sub.0.69 Cd.sub.0.31 Te/N-Hg.sub.0.636 Cd.sub.0.364 Te with each side carrier concentration of 5.times.10.sup.15 and 1.times.10.sub.16 cm.sup.-3, respectively.
    Type: Grant
    Filed: May 13, 1998
    Date of Patent: April 11, 2000
    Assignee: Agency for Defense Development
    Inventors: Seung-Man Park, Jae Ryong Yoon, Jae Mook Kim, Hee Chul Lee, Choong-Ki Kim
  • Patent number: 6043548
    Abstract: Self stabilizing concentration profiles are achieved in solids. More particularly, semiconductor devices are made from n- or p-type mercury cadmium telluride (MCT) of the general formula Hg.sub.x Cd.sub.1-x Te where x=0.2 to 0.5 and n- or p-type zinc mercury telluride (ZMT) of the general formula Zn.sub.x Hg.sub.1-x Te where x=0.4 to 0.6. Silver, incorporated as a doping impurity or applied as an evaporated spot electromigrated within the MCT or ZMT to create one or more p-n junctions, usually under the influence of a pulsed positive bias. The resulting concentration profiles of silver and opposing internal electric fields of the p-n junctions achieve a balancing equilibrium that preserves and maintains the stability of the concentration profiles. For a specific telluride composition, Hg.sub.0.3 Cd.sub.0.7 Te, indium is the n-type dopant of choice.
    Type: Grant
    Filed: December 12, 1996
    Date of Patent: March 28, 2000
    Assignee: Yeda Research and Development Co., Ltd.
    Inventors: David Cahen, Konstantin Gartsman, Igor Lyubomirsky
  • Patent number: 5952703
    Abstract: A semiconductor device having: a support substrate having an upper surface; a HgTe layer formed on the support substrate; and a HgCdTe layer directly formed on the HgTe layer. A semiconductor device of another type having: a support substrate having an exposed upper surface tilted from the (100) plane of a single crystal with a diamond structure by a certain angle, along a direction offset by an angle larger than 0.degree. and smaller than 45.degree. from the ?011! direction in the (100) plane; a group III-V compound semiconductor layer formed on the support substrate; and a group II-VI compound semiconductor layer formed on the group III-V compound semiconductor layer.
    Type: Grant
    Filed: December 21, 1995
    Date of Patent: September 14, 1999
    Assignee: Fujitsu Limited
    Inventors: Satoshi Murakami, Tetsuo Saito, Hironori Nishino, Yoichiro Sakachi, Tohru Okamoto, Kenji Maruyama
  • Patent number: 5900071
    Abstract: A superlattice structure comprising alternating layers of material such as (PbEuTeSe).sub.m and (BiSbn).sub.n where m and n are the number of PbEuTeSe and BiSb monolayers per superlattice period. For one superlattice structure the respective quantum barrier layers may be formed from electrical insulating material and the respective quantum well layers may be formed from semimetal material. For some applications superlattice structures with 10,000 or more periods may be grown. For example, the superlattice structure may comprise alternating layers of (Pb.sub.1-y Eu.sub.y Te.sub.1-z Se.sub.z).sub.m and (Bi.sub.x Sb.sub.1-x).sub.n. According to one embodiment, the superlattice structure may comprise a plurality of layers comprising m layers of (Pb.sub.1-y Eu.sub.y Te.sub.1-z Se.sub.z).sub.m and n layers of Bi.sub.0.9 Sb.sub.0.1, where m and n are preferably between 2 and 20, grown on a BaF.sub.2 substrate with a buffer layer of PbTe separating the substrate and the superlattice structure.
    Type: Grant
    Filed: September 8, 1997
    Date of Patent: May 4, 1999
    Assignee: Massachusetts Institute of Technology
    Inventor: Theodore C. Harman
  • Patent number: 5883683
    Abstract: A nonlinear device of the present invention includes: a first electrode and a second electrode at least partially opposing each other; and a nonlinear resistant layer made of a material mainly containing zinc sulfide, formed so as to be in contact with the first electrode and the second electrode, wherein at least one of the first electrode and the second electrode is made of an electrode material satisfying a relationship .DELTA.G.sub.M -.DELTA.G.sub.Zn >0, where .DELTA.G.sub.M is standard free energy of a generation reaction of a sulfide of the electrode material and .DELTA.G.sub.Zn is standard free energy of a generation reaction of a sulfide of zinc.
    Type: Grant
    Filed: July 7, 1997
    Date of Patent: March 16, 1999
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Satoshi Yamaue, Masaru Yoshida
  • Patent number: 5831297
    Abstract: The present invention provides a structure of a metal-insulator-semiconductor (MIS)-like multiple-negative-differential-resistance (MNDR) device and the fabrication method thereof. The device of the present invention has the characteristics of dual-route and MNDR at low temperatures. These characteristics result from the successive barrier-lowering and potential-redistribution effect when conducting carriers fall into a quantum well. MNDR devices have excellent potential in multiple-value logic circuitry applications and are capable of reducing circuitry complexity.
    Type: Grant
    Filed: April 7, 1997
    Date of Patent: November 3, 1998
    Assignee: National Science Council
    Inventors: Wen-Chau Liu, Lih-Wen Laih
  • Patent number: 5770887
    Abstract: A GaN single crystal having a full width at half-maximum of the double-crystal X-ray rocking curve of 5-250 sec and a thickness of not less than 80 .mu.m, a method for producing the GaN single crystal having superior quality and sufficient thickness permitting its use as a substrate and a semiconductor light emitting element having high luminance and high reliability, comprising, as a substrate, the GaN single crystal having superior quality and/or sufficient thickness permitting its use as a substrate.
    Type: Grant
    Filed: October 11, 1994
    Date of Patent: June 23, 1998
    Assignee: Mitsubishi Cable Industries, Ltd.
    Inventors: Kazuyuki Tadatomo, Shinichi Watabe, Hiroaki Okagawa, Kazumasa Hiramatsu
  • Patent number: 5767536
    Abstract: A II-VI group compound semiconductor device comprising a Zn.sub.X Mg.sub.1-X S.sub.Y Se.sub.1-Y (0.ltoreq.X.ltoreq.1, 0.ltoreq.Y.ltoreq.1) semiconductor layer, an intermediate layer comprising a compound of an element constituting the semiconductor layer and an additive element of Cd, Te or Hg formed on the semiconductor layer, and an electrode layer containing Ni, Pt or Pd formed on the intermediate layer.
    Type: Grant
    Filed: November 25, 1996
    Date of Patent: June 16, 1998
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masanori Murakami, Yasuo Koide, Nobuaki Teraguchi, Yoshitaka Tomomura
  • Patent number: 5751018
    Abstract: Methods are described for attaching semiconductor nanocrystals to solid inorganic surfaces, using self-assembled bifunctional organic monolayers as bridge compounds. Two different techniques are presented. One relies on the formation of self-assembled monolayers on these surfaces. When exposed to solutions of nanocrystals, these bridge compounds bind the crystals and anchor them to the surface. The second technique attaches nanocrystals already coated with bridge compounds to the surfaces. Analyses indicate the presence of quantum confined clusters on the surfaces at the nanolayer level. These materials allow electron spectroscopies to be completed on condensed phase clusters, and represent a first step towards synthesis of an organized assembly of clusters. These new products are also disclosed.
    Type: Grant
    Filed: April 29, 1994
    Date of Patent: May 12, 1998
    Assignee: The Regents of the University of CAlifornia
    Inventors: A. Paul Alivisatos, Vicki L. Colvin
  • Patent number: 5654583
    Abstract: The semiconductor device has a semiconductor structure directly bonded onto another semiconductor structure of a different kind from the former. These two semiconductor structures are arranged in such a way that their crystal structures in a cross section perpendicular to the bonded interface of the two semiconductor structures are different from each other or that their lattice orders are not equivalent. This can be applied to direct bonding of any combination of semiconductor structures in any crystallographic orientation relation. This also allows bonding of three or more kinds of semiconductor structures.
    Type: Grant
    Filed: June 23, 1995
    Date of Patent: August 5, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Yae Okuno, Kazuhisa Uomi, Masahiro Aoki, Misuzu Sagawa
  • Patent number: 5654558
    Abstract: This invention describes a nanometer scale interband lateral resonant tunneling transistor, and the method for producing the same, with lateral geometry, good fanout properties and suitable for incorporation into large-scale integrated circuits. The transistor is of a single gate design and operation is based on resonant tunneling processes in narrow-gap nanostructures which are highly responsive to quantum phenomena. Such quantum-effect devices can have very high density, operate at much higher temperatures and are capable of driving other devices.
    Type: Grant
    Filed: November 14, 1994
    Date of Patent: August 5, 1997
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Jerry R. Meyer, Craig A. Hoffman, Filbert J. Bartoli, Jr.
  • Patent number: 5644165
    Abstract: A p-type ohmic metal electrode for use with a group II-VI semiconductor device. The p-type ohmic metal electrode is made of a group II-IV p-type semiconductor layer having a group II element other than zinc dispersed in that layer disposed on the group II-IV semiconductor device, and a metal electrode layer disposed on the group II-IV semiconductor layer including the group II element other than zinc. Also disclosed is a group II-IV semiconductor device including a p-type group II-IV semiconductor containing zinc and selenium and the above ohmic metal electrode disposed on the group II-IV semiconductor device. Additionally, a group II-IV semiconductor device including a p-type group II-IV semiconductor containing zinc and selenium, a layer of a group II element other than zinc disposed on the group II-IV semiconductor device, and a metal electrode layer disposed on the layer of the group II element other than zinc is disclosed.
    Type: Grant
    Filed: February 27, 1996
    Date of Patent: July 1, 1997
    Assignee: Mitsubishi Kasei Corporation
    Inventor: Hideki Goto
  • Patent number: 5581117
    Abstract: The present invention provides an Si base semiconductor monocrystal substrate which includes an Si(11n) substrate where n=1.5-2.5. An intermediate layer is formed on the Si(11n) substrate. The intermediate layer is made of a material selected from the group consisting of ZnTe and Zn-rich CdZnTe, The intermediate layer has a thickness in the range of 50-200 angstroms. The intermediate layer is oriented in a (11n')B plane. An upper layer is formed on the intermediate layer. The upper layer is made of a material selected from the group consisting of CdTe and Cd-rich CdZnTe. The upper layer is oriented in a (11n")B plane. The indexes n' and n" satisfy the following equations. ##EQU1## where y is the lattice mismatch between the Si substrate and the intermediate layer. ##EQU2## where y' is the lattice mismatch between the Si substrate and the upper layer.
    Type: Grant
    Filed: December 13, 1995
    Date of Patent: December 3, 1996
    Assignee: NEC Corporation
    Inventor: Masaya Kawano
  • Patent number: 5574296
    Abstract: An electromagnetic radiation transducer is provided having a p-type ZnSe layer and an n-type layer. The p-type ZnSe layer has a net donor to net acceptor ratio (N.sub.D /N.sub.A) of less than or equal to about 0.8. The net acceptor concentration is greater than about 5.times.10.sup.15 cm .sup.-3 and the resistivity is less than 15 .OMEGA.-cm. The p-type ZnSe layer is deposited by doping the ZnSe during fabrication with a neutral free-radical source.
    Type: Grant
    Filed: July 21, 1993
    Date of Patent: November 12, 1996
    Assignee: Minnesota Mining And Manufacturing Company
    Inventors: Robert M. Park, James M. DePuydt, Hwa Cheng, Michael A. Haase
  • Patent number: 5559359
    Abstract: A passive element structure and method for a microwave integrated circuit reduces signal propagation losses. In one approach, a passive element (10) has an insulating layer (12) overlying a silicon substrate (14). A metal layer (16) comprising a signal line (18) and a groundplane (20) is disposed overlying the insulating layer (12), and at least a portion of the metal layer (16) contacts the substrate (14) through at least one opening (22, 24) in the insulating layer (12). The silicon substrate (14) has a resistivity greater than 2,000 ohm-cm, and the passive element (10) preferably carries signals having frequencies greater than 500 MHz. Signal losses in the passive element (10) are minimized because the charge density at the surface (15) of the substrate (14) underlying the metal layer (16) is significantly reduced. In one example, the passive element (10) is a coplanar waveguide transmission line.
    Type: Grant
    Filed: January 3, 1995
    Date of Patent: September 24, 1996
    Inventor: Adolfo C. Reyes
  • Patent number: 5550387
    Abstract: A thermoelectric element having a very large number of alternating layers of semiconductor material. The alternating layers all have the same crystalline structure. The inventors have demonstrated that materials produced in accordance with this invention provide figures of merit more than six times that of prior art thermoelectric materials. A preferred embodiment is a superlattice of Si, as a barrier material, and SiGe, as a conducting material, both of which have the same cubic structure. Another preferred embodiment is a superlattice of B--C alloys, the layers of which would be different stoichiometric forms of B--C but in all cases the crystalline structure would be alpha 0. In a preferred embodiment the layers are grown under conditions as to cause them to be strained at their operating temperature range in order to improve the thermoelectric properties.
    Type: Grant
    Filed: August 29, 1994
    Date of Patent: August 27, 1996
    Assignee: Hi-Z Corporation
    Inventors: Norbert B. Elsner, Saeid Ghamaty
  • Patent number: 5548137
    Abstract: Group II-VI compound semiconductor light emitting devices which include at least one II-VI quantum well region of a well layer disposed between first and second barrier layers is disclosed. The quantum well region is sandwiched between first and second cladding layers of a II-VI semiconductor material. The first cladding layer is formed on and lattice matched to the first barrier layer and to a substrate of a III-V compound semiconductor material. The second cladding layer is lattice matched to the second barrier layer. The quantum well layer comprises a II-VI compound semiconductor material having the formula A.sub.x B.sub.(1-x) C wherein A and B are two different elements from Group II and C is at least one element from Group VI. When the second cladding layer has a p-type conductivity, a graded bandgap ohmic contact according to the present invention can be utilized.
    Type: Grant
    Filed: March 7, 1994
    Date of Patent: August 20, 1996
    Assignee: Research Corporation Technologies, Inc.
    Inventors: Yongping Fan, Jung Han, Arto V. Nurimikko, Robert L. Gunshor, Li He
  • Patent number: 5541118
    Abstract: A process for producing a layer of cadmium sulfide on a cadmium telluride surface to be employed in a photovoltaic device. The process comprises providing a cadmium telluride surface which is exposed to a hydrogen sulfide plasma at an exposure flow rate, an exposure time and an exposure temperature sufficient to permit reaction between the hydrogen sulfide and cadmium telluride to thereby form a cadmium sulfide layer on the cadmium telluride surface and accomplish passivation. In addition to passivation, a heterojunction at the interface of the cadmium sulfide and the cadmium telluride can be formed when the layer of cadmium sulfide formed on the cadmium telluride is of sufficient thickness.
    Type: Grant
    Filed: May 22, 1995
    Date of Patent: July 30, 1996
    Assignee: Midwest Research Institute
    Inventors: Dean H. Levi, Art J. Nelson, Richard K. Ahrenkiel
  • Patent number: 5506423
    Abstract: A semi-conductor light-emitting device has a substrate, an active layer formed on the substrate for emitting light when an electric current is supplied, a current spreading layer formed on the active layer for spreading an electric current, a light-outputting layer formed on the current spreading layer, and electrodes provided on the semiconductor substrate and the light emitting layer for providing electric current to the active layer. In the device, the current spreading layer is formed of zinc telluride (ZnTe).
    Type: Grant
    Filed: July 14, 1994
    Date of Patent: April 9, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Ryo Saeki
  • Patent number: 5420445
    Abstract: Only the areas of the CdTe/HgCdTe interface of a FPA detector circuit which is coupled by an epoxy to a silicon-based integrated circuit that require interdiffusing are heated to a sufficiently high temperature or have photons of light impinging thereon for a sufficient time to cause interdiffusion of the two layers by the travel of tellurium into the HgCdTe and the travel of mercury into the CdTe. The vast majority of the wafer is masked with an aluminum thin film to greatly reduce heat gain or photon transmission. An advantage of the process in accordance with the present invention is that only a very small fraction of the HgCdTe/epoxy/silicon-based integrated circuit wafer receives incoming energy during interdiffusion whereby problems caused by the differences in coefficient of thermal expansion between silicon and HgCdTe at the epoxy interface are minimized.
    Type: Grant
    Filed: February 22, 1993
    Date of Patent: May 30, 1995
    Assignee: Texas Instruments Incorporated
    Inventors: Michael F. Chisholm, David I. Forehand
  • Patent number: 5382812
    Abstract: A light emitting semiconductor heterojunction includes a first layer of n-type semiconducting material comprising a Group II-VI material, and a second layer of p-type semiconducting diamond on the first layer. Preferably the Group II-VI material includes a Group II material selected from the group consisting of zinc and cadmium, and the Group VI material is selected from the group consisting of sulfur and selenium. The light emitting heterojunction will produce light having a wavelength in the range of about 440-550 nanometers, depending on the composition and the temperature of operation. One embodiment of the device is a surface emitting device and includes a contact layer on the diamond layer having a predetermined shape, such as a ring, overlying only a portion of the diamond layer for permitting surface emission of light from diamond layer.
    Type: Grant
    Filed: April 14, 1993
    Date of Patent: January 17, 1995
    Assignee: Kobe Development Corporation
    Inventor: David L. Dreifus
  • Patent number: 5382813
    Abstract: A light emission diode comprises a semiconductor substrate and a pn junction structure including an n-type ZnS compound semiconductor layer and a p-type ZnS compound semiconductor layer, Al being present in at least one of the semiconductor layers. By this, the diode is able to emit blue light at a high luminous intensity.
    Type: Grant
    Filed: November 9, 1993
    Date of Patent: January 17, 1995
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Yoshio Morita
  • Patent number: 5374841
    Abstract: A HgCdTe S-I-S (semiconductor-insulator-semiconductor) two color infrared detector wherein the semiconductor regions are HgCdTe with different compositions for the desired spectral regions. The device is operated as a simple integrating MIS device with respect to one semiconductor. The structure can be grown by current MBE techniques and does not require any significant additional steps with regard to fabrication.
    Type: Grant
    Filed: January 11, 1994
    Date of Patent: December 20, 1994
    Assignee: Texas Instruments Incorporated
    Inventor: Michael W. Goodwin
  • Patent number: 5366927
    Abstract: An ohmic contact to a p-type zinc selenide (ZnSe) layer in a Group II-VI semiconductor device, includes a zinc telluride selenide (ZnTe.sub.x Se.sub.1-x) layer on the zinc selenide layer, a mercury selenide (HgSe) layer on the zinc telluride selenide layer and a conductor (such as metal) layer on the mercury selenide layer. The zinc telluride selenide and mercury selenide layers between the p-type zinc selenide and the conductor layer provide an ohmic contact by eliminating the band offset between the wide bandgap zinc selenide and the conductor. Step graded, linear graded, and parabolic graded layers of zinc telluride selenide may be provided. An integrated heterostructure is formed by epitaxially depositing the ohmic contact on the Group II-VI device. A removable overcoat layer may be formed on the Group II-VI device to allow room temperature atmospheric pressure transfer of the device from a zinc based deposition chamber to a mercury based deposition chamber, for deposition of the ohmic contact.
    Type: Grant
    Filed: September 28, 1993
    Date of Patent: November 22, 1994
    Assignee: North Carolina State University
    Inventor: Jan F. Schetzina
  • Patent number: RE38582
    Abstract: A multi-layer Auger suppressed diode having at least two exclusion interfaces and at least two extraction interfaces. A specific embodiment has two composite contacts, each consisting of a heavily doped layer (3, 4) and a buffer layer (8, 9) of lower doped, high bandgap material sandwiched between the heavily doped layer and the active region (2) of the device.
    Type: Grant
    Filed: June 26, 2002
    Date of Patent: September 14, 2004
    Assignee: QinetiQ Limited
    Inventor: Anthony M. White