Group Iii-v Compound (e.g., Inp) Patents (Class 257/615)
  • Patent number: 10418248
    Abstract: Disclosed is a method of chemically-mechanically polishing a substrate. The method comprises, consists of, or consists essentially of (a) contacting a substrate containing at least one Group III-V material, with a polishing pad and a chemical-mechanical polishing composition comprising water, abrasive particles having a negative surface charge, and an oxidizing agent for oxidizing the Group III-V material in an amount of from about 0.01 wt. % to about 5 wt. %, wherein the polishing composition has a pH of from about 2 to about 5; (b) moving the polishing pad and the chemical-mechanical polishing composition relative to the substrate; and (c) abrading at least a portion of the substrate to polish the substrate. In some embodiments, the Group III-V material is a semiconductor that includes at least one element from Group III of the Periodic Table and at least one element from Group V of the Periodic Table.
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: September 17, 2019
    Assignee: Cabot Microelectronics Corporation
    Inventors: Benjamin Petro, Glenn Whitener, William Ward
  • Patent number: 10355169
    Abstract: Disclosed is a substrate structure and a method for forming the same, in which a high-quality nitride semiconductor layer may be formed with a reduced stress applied to the nitride semiconductor layer at the growth of the nitride semiconductor layer and also be easily separated from the substrate, and a semiconductor lamination structure using the same and a method for forming the same, and a method for manufacturing a nitride semiconductor using the same. The substrate structure includes a single-crystal substrate heterogeneous from a nitride semiconductor, and a crystallized inorganic thin film having a leg portion configured to contact the substrate to define an integrated cavity between the leg portion and the substrate and an upper surface extending from the leg portion and parallel to the substrate, the crystallized inorganic thin film having the same crystal structure as the substrate.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: July 16, 2019
    Assignee: Hexasolution Co., Ltd.
    Inventors: Duk-Kyu Bae, Young-Boo Moon, Yongjo Park
  • Patent number: 10340886
    Abstract: A ceramic substrate is formed of a polycrystalline ceramic and has a supporting main surface. The supporting main surface has a roughness of 0.01 nm or more and 3.0 nm or less in terms of Sa. The number of projections and depressions with a height of 1 nm or more in a square region with 50 ?m sides on the supporting main surface is less than 5 on average, and the number of projections and depressions with a height of 2 nm or more in the square region is less than 1 on average.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: July 2, 2019
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Keiichiro Geshi, Shigeru Nakayama
  • Patent number: 10297501
    Abstract: A wafer has a front face that is partitioned by a plurality of streets crossing with each other into a plurality of regions in each of which a device is formed. A surface protective tape is adhered to the front face of the wafer. Then a laser beam having a wavelength transparent to the wafer is irradiated along the streets from a rear face side of the wafer to form a modified layer inside the wafer. Then the wafer is ground from the rear face side to thin the wafer. When the surface protective tape is applied, the surface protective tape is heated. When the modified layer is formed, cracks extend from the modified layer to the front face of the wafer. When ground, the wafer is divided into individual chips with the cracks serving as boundaries.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: May 21, 2019
    Assignee: DISCO CORPORATION
    Inventors: Masamitsu Agari, Bae Tewoo
  • Patent number: 10243104
    Abstract: A composition of matter comprising a plurality of nanowires on a substrate, said nanowires having been grown epitaxially on said substrate in the presence of a metal catalyst such that a catalyst deposit is located at the top of at least some of said nanowires, wherein said nanowires comprise at least one group III-V compound or at least one group II-VI compound or comprises at least one non carbon group IV element; and wherein a graphitic layer is in contact with at least some of the catalyst deposits on top of said nanowires.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: March 26, 2019
    Assignee: NORWEGIAN UNIVERESITY OF SCIENCE AND TECHNOLOGY (NTNU)
    Inventors: Helge Weman, Bjørn-Ove Fimland, Dong Chul Kim
  • Patent number: 10218346
    Abstract: Large area, high current, lateral GaN power transistors are implemented using an on-chip interconnect topology wherein the transistor is arranged as an array of sections, each section comprising a set of transistor islands; gate and source buses that form each gate drive loop have substantially the same track widths; the source bus runs over or under the gate bus, and the tracks are inductively coupled to provide flux cancellation in the gate drive loop, thereby reducing parasitic inductances. The gate delay in each gate drive loop is reduced, minimizing the gate drive phase difference across the transistor. An overlying current redistribution layer preferably has a track width no greater than that of the underlying source and drain buses, for efficient coupling. This topology provides improved scalability, enabling fabrication of multi-section, large scale, high current lateral GaN transistors with reduced gate drive loop inductance, for improved operational stability.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: February 26, 2019
    Assignee: GaN Systems Inc.
    Inventors: Ahmad Mizan, Greg P. Klowak, Xiaodong Cui
  • Patent number: 10094047
    Abstract: A wafer is produced from a compound single crystal ingot having end surface. A separation plane is formed by setting the focal point of a laser beam inside the ingot at a predetermined depth from the end surface. The depth corresponds to the thickness of the wafer to be produced. The laser beam is applied to the end surface to form a modified layer parallel to the end surface and cracks extending from the modified layer, thus forming the separation plane. The ingot has first atoms having a larger atomic weight and second atoms having a smaller atomic weight, and the end surface of the ingot is set as a polar plane where the second atoms are arranged in forming the separation plane. After producing the wafer from the ingot, the first end surface is ground to be flattened.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: October 9, 2018
    Assignee: Disco Corporation
    Inventor: Kazuya Hirata
  • Patent number: 9978845
    Abstract: Methods and structures for forming flat, continuous, planar, epitaxial layers of semipolar III-nitride materials on patterned sapphire substrates are described. Semipolar GaN may be grown from inclined c-plane facets on a patterned sapphire substrate, and coalesced to form a continuous layer of semipolar III-nitride semiconductor over the sapphire substrate. Planarization of the layer is followed by crystal regrowth using a nitrogen carrier gas to produce a flat, microfabrication-grade, process surface of semipolar III-nitride semiconductor across the substrate. Quality multiple quantum wells can be fabricated in the regrown semipolar material.
    Type: Grant
    Filed: April 15, 2015
    Date of Patent: May 22, 2018
    Assignee: Yale University
    Inventors: Jung Han, Benjamin Leung
  • Patent number: 9954089
    Abstract: There are disclosed herein various implementations of a semiconductor component including a protrusion propagation body. The semiconductor component includes a substrate, a III-Nitride intermediate stack including the protrusion propagation body situated over the substrate, a III-Nitride buffer layer situated over the group III-V intermediate stack, and a III-Nitride device fabricated over the group III-V buffer layer. The protrusion propagation body includes at least a protrusion generating layer and two or more protrusion spreading multilayers.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: April 24, 2018
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Chan Kyung Choi, Mihir Tungare, Peter Wook Kim
  • Patent number: 9941442
    Abstract: A crystal substrate is composed of a crystal of a nitride of a group 13 element and has a first main face and a second main face. The crystal substrate includes a low carrier concentration region and a high carrier concentration region both extending between the first main face and second main face. The low carrier concentration region has a carrier concentration of 1018/cm3 or lower and a defect density of 107/cm2 or lower. The high carrier concentration region has a carrier concentration of 1019/cm3 or higher and a defect density of 108/cm2 or higher.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: April 10, 2018
    Assignee: NGK INSULATORS, LTD.
    Inventors: Makoto Iwai, Takashi Yoshino
  • Patent number: 9899568
    Abstract: For a Periodic Table Group 13 metal nitride semiconductor crystal obtained by epitaxial growth on the main surface of a base substrate that has a nonpolar plane and/or a semipolar plane as its main surface, an object of the present invention is to provide a high-quality semiconductor crystal that has a low absorption coefficient, is favorable for a device, and is controlled dopant concentration in the crystal, and to provide a production method that can produce the semiconductor crystal. A high-quality Periodic Table Group 13 metal nitride semiconductor crystal that has a precisely controlled dopant concentration within the crystal and a low absorption coefficient and that is thus favorable for a device, can be provided by inhibiting oxygen doping caused by impurity oxygen and having the Si concentration higher than the O concentration.
    Type: Grant
    Filed: April 21, 2014
    Date of Patent: February 20, 2018
    Assignee: Mistubishi Chemical Corporation
    Inventors: Yuya Saito, Sumitaka Itoh, Shigeru Terada, Hiromitsu Kimura
  • Patent number: 9890300
    Abstract: Method for chemical mechanical planarization is provided, which includes: forming a dielectric layer containing at least one opening, the dielectric layer is located on a substrate; epitaxially growing a germanium material within the at least one opening of the dielectric layer, the germanium material extending above a topmost surface of the dielectric layer; and planarizing the germanium material using at least one slurry composition to form coplanar surfaces of the germanium material and the dielectric layer, where a slurry composition of at least one slurry composition polishes the germanium material selective to the topmost surface of the dielectric layer, and includes an abrasive, at least one pH modulator, and an oxidizer, the at least one pH modulator including an acidic pH modulator, and lacking a basic pH modulator.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: February 13, 2018
    Assignees: International Business Machines Corporation, JSR Corporation
    Inventors: Tatsuyoshi Kawamoto, Mahadevaiyer Krishnan, Yohei Oishi, Dinesh Kumar Penigalapati, Rachel S. Steiner, James A. Tornello, Tatsuya Yamanaka
  • Patent number: 9875909
    Abstract: A method for planarizing a silicon layer includes providing a silicon layer having at least one recess therein. Next, a photoresist layer is formed to cover the silicon layer and fill up the recess. Then, the photoresist layer is hardened. After that, part of the photoresist layer is removed by taking a top surface of the silicon layer as a stop layer. Finally the photoresist layer and the silicon layer are etched back simultaneously to remove the photoresist layer entirely.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: January 23, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Fu-Shou Tsai, Yu-Ting Li, Li-Chieh Hsu, Yi-Liang Liu, Kun-Ju Li, Po-Cheng Huang, Chien-Nan Lin
  • Patent number: 9871171
    Abstract: A light-emitting device comprises a light-emitting structure capable of emitting a light; an electrode formed on a side of the light-emitting structure; a transparent structure formed on a second side of the light-emitting structure, wherein the transparent structure is aligned to a region of the electrode, and comprises a first transparent layer and a second transparent layer around the first transparent layer; a contact structure formed on the second side of the light-emitting structure; and a reflective layer covering the transparent structure and the contact structure.
    Type: Grant
    Filed: November 7, 2014
    Date of Patent: January 16, 2018
    Assignee: EPISTAR CORPORATION
    Inventors: Jen-Li Hu, Tzu-Chieh Hsu
  • Patent number: 9843162
    Abstract: An assembly includes a carrier and a structure having a core formed on the carrier, wherein the core has a longitudinal extension having two end regions, a first end region is arranged facing the carrier and a second end region is arranged facing away from the carrier, the core is formed as electrically conductive at least in an outer region, the region is at least partially covered with an active zone layer, the active zone layer generates electromagnetic radiation, a mirror layer is provided at least in one end region of the core to reflect electromagnetic radiation in a direction, a first electrical contact layer contacts an electrically conductive region of the core, and a second contact layer contacts the active zone layer.
    Type: Grant
    Filed: June 3, 2014
    Date of Patent: December 12, 2017
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Jelena Ristic, Martin Straβburg, Alfred Lell, Uwe Strauβ
  • Patent number: 9773666
    Abstract: Described herein is a method for growing indium nitride (InN) materials by growing hexagonal and/or cubic InN using a pulsed growth method at a temperature lower than 300° C. Also described is a material comprising InN in a face-centered cubic lattice crystalline structure having an NaCl type phase.
    Type: Grant
    Filed: June 13, 2013
    Date of Patent: September 26, 2017
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Neeraj Nepal, Charles R. Eddy, Jr., Nadeemmullah A. Mahadik, Syed B Qadri, Michael J. Mehl
  • Patent number: 9722138
    Abstract: Embodiments of the invention are directed to a method of separating a wafer of light emitting devices. The method includes scribing a first groove on a dicing street on the wafer and checking the alignment of the wafer using a location of the first groove relative to a feature on the wafer. After checking the alignment, a second groove is scribed on the dicing street.
    Type: Grant
    Filed: October 21, 2014
    Date of Patent: August 1, 2017
    Assignee: Koninklijke Philips N.V.
    Inventors: Rao S. Peddada, Frank Lili Wei
  • Patent number: 9691942
    Abstract: The present invention relates to a single-crystalline aluminum nitride wherein a carbon concentration is 1×1014 atoms/cm3 or more and less than 3×1017 atoms/cm3, a chlorine concentration is 1×1014 to 1×1017 atoms/cm3, and an absorption coefficient at 265 nm wavelength is 40 cm?1 or less.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: June 27, 2017
    Assignees: National University Corporation Tokyo University of Agriculture and Technology, Tokuyama Corporation
    Inventors: Akinori Koukitu, Yoshinao Kumagai, Toru Nagashima, Yuki Hiraren
  • Patent number: 9685323
    Abstract: Embodiments of the present disclosure include a buffer structure suited for III-N device having a foreign substrate. The buffer structure can include a first buffer layer having a first aluminum composition and a second buffer layer formed on the first buffer layer, the second buffer layer having a second aluminum composition. The buffer structure further includes a third buffer layer formed on the second buffer layer at a second interface, the third buffer layer having a third aluminum composition. The first aluminum composition decreases in the first buffer layer towards the interface and the second aluminum composition throughout the second buffer layer is greater than the first aluminum composition at the interface.
    Type: Grant
    Filed: October 16, 2015
    Date of Patent: June 20, 2017
    Assignee: Transphorm Inc.
    Inventors: Stacia Keller, Brian L. Swenson, Nicholas Fichtenbaum
  • Patent number: 9653621
    Abstract: A semiconductor apparatus (10) includes: a layered structure (100) that includes double junction structures that have a first junction (151, 153) where a wide-bandgap layer (102, 104) and a narrow-bandgap layer (101, 103, 105) are layered on each other and a second junction (152, 154) where a narrow-bandgap layer (101, 103, 105) and a wide-bandgap layer (102, 104) are layered on each other, and electrode semiconductor layers (110, 120) are joined to each layer of the layered structure. Each double junction structure includes a pair of a first region (131, 133) that has negative fixed charge and a second region (132, 134) that has positive fixed charge. The first region is closer to the first junction than to a center of the wide-bandgap layer. The second region is closer to the second junction than to the center of the wide-bandgap layer. A 2DEG or a 2DHG is formed at each junction. The semiconductor apparatus functions as an electric energy storage device such as a capacitor.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: May 16, 2017
    Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, TOYOTA SCHOOL FOUNDATION
    Inventors: Tomoyoshi Kushida, Hiroyuki Sakaki, Masato Ohmori
  • Patent number: 9646842
    Abstract: Method for chemical mechanical planarization is provided, which includes: forming a dielectric layer containing at least one opening, the dielectric layer is located on a substrate; epitaxially growing a germanium material within the at least one opening of the dielectric layer, the germanium material extending above a topmost surface of the dielectric layer; and planarizing the germanium material using at least one slurry composition to form coplanar surfaces of the germanium material and the dielectric layer, where a slurry composition of at least one slurry composition polishes the germanium material selective to the topmost surface of the dielectric layer, and includes an abrasive, at least one pH modulator, and an oxidizer, the at least one pH modulator including an acidic pH modulator, and lacking a basic pH modulator.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: May 9, 2017
    Assignees: International Business Machines Corporation, JSR CORPORATION
    Inventors: Tatsuyoshi Kawamoto, Mahadevaiyer Krishnan, Yohei Oishi, Dinesh Kumar Penigalapati, Rachel S. Steiner, James A. Tornello, Tatsuya Yamanaka
  • Patent number: 9646841
    Abstract: A chemical mechanical planarization for a Group III arsenide material is provided in which at least one opening is formed within a dielectric layer located on a substrate. A Group III arsenide material is epitaxially grown within the at least one opening of the dielectric layer which extends above a topmost surface of the dielectric layer. The Group III arsenide material is planarized using at least one slurry composition to form coplanar surfaces of the Group III arsenide material and the dielectric layer, where a slurry composition of the at least one slurry composition polishes the Group III arsenide material selective to the topmost surface of the dielectric layer, and includes an abrasive, at least one pH modulator and an oxidizer, the at least one pH modulator including an acidic pH modulator, but lacks a basic pH modulator, and where the oxidizer suppresses generation of an arsine gas.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: May 9, 2017
    Assignees: International Business Machines Corporation, JSR Corporation
    Inventors: Henry A. Beveridge, Tatsuyoshi Kawamoto, Mahadevaiyer Krishnan, Yohei Oishi, Dinesh Kumar Penigalapati, Rachel S. Steiner, James A. Tornello, Tatsuya Yamanaka
  • Patent number: 9640726
    Abstract: A light emitting device includes a light emitting structure including a second conduction type semiconductor layer, an active layer, and a first conduction type semiconductor layer, a second electrode layer arranged under the light emitting structure, a first electrode layer having at least portion extending to contact the first conduction type semiconductor layer passing the second conduction type semiconductor layer and the active layer, and an insulating layer arranged between the second electrode layer and the first electrode layer, between the second conduction type semiconductor layer and the first electrode layer, and between the active layer and the first electrode layer, wherein said at least one portion of the first electrode layer contacting the first conduction type semiconductor layer has a roughness.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: May 2, 2017
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Sang Youl Lee, Ji Hyung Moon, June O Song, Kwang Ki Choi, Chung Song Kim, Hwan Hee Jeong
  • Patent number: 9559261
    Abstract: A nitride layer with embedded hole structure can be used for fabricating GaN-based LED of high external quantum efficiency through epitaxial growth. The approaches can have advantages such as reducing the complexity chip process for forming hole structure, reducing impacts from the chip process on chip reliability, effective reduction of hole structure size and increase of device stability, crush resistance, and reliability. A fabrication method of an underlayer structure with embedded micro-hole structure is also provided.
    Type: Grant
    Filed: June 14, 2015
    Date of Patent: January 31, 2017
    Assignee: XIAMEN SANAN OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Dongyan Zhang, Jie Zhang, Weihua Du, Xiaofeng Liu, Duxiang Wang
  • Patent number: 9548206
    Abstract: Embodiments of an ohmic contact structure for a Group III nitride semiconductor device and methods of fabrication thereof are disclosed. In general, the ohmic contact structure has a root-mean-squared (RMS) surface roughness of less than 10 nanometers, and more preferably less than or equal to 7.5 nanometers, and more preferably less than or equal to 5 nanometers, and more preferably less than or equal to 2 nanometers, and even more preferably less than or equal to 1.5 nanometers.
    Type: Grant
    Filed: July 14, 2011
    Date of Patent: January 17, 2017
    Assignee: Cree, Inc.
    Inventors: Helmut Hagleitner, Jason Gurganus
  • Patent number: 9548257
    Abstract: A semiconductor device structure includes a layer of III-V compound semiconductor material, a layer of polycrystalline CVD diamond material, and an interface region with a diamond nucleation layer. A Raman signal of the diamond nucleation layer exhibits an sp3 carbon peak at 1332 cm?1 having a full width half maximum of no more than 5.0 cm?1, and one or both of: (i) an sp2 carbon peak at 1550 cm?1 having a height which is no more than 20% of a height of the sp3 carbon peak at 1332 cm?1 after background subtraction when using a Raman excitation source at 633 nm; and (ii) the sp3 carbon peak at 1332 cm?1 is no less than 10% of local background intensity in a Raman spectrum using a Raman excitation source at 785 nm. An average nucleation density at a nucleation surface is no less than 1×108 cm?2 and no more than 1×1012 cm?2.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: January 17, 2017
    Assignee: RFHIC CORPORATION
    Inventor: Firooz Nasser-Faili
  • Patent number: 9543473
    Abstract: Provided is a self-supporting polycrystalline GaN substrate composed of GaN-based single crystal grains having a specific crystal orientation in a direction approximately normal to the substrate. The crystal orientations of individual GaN-based single crystal grains as determined from inverse pole figure mapping by EBSD analysis on the substrate surface are distributed with tilt angles from the specific crystal orientation, the average tilt angle being 1 to 10°. There is also provided a light emitting device including the self-supporting substrate and a light emitting functional layer, which has at least one layer composed of semiconductor single crystal grains, the at least one layer having a single crystal structure in the direction approximately normal to the substrate. The present invention makes it possible to provide a self-supporting polycrystalline GaN substrate having a reduced defect density at the substrate surface, and to provide a light emitting device having a high luminous efficiency.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: January 10, 2017
    Assignee: NGK Insulators, Ltd.
    Inventors: Morimichi Watanabe, Jun Yoshikawa, Yoshitaka Kuraoka, Tsutomu Nanataki
  • Patent number: 9536977
    Abstract: A tunneling field-effect transistor (TFET) device is disclosed. A frustoconical protrusion structure is disposed over a substrate and protruding out of the plane of substrate. A source region is disposed as a top portion of the frustoconical protrusion structure. A sidewall spacer is disposed along sidewall of the source region. A source contact with a critical dimension (CD), which is substantially larger than a width of the source region, is formed on the source region and the sidewall spacer together.
    Type: Grant
    Filed: January 18, 2013
    Date of Patent: January 3, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Harry-Hak-Lay Chuang, Cheng-Cheng Kuo, Chi-Wen Liu, Ming Zhu
  • Patent number: 9530846
    Abstract: A solution is formation of a nitride semiconductor layer on one principal plane of a single crystal substrate through a first layer. Upon selecting arbitrary three places in a radial direction from a cross section cleaved in a diameter portion and observing an interface between the first layer and the nitride semiconductor layer by taking a width of at least 500 nm in the radial direction, a value is within the range of 6 nm or more and 15 nm or less in a mean value of the three places with regard to a difference between a maximum height of a convex top portion and a minimum height of a concave bottom portion of the first layer in a thickness direction from the single crystal substrate toward the nitride semiconductor layer. A value is 10 nm or more and 25 nm or less in the mean value.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: December 27, 2016
    Assignee: CoorsTek KK
    Inventors: Noriko Omori, Hiroshi Oishi, Yoshihisa Abe, Jun Komiyama, Kenichi Eriguchi
  • Patent number: 9502241
    Abstract: Provided is a high-quality Group III nitride crystal of excellent processability. A Group III nitride crystal is produced by forming a film is composed of an oxide, hydroxide and/or oxyhydroxide containing a Group III element by heat-treating a Group III nitride single crystal at 1000° C. or above, and removing the film.
    Type: Grant
    Filed: October 15, 2013
    Date of Patent: November 22, 2016
    Assignee: MITSUSBISHI CHEMICAL CORPORATION
    Inventors: Hajime Matsumoto, Kunitada Suzaki, Kenji Fujito, Satoru Nagao
  • Patent number: 9502245
    Abstract: A method of forming a semiconductor in a long trench. The method may include; forming a first semiconductor on a substrate and in a long trench; forming a first spacer along sidewalls of the long trench and above the first semiconductor, a portion of the first semiconductor remains exposed; recessing the exposed portion of the first semiconductor; forming an insulator layer on the recessed portion of the first semiconductor; forming a second semiconductor on the insulator layer; forming a second spacer on sidewalls of the first spacer and above the second semiconductor, a portion of the second semiconductor remains exposed; removing the exposed portion of the second semiconductor; and removing a frond end and a back end of the first semiconductor and the second semiconductor, wherein the front end and back end are separated by a central region and the central region extends across the width of the long trench.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: November 22, 2016
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 9487885
    Abstract: A process for separating a substrate from an epitaxial layer comprises forming a multilayer substrate comprising a substrate, a lattice matching layer and an epitaxial layer. The method further comprises etching the lattice matching layer by one of a liquid or a vapor phase acid. The lattice matching layer is a metal alloy between the substrate and the epitaxial layer and serves as an etching release layer. The substrate can also be separated from an epitaxial layer by laser lift off process. The process comprises forming a multilayer substrate comprising a substrate, a lattice matching layer and an epitaxial layer, directing laser light at the lattice matching layer, maintaining the laser light on the lattice matching layer for a sufficient period of time so that it is absorbed by free electrons in the lattice matching layer to allow decomposition of the lattice matching layer.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: November 8, 2016
    Assignee: Tivra Corporation
    Inventors: Francisco Machuca, Indranil De
  • Patent number: 9444005
    Abstract: A light emitting diode structure is provided. The light emitting diode structure includes a substrate, a light emitting multi-layer structure, a first current blocking layer, a first current spreading layer, a second current blocking layer and a second current spreading layer. The light emitting multi-layer structure is formed on the substrate by way of stacking. The first current blocking layer is formed on part of the light emitting multi-layer structure. The first current spreading layer covers the first current blocking layer and the light emitting multi-layer structure. The second current blocking layer is formed on part of the first current spreading layer. An orthogonal projection of the second current blocking layer is disposed in an orthogonal projection of the first current blocking layer. The second current spreading layer covers the second current blocking layer and the first current spreading layer.
    Type: Grant
    Filed: August 3, 2015
    Date of Patent: September 13, 2016
    Assignee: LEXTAR ELECTRONICS CORPORATION
    Inventors: Bo-Yu Chen, Po-Hung Tsou, Tzu-Hung Chou
  • Patent number: 9401420
    Abstract: Semiconductor device including: silicon-based substrate; first buffer layer on silicon-based substrate and is formed of first layer containing Al composition and second layer containing less Al than the first layer, the first and second layers being alternately stacked; second buffer layer on the first buffer layer and is formed of third layer containing Al composition and fourth layer containing less Al than the third layer, the third and fourth layers being alternately stacked; and third buffer layer on the second buffer layer and is formed of fifth layer containing Al composition and sixth layer containing less Al than the fifth layer, the fifth and sixth layers being alternately stacked, wherein the second buffer layer contains more Al than the first and third buffer layers. Thus, the semiconductor device leakage can be suppressed while reducing stress which is applied to buffer layer and can improve flatness of active layer upper face.
    Type: Grant
    Filed: May 2, 2014
    Date of Patent: July 26, 2016
    Assignees: SHANKEN ELECTRIC CO., LTD., SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Hiroshi Shikauchi, Ken Sato, Hirokazu Goto, Masaru Shinomiya, Keitaro Tsuchiya, Kazunori Hagimoto
  • Patent number: 9373747
    Abstract: A method for producing an optoelectronic component is provided. A transfer layer, containing InxGa1-xN with 0<x<1, is grown onto a growth substrate. Subsequently, ions are implanted into the transfer layer to form a separation zone, a carrier substrate is applied, and the transfer layer is separated by way of heat treatment. A further transfer layer, containing InyGa1-yN with 0<y?1 and y>x, is grown onto the previously grown transfer layer, ions are implanted into the further transfer layer to form a separation zone, a further carrier substrate is applied, and the further transfer layer is separated by way of heat treatment. Subsequently, a semiconductor layer sequence, containing an active layer, is grown onto the surface of the further transfer layer facing away from the further carrier substrate.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: June 21, 2016
    Assignee: Osram Opto Semiconductors GmbH
    Inventors: Joachim Hertkorn, Tetsuya Taki, Karl Engl, Johannes Baur, Berthold Hahn, Volker Haerle, Ann-Kathrin Haerle, Jakob Johannes Haerle, Johanna Magdalena Haerle
  • Patent number: 9356213
    Abstract: A manufacturing method of a light-emitting diode device. The light-emitting diode device comprises: a substrate (1); an epitaxial layer at one side of the substrate (1) and comprising an N-type layer (2), a P-type layer (4), and an active layer (3) between the N-type layer (2) and the P-type layer (4); an N-type electrode (5); a P-type electrode (7); an adhesive layer (8); and a patterned substrate (9). The light-emitting diode device further comprises an insulating layer (6) between the N-type electrode (5) and the P-type electrode (7), the insulating layer (6) electrically insulating the N-type electrode (5) and the P-type electrode (7). In the manufacturing method thereof, light-emitting efficiency and luminous efficiency of the light-emitting diode device can be improved, wiring is easier as compared with conventional chips, and the manufacturing process can be optimized.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: May 31, 2016
    Assignee: WUXI CHINA RESOURCES HUAJING MICROELECTRONICS CO., LTD.
    Inventors: Lei Wang, Guoqi Li, Zhiyan Yu, Rongsheng Pu
  • Patent number: 9318314
    Abstract: A method of forming a freestanding semiconductor wafer includes providing a semiconductor substrate including a semiconductor layer having a back surface and an upper surface opposite the back surface, wherein the semiconductor layer comprises at least one permanent defect between the upper surface and back surface, removing a portion of the back surface of the semiconductor layer and the permanent defect from the semiconductor layer, and forming a portion of the upper surface after removing a portion of the back surface and the permanent defect.
    Type: Grant
    Filed: March 29, 2013
    Date of Patent: April 19, 2016
    Assignee: SAINT-GOBAIN CRISTAUX ET DECTECTEURS
    Inventors: Jean-Pierre Faurie, Bernard Beaumont
  • Patent number: 9312165
    Abstract: A group III nitride composite substrate includes a group III nitride film and a support substrate formed from a material different in chemical composition from the group III nitride film. The group III nitride film has a thickness of 10 ?m or more. A sheet resistance of a-group III-nitride-film-side main surface of the group III nitride composite substrate is 200 ?/sq or less. A method for manufacturing a group III nitride composite substrate includes the steps of bonding the group III nitride film and the support substrate to each other; and reducing the thickness of at least one of the group III nitride film and the support substrate bonded to each other. Accordingly, a group III nitride composite substrate of a low sheet resistance that is obtained with a high yield as well as a method for manufacturing the same are provided.
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: April 12, 2016
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Akihiro Hachigo, Keiji Ishibashi, Naoki Matsumoto
  • Patent number: 9257574
    Abstract: A diode includes a first semiconductor layer configured by a compound semiconductor containing impurities of a first conductivity type; a high dislocation density region; a second semiconductor layer which is laminated on the first semiconductor layer, which is lower in a concentration of impurities in a region of a side of an interface with the first semiconductor layer than that of the first semiconductor layer, and which has an opening in which a portion which corresponds to the high dislocation density region is removed; an insulating film pattern which is provided to cover an inner wall of the opening; an electrode which is provided so as to cover the insulating film pattern and to contact the second semiconductor layer; and an opposing electrode which is provided to interpose the first semiconductor layer, the second semiconductor layer and the insulating film pattern between the electrode and the opposing electrode.
    Type: Grant
    Filed: August 21, 2013
    Date of Patent: February 9, 2016
    Assignee: SONY CORPORATION
    Inventors: Shigeru Kanematsu, Masashi Yanagita
  • Patent number: 9234299
    Abstract: A method for producing a group III nitride single crystal (ingot) includes providing a seed crystal comprising a first crystal face that is perpendicular to a growth direction of the single crystal and has a first predetermined area, and a second crystal face that is inclined to the growth direction and has a second predetermined area and growing the group III nitride single crystal on the first crystal face and the second crystal face by controlling a growth condition of the single crystal so as not to change the first predetermined area and the second predetermined area. A method for producing a group III nitride single crystal substrate includes further cutting the group III nitride single crystal substrate off from the grown group III nitride single crystal (ingot).
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: January 12, 2016
    Assignee: SCIOCS COMPANY LIMITED
    Inventor: Takehiro Yoshida
  • Patent number: 9136107
    Abstract: A method for manufacturing a semiconductor device includes forming an electron transit layer on a semiconductor substrate, forming an electron supply layer on the electron transit layer, forming a cap layer on the electron supply layer, forming a protection layer on the cap layer, the protection layer having an opening part, through which a part of the cap layer is exposed, and forming an oxidation film on an exposed surface of the cap layer by a wet process.
    Type: Grant
    Filed: December 6, 2013
    Date of Patent: September 15, 2015
    Assignee: Transphorm Japan, Inc.
    Inventors: Yoshiyuki Katani, Shinichi Akiyama
  • Patent number: 9130120
    Abstract: A substrate comprises a Group III-V material having an upper surface and a buffer layer having a thickness of not greater than about 1.3 ?m and overlying the upper surface of the substrate. A plurality of optoelectronic devices formed on the substrate having a normalized light emission wavelength standard deviation of not greater than about 0.0641 nm/cm2 at a wavelength within a range of between about 400 nm to about 550 nm.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: September 8, 2015
    Assignee: Saint-Gobain Cristaux Et Detecteurs
    Inventors: Jean-Pierre Faurie, Bernard Beaumont
  • Patent number: 9105755
    Abstract: There is provided a nitride semiconductor epitaxial substrate having a group III nitride semiconductor layer with C-plane as a surface, grown on a substrate via a buffer layer of the group III nitride semiconductor containing Al, wherein the buffer layer has an inversion domain on the surface.
    Type: Grant
    Filed: June 15, 2012
    Date of Patent: August 11, 2015
    Assignee: HITACHI METALS, LTD.
    Inventors: Hajime Fujikura, Taichiroo Konno, Michiko Matsuda
  • Patent number: 9064685
    Abstract: A method of forming a semiconductive substrate material for an electronic device including forming a plurality of semiconductive layers on a substrate during a continuous growth process in a reaction chamber, wherein during the continuous growth process, a release layer is formed between a base layer and an epitaxial layer by altering at least one growth process parameter during the continuous growth process. The method also including separating the plurality of semiconductive layers from the substrate.
    Type: Grant
    Filed: November 21, 2014
    Date of Patent: June 23, 2015
    Assignee: Saint-Gobain Cristaux Et Detecteurs
    Inventors: Jean-Pierre Faurie, Bernard Beaumont
  • Publication number: 20150137318
    Abstract: A semiconductor wafer is provided. The semiconductor wafer comprises a sacrificial layer, a first semiconductor crystal layer, and a second semiconductor crystal layer above a semiconductor crystal layer forming wafer, wherein the semiconductor crystal layer forming wafer, the sacrificial layer, the first semiconductor crystal layer and the second semiconductor crystal layer are arranged in the order of the semiconductor crystal layer forming wafer, the sacrificial layer, the first semiconductor crystal layer and the second semiconductor crystal layer, a first atom of one type selected from a plurality of types of atoms constituting the semiconductor crystal layer forming wafer or the sacrificial layer is contained in the first semiconductor crystal layer and the second semiconductor crystal layer as an impurity, and the concentration of the first atom in the second semiconductor crystal layer is lower than the concentration of the first atom in the first semiconductor crystal layer.
    Type: Application
    Filed: December 12, 2014
    Publication date: May 21, 2015
    Applicants: SUMITOMO CHEMICAL COMPANY, LIMITED, NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Takenori OSADA, Tomoyuki TAKADA, Masahiko HATA, Tetsuji YASUDA, Tatsuro MAEDA, Taro ITATANI
  • Publication number: 20150137317
    Abstract: A semiconductor wafer is provided. The semiconductor wafer comprises a sacrificial layer and a semiconductor crystal layer above a semiconductor crystal layer forming wafer, the semiconductor crystal layer forming wafer, the sacrificial layer and the semiconductor crystal layer being arranged in the order of the semiconductor crystal layer forming wafer, the sacrificial layer and the semiconductor crystal layer, wherein the semiconductor wafer comprises a diffusion inhibiting layer that inhibits diffusion of a first atom of one type selected from a plurality of types of atoms constituting the semiconductor crystal layer forming wafer or the sacrificial layer, at any cross-sectional position between (a) the interface of the semiconductor crystal layer forming wafer that faces the sacrificial layer and (b) a middle of the semiconductor crystal layer.
    Type: Application
    Filed: December 12, 2014
    Publication date: May 21, 2015
    Applicants: SUMITOMO CHEMICAL COMPANY, LIMITED, NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Takenori OSADA, Tomoyuki TAKADA, Masahiko HATA, Tetsuji YASUDA, Tatsuro MAEDA, Taro ITATANI
  • Publication number: 20150137319
    Abstract: In a semiconductor device 100, it is possible to prevent C from piling up at a boundary face between an epitaxial layer 22 and a group III nitride semiconductor substrate 10 by the presence of 30×1010 pieces/cm2 to 2000×1010 pieces/cm2 of sulfide in terms of S and 2 at % to 20 at % of oxide in terms of O in a surface layer 12. By thus preventing C from piling up, a high-resistivity layer is prevented from being formed on the boundary face between the epitaxial layer 22 and the group III nitride semiconductor substrate 10. Accordingly, it is possible to reduce electrical resistance at the boundary face between the epitaxial layer 22 and the group III nitride semiconductor substrate 10, and improve the crystal quality of the epitaxial layer 22. Consequently, it is possible to improve the emission intensity and yield of the semiconductor device 100.
    Type: Application
    Filed: December 22, 2014
    Publication date: May 21, 2015
    Inventor: Keiji ISHIBASHI
  • Patent number: 9035429
    Abstract: There is provided a method of processing a surface of a group III nitride crystal, that includes the steps of: polishing a surface of a group III nitride crystal with a polishing slurry containing abrasive grains; and thereafter polishing the surface of the group III nitride crystal with a polishing liquid at least once, and each step of polishing with the polishing liquid employs a basic polishing liquid or an acidic polishing liquid as the polishing liquid. The step of polishing with the basic or acidic polishing liquid allows removal of impurity such as abrasive grains remaining on the surface of the group III nitride crystal after it is polished with the slurry containing the abrasive grains.
    Type: Grant
    Filed: November 19, 2012
    Date of Patent: May 19, 2015
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Takayuki Nishiura, Keiji Ishibashi
  • Patent number: 9035318
    Abstract: A semiconductor device includes a GaN FET with an overvoltage clamping component electrically coupled to a drain node of the GaN FET and coupled in series to a voltage dropping component. The voltage dropping component is electrically coupled to a terminal which provides an off-state bias for the GaN FET. The overvoltage clamping component conducts insignificant current when a voltage at the drain node of the GaN FET is less than the breakdown voltage of the GaN FET and conducts significant current when the voltage rises above a safe voltage limit. The voltage dropping component is configured to provide a voltage drop which increases as current from the overvoltage clamping component increases. The semiconductor device is configured to turn on the GaN FET when the voltage drop across the voltage dropping component reaches a threshold value.
    Type: Grant
    Filed: May 3, 2013
    Date of Patent: May 19, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sameer Pendharkar, Naveen Tipirneni
  • Patent number: 9018736
    Abstract: A semiconductor device includes a substrate having a hexagonal crystalline structure and a (0001) surface, and conductive films on the surface of the substrate. The conductive films include a first conductive film and a second conductive film located above the first conductive film with respect to the surface, wherein the first conductive film has a crystalline structure which does not have a plane that has a symmetry equivalent to the symmetry of atomic arrangement in the surface of the substrate, the second conductive film has a crystalline structure having at least one plane that has a symmetry equivalent to the symmetry of atomic arrangement in the surface of the substrate, and the second conductive film is polycrystalline and has a grain size no larger than 15 ?m.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: April 28, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kazuhiro Maeda, Toshihiko Shiga