Abstract: Embodiments of the present disclosure describe a white light illumination system using InGaN-based orange nanowires (NWs) LED, in conjunction with a blue LD for high speed optical wireless communications. By changing the relative intensities of an ultrabroad linewidth orange LED and narrow-linewidth blue LD components, a hybrid LED/LD device achieves correlated color temperature (CCT) ranging from 3000 K to above 6000 K with color rendering index (CRI) values reaching 83.1. Orange-emitting NWs LED are utilized as an active-phosphor, while a blue LD was used for both color mixing and optical wireless communications.

Abstract: Techniques related to forming low defect density III-N films, device structures, and systems incorporating such films are discussed. Such techniques include epitaxially growing a first crystalline III-N structure within an opening of a first dielectric layer and extending onto the first dielectric layer, forming a second dielectric layer over the first dielectric layer and laterally adjacent to a portion of the first structure, and epitaxially growing a second crystalline III-N structure extending laterally onto a region of the second dielectric layer.

Abstract: A crystalline oxide semiconductor film with an enhanced electrical property is provided. By use of a mist CVD apparatus, a crystalline oxide semiconductor film with a corundum structure and a principal plane that is an a-plane or an m-plane was obtained on a crystalline substrate by atomizing a raw-material solution containing a dopant that is an n-type dopant to obtain atomized droplets, carrying the atomized droplets by carrier gas onto the crystalline substrate that is an a-plane corundum-structured crystalline substrate or an m-plane corundum-structured crystalline substrate placed in a film-formation chamber, and the atomized droplets were thermally reacted to form the crystalline oxide semiconductor film on the crystalline substrate.

Abstract: Embodiments of wafer bonding method and structures thereof are disclosed. The wafer bonding method can include performing a plasma activation treatment on a front surface of a first and a front surface of a second wafer; performing a silica sol treatment on the front surfaces of the first and the second wafers; performing a preliminary bonding process of the first and second wafer; and performing a heat treatment of the first and the second wafers to bond the front surface of the first wafer to the front surface of the second wafers.

Abstract: The embodiment of the present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate. The semiconductor structure also includes a first buffer layer disposed on the substrate. The semiconductor structure further includes a second buffer layer disposed on the first buffer layer. The semiconductor structure includes a semiconductor-based layer disposed on the second buffer layer. The second buffer layer includes aluminum, and the aluminum content of the second buffer layer gradually increases in the direction away from the substrate.

Abstract: The invention concerns a heterojunction field-effect transistor comprising a stack of first and second III-N type semiconducting layers forming an electron gas or hole layer; a first conduction electrode in electrical contact with the gas layer and a second conduction electrode; a separation layer positioned vertically in line with the first electrode and under the second semiconducting layer; a third semiconducting layer arranged under the separation layer and in electrical contact with the second electrode; a conductive element in electrical contact with the gas layer and electrically connecting the third semiconducting layer and the gas layer; and a control gate positioned between the conductive element and the first conduction electrode.

Abstract: A method for fabricating a semiconductor device includes providing a semiconductor substrate and bonding the semiconductor substrate to a carrier. The semiconductor substrate includes an inert material layer and a semiconductor layer on the inert material layer. The semiconductor substrate is bonded to the carrier such that the inert material layer is between the carrier and the semiconductor substrate. By including an inert material layer between the carrier and the semiconductor substrate, a barrier against diffusion for any bonding agents used to bond the semiconductor substrate to the carrier is formed, thereby preserving the integrity of the semiconductor layer and allowing for the easy removal of the semiconductor substrate from the carrier.

Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a third electrode, a first nitride region, a second nitride region, and a first insulating film. The first nitride region includes Alx1Ga1-x1N. The first nitride region includes first and second partial regions, a third partial region between the first and second partial regions, a fourth partial region between the first and third partial regions, and a fifth partial region between the third and second partial regions. The second nitride region includes Alx2Ga1-x2N. The second nitride region includes sixth and seventh partial regions. The first insulating film includes a first insulating region and is between the third partial region and the third electrode. The third partial region has a first surface opposing the first insulating region. The fourth partial region has a second surface opposing the sixth partial region.

Abstract: A method for manufacturing a group III nitride semiconductor substrate includes a sapphire substrate preparation step S10 for preparing a sapphire substrate having, as a main surface, a {10-10} plane or a plane obtained by inclining the {10-10} plane at a predetermined angle in a predetermined direction; a heat treatment step S20 for performing a heat treatment over the sapphire substrate while performing a nitriding treatment or without performing the nitriding treatment; a buffer layer forming step S30 for forming a buffer layer over the main surface of the sapphire substrate after the heat treatment; and a growth step S40 for forming a group III nitride semiconductor layer, in which a growth surface has a predetermined plane orientation, over the buffer layer, in which at least one of a plane orientation of the main surface of the sapphire substrate, presence or absence of the nitriding treatment during the heat treatment, and a growth temperature in the buffer layer forming step is adjusted such that the

Abstract: A semiconductor device includes a first epitaxial layer, a second epitaxial layer disposed below the first epitaxial layer, a conductive layer disposed below and directly contacting the second epitaxial layer, and a plurality of spacers disposed between the second epitaxial layer and the conductive layer. The conductive layer includes a metal. The plurality of spacers include a bulk semiconductor material.

Abstract: The present invention provides a novel method for producing a GaN crystal, the method including growing GaN from vapor phase on a semi-polar or non-polar GaN surface using GaCl3 and NH3 as raw materials. Provided herein is an invention of a method for producing a GaN crystal, including the steps of: (i) preparing a GaN seed crystal having a non-polar or semi-polar surface whose normal direction forms an angle of 85° or more and less than 170° with a [0001] direction of the GaN seed crystal; and (ii) growing GaN from vapor phase on a surface including the non-polar or semi-polar surface of the GaN seed crystal using GaCl3 and NH3 as raw materials.

Abstract: A method for fabricating heteroepitaxial semiconductor material on a mica sheet is disclosed. Firstly, a mica substrate is provided. Then, at least one semiconductor film is deposited on the mica substrate to form a flexible substrate whose flexibility is applied to various applications, such as wearable devices, portable photoelectric equipment, or improving the speed and bandwidth of commercial and military systems, such that the flexible substrate has the competitiveness in the market.

Abstract: A component includes a carrier; and a semiconductor body arranged on the carrier, wherein the semiconductor body includes a semiconductor layer facing away from the carrier, a further semiconductor layer facing the carrier and an optically active layer located therebetween, the carrier has a metallic carrier layer that is contiguous and mechanically stabilizes the component, the carrier includes a mirror layer disposed between the semiconductor body and the carrier layer, and the carrier has a compensating layer directly adjacent to the carrier layer and configured to compensate for internal mechanical strains in the component.

Abstract: A conductive C-plane GaN substrate has a resistivity of 2×10?2 ?·cm or less or an n-type carrier concentration of 1×1018 cm?3 or more at room temperature. At least one virtual line segment with a length of 40 mm can be drawn at least on one main surface of the substrate. The line segment satisfies at least one of the following conditions (A1) and (B1): (A1) when an XRC of (004) reflection is measured at 1 mm intervals on the line segment, a maximum value of XRC-FWHMs across all measurement points is less than 30 arcsec; and (B1) when an XRC of the (004) reflection is measured at 1 mm intervals on the line segment, a difference between maximum and minimum values of XRC peak angles across all the measurement points is less than 0.2°.

Abstract: A conductive C-plane GaN substrate has a resistivity of 2×10?2 ?·cm or less or an n-type carrier concentration of 1×1018 cm?3 or more at room temperature. At least one virtual line segment with a length of 40 mm can be drawn at least on one main surface of the substrate. The line segment satisfies at least one of the following conditions (A1) and (B1): (A1) when an XRC of (004) reflection is measured at 1 mm intervals on the line segment, a maximum value of XRC-FWHMs across all measurement points is less than 30 arcsec; and (B1) when an XRC of the (004) reflection is measured at 1 mm intervals on the line segment, a difference between maximum and minimum values of XRC peak angles across all the measurement points is less than 0.2°.

Abstract: A compound semiconductor field effect transistor may include a channel layer. The compound semiconductor transistor may also include a multi-layer epitaxial barrier layer on the channel layer. The channel layer may be on a doped buffer layer or on a first un-doped buffer layer. The compound semiconductor field effect transistor may further include a gate. The gate may be on a first tier of the multi-layer epitaxial barrier layer, and through a space between portions of a second tier of the multi-layer epitaxial barrier layer.

Abstract: Provided is a semiconductor device including a substrate in which an insulation layer is disposed between a first semiconductor layer and a second semiconductor layer, a through-hole penetrating through the substrate, the through-hole having a first hole penetrating through the first semiconductor layer and a second hole penetrating through the insulation layer and the second semiconductor layer from a bottom surface of the first hole, an epi-layer disposed inside the through-hole, a drain electrode disposed inside the second hole and contacting one surface of the epi-layer, and a source electrode and a gate electrode which are disposed on the other surface of the epi-layer.

Abstract: The present invention relates to a III-N single crystal adhering to a substrate, wherein III denotes at least one element of the third main group of the periodic table of the elements, selected from the group of Al, Ga and In, wherein the III-N single crystal exhibits, within a temperature range of an epitaxial crystal growth, a value (i) of deformation ?XX in the range of <0. Additionally or alternatively, the III-N single crystal exhibits at room temperature a value (ii) of deformation ?XX in the range of <0.

Abstract: A semiconductor light-emitting device comprises an epitaxial structure comprising an main light-extraction surface, a lower surface opposite to the main light-extraction surface, a side surface connecting the main light-extraction surface and the lower surface, a first portion and a second portion between the main light-extraction surface and the first portion, wherein a concentration of a doping material in the second portion is higher than that of the doping material in the first portion and, in a cross-sectional view, the second portion comprises a first width near the main light-extraction surface and second width near the lower surface, and the first width is smaller than the second width.

Abstract: A method of fabricating an epitaxial stack for Group IIIA-N transistors includes depositing at least one Group IIIA-N buffer layer on a substrate in a deposition chamber of a deposition system. At least one Group IIIA-N cap layer is then deposited on the first Group IIIA-N buffer layer. During a cool down from the deposition temperature for the cap layer deposition the gas mixture supplied to the deposition chamber includes NH3 and at least one other gas, wherein the gas mixture provide an ambient in the deposition chamber that is non-etching with respect to the cap layer so that at a surface of the cap layer there is (i) a root mean square (rms) roughness of <10 ? and (ii) a pit density for pits greater than (>) 2 nm deep less than (<) 10 pits per square ?m with an average pit diameter less than (<) 0.05 ?m.

Abstract: Circuit-Under-Pad (CUP) device topologies for high current lateral GaN power transistors comprise first and second levels of on-chip metallization M1 and M2; M1 defines source, drain and gate finger electrodes of a plurality of sections of a multi-section transistor and a gate bus; M2 defines an overlying contact structure comprising a drain pad and source pads extending over active regions of each section. The drain and source pads of M2 are interconnected by conductive micro-vias to respective underlying drain and source finger electrodes of M1. The pad structure and the micro-via interconnections are configured to reduce current density in self-supported widths of source and drain finger electrodes, i.e. to optimize a maximum current density for each section. For reduced gate loop inductance, part of each source pad is routed over the gate bus. Proposed CUP device structures provide for higher current carrying capability and reduced drain-source resistance.

Abstract: A semiconductor structure includes a first GAA transistor and a second GAA transistor. The first GAA transistor includes: a first diffusion region, a second diffusion region, and a first nanowire. The second GAA transistor includes: a third diffusion region, a fourth diffusion region, and a second nanowire. The first diffusion region, the second diffusion region, and the first nanowire are symmetrical with the third diffusion region, the fourth diffusion region, and the second nanowire respectively, the first GAA transistor is arranged to provide a first current to flow through the first nanowire, and the second GAA transistor is arranged to provide a second current to flow through the second nanowire.

Abstract: This invention relates to methods of generating NP gallium nitride (GaN) across large areas (>1 cm2) with controlled pore diameters, pore density, and porosity. Also disclosed are methods of generating novel optoelectronic devices based on porous GaN. Additionally a layer transfer scheme to separate and create free-standing crystalline GaN thin layers is disclosed that enables a new device manufacturing paradigm involving substrate recycling. Other disclosed embodiments of this invention relate to fabrication of GaN based nanocrystals and the use of NP GaN electrodes for electrolysis, water splitting, or photosynthetic process applications.

Abstract: A semiconductor disk of a first crystalline material, which has a first lattice system, is bonded on a process surface of a base substrate, wherein a bonding layer is formed between the semiconductor disk and the base substrate. A second semiconductor layer of a second crystalline material with a second, different lattice system is formed by epitaxy on a first semiconductor layer formed from the semiconductor disk.

Abstract: Crystalline heterostructures including an elevated fin structure extending from a sub-fin structure over a substrate. Devices, such as III-V transistors, may be formed on the raised fin structures while silicon-based devices (e.g., transistors) may be formed in other regions of the silicon substrate. A sub-fin isolation material localized to a transistor channel region of the fin structure may reduce source-to-drain leakage through the sub-fin, improving electrical isolation between source and drain ends of the fin structure. Subsequent to heteroepitaxially forming the fin structure, a portion of the sub-fin may be laterally etched to undercut the fin. The undercut is backfilled with sub-fin isolation material. A gate stack is formed over the fin. Formation of the sub-fin isolation material may be integrated into a self-aligned gate stack replacement process.

Abstract: Disclosed is a method of chemically-mechanically polishing a substrate. The method comprises, consists of, or consists essentially of (a) contacting a substrate containing at least one Group III-V material, with a polishing pad and a chemical-mechanical polishing composition comprising water, abrasive particles having a negative surface charge, and an oxidizing agent for oxidizing the Group III-V material in an amount of from about 0.01 wt. % to about 5 wt. %, wherein the polishing composition has a pH of from about 2 to about 5; (b) moving the polishing pad and the chemical-mechanical polishing composition relative to the substrate; and (c) abrading at least a portion of the substrate to polish the substrate. In some embodiments, the Group III-V material is a semiconductor that includes at least one element from Group III of the Periodic Table and at least one element from Group V of the Periodic Table.

Abstract: Disclosed is a substrate structure and a method for forming the same, in which a high-quality nitride semiconductor layer may be formed with a reduced stress applied to the nitride semiconductor layer at the growth of the nitride semiconductor layer and also be easily separated from the substrate, and a semiconductor lamination structure using the same and a method for forming the same, and a method for manufacturing a nitride semiconductor using the same. The substrate structure includes a single-crystal substrate heterogeneous from a nitride semiconductor, and a crystallized inorganic thin film having a leg portion configured to contact the substrate to define an integrated cavity between the leg portion and the substrate and an upper surface extending from the leg portion and parallel to the substrate, the crystallized inorganic thin film having the same crystal structure as the substrate.

Abstract: A ceramic substrate is formed of a polycrystalline ceramic and has a supporting main surface. The supporting main surface has a roughness of 0.01 nm or more and 3.0 nm or less in terms of Sa. The number of projections and depressions with a height of 1 nm or more in a square region with 50 ?m sides on the supporting main surface is less than 5 on average, and the number of projections and depressions with a height of 2 nm or more in the square region is less than 1 on average.

Abstract: A wafer has a front face that is partitioned by a plurality of streets crossing with each other into a plurality of regions in each of which a device is formed. A surface protective tape is adhered to the front face of the wafer. Then a laser beam having a wavelength transparent to the wafer is irradiated along the streets from a rear face side of the wafer to form a modified layer inside the wafer. Then the wafer is ground from the rear face side to thin the wafer. When the surface protective tape is applied, the surface protective tape is heated. When the modified layer is formed, cracks extend from the modified layer to the front face of the wafer. When ground, the wafer is divided into individual chips with the cracks serving as boundaries.

Abstract: A composition of matter comprising a plurality of nanowires on a substrate, said nanowires having been grown epitaxially on said substrate in the presence of a metal catalyst such that a catalyst deposit is located at the top of at least some of said nanowires, wherein said nanowires comprise at least one group III-V compound or at least one group II-VI compound or comprises at least one non carbon group IV element; and wherein a graphitic layer is in contact with at least some of the catalyst deposits on top of said nanowires.

Abstract: Large area, high current, lateral GaN power transistors are implemented using an on-chip interconnect topology wherein the transistor is arranged as an array of sections, each section comprising a set of transistor islands; gate and source buses that form each gate drive loop have substantially the same track widths; the source bus runs over or under the gate bus, and the tracks are inductively coupled to provide flux cancellation in the gate drive loop, thereby reducing parasitic inductances. The gate delay in each gate drive loop is reduced, minimizing the gate drive phase difference across the transistor. An overlying current redistribution layer preferably has a track width no greater than that of the underlying source and drain buses, for efficient coupling. This topology provides improved scalability, enabling fabrication of multi-section, large scale, high current lateral GaN transistors with reduced gate drive loop inductance, for improved operational stability.

Abstract: A wafer is produced from a compound single crystal ingot having end surface. A separation plane is formed by setting the focal point of a laser beam inside the ingot at a predetermined depth from the end surface. The depth corresponds to the thickness of the wafer to be produced. The laser beam is applied to the end surface to form a modified layer parallel to the end surface and cracks extending from the modified layer, thus forming the separation plane. The ingot has first atoms having a larger atomic weight and second atoms having a smaller atomic weight, and the end surface of the ingot is set as a polar plane where the second atoms are arranged in forming the separation plane. After producing the wafer from the ingot, the first end surface is ground to be flattened.

Abstract: Methods and structures for forming flat, continuous, planar, epitaxial layers of semipolar III-nitride materials on patterned sapphire substrates are described. Semipolar GaN may be grown from inclined c-plane facets on a patterned sapphire substrate, and coalesced to form a continuous layer of semipolar III-nitride semiconductor over the sapphire substrate. Planarization of the layer is followed by crystal regrowth using a nitrogen carrier gas to produce a flat, microfabrication-grade, process surface of semipolar III-nitride semiconductor across the substrate. Quality multiple quantum wells can be fabricated in the regrown semipolar material.

Abstract: There are disclosed herein various implementations of a semiconductor component including a protrusion propagation body. The semiconductor component includes a substrate, a III-Nitride intermediate stack including the protrusion propagation body situated over the substrate, a III-Nitride buffer layer situated over the group III-V intermediate stack, and a III-Nitride device fabricated over the group III-V buffer layer. The protrusion propagation body includes at least a protrusion generating layer and two or more protrusion spreading multilayers.

Abstract: A crystal substrate is composed of a crystal of a nitride of a group 13 element and has a first main face and a second main face. The crystal substrate includes a low carrier concentration region and a high carrier concentration region both extending between the first main face and second main face. The low carrier concentration region has a carrier concentration of 1018/cm3 or lower and a defect density of 107/cm2 or lower. The high carrier concentration region has a carrier concentration of 1019/cm3 or higher and a defect density of 108/cm2 or higher.

Abstract: For a Periodic Table Group 13 metal nitride semiconductor crystal obtained by epitaxial growth on the main surface of a base substrate that has a nonpolar plane and/or a semipolar plane as its main surface, an object of the present invention is to provide a high-quality semiconductor crystal that has a low absorption coefficient, is favorable for a device, and is controlled dopant concentration in the crystal, and to provide a production method that can produce the semiconductor crystal. A high-quality Periodic Table Group 13 metal nitride semiconductor crystal that has a precisely controlled dopant concentration within the crystal and a low absorption coefficient and that is thus favorable for a device, can be provided by inhibiting oxygen doping caused by impurity oxygen and having the Si concentration higher than the O concentration.

Abstract: Method for chemical mechanical planarization is provided, which includes: forming a dielectric layer containing at least one opening, the dielectric layer is located on a substrate; epitaxially growing a germanium material within the at least one opening of the dielectric layer, the germanium material extending above a topmost surface of the dielectric layer; and planarizing the germanium material using at least one slurry composition to form coplanar surfaces of the germanium material and the dielectric layer, where a slurry composition of at least one slurry composition polishes the germanium material selective to the topmost surface of the dielectric layer, and includes an abrasive, at least one pH modulator, and an oxidizer, the at least one pH modulator including an acidic pH modulator, and lacking a basic pH modulator.

Abstract: A method for planarizing a silicon layer includes providing a silicon layer having at least one recess therein. Next, a photoresist layer is formed to cover the silicon layer and fill up the recess. Then, the photoresist layer is hardened. After that, part of the photoresist layer is removed by taking a top surface of the silicon layer as a stop layer. Finally the photoresist layer and the silicon layer are etched back simultaneously to remove the photoresist layer entirely.

Abstract: A light-emitting device comprises a light-emitting structure capable of emitting a light; an electrode formed on a side of the light-emitting structure; a transparent structure formed on a second side of the light-emitting structure, wherein the transparent structure is aligned to a region of the electrode, and comprises a first transparent layer and a second transparent layer around the first transparent layer; a contact structure formed on the second side of the light-emitting structure; and a reflective layer covering the transparent structure and the contact structure.

Abstract: An assembly includes a carrier and a structure having a core formed on the carrier, wherein the core has a longitudinal extension having two end regions, a first end region is arranged facing the carrier and a second end region is arranged facing away from the carrier, the core is formed as electrically conductive at least in an outer region, the region is at least partially covered with an active zone layer, the active zone layer generates electromagnetic radiation, a mirror layer is provided at least in one end region of the core to reflect electromagnetic radiation in a direction, a first electrical contact layer contacts an electrically conductive region of the core, and a second contact layer contacts the active zone layer.

Abstract: Described herein is a method for growing indium nitride (InN) materials by growing hexagonal and/or cubic InN using a pulsed growth method at a temperature lower than 300° C. Also described is a material comprising InN in a face-centered cubic lattice crystalline structure having an NaCl type phase.

Abstract: Embodiments of the invention are directed to a method of separating a wafer of light emitting devices. The method includes scribing a first groove on a dicing street on the wafer and checking the alignment of the wafer using a location of the first groove relative to a feature on the wafer. After checking the alignment, a second groove is scribed on the dicing street.

Abstract: The present invention relates to a single-crystalline aluminum nitride wherein a carbon concentration is 1×1014 atoms/cm3 or more and less than 3×1017 atoms/cm3, a chlorine concentration is 1×1014 to 1×1017 atoms/cm3, and an absorption coefficient at 265 nm wavelength is 40 cm?1 or less.

Abstract: Embodiments of the present disclosure include a buffer structure suited for III-N device having a foreign substrate. The buffer structure can include a first buffer layer having a first aluminum composition and a second buffer layer formed on the first buffer layer, the second buffer layer having a second aluminum composition. The buffer structure further includes a third buffer layer formed on the second buffer layer at a second interface, the third buffer layer having a third aluminum composition. The first aluminum composition decreases in the first buffer layer towards the interface and the second aluminum composition throughout the second buffer layer is greater than the first aluminum composition at the interface.

Abstract: A semiconductor apparatus (10) includes: a layered structure (100) that includes double junction structures that have a first junction (151, 153) where a wide-bandgap layer (102, 104) and a narrow-bandgap layer (101, 103, 105) are layered on each other and a second junction (152, 154) where a narrow-bandgap layer (101, 103, 105) and a wide-bandgap layer (102, 104) are layered on each other, and electrode semiconductor layers (110, 120) are joined to each layer of the layered structure. Each double junction structure includes a pair of a first region (131, 133) that has negative fixed charge and a second region (132, 134) that has positive fixed charge. The first region is closer to the first junction than to a center of the wide-bandgap layer. The second region is closer to the second junction than to the center of the wide-bandgap layer. A 2DEG or a 2DHG is formed at each junction. The semiconductor apparatus functions as an electric energy storage device such as a capacitor.

Abstract: Method for chemical mechanical planarization is provided, which includes: forming a dielectric layer containing at least one opening, the dielectric layer is located on a substrate; epitaxially growing a germanium material within the at least one opening of the dielectric layer, the germanium material extending above a topmost surface of the dielectric layer; and planarizing the germanium material using at least one slurry composition to form coplanar surfaces of the germanium material and the dielectric layer, where a slurry composition of at least one slurry composition polishes the germanium material selective to the topmost surface of the dielectric layer, and includes an abrasive, at least one pH modulator, and an oxidizer, the at least one pH modulator including an acidic pH modulator, and lacking a basic pH modulator.

Abstract: A chemical mechanical planarization for a Group III arsenide material is provided in which at least one opening is formed within a dielectric layer located on a substrate. A Group III arsenide material is epitaxially grown within the at least one opening of the dielectric layer which extends above a topmost surface of the dielectric layer. The Group III arsenide material is planarized using at least one slurry composition to form coplanar surfaces of the Group III arsenide material and the dielectric layer, where a slurry composition of the at least one slurry composition polishes the Group III arsenide material selective to the topmost surface of the dielectric layer, and includes an abrasive, at least one pH modulator and an oxidizer, the at least one pH modulator including an acidic pH modulator, but lacks a basic pH modulator, and where the oxidizer suppresses generation of an arsine gas.

Abstract: A light emitting device includes a light emitting structure including a second conduction type semiconductor layer, an active layer, and a first conduction type semiconductor layer, a second electrode layer arranged under the light emitting structure, a first electrode layer having at least portion extending to contact the first conduction type semiconductor layer passing the second conduction type semiconductor layer and the active layer, and an insulating layer arranged between the second electrode layer and the first electrode layer, between the second conduction type semiconductor layer and the first electrode layer, and between the active layer and the first electrode layer, wherein said at least one portion of the first electrode layer contacting the first conduction type semiconductor layer has a roughness.

Abstract: A nitride layer with embedded hole structure can be used for fabricating GaN-based LED of high external quantum efficiency through epitaxial growth. The approaches can have advantages such as reducing the complexity chip process for forming hole structure, reducing impacts from the chip process on chip reliability, effective reduction of hole structure size and increase of device stability, crush resistance, and reliability. A fabrication method of an underlayer structure with embedded micro-hole structure is also provided.

Abstract: A semiconductor device structure includes a layer of III-V compound semiconductor material, a layer of polycrystalline CVD diamond material, and an interface region with a diamond nucleation layer. A Raman signal of the diamond nucleation layer exhibits an sp3 carbon peak at 1332 cm?1 having a full width half maximum of no more than 5.0 cm?1, and one or both of: (i) an sp2 carbon peak at 1550 cm?1 having a height which is no more than 20% of a height of the sp3 carbon peak at 1332 cm?1 after background subtraction when using a Raman excitation source at 633 nm; and (ii) the sp3 carbon peak at 1332 cm?1 is no less than 10% of local background intensity in a Raman spectrum using a Raman excitation source at 785 nm. An average nucleation density at a nucleation surface is no less than 1×108 cm?2 and no more than 1×1012 cm?2.