Abstract: A light emitting device with graded composition hole tunneling layer is provided. The device comprises a substrate and an n-type semiconductor layer is disposed on the substrate, in which the n-type semiconductor layer comprises a first portion and a second portion. A graded composition hole tunneling layer is disposed on the first portion of the n-type semiconductor layer. An electron blocking layer is disposed on the graded composition hole tunneling layer. A p-type semiconductor layer is disposed on the electron blocking layer. A first electrode is disposed on the p-type semiconductor layer, and a second electrode is disposed on the second portion of the n-type semiconductor layer and is electrical insulated from the first portion of the n-type semiconductor. The graded composition hole tunneling layer is used as the quantum-well to improve the transport efficiency of the holes to increase the light emitting efficiency of the light emitting device.

Abstract: A device includes an epitaxially grown crystalline material within an area confined by an insulator. A surface of the crystalline material has a reduced roughness. One example includes obtaining a surface with reduced roughness by creating process parameters which result in the dominant growth component of the crystal to be supplied laterally from side walls of the insulator. In a preferred embodiment, the area confined by the insulator is an opening in the insulator having an aspect ratio sufficient to trap defects using an ART technique.

Abstract: A GaN single crystal substrate has a main surface with an area of not less than 10 cm2, the main surface has a plane orientation inclined by not less than 65° and not more than 85° with respect to one of a (0001) plane and a (000-1) plane, and the substrate has at least one of a substantially uniform distribution of a carrier concentration in the main surface, a substantially uniform distribution of a dislocation density in the main surface, and a photoelasticity distortion value of not more than 5×10?5, the photoelasticity distortion value being measured by photoelasticity at an arbitrary point in the main surface when light is applied perpendicularly to the main surface at an ambient temperature of 25° C. Thus, the GaN single crystal substrate suitable for manufacture of a GaN-based semiconductor device having a small variation of characteristics can be obtained.

Abstract: The semiconductor wafer includes: a base wafer; and an inhibition layer that is disposed on the base wafer as one piece or to be separate portions from each other, and inhibits growth of a crystal of a compound semiconductor, where the inhibition layer has a plurality of first opening regions that have a plurality of openings penetrating the inhibition layer and leading to the base wafer, each of the plurality of first opening regions includes therein a plurality of first openings disposed in the same arrangement, some of the plurality of first openings are first element forming openings each provided with a first compound semiconductor on which an electronic element is to be formed, and the other of the plurality of first openings are first dummy openings in which no electronic element is to be formed.

Abstract: Provided is a Group III nitride semiconductor device, which comprises an electrically conductive substrate including a primary surface comprised of a first gallium nitride based semiconductor, and a Group III nitride semiconductor region including a first p-type gallium nitride based semiconductor layer and provided on the primary surface. The primary surface of the substrate is inclined at an angle in the range of not less than 50 degrees, and less than 130 degrees from a plane perpendicular to a reference axis extending along the c-axis of the first gallium nitride based semiconductor, an oxygen concentration Noxg of the first p-type gallium nitride based semiconductor layer is not more than 5×1017 cm?3, and a ratio (Noxg/Npd) of the oxygen concentration Noxg to a p-type dopant concentration Npd of the first p-type gallium nitride based semiconductor layer is not more than 1/10.

Abstract: Various embodiments of the present disclosure pertain to selective photo-enhanced wet oxidation for nitride layer regrowth on substrates. In one aspect, a method may comprise: forming a first III-nitride layer with a first low bandgap energy on a first surface of a substrate; forming a second III-nitride layer with a first high bandgap energy on the first III-nitride layer; transforming portions of the first III-nitride layer into a plurality of III-oxide stripes by photo-enhanced wet oxidation; forming a plurality of III-nitride nanowires with a second low bandgap energy on the second III-nitride layer between the III-oxide stripes; and selectively transforming at least some of the III-nitride nanowires into III-oxide nanowires by selective photo-enhanced oxidation.

Abstract: A group III nitride composite substrate includes a group III nitride film and a support substrate formed from a material different in chemical composition from the group III nitride film. The group III nitride film has a thickness of 10 ?m or more. A sheet resistance of a-group III-nitride-film-side main surface of the group III nitride composite substrate is 200 ?/sq or less. A method for manufacturing a group III nitride composite substrate includes the steps of bonding the group III nitride film and the support substrate to each other; and reducing the thickness of at least one of the group III nitride film and the support substrate bonded to each other. Accordingly, a group III nitride composite substrate of a low sheet resistance that is obtained with a high yield as well as a method for manufacturing the same are provided.

Abstract: A thermoelectric conversion material is provided, in which only a desired crystal is selectively precipitated. An MxV2O5 crystal is selectively precipitated in vanadium-based glass, wherein M is one metal element selected from the group consisting of iron, arsenic, antimony, bismuth, tungsten, molybdenum, manganese, nickel, copper, silver, an alkali metal and an alkaline earth metal, and 0<x<1.

Abstract: Methods of depositing III-nitride semiconductor materials on substrates include depositing a layer of III-nitride semiconductor material on a surface of a substrate in a nucleation HVPE process stage to form a nucleation layer having a microstructure comprising at least some amorphous III-nitride semiconductor material. The nucleation layer may be annealed to form crystalline islands of epitaxial nucleation material on the surface of the substrate. The islands of epitaxial nucleation material may be grown and coalesced in a coalescence HVPE process stage to form a nucleation template layer of the epitaxial nucleation material. The nucleation template layer may at least substantially cover the surface of the substrate. Additional III-nitride semiconductor material may be deposited over the nucleation template layer of the epitaxial nucleation material in an additional HVPE process stage. Final and intermediate structures comprising III-nitride semiconductor material are formed by such methods.

Abstract: A temperature stable (color and efficiency) III-nitride based amber (585 nm) light-emitting diode is based on a novel hybrid nanowire-planar structure. The arrays of GaN nanowires enable radial InGaN/GaN quantum well LED structures with high indium content and high material quality. The high efficiency and temperature stable direct yellow and red phosphor-free emitters enable high efficiency white LEDs based on the RGYB color-mixing approach.

Abstract: A nitride semiconductor crystal producing method, a nitride semiconductor epitaxial wafer, and a nitride semiconductor freestanding substrate, by which it is possible to suppress the occurrence of cracking in the nitride semiconductor crystal and to ensure the enhancement of the yield of the nitride semiconductor crystal. The nitride semiconductor crystal producing method includes growing a nitride semiconductor crystal over a seed crystal substrate, while applying an etching action to an outer end of the seed crystal substrate during the growing of the nitride semiconductor crystal.

Abstract: A method for making conductive traces and interconnects on a surface of a substrate includes, for an embodiment, forming a dielectric or polymer layer on the surface of the substrate, forming a seed layer of an electrically conductive material on the dielectric or polymer layer, patterning a photoresist on the seed layer, forming the conductive traces on the patterned photoresist and seed layer, removing the photoresist from the substrate, and irradiating the surface of the substrate with a fluence of laser light effective to ablate the seed layer from areas of the substrate surface exclusive of the conductive traces.

Abstract: A nitride semiconductor device includes a first nitride semiconductor layer, and an npn junction structure including a second nitride semiconductor layer of an n-type conductivity, a third nitride semiconductor layer of a p-type conductivity, and a fourth nitride semiconductor layer of an n-type conductivity layered in this order on the first nitride semiconductor layer. The third nitride semiconductor layer includes two or more uncovered regions which are uncovered with the fourth nitride semiconductor layer.

Abstract: According to one embodiment, a semiconductor light-emitting device includes: a first conductivity type first semiconductor layer containing a nitride semiconductor crystal and having a tensile stress in a (0001) surface; a second conductivity type second semiconductor layer containing a nitride semiconductor crystal and having a tensile stress in the (0001) surface; a light emitting layer provided between the first semiconductor layer and the second semiconductor layer, containing a nitride semiconductor crystal, and having an average lattice constant larger than the lattice constant of the first semiconductor layer; and a first stress application layer provided on a side opposite to the light emitting layer of the first semiconductor layer and applying a compressive stress to the first semiconductor layer.

Abstract: A group III nitride crystal substrate is provided in which a uniform distortion at a surface layer of the crystal substrate represented by a value of |d1 ?d2 |/d2 obtained from a plane spacing d1 at the X-ray penetration depth of 0.3 ?m and a plane spacing d2 at the X-ray penetration depth of 5 ?m is equal to or lower than 1.9 ×10?3, and the main surface has a plane orientation inclined in the <10-10> direction at an angle equal to or greater than 10° and equal to or smaller than 80° with respect to one of (0001) and (000-1) planes of the crystal substrate. A group III nitride crystal substrate suitable for manufacturing a light emitting device with a blue shift of an emission suppressed, an epilayer-containing group III nitride crystal substrate, a semiconductor device and a method of manufacturing the same can thereby be provided.

Abstract: A silicon/germanium material and a silicon/carbon material may be provided in transistors of different conductivity type on the basis of an appropriate manufacturing regime without unduly contributing to overall process complexity. Furthermore, appropriate implantation species may be provided through exposed surface areas of the cavities prior to forming the corresponding strained semiconductor alloy, thereby additionally contributing to enhanced overall transistor performance. In other embodiments a silicon/carbon material may be formed in a P-channel transistor and an N-channel transistor, while the corresponding tensile strain component may be overcompensated for by means of a stress memorization technique in the P-channel transistor. Thus, the advantageous effects of the carbon species, such as enhancing overall dopant profile of P-channel transistors, may be combined with an efficient strain component while enhanced overall process uniformity may also be accomplished.

Abstract: A circuit structure includes a substrate and a patterned dielectric layer over the substrate. The patterned dielectric layer includes a plurality of vias; and a number of group-III group-V (III-V) compound semiconductor layer. The III-V compound semiconductor layers include a first layer in the vias, a second layer over the first layer and the dielectric layer, and a bulk layer over the second layer.

Abstract: Methods of fabricating semiconductor devices or structures include bonding a layer of semiconductor material to another material at a temperature, and subsequently changing the temperature of the layer of semiconductor material. The another material may be selected to exhibit a coefficient of thermal expansion such that, as the temperature of the layer of semiconductor material is changed, a controlled and/or selected lattice parameter is imparted to or retained in the layer of semiconductor material. In some embodiments, the layer of semiconductor material may comprise a III-V type semiconductor material, such as, for example, indium gallium nitride. Novel intermediate structures are formed during such methods. Engineered substrates include a layer of semiconductor material having an average lattice parameter at room temperature proximate an average lattice parameter of the layer of semiconductor material previously attained at an elevated temperature.

Abstract: Methods for integrating wide-gap semiconductors, and specifically, gallium nitride epilayers with synthetic diamond substrates are disclosed. Diamond substrates are created by depositing synthetic diamond onto a nucleating layer deposited or formed on a layered structure that comprises at least one layer made out of gallium nitride. Methods for manufacturing GaN-on-diamond wafers with low bow and high crystalline quality are disclosed along with preferred choices for manufacturing GaN-on-diamond wafers and chips tailored to specific applications.

Abstract: A semiconductor substrate includes a sapphire substrate including an a-plane main surface and a groove in a surface thereof, the groove includes side surfaces and a bottom surface, and a Group III nitride semiconductor layer formed on the sapphire substrate. Both side surfaces of the groove assume a c-plane of sapphire. An axis perpendicular to one of the side surfaces of the groove of the Group III nitride semiconductor layer assumes a c-axis of Group III nitride semiconductor. A plane parallel to the main surface of the sapphire substrate of the Group III nitride semiconductor layer assumes an m-plane of Group III nitride semiconductor.

Abstract: The invention relates to a new High Electron Mobility Transistor (HEMT), made essentially of layers of Group XIII element(s) nitride(s). Contrary to currently available transistors of this type, the transistor according to the invention is produced on a homosubstrate made of gallium-containing nitride, has no nucleation layer and its buffer layer is remarkably thinner than in known HEMTs. Preferably, at least the buffer layer, being a part of the transistor according to the present invention, is produced by epitaxial methods and the direction of growth of said layer in an epitaxial process is essentially perpendicular to the direction of growth of the substrate. The invention relates also to a method of manufacturing of High Electron Mobility Transistor (HEMT).

Abstract: A light emitting device is disclosed. The light emitting device includes a first conductive type semiconductor layer, an active layer disposed on the first conductive type semiconductor layer, a tunnel junction layer comprising a second conductive type nitride semiconductor layer and a first conductive type nitride semiconductor layer disposed on the active layer, wherein the first conductive type nitride semiconductor layer and the second conductive type nitride semiconductor layer are PN junctioned, a first electrode disposed on the first conductive type semiconductor layer, and a second electrode disposed on the first conductive type nitride semiconductor layer, wherein a portion of the second electrode is in schottky contact with the second conductive type nitride semiconductor layer through the first conductive type nitride semiconductor layer.

Abstract: Forming an alignment mark on a semiconductor structure using an optical lithography to form a metal alignment mark on a substrate of the structure, using the formed metal alignment mark to form a first feature of a semiconductor device being formed on the substrate using optical lithography, and using the formed metal alignment mark to form a second, different feature for the semiconductor using electron beam lithography. In one embodiment, the first feature is an ohmic contact, the second feature is a Schottky contact, the metal alignment mark is a refractory metal or a refractory metal compound having an atomic weight greater than 60 such as TaN and the semiconductor device is a GaN semiconductor device. A semiconductor structure having a metal alignment mark on a zero layer of the structure, the metal alignment mark is a TaN and the semiconductor is GaN.

Abstract: Quantum-well-based semiconductor devices and methods of forming quantum-well-based semiconductor devices are described. A method includes providing a hetero-structure disposed above a substrate and including a quantum-well channel region. The method also includes forming a source and drain material region above the quantum-well channel region. The method also includes forming a trench in the source and drain material region to provide a source region separated from a drain region. The method also includes forming a gate dielectric layer in the trench, between the source and drain regions; and forming a gate electrode in the trench, above the gate dielectric layer.

Abstract: A process for producing a doped III-N bulk crystal, wherein III denotes at least one element of the main group III of the periodic system, selected from Al, Ga and In, wherein the doped crystalline III-N layer or the doped III-N bulk crystal is deposited on a substrate or template in a reactor, and wherein the feeding of at least one dopant into the reactor is carried out in admixture with at least one group III material. In this manner, III-N bulk crystals and III-N single crystal substrates separated therefrom can be obtained with a very homogeneous distribution of dopants in the growth direction as well as in the growth plane perpendicular thereto, a very homogeneous distribution of charge carriers and/or of the specific electric resistivity in the growth direction as well as in the growth plane perpendicular thereto, and a very good crystal quality.

Abstract: A semiconductor structure includes a III-nitride substrate and a first III-nitride epitaxial layer of a first conductivity type coupled to the III-nitride substrate. The semiconductor structure also includes a first III-nitride epitaxial structure of the first conductivity type coupled to the first III-nitride epitaxial layer and a second III-nitride epitaxial structure of the first conductivity type coupled to the first III-nitride epitaxial structure. The semiconductor structure further includes a second III-nitride epitaxial layer coupled to the first III-nitride epitaxial structure. The second III-nitride epitaxial layer is of a second conductivity type and is not electrically connected to the second III-nitride epitaxial structure.

Abstract: An object of the present invention is to address the problems described herein and to provide a III-nitride semiconductor epitaxial substrate, a III-nitride semiconductor element, and a III-nitride semiconductor freestanding substrate, which have good crystallinity, not only with AlGaN, GaN, or GaInN, the growth temperature of which is at or below 1050° C., but also with AlxGa1-xN, the growth temperature of which is high and which has a high Al composition, as well as a III-nitride semiconductor growth substrate for fabricating these and a method for efficiently fabricating these. The invention is characterized by being equipped with: a crystal growth substrate, at least the surface portion of which substrate includes a III-nitride semiconductor containing Al; and a single metallic layer formed on the surface portion, the single metallic layer being made from Zr or Hf.

Abstract: A nonpolar III-nitride film grown on a miscut angle of a substrate, in order to suppress the surface undulations, is provided. The surface morphology of the film is improved with a miscut angle towards an a-axis direction comprising a 0.15° or greater miscut angle towards the a-axis direction and a less than 30° miscut angle towards the a-axis direction.

Abstract: Methods of fabricating semiconductor structures include forming a plurality of openings extending through a semiconductor material and at least partially through a metal material and deforming the metal material to relax a remaining portion of the semiconductor material. The metal material may be deformed by exposing the metal material to a temperature sufficient to alter (i.e., increase) its ductility. The metal material may be formed from one or more of hafnium, zirconium, yttrium, and a metallic glass. Another semiconductor material may be deposited over the remaining portions of the semiconductor material, and a portion of the metal material may be removed from between each of the remaining portions of the semiconductor material. Semiconductor structures may be formed using such methods.

Abstract: Provided is a semiconductor substrate and a method for manufacturing the same. The semiconductor substrate includes a substrate, a discontinuously formed hemispheric metal layer on the substrate, and a semiconductor layer on the hemispheric metal layer. A plurality of voids on the interface of the substrate and discontinuous hemisphere are formed to absorb or relax the stain of interface. Accordingly, even if a subsequent layer is relatively thickly formed on the substrate, substrate bow or warpage can be minimized.

Abstract: To grow a gallium nitride crystal, a seed-crystal substrate is first immersed in a melt mixture containing gallium and sodium. Then, a gallium nitride crystal is grown on the seed-crystal substrate under heating the melt mixture in a pressurized atmosphere containing nitrogen gas and not containing oxygen. At this time, the gallium nitride crystal is grown on the seed-crystal substrate under a first stirring condition of stirring the melt mixture, the first stirring condition being set for providing a rough growth surface, and the gallium nitride crystal is subsequently grown on the seed-crystal substrate under a second stirring condition of stirring the melt mixture, the second stirring condition being set for providing a smooth growth surface.

Abstract: A method for fabricating a high quality freestanding nonpolar and semipolar nitride substrate with increased surface area, comprising stacking multiple films by growing the films one on top of each other with different and non-orthogonal growth directions.

Abstract: Large area single crystal III-V nitride material having an area of at least 2 cm2, having a uniformly low dislocation density not exceeding 3×106 dislocations per cm2 of growth surface area, and including a plurality of distinct regions having elevated impurity concentration, wherein each distinct region has at least one dimension greater than 50 microns, is disclosed. Such material can be formed on a substrate by a process including (i) a first phase of growing the III-V nitride material on the substrate under pitted growth conditions, e.g., forming pits over at least 50% of the growth surface of the III-V nitride material, wherein the pit density on the growth surface is at least 102 pits/cm2 of the growth surface, and (ii) a second phase of growing the III-V nitride material under pit-filling conditions.

Abstract: Technology of making freestanding gallium nitride (GaN) wafers has been matured at length. Gallium nitride is rigid but fragile. Chamfering of a periphery of a GaN wafer is difficult. At present edges are chamfered by a rotary whetstone of gross granules with weak pressure. Minimum roughness of the chamfered edges is still about Ra 10 ?m to Ra 6 ?m. The large edge roughness causes scratches, cracks, splits or breaks in transferring process or wafer process. A wafer of the present invention is bevelled by fixing the wafer to a chuck of a rotor, bringing an edge of the wafer into contact with an elastic whetting material having a soft matrix and granules implanted on the soft matrix, rotating the wafer and feeding the whetting material. Favorably, several times of chamfering edges by changing the whetting materials of smaller granules are given to the wafer. The chamfering can realize small roughness of Ra10 nm and Ra5 ?m at edges of wafers.

Abstract: A method includes forming a stress compensating stack over a substrate, where the stress compensating stack has compressive stress on the substrate. The method also includes forming one or more Group III-nitride islands over the substrate, where the one or more Group III-nitride islands have tensile stress on the substrate. The method further includes at least partially counteracting the tensile stress from the one or more Group III-nitride islands using the compressive stress from the stress compensating stack. Forming the stress compensating stack could include forming one or more oxide layers and one or more nitride layers over the substrate. The one or more oxide layers can have compressive stress, the one or more nitride layers can have tensile stress, and the oxide and nitride layers could collectively have compressive stress. Thicknesses of the oxide and nitride layers can be selected to provide the desired amount of stress compensation.

Abstract: An object of the invention is to improve the accuracy of light detection in a photosensor, and to increase the light-receiving area of the photosensor. The photosensor includes: a light-receiving element which converts light into an electric signal; a first transistor which transfers the electric signal; and a second transistor which amplifies the electric signal. The light-receiving element includes a silicon semiconductor, and the first transistor includes an oxide semiconductor. The light-receiving element is a lateral-junction photodiode, and an n-region or a p-region included in the light-receiving element overlaps with the first transistor.

Abstract: Techniques for crack-free growth of GaN, and related, films on larger-size substrates via spatially confined epitaxy are described.

Abstract: Provided is a method of manufacturing III-nitride crystal having a major surface of plane orientation other than {0001}, designated by choice, the III-nitride crystal manufacturing method including: a step of slicing III-nitride bulk crystal through a plurality of planes defining a predetermined slice thickness in the direction of the designated plane orientation, to produce a plurality of III-nitride crystal substrates having a major surface of the designated plane orientation; a step of disposing the substrates adjoining each other sideways in a manner such that the major surfaces of the substrates parallel each other and such that any difference in slice thickness between two adjoining III-nitride crystal substrates is not greater than 0.1 mm; and a step of growing III-nitride crystal onto the major surfaces of the substrates.

Abstract: A semiconductor device including: an FET; a MOSFET having a drain thereof connected with a source of the FET; a resistor having one end thereof connected with a gate of the FET and having the other end thereof connected with a source of the MOSFET; and a diode having an anode thereof connected with the gate of the FET and having a cathode thereof connected with the source of the MOSFET.

Abstract: A method of fabricating a solar cell on a conveyer belt is provided. The method includes the following steps. A first surface of an aluminum foil is coated with a layer of phosphorous mixed with a plurality of graphite powders and put on the conveyer belt. A first thermal treatment is performed to activate a portion of the aluminum foil and the phosphorous layer on the first surface to form an aluminum phosphide (AlP) layer. A molten silicon material is spray-coated on a second surface of the remaining aluminum foil, and a second thermal treatment is performed to make the silicon material transferring into a p-type polySi layer on the n-type AlP layer. A solar cell including the n-type AlP layer and the p-type polySi layer is formed, and the solar cell is respectively annealed and cooled down in a first and a second vertical stack.

Abstract: A compound semiconductor substrate includes a first substrate and a second substrate made of single crystal gallium nitride. In each of the first substrate and the second substrate, one surface is a (0001) Ga-face and an opposite surface is a (000-1) N-face. The first substrate and the second substrate are bonded to each other in a state where the (000-1) N-face of the first substrate and the (000-1) N-face of the second substrate face each other, and the (0001) Ga-face of the first substrate and the (0001) Ga-face of the second substrate are exposed.

Abstract: A mechanical memory transistor includes a substrate having formed thereon a source region and a drain region. An oxide is formed upon a portion of the source region and upon a portion of the drain region. A pull up electrode is positioned above the substrate such that a gap is formed between the pull up electrode and the substrate. A movable gate has a first position and a second position. The movable gate is located in the gap between the pull up electrode and the substrate. The movable gate is in contact with the pull up electrode when the movable gate is in a first position and is in contact with the oxide to form a gate region when the movable gate is in the second position. The movable gate, in conjunction with the source region and the drain region and when the movable gate is in the second position, form a transistor that can be utilized as a non-volatile memory element.

Abstract: A group III nitride semiconductor crystal substrate has a diameter of at least 25 mm and not more than 160 mm. The resistivity of the group III nitride semiconductor crystal substrate is at least 1×10?4 ?·cm and not more than 0.1 ?·cm. The resistivity distribution in the diameter direction of the group III nitride semiconductor crystal is at least ?30% and not more than 30%. The resistivity distribution in the thickness direction of the group III nitride semiconductor crystal is at least ?16% and not more than 16%.

Abstract: There is provided a method of producing a semiconductor wafer, including: forming a compound semiconductor layer on a base wafer by epitaxial growth; cleansing a surface of the compound semiconductor layer by means of a cleansing agent containing a selenium compound; and forming an insulating layer on the surface of the compound semiconductor layer. Examples of the selenium compound include a selenium oxide. Examples of the selenium oxide include H2SeO3. The cleansing agent may further contain one or more substances selected from the group consisting of water, ammonium, and ethanol. When the surface of the compound semiconductor layer is made of InxGa1-xAs (0?x?1), the insulating layer is preferably made of Al2O3, and Al2O3 is preferably formed by ALD.

Abstract: According to one disclosed embodiment, an electrical contact for use on a semiconductor device comprises an electrode stack including a plurality of metal layers and a capping layer formed over the plurality of metal layers. The capping layer comprises a refractory metal nitride. In one embodiment, a method for fabricating an electrical contact for use on a semiconductor device comprises forming an electrode stack including a plurality of metal layers over the semiconductor device, and depositing a refractory metal nitride capping layer of the electrode stack over the plurality of metal layers. The method may further comprise annealing the electrode stack at a temperature of less than approximately 875° C. In some embodiments, the method may additionally include forming one of a Schottky metal layer and a gate insulator layer between the electrode stack and the semiconductor device.

Abstract: The present invention provides a method of growing an ingot of group III nitride. Group III nitride crystals such as GaN are grown by the ammonothermal method on both sides of a seed to form an ingot and the ingot is sliced into wafers. The wafer including the first-generation seed is sliced thicker than the other wafers so that the wafer including the first-generation seed does not break. The wafer including the first-generation seed crystal can be used as a seed for the next ammonothermal growth.

Abstract: The invention provides, in one instance, a group III nitride wafer sliced from a group III nitride ingot, polished to remove the surface damage layer and tested with x-ray diffraction. The x-ray incident beam is irradiated at an angle less than 15 degree and diffraction peak intensity is evaluated. The group III nitride wafer passing this test has sufficient surface quality for device fabrication. The invention also provides, in one instance, a method of producing group III nitride wafer by slicing a group III nitride ingot, polishing at least one surface of the wafer, and testing the surface quality with x-ray diffraction having an incident beam angle less than 15 degree to the surface. The invention also provides, in an instance, a test method for testing the surface quality of group III nitride wafers using x-ray diffraction having an incident beam angle less than 15 degree to the surface.

Abstract: The present invention provides a method of growing an ingot of group III nitride. Group III nitride crystals such as GaN are grown by the ammonothermal method on both sides of a seed to form an ingot and the ingot is sliced into wafers. The wafer including the first-generation seed is sliced thicker than the other wafers so that the wafer including the first-generation seed does not break. The wafer including the first-generation seed crystal can be used as a seed for the next ammonothermal growth.

Abstract: Millimeter-scale GaN single crystals in filamentary form, also known as GaN whiskers, grown from solution and a process for preparing the same at moderate temperatures and near atmospheric pressures are provided. GaN whiskers can be grown from a GaN source in a reaction vessel subjected to a temperature gradient at nitrogen pressure. The GaN source can be formed in situ as part of an exchange reaction or can be preexisting GaN material. The GaN source is dissolved in a solvent and precipitates out of the solution as millimeter-scale single crystal filaments as a result of the applied temperature gradient.

Abstract: The present invention provides a method for producing a Group III nitride semiconductor. The method includes forming a groove in a surface of a growth substrate through etching; forming a buffer film on the groove-formed surface of the growth substrate through sputtering; heating, in an atmosphere containing hydrogen and ammonia, the substrate to a temperature at which a Group III nitride semiconductor of interest is grown; and epitaxially growing the Group III nitride semiconductor on side surfaces of the groove at the growth temperature. The thickness of the buffer film or the growth temperature is regulated so that the Group III nitride semiconductor is grown primarily on the side surfaces of the groove in a direction parallel to the main surface of the growth substrate.