Abstract: Embodiments of an ohmic contact structure for a Group III nitride semiconductor device and methods of fabrication thereof are disclosed. In general, the ohmic contact structure has a root-mean-squared (RMS) surface roughness of less than 10 nanometers, and more preferably less than or equal to 7.5 nanometers, and more preferably less than or equal to 5 nanometers, and more preferably less than or equal to 2 nanometers, and even more preferably less than or equal to 1.5 nanometers.

Abstract: Provided is a self-supporting polycrystalline GaN substrate composed of GaN-based single crystal grains having a specific crystal orientation in a direction approximately normal to the substrate. The crystal orientations of individual GaN-based single crystal grains as determined from inverse pole figure mapping by EBSD analysis on the substrate surface are distributed with tilt angles from the specific crystal orientation, the average tilt angle being 1 to 10°. There is also provided a light emitting device including the self-supporting substrate and a light emitting functional layer, which has at least one layer composed of semiconductor single crystal grains, the at least one layer having a single crystal structure in the direction approximately normal to the substrate. The present invention makes it possible to provide a self-supporting polycrystalline GaN substrate having a reduced defect density at the substrate surface, and to provide a light emitting device having a high luminous efficiency.

Abstract: A tunneling field-effect transistor (TFET) device is disclosed. A frustoconical protrusion structure is disposed over a substrate and protruding out of the plane of substrate. A source region is disposed as a top portion of the frustoconical protrusion structure. A sidewall spacer is disposed along sidewall of the source region. A source contact with a critical dimension (CD), which is substantially larger than a width of the source region, is formed on the source region and the sidewall spacer together.

Abstract: A solution is formation of a nitride semiconductor layer on one principal plane of a single crystal substrate through a first layer. Upon selecting arbitrary three places in a radial direction from a cross section cleaved in a diameter portion and observing an interface between the first layer and the nitride semiconductor layer by taking a width of at least 500 nm in the radial direction, a value is within the range of 6 nm or more and 15 nm or less in a mean value of the three places with regard to a difference between a maximum height of a convex top portion and a minimum height of a concave bottom portion of the first layer in a thickness direction from the single crystal substrate toward the nitride semiconductor layer. A value is 10 nm or more and 25 nm or less in the mean value.

Abstract: Provided is a high-quality Group III nitride crystal of excellent processability. A Group III nitride crystal is produced by forming a film is composed of an oxide, hydroxide and/or oxyhydroxide containing a Group III element by heat-treating a Group III nitride single crystal at 1000° C. or above, and removing the film.

Abstract: A method of forming a semiconductor in a long trench. The method may include; forming a first semiconductor on a substrate and in a long trench; forming a first spacer along sidewalls of the long trench and above the first semiconductor, a portion of the first semiconductor remains exposed; recessing the exposed portion of the first semiconductor; forming an insulator layer on the recessed portion of the first semiconductor; forming a second semiconductor on the insulator layer; forming a second spacer on sidewalls of the first spacer and above the second semiconductor, a portion of the second semiconductor remains exposed; removing the exposed portion of the second semiconductor; and removing a frond end and a back end of the first semiconductor and the second semiconductor, wherein the front end and back end are separated by a central region and the central region extends across the width of the long trench.

Abstract: A process for separating a substrate from an epitaxial layer comprises forming a multilayer substrate comprising a substrate, a lattice matching layer and an epitaxial layer. The method further comprises etching the lattice matching layer by one of a liquid or a vapor phase acid. The lattice matching layer is a metal alloy between the substrate and the epitaxial layer and serves as an etching release layer. The substrate can also be separated from an epitaxial layer by laser lift off process. The process comprises forming a multilayer substrate comprising a substrate, a lattice matching layer and an epitaxial layer, directing laser light at the lattice matching layer, maintaining the laser light on the lattice matching layer for a sufficient period of time so that it is absorbed by free electrons in the lattice matching layer to allow decomposition of the lattice matching layer.

Abstract: A light emitting diode structure is provided. The light emitting diode structure includes a substrate, a light emitting multi-layer structure, a first current blocking layer, a first current spreading layer, a second current blocking layer and a second current spreading layer. The light emitting multi-layer structure is formed on the substrate by way of stacking. The first current blocking layer is formed on part of the light emitting multi-layer structure. The first current spreading layer covers the first current blocking layer and the light emitting multi-layer structure. The second current blocking layer is formed on part of the first current spreading layer. An orthogonal projection of the second current blocking layer is disposed in an orthogonal projection of the first current blocking layer. The second current spreading layer covers the second current blocking layer and the first current spreading layer.

Abstract: Semiconductor device including: silicon-based substrate; first buffer layer on silicon-based substrate and is formed of first layer containing Al composition and second layer containing less Al than the first layer, the first and second layers being alternately stacked; second buffer layer on the first buffer layer and is formed of third layer containing Al composition and fourth layer containing less Al than the third layer, the third and fourth layers being alternately stacked; and third buffer layer on the second buffer layer and is formed of fifth layer containing Al composition and sixth layer containing less Al than the fifth layer, the fifth and sixth layers being alternately stacked, wherein the second buffer layer contains more Al than the first and third buffer layers. Thus, the semiconductor device leakage can be suppressed while reducing stress which is applied to buffer layer and can improve flatness of active layer upper face.

Abstract: A method for producing an optoelectronic component is provided. A transfer layer, containing InxGa1-xN with 0<x<1, is grown onto a growth substrate. Subsequently, ions are implanted into the transfer layer to form a separation zone, a carrier substrate is applied, and the transfer layer is separated by way of heat treatment. A further transfer layer, containing InyGa1-yN with 0<y?1 and y>x, is grown onto the previously grown transfer layer, ions are implanted into the further transfer layer to form a separation zone, a further carrier substrate is applied, and the further transfer layer is separated by way of heat treatment. Subsequently, a semiconductor layer sequence, containing an active layer, is grown onto the surface of the further transfer layer facing away from the further carrier substrate.

Abstract: A manufacturing method of a light-emitting diode device. The light-emitting diode device comprises: a substrate (1); an epitaxial layer at one side of the substrate (1) and comprising an N-type layer (2), a P-type layer (4), and an active layer (3) between the N-type layer (2) and the P-type layer (4); an N-type electrode (5); a P-type electrode (7); an adhesive layer (8); and a patterned substrate (9). The light-emitting diode device further comprises an insulating layer (6) between the N-type electrode (5) and the P-type electrode (7), the insulating layer (6) electrically insulating the N-type electrode (5) and the P-type electrode (7). In the manufacturing method thereof, light-emitting efficiency and luminous efficiency of the light-emitting diode device can be improved, wiring is easier as compared with conventional chips, and the manufacturing process can be optimized.

Abstract: A method of forming a freestanding semiconductor wafer includes providing a semiconductor substrate including a semiconductor layer having a back surface and an upper surface opposite the back surface, wherein the semiconductor layer comprises at least one permanent defect between the upper surface and back surface, removing a portion of the back surface of the semiconductor layer and the permanent defect from the semiconductor layer, and forming a portion of the upper surface after removing a portion of the back surface and the permanent defect.

Abstract: A group III nitride composite substrate includes a group III nitride film and a support substrate formed from a material different in chemical composition from the group III nitride film. The group III nitride film has a thickness of 10 ?m or more. A sheet resistance of a-group III-nitride-film-side main surface of the group III nitride composite substrate is 200 ?/sq or less. A method for manufacturing a group III nitride composite substrate includes the steps of bonding the group III nitride film and the support substrate to each other; and reducing the thickness of at least one of the group III nitride film and the support substrate bonded to each other. Accordingly, a group III nitride composite substrate of a low sheet resistance that is obtained with a high yield as well as a method for manufacturing the same are provided.

Abstract: A diode includes a first semiconductor layer configured by a compound semiconductor containing impurities of a first conductivity type; a high dislocation density region; a second semiconductor layer which is laminated on the first semiconductor layer, which is lower in a concentration of impurities in a region of a side of an interface with the first semiconductor layer than that of the first semiconductor layer, and which has an opening in which a portion which corresponds to the high dislocation density region is removed; an insulating film pattern which is provided to cover an inner wall of the opening; an electrode which is provided so as to cover the insulating film pattern and to contact the second semiconductor layer; and an opposing electrode which is provided to interpose the first semiconductor layer, the second semiconductor layer and the insulating film pattern between the electrode and the opposing electrode.

Abstract: A method for producing a group III nitride single crystal (ingot) includes providing a seed crystal comprising a first crystal face that is perpendicular to a growth direction of the single crystal and has a first predetermined area, and a second crystal face that is inclined to the growth direction and has a second predetermined area and growing the group III nitride single crystal on the first crystal face and the second crystal face by controlling a growth condition of the single crystal so as not to change the first predetermined area and the second predetermined area. A method for producing a group III nitride single crystal substrate includes further cutting the group III nitride single crystal substrate off from the grown group III nitride single crystal (ingot).

Abstract: A method for manufacturing a semiconductor device includes forming an electron transit layer on a semiconductor substrate, forming an electron supply layer on the electron transit layer, forming a cap layer on the electron supply layer, forming a protection layer on the cap layer, the protection layer having an opening part, through which a part of the cap layer is exposed, and forming an oxidation film on an exposed surface of the cap layer by a wet process.

Abstract: A substrate comprises a Group III-V material having an upper surface and a buffer layer having a thickness of not greater than about 1.3 ?m and overlying the upper surface of the substrate. A plurality of optoelectronic devices formed on the substrate having a normalized light emission wavelength standard deviation of not greater than about 0.0641 nm/cm2 at a wavelength within a range of between about 400 nm to about 550 nm.

Abstract: There is provided a nitride semiconductor epitaxial substrate having a group III nitride semiconductor layer with C-plane as a surface, grown on a substrate via a buffer layer of the group III nitride semiconductor containing Al, wherein the buffer layer has an inversion domain on the surface.

Abstract: A method of forming a semiconductive substrate material for an electronic device including forming a plurality of semiconductive layers on a substrate during a continuous growth process in a reaction chamber, wherein during the continuous growth process, a release layer is formed between a base layer and an epitaxial layer by altering at least one growth process parameter during the continuous growth process. The method also including separating the plurality of semiconductive layers from the substrate.

Abstract: A semiconductor wafer is provided. The semiconductor wafer comprises a sacrificial layer and a semiconductor crystal layer above a semiconductor crystal layer forming wafer, the semiconductor crystal layer forming wafer, the sacrificial layer and the semiconductor crystal layer being arranged in the order of the semiconductor crystal layer forming wafer, the sacrificial layer and the semiconductor crystal layer, wherein the semiconductor wafer comprises a diffusion inhibiting layer that inhibits diffusion of a first atom of one type selected from a plurality of types of atoms constituting the semiconductor crystal layer forming wafer or the sacrificial layer, at any cross-sectional position between (a) the interface of the semiconductor crystal layer forming wafer that faces the sacrificial layer and (b) a middle of the semiconductor crystal layer.

Abstract: A semiconductor wafer is provided. The semiconductor wafer comprises a sacrificial layer, a first semiconductor crystal layer, and a second semiconductor crystal layer above a semiconductor crystal layer forming wafer, wherein the semiconductor crystal layer forming wafer, the sacrificial layer, the first semiconductor crystal layer and the second semiconductor crystal layer are arranged in the order of the semiconductor crystal layer forming wafer, the sacrificial layer, the first semiconductor crystal layer and the second semiconductor crystal layer, a first atom of one type selected from a plurality of types of atoms constituting the semiconductor crystal layer forming wafer or the sacrificial layer is contained in the first semiconductor crystal layer and the second semiconductor crystal layer as an impurity, and the concentration of the first atom in the second semiconductor crystal layer is lower than the concentration of the first atom in the first semiconductor crystal layer.

Abstract: In a semiconductor device 100, it is possible to prevent C from piling up at a boundary face between an epitaxial layer 22 and a group III nitride semiconductor substrate 10 by the presence of 30×1010 pieces/cm2 to 2000×1010 pieces/cm2 of sulfide in terms of S and 2 at % to 20 at % of oxide in terms of O in a surface layer 12. By thus preventing C from piling up, a high-resistivity layer is prevented from being formed on the boundary face between the epitaxial layer 22 and the group III nitride semiconductor substrate 10. Accordingly, it is possible to reduce electrical resistance at the boundary face between the epitaxial layer 22 and the group III nitride semiconductor substrate 10, and improve the crystal quality of the epitaxial layer 22. Consequently, it is possible to improve the emission intensity and yield of the semiconductor device 100.

Abstract: A semiconductor device includes a GaN FET with an overvoltage clamping component electrically coupled to a drain node of the GaN FET and coupled in series to a voltage dropping component. The voltage dropping component is electrically coupled to a terminal which provides an off-state bias for the GaN FET. The overvoltage clamping component conducts insignificant current when a voltage at the drain node of the GaN FET is less than the breakdown voltage of the GaN FET and conducts significant current when the voltage rises above a safe voltage limit. The voltage dropping component is configured to provide a voltage drop which increases as current from the overvoltage clamping component increases. The semiconductor device is configured to turn on the GaN FET when the voltage drop across the voltage dropping component reaches a threshold value.

Abstract: There is provided a method of processing a surface of a group III nitride crystal, that includes the steps of: polishing a surface of a group III nitride crystal with a polishing slurry containing abrasive grains; and thereafter polishing the surface of the group III nitride crystal with a polishing liquid at least once, and each step of polishing with the polishing liquid employs a basic polishing liquid or an acidic polishing liquid as the polishing liquid. The step of polishing with the basic or acidic polishing liquid allows removal of impurity such as abrasive grains remaining on the surface of the group III nitride crystal after it is polished with the slurry containing the abrasive grains.

Abstract: A semiconductor device includes a substrate having a hexagonal crystalline structure and a (0001) surface, and conductive films on the surface of the substrate. The conductive films include a first conductive film and a second conductive film located above the first conductive film with respect to the surface, wherein the first conductive film has a crystalline structure which does not have a plane that has a symmetry equivalent to the symmetry of atomic arrangement in the surface of the substrate, the second conductive film has a crystalline structure having at least one plane that has a symmetry equivalent to the symmetry of atomic arrangement in the surface of the substrate, and the second conductive film is polycrystalline and has a grain size no larger than 15 ?m.

Abstract: A semiconductor apparatus (10) includes: a layered structure (100) that includes double junction structures that have a first junction (151, 153) where a wide-bandgap layer (102, 104) and a narrow-bandgap layer (101, 103, 105) are layered on each other and a second junction (152, 154) where a narrow-bandgap layer (101, 103, 105) and a wide-bandgap layer (102, 104) are layered on each other, and electrode semiconductor layers (110, 120) are joined to each layer of the layered structure. Each double junction structure includes a pair of a first region (131, 133) that has negative fixed charge and a second region (132, 134) that has positive fixed charge. The first region is closer to the first junction than to a center of the wide-bandgap layer. The second region is closer to the second junction than to the center of the wide-bandgap layer. A 2DEG or a 2DHG is formed at each junction. The semiconductor apparatus functions as an electric energy storage device such as a capacitor.

Abstract: There is provided a group III nitride semiconductor crystal, containing a donor-type impurity and having a hydrogen concentration of 2.0E+16 cm?3 or less in a crystal.

Abstract: Gallium nitride wafer substrate for solid state lighting devices, and associated systems and methods. A method for making an SSL device substrate in accordance with one embodiment of the disclosure includes forming multiple crystals carried by a support member, with the crystals having an orientation selected to facilitate formation of gallium nitride. The method can further include forming a volume of gallium nitride carried by the crystals, with the selected orientation of the crystals at least partially controlling a crystal orientation of the gallium nitride, and without bonding the gallium nitride, as a unit, to the support member. In other embodiments, the number of crystals can be increased by a process that includes annealing a region in which the crystals are present, etching the region to remove crystals having an orientation other than the selected orientation, and/or growing the crystals having the selected orientation.

Abstract: The present invention relates to growth of III-V semiconductor nanowires (2) on a Si substrate (3). Controlled vertical nanowire growth is achieved by a step, to be taken prior to the growing of the nanowire, of providing group III or group V atoms to a (111) surface of the Si substrate to provide a group III or group V 5 surface termination (4). A nanostructured device including a plurality of aligned III-V semiconductor nanowires (2) grown on, and protruding from, a (111) surface of a Si substrate (3) in an ordered pattern in compliance with a predetermined device layout is also presented.

Abstract: In heteroepitaxially growing a group-III nitride semiconductor on a Si single crystal substrate, the occurrence of cracks initiating in the wafer edge portion can be suppressed. Region A is an outermost peripheral portion outside the principal surface, being a bevel portion tapered. Regions B and C are on the same plane (the principal surface), region B (mirror-surface portion) being the center portion of the principal surface, and region C a region in the principal surface edge portion surrounding region B. The principal surface has a plane orientation, and in region B, is mirror-surface-finished. Region B occupies most of the principal surface of this Si single crystal substrate, and a semiconductor device is manufactured therein. Region C (surface-roughened portion) has a plane orientation as with region B, however, region B is mirror-surface-finished, whereas region C is surface-roughened.

Abstract: An object of the present invention is to provide a GaN-based light emitting diode element having a great emission efficiency and suitable for an excitation light source for a white LED. The GaN-based light emitting diode element includes an n-type conductive m-plane GaN substrate, a light emitting diode structure which is formed of a GaN-based semiconductor, on a front face of the m-plane GaN substrate, and an n-side ohmic electrode formed on a rear face of the m-plane GaN substrate, wherein a forward voltage is 4.0 V or less when a forward current applied to the light emitting diode element is 20 mA.

Abstract: A semiconductor device that includes one semiconductor device formed in one semiconductor material and a second semiconductor device formed in another semiconductor material on a common substrate, and a method of fabricating the semiconductor device.

Abstract: A semiconductor substrate that includes a semiconductor layer that exhibits high crystallinity includes a graphite layer formed of a heterocyclic polymer obtained by condensing an aromatic tetracarboxylic acid and an aromatic tetramine, and a semiconductor layer that is grown on the surface of the graphite layer, or includes a substrate that includes a graphite layer formed of a heterocyclic polymer obtained by condensing an aromatic tetracarboxylic acid and an aromatic tetramine on its surface, a buffer layer that is grown on the surface of the graphite layer, and a semiconductor layer that is grown on the surface of the buffer layer.

Abstract: Millimeter-scale GaN single crystals in filamentary form, also known as GaN whiskers, grown from solution and a process for preparing the same at moderate temperatures and near atmospheric pressures are provided. GaN whiskers can be grown from a GaN source in a reaction vessel subjected to a temperature gradient at nitrogen pressure. The GaN source can be formed in situ as part of an exchange reaction or can be preexisting GaN material. The GaN source is dissolved in a solvent and precipitates out of the solution as millimeter-scale single crystal filaments as a result of the applied temperature gradient.

Abstract: The present invention provides an epitaxial substrate including a silicon substrate containing oxygen atoms in concentrations of 4×1017 cm?3 or more and 6×1017 cm?3 or less and containing boron atoms in concentrations of 5×1018 cm?3 or more and 6×1019 cm?3 or less and a semiconductor layer that is placed on the silicon substrate and is made of a material having a thermal expansion coefficient different from the thermal expansion coefficient of the silicon substrate. As a result, the epitaxial substrate in which the occurrence of warpage caused by the stress between the silicon substrate and the semiconductor layer is suppressed is provided.

Abstract: Provided is a composite substrate manufacturing method, including at least: a first raw board deforming step of preparing a first substrate by deforming a first raw board having at least one surface as a minor surface into a state in which the minor surface warps outward; and a joining step of joining, after the first raw board deforming step, a protruding surface of the first substrate and one surface of a second substrate to each other, thereby manufacturing a composite substrate including the first substrate and the second substrate, in which the second substrate is any one substrate selected from a substrate having both surfaces as substantially flat surfaces and a substrate that warps so that a surface thereof to be joined to the first substrate warps outward. Also provided are a semiconductor element manufacturing method, a composite substrate and a semiconductor element manufactured.

Abstract: An assembly (60) includes a substrate (1) that is provided with at least one electrical contact (3a), a flexible printed circuit membrane (51) including an electrically insulating film (6) and an electrically conducting layer (7) that is at least partially covering the insulating film (6). The conducting layer (7) is at least locally accessible from outside of the membrane (51). A connection element (10) is provided for electrically connecting the at least one electrical contact (3a) and the conducting layer (7) at a position where the conducting layer (7) is accessible, to form an electrical connection between the substrate (1) and the membrane (51). A chip package (70) includes a housing (15) having at least one electrically conducting terminal, and an assembly (60) as mentioned. The flexible printed circuit membrane (51) is arranged for electrically connecting the substrate and the at least one terminal of the housing (15).

Abstract: A nitride semiconductor growth apparatus of the present invention comprises a chamber into which a reactive gas containing nitrogen is to be introduced as a material gas and a reaction part which is placed in the chamber and in which the material gas is brought into reaction to grow a nitride semiconductor. In the nitride semiconductor growth apparatus, in a region which includes a reaction part and part of an upstream side from a reaction part with respect to a flow of a material gas, portions to be in contact with the material gas (a gas introducing part, a current introducing part and a view port part and the like) are made from non-copper material (i.e., material containing no copper).

Abstract: A second epitaxial layer is grown epitaxially over a first epitaxial layer. The first epitaxial layer includes an epitaxially grown layer and a defect layer. The defect layer is disposed over the epitaxially grown layer and serves as a surface layer of the first epitaxial layer. The defect density of the defect layer is 5×1017 cm?2 or more. Defects penetrating through the defect layer form loops in the second epitaxial layer.

Abstract: Embodiments relate to semiconductor structures and methods of forming them. In some embodiments, the methods may be used to fabricate semiconductor structures of III-V materials, such as InGaN. An In-III-V semiconductor layer is grown with an Indium concentration above a saturation regime by adjusting growth conditions such as a temperature of a growth surface to create a super-saturation regime wherein the In-III-V semiconductor layer will grow with a diminished density of V-pits relative to the saturation regime.

Abstract: A step-flow growth of a group-III nitride single crystal on a silicon single crystal substrate is promoted. A layer of oxide oriented to a <111> axis of silicon single crystal is formed on a surface of a silicon single crystal substrate, and group-III nitride single crystal is crystallized on a surface of the layer of oxide. Thereupon, a <0001> axis of the group-III nitride single crystal undergoing crystal growth is oriented to a c-axis of the oxide. When the silicon single crystal substrate is provided with a miscut angle, step-flow growth of the group-III nitride single crystal occurs. By deoxidizing a silicon oxide layer formed at an interface of the silicon single crystal and the oxide, orientation of the oxide is improved.

Abstract: The purpose of the present invention is to provide a good ohmic contact for an n-type Group-III nitride semiconductor. An n-type GaN layer and a p-type GaN layer are aequentially formed on a lift-off layer (growth step). A p-side electrode is formed on the top face of the p-type GaN layer. A copper block is formed over the entire area of the top face through a cap metal. Then, the lift-off layer is removed by making a chemical treatment (lift-off step). Then, a laminate structure constituted by the n-type GaN layer, with which the surface of the N polar plane has been exposed, and the p-type GaN layer is subjected to anisotropic wet etching (surface etching step). The N-polar surface after the etching has irregularities constituted by {10-1-1} planes. Then, an n-side electrode is formed on the bottom face of the n-type GaN layer (electrode formation step).

Abstract: A compound semiconductor device includes: a substrate; an electron transit layer formed over the substrate; an electron supply layer formed over the electron transit layer; and a buffer layer formed between the substrate and the electron transit layer and including AlxGa1-xN(0?x?1), wherein the x value represents a plurality of maximums and a plurality of minimums in the direction of the thickness of the buffer layer, and the variation of x in any area having a 1 nm thickness in the buffer layer is 0.5 or less.

Abstract: Objects of the present invention are to provide a method for producing a Group III nitride semiconductor single crystal, which method enables production of a Group III nitride semiconductor single crystal having a flat surface by means of a crucible having any inside diameter; to provide a self-standing substrate obtained from the Group III nitride semiconductor single crystal; and to provide a semiconductor device employing the self-standing substrate. The production method includes adding the template, a flux, and semiconductor raw materials to a crucible and growing a Group III nitride semiconductor single crystal while the crucible is rotated. In the growth of the semiconductor single crystal, the crucible having an inside diameter R (mm) is rotated at a maximum rotation speed ? (rpm) satisfying the following conditions: ?1?4????1+4; ?1=10z; and z=?0.78×log10(R)+3.1.

Abstract: A semiconductor device that includes a Group III-V semiconductor substrate, circuit elements in and on the substrate, a first metal layer over the substrate, and an interlayer dielectric (ILD) layer. The ILD layer defines a via that extends through it to the first metal layer. Over the ILD layer is thick second metal layer and a passivation layer. The second metal layer includes an interconnect that extends through the via into contact with the first metal layer. The second metal layer is patterned to define at least one conductor. The passivation layer covers the second metal layer and the interlayer dielectric layer, and includes stacked regions of dielectric material. Ones of the regions under tensile stress alternate with ones of the regions under compressive stress, such that the passivation layer is subject to net compressive stress.

Abstract: A method of forming a group III-V material layer, a semiconductor device including the group III-V material layer, and a method of manufacturing the semiconductor device. The semiconductor device includes a substrate; a group III-V channel layer formed on the substrate; a gate insulating layer formed on the group III-V channel layer; and a gate electrode and source and drain electrodes formed on the gate insulating layer, the source and drain electrodes having intervals from the gate electrode, wherein voids exist between a lower portion of the group III-V channel layer and an insulating layer. The group III-V channel layer may include a binary, ternary, or quaternary material.

Abstract: There are disclosed herein various implementations of semiconductor structures including III-Nitride interlayer modules. One exemplary implementation comprises a substrate and a first transition body over the substrate. The first transition body has a first lattice parameter at a first surface and a second lattice parameter at a second surface opposite the first surface. The exemplary implementation further comprises a second transition body, such as a transition module, having a smaller lattice parameter at a lower surface overlying the second surface of the first transition body and a larger lattice parameter at an upper surface of the second transition body, as well as a III-Nitride semiconductor layer over the second transition body. The second transition body may consist of two or more transition modules, and each transition module may include two or more interlayers. The first and second transition bodies reduce strain for the semiconductor structure.

Abstract: The present invention relates to a LED (light-emitting diode) phosphor and fabricating method thereof, and particularly relates to a LED phosphor having a light-emitting thin film (or photoluminescence thin film) made of an organic material and a zinc oxide microstructure (or nanostructure) and a method for fabricating the LED phosphor by hydrothermal method and combination of the organic material and the zinc oxide microstructure (or nanostructure). In this invention, the light-emitting thin film (or photoluminescence thin film) made of the organic material and the zinc oxide microstructure (or nanostructure) is applied instead of rare earth elements to fabricate the LED phosphor. Therefore, the cost of the LED phosphor and the white LED can be reduced and the processes for fabricating the LED phosphor and the white LED can be simplified.

Abstract: A multilayer substrate structure comprises a substrate, a thermal matching layer formed on the substrate and a lattice matching layer above the thermal matching layer. The thermal matching layer includes at least one of molybdenum, molybdenum-copper, mullite, sapphire, graphite, aluminum-oxynitrides, silicon, silicon carbide, zinc oxides, and rare earth oxides. The lattice matching layer includes a first chemical element and a second chemical element to form an alloy. The first and second chemical element has similar crystal structures and chemical properties. The coefficient of thermal expansion of the thermal matching layer and the lattice parameter of the lattice matching layer are both approximately equal to that of a member of group III-V compound semiconductors. The lattice constant of the lattice matching layer is approximately equal to that of a member of group III-V compound semiconductor.

Abstract: In a semiconductor device 100, it is possible to prevent C from piling up at a boundary face between an epitaxial layer 22 and a group III nitride semiconductor substrate 10 by the presence of 30×1010 pieces/cm2 to 2000×1010 pieces/cm2 of sulfide in terms of S and 2 at % to 20 at % of oxide in terms of O in a surface layer 12. By thus preventing C from piling up, a high-resistivity layer is prevented from being formed on the boundary face between the epitaxial layer 22 and the group III nitride semiconductor substrate 10. Accordingly, it is possible to reduce electrical resistance at the boundary face between the epitaxial layer 22 and the group III nitride semiconductor substrate 10, and improve the crystal quality of the epitaxial layer 22. Consequently, it is possible to improve the emission intensity and yield of the semiconductor device 100.