Containing Germanium, Ge Patents (Class 257/616)
  • Patent number: 10522470
    Abstract: A package structure including a first semiconductor die, a second semiconductor die, a molding compound, an interconnect structure, first conductive features, through insulator vias, an insulating encapsulant and a redistribution layer is provided. The molding compound is encapsulating the first semiconductor die and the second semiconductor die. The interconnect structure is disposed on the molding compound and electrically connecting the first semiconductor die to the second semiconductor die. The first conductive features are electrically connected to the first semiconductor die and the second semiconductor die, wherein each of the first conductive features has a recessed portion. The through insulator vias are disposed on the recessed portion of the first conductive features and electrically connected to the first and second semiconductor die. The insulating encapsulant is encapsulating the interconnect structure and the through insulator vias.
    Type: Grant
    Filed: July 15, 2018
    Date of Patent: December 31, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jung-Hua Chang, Chin-Fu Kao
  • Patent number: 10438999
    Abstract: A switching device, according to one embodiment, includes: a cylindrical pillar gate contact, an annular cylindrical channel which encircles a portion of the cylindrical pillar gate contact, an annular cylindrical oxide layer which encircles a portion of the annular cylindrical channel, and a source contact tab which encircles a portion of the annular cylindrical channel toward a first end of the annular cylindrical channel. Other systems are also described in additional embodiments herein which provide various different switching devices having improved components including improved annular cylindrical channel structures, improved source contacts, and/or improved cylindrical pillar gate contacts. These improved systems and components thereof may be implemented in vertical annular transistor structures in comparison to conventional surface transistor structures.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: October 8, 2019
    Assignee: SPIN MEMORY, INC.
    Inventors: Gian Sharma, Amitay Levi, Andrew J. Walker, Kuk-Hwan Kim, Dafna Beery
  • Patent number: 10424482
    Abstract: A method for manufacturing a semiconductor device includes forming a plurality of amorphous silicon germanium (a-SiGe) structures having a first percentage of germanium on a substrate, forming a plurality of spacers on sides of the plurality of a-SiGe structures, performing an annealing to convert a portion of each of the a-SiGe structures into respective portions comprising a-SiGe having a second percentage of germanium higher than the first percentage of germanium, and to convert each of the spacers into respective silicon oxide portions, removing from the substrate at least one of: one or more unconverted portions of the a-SiGe structures having the first percentage of germanium, one or more of the converted portions of a-SiGe structures, and one or more of the silicon oxide portions, and transferring a pattern to the substrate to form a plurality of patterned substrate portions, wherein the pattern includes the portions remaining after the removing.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: September 24, 2019
    Assignee: International Business Machines Corporation
    Inventors: Peng Xu, Kangguo Cheng, Choonghyun Lee, Juntao Li
  • Patent number: 10411096
    Abstract: Various nanostructures, including silicon nanowires and encapsulated silicon nanoislands, and methods of making the nanostructures are provided. The methods can include providing a fin structure extending above a substrate, wherein the fin structure has at least one silicon layer and at least two silicon:germanium alloy (SiGe) layers that define sidewalls of the fin structure; and annealing the fin structure in oxygen to form a silicon nanowire assembly. The silicon nanowire assembly can include a silicon nanowire, a SiGe matrix surrounding the silicon nanowire; and a silicon oxide layer disposed on the SiGe matrix. The annealing can be, for example, at a temperature between 800° C. and 1000° C. for five minutes to sixty minutes. The silicon nanowire can have a long axis extending along the fin axis, with perpendicular first and second dimensions extending less than 50 nm along directions perpendicular to the fin axis.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: September 10, 2019
    Assignees: UNIVERSITY OF FLORIDA RESEARCH FOUNDATION, INC., VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Christopher Hatem, Kevin S. Jones, William M. Brewer
  • Patent number: 10304738
    Abstract: The present invention relates to a method for the production of layers of solid material, in particular for use as wafers. The method may include the following steps: providing a workpiece for the separation of the layers of solid material with the workpiece optionally having at least one exposed surface, producing and/or providing a carrier unit for receiving at least one layer of solid material having the carrier unit optionally having a receiving layer for holding the layer of solid material, attaching the receiving layer to the exposed surface of the workpiece forming a composite structure, producing a break initiation point by means of pre-defined local stress induction in the peripheral region, including at the edge, of the workpiece, and separating the layer of solid material from the workpiece starting from the break initiation point.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: May 28, 2019
    Assignee: Siltectra
    Inventors: Lukas Lichtensteiger, Wolfram Drescher
  • Patent number: 10211338
    Abstract: Integrated circuits including tunnel transistors and methods for fabricating such integrated circuits are provided. An exemplary method for fabricating an integrated device includes forming a lower source/drain region in and/or over a semiconductor substrate. The method forms a channel region overlying the lower source/drain region. The method also forms an upper source/drain region overlying the channel region. The method includes forming a gate structure beside the channel region.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: February 19, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Eng Huat Toh, Kiok Boone Elgin Quek
  • Patent number: 10170592
    Abstract: The present disclosure provides a method of fabricating a nonplanar circuit device. The method includes receiving a substrate having a first semiconductor layer of a first semiconductor material and a second semiconductor layer of a second semiconductor material on the first semiconductor layer, wherein the second semiconductor material is different from the first semiconductor material in composition. The method further includes patterning the first and second semiconductor layers to form a fin structure in the first and second semiconductor layers. The method further includes performing a selective oxidization process to the first semiconductor layer such that a bottom portion of the first semiconductor layer is oxidized.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: January 1, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Kuo-Cheng Ching, Guan-Lin Chen
  • Patent number: 10163933
    Abstract: Methods of forming a buffer layer to imprint ferroelectric phase in a ferroelectric layer and the resulting devices are provided. Embodiments include forming a substrate; forming a buffer layer over the substrate; forming a ferroelectric layer over the buffer layer; forming a channel layer over the ferroelectric layer; forming a gate oxide layer over a portion of the channel layer; and forming a gate over the gate oxide layer.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: December 25, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ralf Richter, Stefan Dünkel, Martin Trentzsch, Sven Beyer
  • Patent number: 10115824
    Abstract: A method for fabricating a semiconductor device includes forming a gate stack on a semiconductor substrate, forming a source/drain region on an exposed portion of the substrate, and forming a semiconductor material layer on the source/drain region. A first liner layer is deposited on the semiconductor material layer, and a second liner layer is deposited on the first liner layer. A conductive contact material is deposited on the second liner layer.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: October 30, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Oleg Gluschenkov, Zuoguang Liu, Shogo Mochizuki, Hiroaki Niimi, Ruilong Xie
  • Patent number: 10074814
    Abstract: The present invention provides novel two-dimensional van der Waals materials and stacks of those materials. Also provided are methods of making and using such materials.
    Type: Grant
    Filed: April 3, 2014
    Date of Patent: September 11, 2018
    Assignee: OHIO STATE INNOVATION FOUNDATION
    Inventors: Joshua Goldberger, Shishi Jiang, Elisabeth Bianco
  • Patent number: 9994736
    Abstract: A CMP slurry composition which provides for a high Ge- or SiGe-to-dielectric material selectivity a low rate of Ge or SiGe recess formation includes an oxidant and a germanium removal rate enhancer including at least one of a methylpyridine compound and a methylpyridine derivative compound. In some examples, the slurry composition also includes an etching inhibitor. In some cases, the slurry composition may include an abrasive, a surfactant, an organic complexant, a chelating agent, an organic or inorganic acid, an organic or inorganic base, a corrosion inhibitor, or a buffer. The slurry composition may be distributed onto a surface of a polishing pad disposed on a platen that is configured to rotate. Additionally, a workpiece carrier configured to house a substrate may bring the substrate into contact with the rotating polishing pad and thereby polish the substrate utilizing the slurry composition.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: June 12, 2018
    Assignees: Taiwan Semiconductor Manufacturing Company, Ltd., UWIZ Technology Co., Ltd.
    Inventors: Chia-Jung Hsu, Yun-Lung Ho, Neng-Kuo Chen, Song-Yuan Chang, Teng-Chun Tsai
  • Patent number: 9917060
    Abstract: A method for fabricating a semiconductor device includes forming a gate stack on a semiconductor substrate, forming a source/drain region on an exposed portion of the substrate, and forming a semiconductor material layer on the source/drain region. A first liner layer is deposited on the semiconductor material layer, and a second liner layer is deposited on the first liner layer. A conductive contact material is deposited on the second liner layer.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: March 13, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Oleg Gluschenkov, Zuoguang Liu, Shogo Mochizuki, Hiroaki Niimi, Ruilong Xie
  • Patent number: 9721827
    Abstract: One or more semiconductor arrangements are provided. The semiconductor arrangements include a buried layer over a well, a dielectric layer over the buried layer, a first gate stack over the dielectric layer and a S/D region disposed proximate the first gate stack. The S/D region has a first tip proximity region that extends under the first gate stack. One or more methods of forming a semiconductor arrangement are also provided. The methods include forming a S/D recess in at least one of a dielectric layer, a buried layer or a well, wherein the S/D recess is proximate a first gate stack and has a first recess tip proximity region that extends under the first gate stack as a function of the buried layer, and forming a S/D region in the S/D recess such that the S/D region has a first tip proximity region that extends under the first gate stack.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: August 1, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Wei-Fan Lee, Yuan-feng Chao, Yen Chuang
  • Patent number: 9553031
    Abstract: A method for making an integrated circuit includes a) providing a substrate including n-type metal oxide semiconductor field effect transistors (NMOSFETs) and p-type metal oxide semiconductor field effect transistors (PMOSFETs), wherein channel regions of the NMOSFETs and the PMOSFETs include germanium; b) depositing and patterning a mask layer to mask the channel regions of the PMOSFETs and to not mask the channel regions of the NMOSFETs; c) passivating an exposed surface of the substrate; d) removing the mask layer; and e) depositing a metal contact layer on both the NMOSFETs and the PMOSFETs.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: January 24, 2017
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Paul Raymond Besser, Thorsten Lill
  • Patent number: 9478658
    Abstract: A device and method for inducing stress in a semiconductor layer includes providing a substrate having a dielectric layer formed between a first semiconductor layer and a second semiconductor layer and processing the second semiconductor layer to form an amorphized material. A stress layer is deposited on the first semiconductor layer. The wafer is annealed to memorize stress in the second semiconductor layer by recrystallizing the amorphized material.
    Type: Grant
    Filed: May 20, 2015
    Date of Patent: October 25, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Pranita Kulkarni, Ghavam G. Shahidi
  • Patent number: 9455141
    Abstract: Embodiments of the invention include a method for fabricating a SiGe fin and the resulting structure. A SOI substrate is provided, including at least a silicon layer on top of a BOX. At least one fin upon a thin layer of silicon and a hard mask layer over the at least one fin is formed using the silicon layer on top of the BOX. A SiGe layer is epitaxially grown from exposed portions of the fin and the thin layer of silicon. Spacers are formed on sidewalls of the hard mask. Regions of the SiGe layer and the thin layer of silicon not protected by the spacers are etched, such that portions of the BOX are exposed. A condensation process converts the fin to SiGe and to convert the SiGe layer to oxide. The hard mask, the spacers, and the oxide layer are removed.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: September 27, 2016
    Assignee: GlobalFoundries, Inc.
    Inventors: Kanggou Cheng, Ali Khakifirooz, Alexander Reznicek, Dominic J. Schepis
  • Patent number: 9385110
    Abstract: A link device with a large density routing is attached to a package in order to provide a high-density interconnect pathway to interconnect semiconductor devices. In an embodiment the package is an integrated fan out package. The link device may be bonded on either side of the package, and the package may optionally comprise through package vias. The link device may also be an integrated passive device that includes resistors, inductor, and capacitor components.
    Type: Grant
    Filed: August 19, 2014
    Date of Patent: July 5, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Yang Yeh, Ming-Tsun Lin, Hau Tao
  • Patent number: 9330905
    Abstract: A semiconductor device, in which the generation of interface states in the interface region between a nitride semiconductor layer and an aluminum oxide layer is suppressed, includes a first nitride semiconductor layer and an aluminum oxide layer. The first nitride semiconductor layer includes Ga. The aluminum oxide layer directly contacts the upper surface of the first nitride semiconductor layer, and includes H (hydrogen) atoms at least within a defined region from the interface with the first nitride semiconductor layer. In addition, the peak value of an H atom concentration in the above region is in a range of 1×1020 cm?3 to 5×1021 cm?3.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: May 3, 2016
    Assignee: Renesas Electronics Corporation
    Inventor: Takashi Onizawa
  • Patent number: 9123702
    Abstract: Methods and devices for connecting a through via and a terminal of a transistor formed of a strained silicon material are provided. The terminal, which can be a source or a drain of a NMOS or a PMOS transistor, is formed within a substrate. A first contact within a first inter-layer dielectric (ILD) layer over the substrate is formed over and connected to the terminal. A through via extends through the first ILD layer into the substrate. A second contact is formed over and connected to the first contact and the through via within a second ILD layer and a contact etch stop layer (CESL). The second ILD layer is over the CESL, and the CESL is over the first ILD layer, which are all below a first inter-metal dielectric (IMD) layer and the first metal layer of the transistor.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: September 1, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Yu-Young Wang, Sen-Bor Jan
  • Patent number: 9093554
    Abstract: In one example, a method disclosed herein includes the steps of forming a gate structure for a first transistor and a second transistor above a semiconducting substrate, forming a liner layer above the gate structures and performing a plurality of extension ion implant processes through the liner layer to form extension implant regions in the substrate for the first transistor and the second transistor. The method further includes forming a first sidewall spacer proximate the gate structure for the first transistor and a patterned hard mask layer positioned above the second transistor, performing at least one etching process to remove the first sidewall spacer, the patterned hard mask layer and the liner layer, forming a second sidewall spacer proximate both of the gate structures and performing a plurality of source/drain ion implant processes to form deep source/drain implant regions in the substrate for the first transistor and the second transistor.
    Type: Grant
    Filed: May 14, 2012
    Date of Patent: July 28, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stefan Flachowsky, Ricardo P. Mikalo, Jan Hoentschel
  • Patent number: 9048167
    Abstract: A semiconductor device and a method for fabricating a semiconductor device involve a semiconductor layer that includes a first material and a second material. The first and second materials can be silicon and germanium. A contact of the device has a portion proximal to the semiconductor layer and a portion distal to the semiconductor layer. The distal portion includes the first material and the second material. A metal layer formed adjacent to the relaxed semiconductor layer and adjacent to the distal portion of the contact is simultaneously reacted with the relaxed semiconductor layer and with the distal portion of the contact to provide metallic contact material.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: June 2, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Matthew T. Currie, Richard Hammond
  • Patent number: 9035430
    Abstract: A semiconductor substrate including a first epitaxial semiconductor layer is provided. The first epitaxial semiconductor layer includes a first semiconductor material, and can be formed on an underlying epitaxial substrate layer, or can be the entirety of the semiconductor substrate. A second epitaxial semiconductor layer including a second semiconductor material is epitaxially formed upon the first epitaxial semiconductor layer. Semiconductor fins including portions of the second single crystalline semiconductor material are formed by patterning the second epitaxial semiconductor layer employing the first epitaxial semiconductor layer as an etch stop layer. At least an upper portion of the first epitaxial semiconductor layer is oxidized to provide a localized oxide layer that electrically isolates the semiconductor fins.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: May 19, 2015
    Assignee: International Business Machines Corporation
    Inventors: Reinaldo A. Vega, Michael V. Aquilino, Daniel J. Jaeger
  • Publication number: 20150123146
    Abstract: A semiconductor structure includes a bulk silicon substrate and one or more silicon fins coupled to the bulk silicon substrate. Stress-inducing material(s), such as silicon, are epitaxially grown on the fins into naturally diamond-shaped structures using a controlled selective epitaxial growth. The diamond shaped structures are subjected to annealing at about 750° C. to about 850° C. to increase an area of (100) surface orientation by reshaping the shaped structures from the annealing. Additional epitaxy is grown on the increased (100) area. Multiple cycles of increasing the area of (100) surface orientation (e.g., by the annealing) and growing additional epitaxy on the increased area are performed to decrease the width of the shaped structures, increasing the space between them to prevent them from merging, while also increasing their volume.
    Type: Application
    Filed: November 4, 2013
    Publication date: May 7, 2015
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Bharat KRISHNAN, Jody A. FRONHEISER, Jinping LIU, Bongki LEE
  • Publication number: 20150102465
    Abstract: Suspended structures are provided using selective etch technology. Such structures can be protected on all sides when the selective undercut etch is performed, thereby providing excellent control of feature geometry combined with superior material quality.
    Type: Application
    Filed: October 10, 2014
    Publication date: April 16, 2015
    Inventors: Robert Chen, James S. Harris, JR., Suyog Gupta
  • Patent number: 9006720
    Abstract: Laser pyrolysis reactor designs and corresponding reactant inlet nozzles are described to provide desirable particle quenching that is particularly suitable for the synthesis of elemental silicon particles. In particular, the nozzles can have a design to encourage nucleation and quenching with inert gas based on a significant flow of inert gas surrounding the reactant precursor flow and with a large inert entrainment flow effectively surrounding the reactant precursor and quench gas flows. Improved silicon nanoparticle inks are described that has silicon nanoparticles without any surface modification with organic compounds. The silicon ink properties can be engineered for particular printing applications, such as inkjet printing, gravure printing or screen printing. Appropriate processing methods are described to provide flexibility for ink designs without surface modifying the silicon nanoparticles.
    Type: Grant
    Filed: April 8, 2013
    Date of Patent: April 14, 2015
    Assignee: NanoGram Corporation
    Inventors: Shivkumar Chiruvolu, Igor Altman, Bernard M. Frey, Weidong Li, Guojun Liu, Robert B. Lynch, Gina Elizabeth Pengra-Leung, Uma Srinivasan
  • Publication number: 20150048485
    Abstract: Methods of forming germanium-tin films using germane as a precursor are disclosed. Exemplary methods include growing films including germanium and tin in an epitaxial chemical vapor deposition reactor, wherein a ratio of a tin precursor to germane is less than 0.1. Also disclosed are structures and devices including germanium-tin films formed using the methods described herein.
    Type: Application
    Filed: August 14, 2013
    Publication date: February 19, 2015
    Applicant: ASM IP Holding B.V.
    Inventor: John Tolle
  • Patent number: 8952419
    Abstract: A semiconductor device includes a substrate, a buffer layer on the substrate, and a plurality of nitride semiconductor layers on the buffer layer. The semiconductor device further includes at least one masking layer and at least one inter layer between the plurality of nitride semiconductor layers. The at least one inter layer is on the at least one masking layer.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: February 10, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-jo Tak, Jae-won Lee, Young-soo Park, Jun-youn Kim
  • Publication number: 20150028454
    Abstract: Silicon and silicon germanium fins are formed on a semiconductor wafer or other substrate in a manner that facilitates production of closely spaced nFET and pFET devices. A patterned mandrel layer is employed for forming one or more recesses in the wafer prior to the epitaxial growth of a silicon germanium layer that fills the recess. Spacers are formed on the side walls of the patterned mandrel layer followed by removal of the mandrel layer. The exposed areas of the wafer and silicon germanium layer between the spacers are etched to form fins usable for nFET devices from the wafer and fins usable for pFET devices from the silicon germanium layer.
    Type: Application
    Filed: July 24, 2013
    Publication date: January 29, 2015
    Inventors: KANGGUO CHENG, ALI KHAKIFIROOZ, ALEXANDER REZNICEK, GHAVAM G. SHAHIDI
  • Patent number: 8927376
    Abstract: A method for forming epitaxial layer is disclosed. The method includes the steps of providing a semiconductor substrate, and forming an undoped first epitaxial layer in the semiconductor substrate. Preferably, the semiconductor substrate includes at least a recess, the undoped first epitaxial layer has a lattice constant, a bottom thickness, and a side thickness, in which the lattice constant is different from a lattice constant of the semiconductor substrate and the bottom thickness is substantially larger than or equal to the side thickness.
    Type: Grant
    Filed: April 24, 2014
    Date of Patent: January 6, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Chin-I Liao, Teng-Chun Hsuan, Chin-Cheng Chien
  • Patent number: 8921210
    Abstract: A method of forming a semiconductive substrate material for an electronic device including forming a plurality of semiconductive layers on a substrate during a continuous growth process in a reaction chamber, wherein during the continuous growth process, a release layer is formed between a base layer and an epitaxial layer by altering at least one growth process parameter during the continuous growth process. The method also including separating the plurality of semiconductive layers from the substrate.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: December 30, 2014
    Assignee: Saint-Gobain Cristaux et Detecteurs
    Inventors: Jean-Pierre Faurie, Bernard Beaumont
  • Patent number: 8901566
    Abstract: A semiconductor device and method of manufacturing a semiconductor device. The semiconductor device includes channels for a pFET and an nFET. A SiGe layer is selectively grown in the source and drain regions of the pFET channel and a Si:C layer is selectively grown in source and drain regions of the nFET channel. The SiGe and Si:C layer match a lattice network of the underlying Si layer to create a stress component. In one implementation, this causes a compressive component in the pFET channel and a tensile component in the nFET channel.
    Type: Grant
    Filed: August 31, 2007
    Date of Patent: December 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Huajie Chen, Dureseti Chidambarrao, Omer H. Dokumaci
  • Patent number: 8883573
    Abstract: The present disclosure relates to the field of fabricating microelectronic devices. In at least one embodiment, the present disclosure relates to forming an isolated nanowire, wherein isolation structure adjacent the nanowire provides a substantially level surface for the formation of microelectronic structures thereon.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: November 11, 2014
    Assignee: Intel Corporation
    Inventors: Uday Shah, Benjamin Chu-Kung, Been-Yih Jin, Ravi Pillarisetty, Marko Radosavljevic, Willy Rachmady
  • Publication number: 20140312301
    Abstract: Described is a method for producing a semiconductor device (100), in which at least one column-shaped or wall-shaped semiconductor device (10, 20) extending in a main direction (z) is formed on a substrate (30), wherein at least two sections (11, 13, 21, 23) of a first crystal type and one section (12, 22) of a second crystal type therebetween are formed in an active region (40), each section with a respective predetermined height (h1, h2), wherein the first and second crystal types have different lattice constants and each of the sections of the first crystal type has a lattice strain which depends on the lattice constants in the section of the second crystal type.
    Type: Application
    Filed: November 9, 2012
    Publication date: October 23, 2014
    Applicant: Forschungsverbund Berlin e.V.
    Inventors: Oliver Brandt, Lutz Geelhaar, Vladimir Kaganer, Martin Woelz
  • Publication number: 20140284769
    Abstract: The present disclosure concerns a method involving: forming a strained silicon germanium layer by epitaxial growth over a silicon layer disposed on a substrate; implanting atoms to amorphize the silicon layer and a lower portion of the silicon germanium layer, without amorphizing a surface portion of the silicon germanium layer; and annealing, to at least partially relax the silicon germanium layer and to re-crystallize the lower portion of the silicon germanium layer and the silicon layer, so that the silicon layer becomes a strained silicon layer.
    Type: Application
    Filed: March 20, 2014
    Publication date: September 25, 2014
    Inventors: Aomar Halimaoui, Jean-Michel Hartmann
  • Publication number: 20140264755
    Abstract: Various embodiments form silicon and silicon germanium fins on a semiconductor wafer. In one embodiment a semiconductor wafer is obtained. The semiconductor wafer comprises a substrate, a dielectric layer, and a semiconductor layer including silicon germanium (SiGe). At least one SiGe fin is formed from at least a first SiGe region of the semiconductor layer in at least one PFET region of the semiconductor wafer. Strained silicon is epitaxially grown on at least a second SiGe region of the semiconductor layer. At least one strained silicon fin is formed from the strained silicon in at least one NFET region of the semiconductor wafer.
    Type: Application
    Filed: March 13, 2013
    Publication date: September 18, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: INTERNATIONAL BUSINESS MACHINES CORPORATION
  • Publication number: 20140252555
    Abstract: According to one embodiment, a substrate for forming elements includes a substrate; an insulating film provided on the substrate; and a Ge layer or an SiGe layer bonded to the substrate via the insulating film. The insulating film is a laminated structure comprising a plurality of films including an oxide film, a high-dielectric constant insulating film, and a compound insulating film including a metal element and Ge.
    Type: Application
    Filed: May 16, 2014
    Publication date: September 11, 2014
    Inventor: Keiji IKEDA
  • Patent number: 8823143
    Abstract: Methods for electrodepositing germanium on various semiconductor substrates such as Si, Ge, SiGe, and GaAs are provided. The electrodeposited germanium can be formed as a blanket or patterned film, and may be crystallized by solid phase epitaxy to the orientation of the underlying semiconductor substrate by subsequent annealing. These plated germanium layers may be used as the channel regions of high-mobility channel field effect transistors (FETs) in complementary metal oxide semiconductor (CMOS) circuits.
    Type: Grant
    Filed: August 14, 2009
    Date of Patent: September 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Hariklia Deligianni, Qiang Huang, Lubomyr T. Romankiw, Devendra K. Sadana, Katherine L. Saenger
  • Patent number: 8821635
    Abstract: Si—Ge materials are grown on Si(100) with Ge-rich contents (Ge>50 at. %) and precise stoichiometries SiGe, SiGe2, SiGe3 and SiGe4. New hydrides with direct Si—Ge bonds derived from the family of compounds (H3Ge)xSiH4-x (x=1-4) are used to grow uniform, relaxed, and highly planar films with low defect densities at unprecedented low temperatures between about 300-450° C. At about 500-700° C., SiGex quantum dots are grown with narrow size distribution, defect-free microstructures and highly homogeneous elemental content at the atomic level. The method provides for precise control of morphology, composition, structure and strain. The grown materials possess the required characteristics for high frequency electronic and optical applications, and for templates and buffer layers for high mobility Si and Ge channel devices.
    Type: Grant
    Filed: April 8, 2005
    Date of Patent: September 2, 2014
    Assignee: Arizona Board of Regents on Behalf of Arizona State University
    Inventors: John Kouvetakis, Ignatius S. T. Tsong, Changwu Hu, John Tolle
  • Patent number: 8816401
    Abstract: Structures and methods of making a heterojunction bipolar transistor (HBT) device that include: an n-type collector region disposed within a crystalline silicon layer; a p-type intrinsic base comprising a boron-doped silicon germanium crystal that is disposed on a top surface of an underlying crystalline Si layer, which is bounded by shallow trench isolators (STIs), and that forms angled facets on interfaces of the underlying crystalline Si layer with the shallow trench isolators (STIs); a Ge-rich, crystalline silicon germanium layer that is disposed on the angled facets and not on a top surface of the p-type intrinsic base; and an n-type crystalline emitter disposed on a top surface and not on the angled lateral facets of the p-type intrinsic base.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: August 26, 2014
    Assignee: International Business Machines Corporation
    Inventors: Renata A. Camillo-Castillo, Jeffrey B. Johnson
  • Patent number: 8809906
    Abstract: A semiconductor optical device includes a first clad layer, a second clad layer and an optical waveguide layer sandwiched between the first clad layer and the second clad layer, wherein the optical waveguide layer includes a first semiconductor layer, a second semiconductor layer disposed on the first semiconductor layer and extending in one direction, and a third semiconductor layer covering a top surface of the second semiconductor layer, and wherein the first semiconductor layer includes an n-type region disposed on one side of the second semiconductor layer, a p-type region disposed on the other side of the second semiconductor layer, and an i-type region disposed between the n-type region and the p-type region, and wherein the second semiconductor layer has a band gap narrower than band gaps of the first semiconductor layer and the third semiconductor layer.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: August 19, 2014
    Assignee: Fujitsu Limited
    Inventors: Lei Zhu, Shigeaki Sekiguchi, Shinsuke Tanaka, Kenichi Kawaguchi
  • Patent number: 8802963
    Abstract: A thermoelectric conversion material is provided, in which only a desired crystal is selectively precipitated. An MxV2O5 crystal is selectively precipitated in vanadium-based glass, wherein M is one metal element selected from the group consisting of iron, arsenic, antimony, bismuth, tungsten, molybdenum, manganese, nickel, copper, silver, an alkali metal and an alkaline earth metal, and 0<x<1.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: August 12, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Tadashi Fujieda, Takashi Naito, Takuya Aoyagi
  • Publication number: 20140217554
    Abstract: A crystal laminate structure, in which crystals can be epitaxially grown on a ?-Ga2O3-based substrate with high efficiency to produce a high-quality ?-Ga2O3-based crystal film on the substrate; and a method for producing the crystal laminate structure are provided. The crystal laminate structure includes: a ?-Ga2O3-based substrate, of which the major face is a face that is rotated by 50 to 90° inclusive with respect to face; and a ?-Ga2O3-based crystal film which is formed by the epitaxial crystal growth on the major face of the ?-Ga2O3-based substrate.
    Type: Application
    Filed: August 2, 2012
    Publication date: August 7, 2014
    Applicant: TAMURA CORPORATION
    Inventor: Kohei Sasaki
  • Patent number: 8796788
    Abstract: An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides a processing for forming improved source/drain features in the semiconductor device. Semiconductor devices with the improved source/drain features may prevent or reduce defects and achieve high strain effect resulting from epi layers. In an embodiment, the source/drain features comprises a second portion surrounding a first portion, and a third portion between the second portion and the semiconductor substrate, wherein the second portion has a composition different from the first and third portions.
    Type: Grant
    Filed: January 19, 2011
    Date of Patent: August 5, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsz-Mei Kwok, Hsueh-Chang Sung, Kuan-Yu Chen, Hsien-Hsin Lin
  • Patent number: 8796807
    Abstract: By incorporating germanium material into thermal sensing diode structures, the sensitivity thereof may be significantly increased. In some illustrative embodiments, the process for incorporating the germanium material may be performed with high compatibility with a process flow for incorporating a silicon/germanium material into P-channel transistors of sophisticated semiconductor devices. Hence, temperature control efficiency may be increased with reduced die area consumption.
    Type: Grant
    Filed: October 3, 2011
    Date of Patent: August 5, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Rolf Stephan, Markus Forsberg, Gert Burbach, Anthony Mowry
  • Patent number: 8796744
    Abstract: The present invention discloses a semiconductor device, which comprises a substrate, a buffer layer on the substrate, an inversely doped isolation layer on the buffer layer, a barrier layer on the inversely doped isolation layer, a channel layer on the barrier layer, a gate stack structure on the channel layer, and source and drain regions at both sides of the gate stack structure, characterized in that the buffer layer and/or the barrier layer and/or the inversely doped isolation layer are formed of SiGe alloys or SiGeSn alloys, and the channel layer is formed of a GeSn alloy. The semiconductor device according to the present invention uses a quantum well structure of SiGe/GeSn/SiGe to restrict transportation of carriers, and it introduces a stress through lattice mis-match to greatly increase the carrier mobility, thus improving the device driving capability so as to be adapted to high-speed and high-frequency application.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: August 5, 2014
    Assignee: The Institute of Microelectronics Chinese Academy of Science
    Inventors: Xiaolong Ma, Huaxiang Yin, Sen Xu, Huilong Zhu
  • Patent number: 8772878
    Abstract: A silicon/germanium material and a silicon/carbon material may be provided in transistors of different conductivity type on the basis of an appropriate manufacturing regime without unduly contributing to overall process complexity. Furthermore, appropriate implantation species may be provided through exposed surface areas of the cavities prior to forming the corresponding strained semiconductor alloy, thereby additionally contributing to enhanced overall transistor performance. In other embodiments a silicon/carbon material may be formed in a P-channel transistor and an N-channel transistor, while the corresponding tensile strain component may be overcompensated for by means of a stress memorization technique in the P-channel transistor. Thus, the advantageous effects of the carbon species, such as enhancing overall dopant profile of P-channel transistors, may be combined with an efficient strain component while enhanced overall process uniformity may also be accomplished.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: July 8, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jan Hoentschel, Vassilios Papageorgiou, Belinda Hannon
  • Publication number: 20140167223
    Abstract: A system and a method of self-cooling a semiconductor package are described. A cell is formed, which contains a thermally conductive and electrically insulative material, sandwiched between a first thermally conductive plate and a second thermally conductive plate. A plurality of integrated circuits are formed by combinatorial processing. The plurality of integrated circuits are interconnected into a semiconductor integrated circuit package. The cell is thermally bonded to the semiconductor integrated circuit package. The first thermally conductive plate is electrically connected to the semiconductor integrated circuit package. A current is supplied to the second thermally conductive plate by an electrical lead from a supply voltage. Power is provided in series to the semiconductor integrated circuit package and through the cell.
    Type: Application
    Filed: December 17, 2012
    Publication date: June 19, 2014
    Applicant: INTERMOLECULAR, INC.
    Inventor: Tony W. Firth
  • Patent number: 8754448
    Abstract: A semiconductor device includes a semiconductor substrate and a plurality of transistors. The semiconductor substrate includes at least an iso region (namely an open region) and at least a dense region. The transistors are disposed in the iso region and the dense region respectively. Each transistor includes at least a source/drain region. The source/drain region includes a first epitaxial layer having a bottom thickness and a side thickness, and the bottom thickness is substantially larger than or equal to the side thickness.
    Type: Grant
    Filed: November 1, 2011
    Date of Patent: June 17, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chin-I Liao, Teng-Chun Hsuan, Chin-Cheng Chien
  • Patent number: 8748269
    Abstract: Quantum-well-based semiconductor devices and methods of forming quantum-well-based semiconductor devices are described. A method includes providing a hetero-structure disposed above a substrate and including a quantum-well channel region. The method also includes forming a source and drain material region above the quantum-well channel region. The method also includes forming a trench in the source and drain material region to provide a source region separated from a drain region. The method also includes forming a gate dielectric layer in the trench, between the source and drain regions; and forming a gate electrode in the trench, above the gate dielectric layer.
    Type: Grant
    Filed: August 16, 2013
    Date of Patent: June 10, 2014
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Marko Radosavljevic, Ravi Pillarisetty, Robert S. Chau, Matthew V. Metz
  • Patent number: 8742628
    Abstract: A solid state circuit breaker includes a first terminal; a second terminal; a first wide-band gap field effect transistor coupled to the first terminal; a second wide-band gap field effect transistor coupled to the second terminal, wherein the first wide-band gap field effect transistor and the second wide-band gap field effect transistor are common-source connected to one another; and a bi-directional snubber device coupled to the first wide-band gap field effect transistor and the second wide-band gap field effect transistor. Such a solid state circuit breaker may also include a gate drive circuit coupled to the first wide-band gap field effect transistor and the second wide-band gap field effect transistor, where the gate drive circuit may comprise a voltage regulation stage and a drive stage.
    Type: Grant
    Filed: April 28, 2010
    Date of Patent: June 3, 2014
    Assignee: The United States of America as represented by the Secretary of the Army
    Inventor: Damian P. Urciuoli