Abstract: A substrate for integrated components including a support structure and a thin non-conductive film. An intermediate film is placed between the support structure and the thin non-conductive film. The intermediate film is a sacrificial film which may be removed chemically. By doing so, the thin non-conductive film may be liberated from the support structure. The intermediate film is traversed by channels which carry the chemicals for removing the sacrificial film. The channels may form a grid on the surface of the intermediate film.

Abstract: A microelectronic integrated circuit includes a semiconductor substrate, and a plurality of microelectronic devices formed on the substrate. Each device has a periphery defined by a hexagon, and includes an active area formed within the periphery. A first terminal and a second terminal are formed in the active area adjacent to edges of the hexagon that are separated by another edge. First to third gates are formed between the first and second terminals, and have gate terminals formed outside the active area adjacent to other edges of the hexagon. The power supply connections to the first and second terminals, the conductivity type (NMOS or PMOS), and the addition of a pull-up or a pull-down resistor is selected for each device to provide a desired AND, NAND, OR or NOR function. The devices are interconnected using three direction routing based on hexagonal geometry.

Abstract: Micromechanical microwave switches with both ohmic and capacitive coupling of rf lines and integration in multiple throw switches useful in microwave arrays.

Abstract: A semiconductor device is produced through electrolytic etching process. The device comprises a P-type silicon substrate. An N-type epitaxial layer is formed on the silicon substrate. P-type regions are defined in the N-type epitaxial layer. N-type regions are defined in some of the P-type regions. A first wiring layer connects to predetermined ones of the P-type regions. A second wiring layer connects to predetermined ones of the N-type regions. The semiconductor device has a given part which has such a possibility that a predetermined magnitude of leakage current flows therethrough between the first and second wiring layers when subjected to the electrolytic etching process. The semiconductor device further has a circuit which is electrically connected to one of the first and second wiring layers. The circuit is capable of removing the possibility of the leakage current flow through the given part when opened.

Abstract: Mesa diodes of improved mechanical properties are formed by providing a central depression in the regions of the chip from which the mesa is formed before the diffusion step that forms the rectifying junction in the mesa. In symmetric diodes, symmetric depressions are formed on both the top and bottom surfaces of the chip.

Abstract: General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.

Abstract: Fabrication of semiconductor devices with movable structures includes local oxidation of a wafer and oxide removal to form a depression in an elevated bonding surface. A second wafer is fusion bonded to the elevated bonding surface and shaped to form a flexible membrane. An alternative fabrication technique forms a spacer having a depression on a first wafer and active regions on a second wafer, and fusion bonds the wafers together with the depression over the active regions. Devices formed are integrable with standard MOS devices and include FETs, capacitors, and sensors with movable membranes. An FET sensor has gate and drain coupled together and a drain-source voltage which depends on the gate's deflection. Selected operating current, channel length, and channel width provide a drain-source voltage linearly related to gate deflection.

Abstract: A microelectronic integrated circuit includes a semiconductor substrate, and a plurality of microelectronic devices formed on the substrate. Each device has a periphery defined by a hexagon, and includes an active area formed within the periphery, a central terminal formed in a central portion of the active area, and interconnected first to third terminals formed in the active area adjacent to edges of the hexagon that are separated by other edges. First to third gates are formed between the first to third terminals respectively and the central terminal, and have contacts formed outside the active area adjacent to the other edges of the hexagon. The power supply connections to the central terminal and the first to third terminals, the conductivity type (NMOS or PMOS), and the addition of a pull-up or a pull-down resistor is selected for each device to provide a desired OR, NOR, AND or NAND function. The devices are interconnected using three direction routing based on hexagonal geometry.

Abstract: A liquid crystal image display unit created on a substrate non-transparent to the light in the visible radiation area, characterized in that a portion beneath a liquid crystal pixel part on said substrate is removed, so that the light is made transmissive through said liquid crystal pixel part.

Abstract: A semiconductor sensor comprising a semiconductor substrate and a glass substrate. The semiconductor substrate includes a support member having an opening centrally defined therein, a diaphragm positioned in the opening of the support member, and a flexible supporting means for supporting and coupling the diaphragm and the support member. The glass substrate includes a portion facing the diaphragm and the supporting means and at least one recess defined in this portion which faces the entirety of the supporting means. The glass substrate also includes a metal layer deposited on a surface of the glass substrate and a dielectric layer deposited on the metal layer such that the dielectric layer faces the diaphragm.

Abstract: A semiconductor device comprises a piezoresistive pressure sensor (12), which has a membrane (14), which is constituted by a conducting epitaxy layer (16), which is applied to a conducting semiconductor substrate (18) of the opposite conductivity. On the outer surface (20) of the membrane facing away from the semiconductor substrate (18) at least one piezoresistor (22) is incorporated. Between the semiconductor substrate (18) and the epitaxy layer (16) an annularly structured intermediate layer (28) is incorporated, which defines a region (26'), adjoining the inner surface (24) of the membrane, of an opening (26) extending through the semiconductor substrate (18). This opening (26) is produced by anisotropic semiconductor etching, the intermediate layer (28) having a conductivity which is opposite to that of the semiconductor substrate so that this intermediate layer (28) functions as an etch stopping means and is not attacked by the etchant.

Abstract: A semiconductor device having a high-speed device and a uniform plane bearing is provided. Device formation regions (51, 52, and 55) are formed on upper surfaces of the silicon substrate (21 and 22), and device isolation regions (9) acting as insulating layer are formed therebetween. The silicon substrate is etched to shape a bottom recessed part (8). The bottom recessed part (8) is formed in such a manner that it borders on the device isolation region (9) and allows the device formation regions (51, 52, and 55) to be emerged therefrom. This structure enables a pn junction to be eliminated, realizing a semiconductor device capable of high-speed operation. Further, each device is formed in an N.sup.- type silicon layer (22) which is grown from the silicon substrate, and thereafter is insulated by forming the bottom recessed part (8). Accordingly, the semiconductor device has a uniform plane bearing.

Abstract: A miniature electronic element is provided formed of and within a single crystal of semiconductor material on which are formed top and bottom surface layers of an oxide of the semiconductor material, and including at least one isolated island of semiconductor material formed in the remaining material between the top and bottom surface layers. Contact members may be attached in predetermined spatial relation to at least one of the top and bottom surface layers and extend through the one surface to the island of material connecting thereto in spaced relation, whereby the material of the island between the contact members provides an electrical path of predetermined value between the contact members. An isolating chamber (or chambers) is formed between the surface layers around the isolated island of material to provide thermal isolation to the island of material.

Abstract: Stress sensitive P-N junction devices are fabricated by forming a porous layer in a semiconductor of a given conductivity, diffusing dopants of the opposite conductivity into the porous layer and forming a non-porous layer on the porous layer. This results in a microporous structure having a plurality of microcrystalline regions extending therethrough, which enhances the quantum confinement of energetic carriers and results in a device which is highly sensitive to stress.

Abstract: A heterojunction bipolar transistor comprises n.sup.+ -type GaAs collector contact region, an n-type GaAs collector region, a p.sup.+ -type GaAs base region, an n-type AlGaAs emitter region, and an n.sup.+ -type InGaAs emitter contact region, all of which are formed on a semiinsulative GaAs substrate. A heterojunction is formed by the base region and the emitter region. The emitter region is formed in mesa shape by dry etching. Around this mesa, B.sup.+ ion-implanted high-resistance region is formed. The base-emitter Junction is isolated from the ion-implanted region. The heterojunction bipolar transistor therefore has little on-voltage changes.

Abstract: A field effect transistor is disclosed in which a source region and a drain region are formed to be reverse mesa on a semi-insulating semiconductor substrate with an insulating layer thereon by using a crystal growth characteristic corresponding to the crystal orientation. A channel layer and a gate electrode are formed by self-alignment on the upper part of a void formed according to the reverse mesa of the source and the drain regions, so that the channel layer and the semiconductor substrate are electrically separated by the void. By such a construction, a leakage current and backgating effect are removed, and a fast field effect transistor is attained owing to the reduction of an effective channel length and a gate resistance.

Abstract: A structure is provided to integrate bulk structure resonators into a monolithic integrated circuit chip. The chip also contains the remaining circuit components (17, 21, 24) required for the desired system function. Micromachining techniques are used to fabricate both support and a cavity (11, 27, 28) which allows mechanical vibration without interference. Alternative embodiments incorporate the use of non-piezoelectric mechanical resonators (14), quartz crystal resonators (18) and thin film piezoelectric resonators (22). Each type of resonator is used for the range of frequencies to which it is suited, providing a family of monolithic resonators capable of being used with integrated circuits having operating frequencies from a few hundred hertz to over 500 Mhz.

Abstract: A semiconductor device has material removed from the back of the substrate and a manufacturing process is provided for manufacturing these devices. In the exemplary embodiment, a GaAs FET chip is formed by a process including the step of etching the GaAs substrate from the back of the chip in a defined removal region to reduce the dielectric constant in the region of the source-to-drain path. A buffer layer of differing material provided between the active layers and the substrate prevents etching of the active layers during the removal process. To allow simplified etching patterns, the source-to-drain path may be laid out on the surface of the chip in a variety of patterns, including "packed" patterns concentrating a large path area in a small surface area of the chip. Optionally, this buffer layer may also be etched away in a further processing step.

Abstract: A microwave is made of a stack of layers. A sculptured silicon substrate is held between two covers each consisting of one or more layers. The inlet and the outlet of the microvalve are formed by perforations in the respective covers. A central valve plate is sculptured out of the silicon substrate with surfaces respectively facing the two covers in the region of the inlet and outlet in a symmetrical fashion. The valve plate is connected to the outer frame portion of the silicon substrate by one or more silicon strips. The valve plate is also shaped as a closure member near the inlet and/or the outlet. Electrodes are provided on the covers opposite the valve plate so that the valve can be electrostatically actuated with the valve plate serving as counterelectrode for these electrodes on the covers.

Abstract: A semiconductor pressure sensor of this invention is intended to provide a semiconductor pressure sensor having an excellent electrical isolation between the supporting means of the semiconductor pressure sensor and the semiconductor substrate, the semiconductor pressure sensor basically comprising a semiconductor substrate having a first semiconductor region in which at least a semiconductor device is formed, a second semiconductor region and an isolated layer buried between the first and second semiconductor regions, a cavity provided in the second semiconductor region, the opening thereof existing on the main surface of the second semiconductor region and a strain detecting portion consisting of the semiconductor device and provided in the first semiconductor region opposite to the cavity.