Abstract: A semiconductor device and a manufacturing method thereof uses a semiconductor substrate of silicon carbide. On one principal surface side of the substrate, at its central section, a layer of silicon carbide or gallium nitride as a semiconductor layer having the thickness at least necessary for breakdown voltage blocking is epitaxially grown or formed from part of the substrate. A recess is formed in the other principal surface side of substrate at a position facing the central section. A supporting section surrounds the bottom of the recess and provides the side face of the recess. The recess is formed by processing such as dry etching. The semiconductor device, even though the semiconductor substrate is made thinner for the realization of small on-resistance, can maintain the strength of the semiconductor substrate capable of reducing occurrence of a wafer cracking during the manufacturing process.

Abstract: One embodiment of the present invention provides a system for facilitating proximity communication between semiconductor chips. The system includes a base chip and a bridge chip, each of which includes an active face upon which active circuitry and signal pads reside, and a back face opposite the active face. The active face of the bridge chip is bonded to the active face of the base chip. Then, an identified portion of the active face of the bridge chip is thinned via etching and is removed by planarizing the back face of the bridge chip, thereby creating an opening in the bridge chip that exposes a portion of the active face of the base chip.

Abstract: An exemplary method for forming gaps in a micromechanical device includes providing a substrate. A first material layer is deposited over the substrate. A sacrificial layer is deposited over the first material layer. A second material layer is deposited over the sacrificial layer such that at least a portion of the sacrificial layer is exposed. The exposed portion of the sacrificial layer is etched by dry etching. The remaining portion of the sacrificial layer is etched by wet etching to form gaps between the first material layer and the second material layer. One or more bulges are formed at one side of the second material layer facing the first material layer, and are a portion of the sacrificial layer remaining after the wet etching.

Abstract: Methods of forming microelectronic device wafers include fabricating a plurality of semiconductor dies at an active side of a semiconductor wafer, depositing a mask on the semiconductor wafer, removing a central portion of the mask and the semiconductor wafer, and etching. The semiconductor wafer has an outer perimeter edge and a backside that is spaced from the active side by a first thickness. The mask is deposited on the backside of the semiconductor wafer and has a face that is spaced from the backside by a mask thickness. The thinned portion has a thinned surface that is spaced from the active side by a second thickness that is less than the first thickness, and the thinned surface is etched.

Abstract: A sensor for selectively determining the presence and measuring the amount of hydrogen in the vicinity of the sensor. The sensor comprises a MEMS device coated with a nanostructured thin film of indium oxide doped tin oxide with an over layer of nanostructured barium cerate with platinum catalyst nanoparticles. Initial exposure to a UV light source, at room temperature, causes burning of organic residues present on the sensor surface and provides a clean surface for sensing hydrogen at room temperature. A giant room temperature hydrogen sensitivity is observed after making the UV source off. The hydrogen sensor of the invention can be usefully employed for the detection of hydrogen in an environment susceptible to the incursion or generation of hydrogen and may be conveniently used at room temperature.

Abstract: A wafer with an orientation notch being cut in a portion of its circumference, the wafer includes: a reinforcing flange formed upright at periphery; and a thin section surrounded by the reinforcing flange and having a smaller thickness than the reinforcing flange. The reinforcing flange includes a circumferential portion formed upright along the circumference and a notch portion formed upright near the orientation notch, and a width of the circumferential portion as viewed parallel to a major surface of the wafer is smaller than a depth of the orientation notch as viewed parallel to the major surface.

Abstract: A nano-fuse structural arrangement, includes, for example, a semiconductor substrate having an electrically conductive region formed thereon; an electrically conductive elongated nano-structure having a maximum diameter of less than approximately 50 nm and a maximum length of approximately 250 nm and being formed on the electrically conductive region; a barrier having barrier parts completely spaced from and completely surrounding elongated outer surfaces of the nano-structure, the spaces between the barrier and surfaces consisting essentially of a vacuum and being approximately equally spaced, so that the electrically conductive elongated nano-structure is blowable responsive to an electrical current flowable there through in a range of approximately 4 ?A to approximately 120 ?A.

Abstract: A microelectronic element, e.g., a semiconductor chip having a silicon-on-insulator layer (“SOI layer”) separated from a bulk monocrystalline silicon layer by a buried oxide (BOX) layer in which a crack stop extends in first lateral directions at least generally parallel to the edges of the chip to define a ring-like barrier separating an active portion of the chip inside the barrier with a peripheral portion of the chip. The crack stop can include a first crack stop ring contacting a silicon portion of the chip above the BOX layer; the first crack stop ring may extend continuously in the first lateral directions to surround the active portion of the chip. A guard ring (“GR”) including a GR contact ring can extend downwardly through the SOI layer and the BOX layer to conductively contact the bulk monocrystalline silicon region, the GR contact ring extending at least generally parallel to the first crack stop ring to surround the active portion of the chip.

Abstract: An inventive semiconductor device includes a semiconductor chip having a passivation film, and a sealing resin layer provided over the passivation film for sealing a front side of the semiconductor chip. The sealing resin layer extends to a side surface of the passivation film to cover the side surface.

Abstract: Latch-up resistant semiconductor structures formed on a hybrid substrate and methods of forming such latch-up resistant semiconductor structures. The hybrid substrate is characterized by first and second semiconductor regions that are formed on a bulk semiconductor region. The second semiconductor region is separated from the bulk semiconductor region by an insulating layer. The first semiconductor region is separated from the bulk semiconductor region by a conductive region of an opposite conductivity type from the bulk semiconductor region. The buried conductive region thereby the susceptibility of devices built using the first semiconductor region to latch-up.

Abstract: A design for a crack stop and moisture barrier for a semiconductor device includes a plurality of discrete conductive features formed at the edge of an integrated circuit proximate a scribe line. The discrete conductive features may comprise a plurality of staggered lines, a plurality of horseshoe-shaped lines, or a combination of both.

Abstract: Reinforced smart cards with and methods of making an integrated circuit chip for smart are disclosed. In some embodiments, a method includes generally providing an integrated circuit wafer including a plurality of integrated circuits, providing a stiffener, attaching the stiffener top surface to the wafer bottom surface, and physically separating integrated circuits. The wafer can be substantially disc-shaped with a wafer perimeter. Integrated circuits can be disposed on the wafer's top surface, and the wafer's bottom surface can span a wafer bottom area. The stiffener can have a top surface spanning an area corresponding to a circuitry portion of the wafer's top surface (where integrated circuits can be disposed). The stiffener's can be applied to the wafer's bottom surface to form a wafer/stiffener assembly.

Abstract: A wafer with an orientation notch being cut in a portion of its circumference, the wafer includes: a reinforcing flange formed upright at periphery; and a thin section surrounded by the reinforcing flange and having a smaller thickness than the reinforcing flange. The reinforcing flange includes a circumferential portion formed upright along the circumference and a notch portion formed upright near the orientation notch, and a width of the circumferential portion as viewed parallel to a major surface of the wafer is smaller than a depth of the orientation notch as viewed parallel to the major surface.

Abstract: A RF system which includes a silicon substrate formed with at least one via-hole filled with conductive material so that both sides of the silicon substrate are electrically connected with one another; at least one flat device formed on one side of the silicon substrate; and at least one RF MEMS device formed on the other side of the silicon substrate.

Abstract: A substrate for a semiconductor package having a reinforcing member that prevents or minimizes distortions is presented. The substrate for the semiconductor package includes a substrate body, an insulation layer, and a reinforcing member. The substrate body has a first region having a plurality of chip mount regions, a second region disposed along a periphery of the first region, a circuit pattern disposed in each chip mount region and a dummy pattern disposed along the second region. The insulation layer covers the first and second regions and has an opening exposing some portion of each circuit pattern. The reinforcing member is disposed in the second region and prevents deflection of the substrate body.

Abstract: A conveyance system for a semiconductor wafer can be used without any change before and after a support plate is adhered to the wafer. Also, the finish accuracy of the wafer and the positioning accuracy between the wafer and the support plate can be relaxed, thus improving the manufacturing efficiency. The wafer is formed on its peripheral portion with a stepped portion, which is deeper than a finished thickness obtained by partial removal of the rear surface thereof and which can be eliminated by the partial removal of the wafer rear surface. The separation portion has a length which extends radially outward from a flat surface, and which is greater than a total sum of a maximum-minimum difference between the finish allowances of the diameters of the wafer and the support plate, and a maximum value of a positioning error between the wafer and the support plate generated upon adhesion thereof.

Abstract: A semiconductor wafer which is generally circular, and which has on its face an annular surplus region present in an outer peripheral edge portion of the face, and a circular device region surrounded by the surplus region, the device region having many semiconductor devices disposed therein. A circular concavity is formed in the back of the semiconductor wafer in correspondence with the device region, and the device region is relatively thin, while the surplus region is relatively thick.

Abstract: A microstructure which forms a micromachine is formed by using a silicon wafer as a mainstream, conventionally. In view of this, the invention provides a manufacturing method of a micromachine in which a microstructure is formed over an insulating substrate. The invention provides a micromachine including a layer containing polycrystalline silicon which is crystallized by thermal crystallization or laser crystallization using a metal element and including a space over or under the layer. Such polycrystalline silicon can be formed over an insulating surface and has high strength, therefore, it can be used as a microstructure as well. As a result, a microstructure formed over an insulating substrate or a micromachine provided with a microstructure can be provided.

Abstract: In a method for manufacturing a micromechanical device having a region for forming an integrated circuit, at first a first layer is produced on a deeper-lying part in the substrate. Subsequently, a membrane layer is produced on the first layer and at least one channel completely penetrating the membrane layer is introduced in the membrane layer. After that, a region of the first layer below the membrane layer is removed to form a cavity. Finally, the channel is sealed and a planar surface is formed.

Abstract: The present invention provides stretchable, and optionally printable, semiconductors and electronic circuits capable of providing good performance when stretched, compressed, flexed or otherwise deformed. Stretchable semiconductors and electronic circuits of the present invention preferred for some applications are flexible, in addition to being stretchable, and thus are capable of significant elongation, flexing, bending or other deformation along one or more axes. Further, stretchable semiconductors and electronic circuits of the present invention may be adapted to a wide range of device configurations to provide fully flexible electronic and optoelectronic devices.

Abstract: Electromechanical non-volatile memory devices are provided including a semiconductor substrate having an upper surface including insulation characteristics. A first electrode pattern is provided on the semiconductor substrate. The first electrode pattern exposes portions of a surface of the semiconductor substrate therethrough. A conformal bit line is provided on the first electrode pattern and the exposed surface of semiconductor substrate. The bit line is spaced apart from a sidewall of the first electrode pattern and includes a conductive material having an elasticity generated by a voltage difference. An insulating layer pattern is provided on an upper surface of the bit line located on the semiconductor substrate. A second electrode pattern is spaced apart from the bit line and provided on the insulating layer pattern. The second electrode pattern faces the first electrode pattern.

Abstract: Disclosed is a semiconductor wafer and method of fabricating the same. The semiconductor wafer is comprised of a semiconductor layer formed on an insulation layer on a base substrate. The semiconductor layer includes a surface region organized in a first crystallographic orientation, and another surface region organized in a second crystallographic orientation. The performance of a semiconductor device with unit elements that use charges, which are activated in high mobility to the crystallographic orientation, as carriers is enhanced. The semiconductor wafer is completed by forming the semiconductor layer with the second crystallographic orientation on the plane of the first crystallographic orientation, growing an epitaxial layer, forming the insulation layer on the epitaxial layer, and then bonding the insulation layer to the base substrate.

Abstract: A method of forming an actuator and a relay using a micro-electromechanical (MEMS)-based process is disclosed. The method first forms the lower sections of a square copper coil, and then forms an actuation member that includes a core section and a horizontally adjacent floating cantilever section. The core section, which lies directly over the lower coil sections, is electrically isolated from the lower coil sections. The method next forms the side and upper sections of the coil, along with first and second electrodes that are separated by a switch gap. The first electrode lies directly over an end of the core section, while the second electrode lies directly over an end of the floating cantilever section.

Abstract: An accelerator sensor includes a semiconductor substrate having a main front surface and a main rear surface, a first groove portion being formed along a front surface pattern, in the main front surface, a second groove portion being formed along a rear surface pattern, in the main rear surface, a through-hole being formed because of connection between at least parts of the first groove portion and the second groove portion and at least one groove width variation portion being formed in at least one of inner walls of the first groove portion. An offset of the rear surface pattern to the front surface pattern can be inspected easily by existence of the groove width variation portion.

Abstract: A chip module with a substrate having a top side, a chip mounted on the top side of the substrate, and an encapsulation includes an encapsulation material. The encapsulation is applied on the chip and the top side of the substrate in such a way that the chip and the top side of the substrate are at least partly covered. The encapsulation material includes a polymer composition having at least a first polymer component and a second polymer component which are chemically covalently bonded by means of a crosslinker, the first polymer component imparting resistance toward a first class of chemically reactive compounds and the second polymer component imparting resistance toward a second class of chemically reactive compounds, the reactivities differing between the first and second classes of chemically reactive compounds.

Abstract: In a semiconductor device, and a method of fabricating the same, the semiconductor device includes a protrusion extending from a substrate and a selective epitaxial growth (SEG) layer surrounding an upper portion of the protrusion, the SEG layer exposing sidewalls of a channel region of the protrusion.

Abstract: Semiconductor devices and stacked die assemblies, and methods of fabricating the devices and assemblies for increasing semiconductor device density are provided.

Abstract: The present invention relates to a process for preparing a robust crack-absorbing integrated circuit chip comprising a crack trapping structure containing two metal plates and a via-bar structure sandwiched between said plates.

Abstract: A die seal structure for sealing integrated circuit devices formed on a semiconductor substrate. The die seal structure includes a die seal and a junction diode. The die seal only connects to the semiconductor substrate through the junction diode, thereby reducing noise coupling through the die seal. In another aspect of the present invention the die seal structure includes a die seal and a bipolar structure. In this embodiment the die seal only connects to the semiconductor substrate through the bipolar structure.

Abstract: The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations.

Abstract: A memory cell is implemented using a semiconductor fin in which the channel region is along a sidewall of the fin between source and drains regions. One portion of the channel region has a select gate adjacent to it and another other portion has the control gate adjacent to it with a charge storage structure there between. In some embodiments, independent control gate structures are located adjacent opposite sidewalls of the fin so as to implement two memory cells.

Abstract: A semiconductor device includes a semiconductor structure having a first sidewall. A vertical channel region is formed in the semiconductor structure along the first sidewall between a first current electrode region and a second current electrode region. First and second charge storage structures are formed adjacent to the first sidewall in openings of a dielectric layer. The first and second charge storage structures are electrically isolated from each other and from the semiconductor structure. A control electrode is formed adjacent to the first sidewall. In another embodiment, third and fourth charge storage structures may be formed adjacent to a second sidewall of the semiconductor structure in openings of a dielectric layer.

Abstract: A method of producing a substrate that has a transfer crystalline layer transferred from a donor wafer onto a support. The transfer layer can include one or more foreign species to modify its properties. In the preferred embodiment an atomic species is implanted into a zone of the donor wafer that is substantially free of foreign species to form an embrittlement or weakened zone below a bonding face thereof, with the weakened zone and the bonding face delimiting a transfer layer to be transferred. The donor wafer is preferably then bonded at the level of its bonding face to a support. Stresses are then preferably applied to produce a cleavage in the region of the weakened zone to obtain a substrate that includes the support and the transfer layer. Foreign species are preferably diffused into the thickness of the transfer layer prior to implanbumtation or after cleavage to modify the properties of the transfer layer, preferably its electrical or optical properties.

Abstract: The present invention provides stretchable, and optionally printable, semiconductors and electronic circuits capable of providing good performance when stretched, compressed, flexed or otherwise deformed. Stretchable semiconductors and electronic circuits of the present invention preferred for some applications are flexible, in addition to being stretchable, and thus are capable of significant elongation, flexing, bending or other deformation along one or more axes. Further, stretchable semiconductors and electronic circuits of the present invention may be adapted to a wide range of device configurations to provide fully flexible electronic and optoelectronic devices.

Abstract: A wafer having a device region, where a plurality of devices is formed, and an outer peripheral surplus region, which surrounds the device region, on the face of a circular wafer substrate is disclosed. A chamfered portion whose cross-sectional shape defines an arc-shaped surface in a range from the face to the back of the wafer substrate is formed in an outer peripheral end portion of the outer peripheral surplus region of the wafer substrate. A flat surface orthogonal to the face and the back is formed in the chamfered portion as a mark showing the crystal orientation of the wafer substrate. An identification code for specifying the wafer substrate is printed on the flat surface.

Abstract: An elevated containment structure in the shape of a wafer edge ring surrounding a surface of a semiconductor wafer is disclosed, as well as methods of forming and using such a structure. In one embodiment, a wafer edge ring is formed using a stereolithography (STL) process. In another embodiment, a wafer edge ring is formed with a spin coating apparatus provided with a wafer edge exposure (WEE) system. In further embodiments, a wafer edge ring is used to contain a liquid over a wafer active surface during a processing operation. In one embodiment, the wafer edge ring contains a liquid having a higher refractive index than air while exposing a photoresist on the wafer by immersion lithography. In another embodiment, the wafer edge ring contains a curable liquid material while forming a chip scale package (CSP) sealing layer on the wafer.

Abstract: A process of forming ultra thin wafers having an edge support ring is disclosed. The process provides an edge support ring having an angled inner wall compatible with spin etch processes.

Abstract: A method of forming an actuator and a relay using a micro-electromechanical (MEMS)-based process is disclosed. The method first forms the lower sections of a square copper coil, and then forms a magnetic core member. The magnetic core member, which lies directly over the lower coil sections, is electrically isolated from the lower coil sections. The method next forms the side and upper sections of the coil, followed by the formation of an overlying cantilevered magnetic flexible member. Switch electrodes, which are separated by a switch gap, can be formed on the magnetic core member and the magnetic flexible member, and closed and opened in response to the electromagnetic field that arises in response to a current in the coil.

Abstract: A method for making a semiconductor device includes patterning a semiconductor layer, overlying an insulator layer, to create a first active region and a second active region, wherein the first active region is of a different height from the second active region, and wherein at least a portion of the first active region has a first conductivity type and at least a portion of the second active region has a second conductivity type different from the first conductivity type in at least a channel region of the semiconductor device. The method further includes forming a gate structure over at least a portion of the first active region and the second active region. The method further includes removing a portion of the second active region on one side of the semiconductor device.

Abstract: Methods are provided for building integrated circuit transformer devices having compact and optimized architectures for use in MMW (millimeter-wave) applications. The integrated circuit transformer devices have universal and scalable architectures that can be used as templates or building blocks for constructing various types of on-chip devices for millimeter-wave applications.

Abstract: A double-sided etching method using an embedded alignment mark includes: preparing a substrate having first and second alignment marks embedded in an intermediate portion thereof; etching an upper portion of the substrate so as to expose the first alignment mark from a first surface of the substrate; etching the upper portion of the substrate using the exposed first alignment mark; etching a lower portion of the substrate so as to expose the second alignment mark from a second surface of the substrate; and etching the lower portion of the substrate using the exposed second alignment mark.

Abstract: A non-planar microelectronic device, a method of fabricating the device, and a system including the device. The non-planar microelectronic device comprises: a substrate body including a substrate base and a fin, the fin defining a device portion at a top region thereof; a gate dielectric layer extending at a predetermined height on two laterally opposing sidewalls of the fin, the predetermined height corresponding to a height of the device portion; a device isolation layer on the substrate body and having a thickness up to a lower limit of the device portion; a gate electrode on the device isolation layer and further extending on the gate dielectric layer; an isolation element extending on the two laterally opposing sidewalls of the fin up to a lower limit of the gate dielectric layer, the isolation element being adapted to reduce any fringe capacitance between the gate electrode and regions of the fin extending below the device portion.

Abstract: An electronic device, including a substrate, a functional structure constituting a functional element formed on the substrate, and a cover structure forming a cavity portion in which the functional structure is disposed, is disclosed. In the electronic device, the cover structure includes a laminated structure of an interlayer insulating film and a wiring layer, the laminated structure being formed on the substrate in such a way that it surrounds the cavity portion, and the cover structure has an upside cover portion covering the cavity portion from above, the upside cover portion being formed with part of the wiring layer that is disposed above the functional structure.

Abstract: Disclosed is an electronic device utilizing interferometric modulation and a package of the device. The packaged device includes a substrate, an interferometric modulation display array formed on the substrate, and a back-plate. The back-plate is placed over the display array with a gap between the back-plate and the display array. The depth of the gap may vary across the back-plate. The back-plate can be curved or have a recess on its interior surface facing the display array. Thickness of the back-plate may vary. The device may include reinforcing structures which are integrated with the back-plate.

Abstract: a semiconductor Array and method for Manufacturing a semiconductor array is provided that includes a substrate, an element layer of a single-crystal semiconductor material, an isolation layer that is formed between the substrate and the element layer and isolates the element layer from the substrate, a number of elements that are formed in the element layer, a trench structure that is adjacent to the isolation layer and that is filled with a filling, to isolate at least one element of the number of elements within the element layer in a lateral direction, whereby the filling has a dielectric, and a self-supporting microstructure that is formed in a structure region defined by the trench structure.

Abstract: A grid structure and method for manufacturing the same. The grid is used for gating a stream of charged particles in certain types of particle measurement instruments, such as ion mobility spectrometers and the like. The methods include various microfabrication techniques for etching and/or depositing grid structure materials on a silicon substrate.

Abstract: A device and a method are described which hermetically seals at least one microstructure within a cavity. Electrical access to the at least one microstructure is provided by through wafer vias formed through a via substrate which supports the at least one microstructure on its front side. The via substrate and a lid wafer may form a hermetic cavity which encloses the at least one microstructure. The through wafer vias are connected to bond pads located outside the cavity by an interconnect structure formed on the back side of the via substrate. Because they are outside the cavity, the bond pads may be placed inside the perimeter of the bond line forming the cavity, thereby greatly reducing the area occupied by the device. The through wafer vias also shorten the circuit length between the microstructure and the interconnect, thus improving heat transfer and signal loss in the device.

Abstract: There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a MEMS device, and technique of fabricating or manufacturing a MEMS device, having mechanical structures encapsulated in a chamber prior to final packaging and a contact area disposed at least partially outside the chamber. The contact area is electrically isolated from nearby electrically conducting regions by way of dielectric isolation trench that is disposed around the contact area. The material that encapsulates the mechanical structures, when deposited, includes one or more of the following attributes: low tensile stress, good step coverage, maintains its integrity when subjected to subsequent processing, does not significantly and/or adversely impact the performance characteristics of the mechanical structures in the chamber (if coated with the material during deposition), and/or facilitates integration with high-performance integrated circuits.

Abstract: An electronic component includes a semiconductor chip with an active front face and a passive rear face, with contact connections and contact surfaces respectively being provided on the active front face and/or on the passive rear face, and with conductive connections being provided in the form of structured conductive tracks for providing an electrical connection from the active front face to the passive rear face. An electronic assembly formed of stacked semiconductor chips, and a method for producing the electronic component and the electronic assembly are also provided.

Abstract: A fin-FET or other multi-gate transistor is disclosed. The transistor comprises a semiconductor substrate having a first lattice constant, and a semiconductor fin extending from the semiconductor substrate. The fin has a second lattice constant, different from the first lattice constant, and a top surface and two opposed side surfaces. The transistor also includes a gate dielectric covering at least a portion of said top surface and said two opposed side surfaces, and a gate electrode covering at least a portion of said gate dielectric. The resulting channel has a strain induced therein by the lattice mismatch between the fin and the substrate. This strain can be tuned by selection of the respective materials.