Abstract: A semiconductor device includes wiring layers formed over a semiconductor wafer, a via-layer between the wiring layers, conductive films in the wiring layers, and a via-plug in the via-layer connecting the conductive films of the wiring layers above and below, a scribe region at an outer periphery of a chip region along an edge of the semiconductor substrate and including a pad region in the vicinity of the edge, the pad region overlapping the conductive films of the plurality of wiring layers in the plan view, the plurality of wiring layers including first second wiring layers, the conductive film of the first wiring layer includes a first conductive pattern formed over an entire surface of said pad region in a plan view, and the conductive film of the second wiring layer includes a second conductive pattern formed in a part of the pad region in a plan view.

Abstract: A semiconductor wafer including a plurality of die fabricated therein in a defined pattern. They are separated from each other by a dicing area or street and at least a portion of adjacent die on the wafer include at least a conductive connection between given adjacent die that is electrically interfaced to circuitry disposed on the given adjacent die.

Abstract: Disclosed are a method for metallization during semiconductor wafer processing and the resulting structures. In this method, a passivation layer is patterned with first openings aligned above and extending vertically to metal structures below. A mask layer is formed and patterned with second openings aligned above the first openings, thereby forming two-tier openings extending vertically through the mask layer and passivation layer to the metal structures below. An electrodeposition process forms, in the two-tier openings, both under-bump pad(s) and additional metal feature(s), which are different from the under-bump pad(s) (e.g., a wirebond pad; a final vertical section of a crackstop structure; and/or a probe pad). Each under-bump pad and additional metal feature initially comprises copper with metal cap layers thereon.

Abstract: An integrated circuit (IC) and a seal ring thereof are provided. The IC includes a first seal ring. The first seal ring is disposed in the IC. The first seal ring includes at least one stagger structure. The at least one stagger structure includes at least one stagger unit. The at least one stagger unit makes staggered connection with another neighboring stagger unit.

Abstract: The present invention relates to a method for thermal stress reduction on a wafer, comprising the steps of providing a patterned wafer with saw lanes between adjacent dies, forming thin holes within the silicon substrate, which holes create a dotted groove in the saw lanes, and wherein no second layer on an opposing side of the wafer is formed, a patterned wafer obtained by said method. The forming of the holes is preferably combined with other processing steps or another step to avoid additional operations and manipulations prior to, or after standard wafer processing, and it therefore optimizes fabrication quality and costs. Preferably the holes within the silicon substrate having a depth of more than 3 to 50 ?m, preferably from 5-40 ?m, like 20 ?m.

Abstract: A semiconductor package is disclosed, which includes: a packaging substrate; a semiconductor element disposed on the packaging substrate in a flip-chip manner; a stopping portion formed at edges of the semiconductor element; an insulating layer formed on an active surface of the semiconductor element and the stopping portion; and an encapsulant formed between the packaging substrate and the insulating layer. The insulating layer has a recessed portion formed on the stopping portion and facing the packaging substrate such that during a reliability test, the recessed portion can prevent delamination occurring between the insulating layer and the stopping portion from extending to the active surface of the semiconductor element.

Abstract: Structures and methods provide a dielectric bridge for use in electroplating. A method comprises: providing a semiconductor wafer with a plurality of die, wherein a first die is adjacent to a second die, and the first die and second die are separated by a dicing street area; forming a patterned dielectric layer overlying the semiconductor wafer, the dielectric layer including a dielectric bridge that crosses the dicing street area; forming a conductive layer (e.g., a metal seed layer) overlying the dielectric layer, wherein a portion of the conductive layer is overlying the dielectric bridge to provide a current pathway from the first die to the second die; and electroplating targeted areas of the conductive layer by providing current to the second die using the current pathway. Other such bridges formed from the dielectric layer provide current pathways to other die on the wafer.

Abstract: A method including forming a plurality of dicing channels in a front side of a wafer; the plurality of dicing channels including a depth at least greater than a desired final thickness of the wafer, filling the plurality of dicing channels with a fill material and removing a portion of the wafer from a back side of the wafer until the desired final thickness is achieved, where a portion of the fill material within the plurality of dicing channel is exposed. The method further including depositing a metal layer on the back side of the wafer; removing the fill material from within the plurality of dicing channels to expose the metal layer at a bottom of the plurality of dicing channels, and removing a portion of the metal layer located at the bottom of the plurality of dicing channels.

Abstract: The present invention provides a technique for improving the reliability of a semiconductor device where spreading of cracking that occurs at the time of dicing to a seal ring can be restricted even in a semiconductor device with a low-k film used as an interlayer insulating film. Dummy vias are formed in each layer on a dicing region side. The dummy vias are formed at the same intervals in a matrix as viewed in a top view. Even in the case where cracking occurs at the time of dicing, the cracking can be prevented from spreading to a seal ring by the dummy vias. As a result, resistance to moisture absorbed in a circuit formation region can be improved, and deterioration in reliability can be prevented.

Abstract: A semiconductor device includes wiring layers formed over a semiconductor wafer, a via-layer between the wiring layers, conductive films in the wiring layers, and a via-plug in the via-layer connecting the conductive films of the wiring layers above and below, a scribe region at an outer periphery of a chip region along an edge of the semiconductor substrate and including a pad region in the vicinity of the edge, the pad region overlapping the conductive films of the plurality of wiring layers in the plan view, the plurality of wiring layers including first second wiring layers, the conductive film of the first wiring layer includes a first conductive pattern formed over an entire surface of said pad region in a plan view, and the conductive film of the second wiring layer includes a second conductive pattern formed in a part of the pad region in a plan view.

Abstract: Provided is a semiconductor device characterized by that first to fourth semiconductor chips are mounted on first to fourth electrodes formed by plating, respectively; the surface of the first semiconductor chip and the upper surface of a fifth electrode, the surface of the second semiconductor chip and the upper surface of the first electrode, the surface of the third semiconductor chip and the upper surface of the fourth electrode, the surface of the fourth semiconductor chip and the upper surface of the fifth electrode, and the upper surface of the second electrode and the upper surface of the third electrode are coupled to each other by first to fifth conductive members, respectively; and the back surfaces of the first to fifth electrodes are exposed from a resin molding. The invention makes it possible to reduce the size and the thickness of a semiconductor device configuring a diode bridge circuit.

Abstract: A chip includes a number a plurality of functional areas of a layer and a number of dummy structures within the layer. The dummy structures are spaced from the functional areas. Each dummy structure has a size that is a function of the size and density of the functional areas.

Abstract: An apparatus includes an image sensor with a frontside and a backside. The image sensor includes an active circuit region and bonding pads. The active circuit region has a first shape that is substantially rectangular. The substantially rectangular first shape has first chamfered corners. A perimeter of the frontside of the image sensor has a second shape that is substantially rectangular. The second substantially rectangular shape has second chamfered corners. The bonding pads are disposed on the frontside of the image sensor. The bonding pads are disposed between the first chamfered corners and the second chamfered corners. The first shape is disposed inside the second shape.

Abstract: A die seal ring is provided. The die seal ring includes a substrate and a first layer extruding from the substrate. The first layer has a first fin ring structure and a layout of the first fin ring structure has a stamp-like shape. In addition, a method for forming a die seal ring is provided. A substrate having an active region is provided. A patterned sacrificial layer is formed on the substrate. A spacer is formed on the sidewall of the patterned sacrificial layer. The patterned sacrificial layer is removed. The substrate is patterned by using the spacer as a mask, thereby simultaneously forming at least a fin structure of a Fin-FET and a first layer of the die seal ring.

Abstract: A semiconductor apparatus includes a semiconductor substrate having a main surface, a multilayer structure circuit formed over the main surface of the semiconductor substrate, a protective wall formed in the same layer as an uppermost layer of the multilayer structure circuit so as to surround the multilayer structure circuit in plan view, and an alignment mark formed in the same layer as the uppermost layer. The alignment mark is formed so as to contact at least part of the protective wall.

Abstract: The present disclosure relates generally to semiconductor techniques. More specifically, embodiments of the present disclosure provide methods for efficiently dicing substrates containing gallium and nitrogen material. Additionally, the present disclosure provides techniques resulting in an optical device comprising a substrate having a dislocation bundle center being used as a conductive region for a contact.

Abstract: Methods of and apparatuses for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of reducing edge warping in a supported semiconductor wafer involves adhering a backside of a semiconductor wafer to an inner portion of a carrier tape of a substrate carrier comprising a tape frame mounted above the carrier tape. The method also involves adhering an adhesive tape to a front side of the semiconductor wafer and to at least a portion of the substrate carrier. The adhesive tape includes an opening exposing an inner region of the front side of the semiconductor wafer.

Abstract: An integrated circuit containing a crack deflecting scribe seal which separates an interior region of the integrated circuit from a scribeline immediately outside the integrated circuit and a method of forming the same. The crack deflecting scribe seal includes continuous metal layers and continuous contacts and continuous vias between the continuous metal layers. The continuous metal layers do not extend past the continuous contacts and continuous vias. The continuous contacts and continuous vias are recessed from edges of the underlying continuous metal layers on the scribeline side of the scribe seal, providing an angled outer surface on the scribe seal which may desirably terminate crack propagation or deflect crack propagation upward to a top surface of the scribeline or the crack deflecting scribe seal.

Abstract: An integrated circuit optical die test interface and associated testing method are described for using scribe area optical mirror structures (106) to perform wafer die tests on MEMS optical beam waveguide (112) and optical circuit elements (113) by perpendicularly deflecting optical test signals (122) from the scribe area optical mirror structures (106) into and out of the plane of the integrated circuit die under test (104) and/or production test die (157).

Abstract: An integrated circuit device includes a semiconductor body, active components formed over the semiconductor body, one or more seal rings surrounding the active components, and a signal line. One or more of the seal rings are configured to provide the primary return path for current flowing through the signal line.

Abstract: A method of forming a wafer level packaged circuit device includes forming a device wafer, the device wafer including a first group of one or more material layers left remaining in a first region of a substrate of the device wafer; and forming a cap wafer configured to be attached to the device wafer, the cap wafer including a second group of one or more material layers left remaining in a second region of a substrate of the cap wafer; wherein a combined thickness of the first and second groups of one or more material layers defines an integrated bond gap control structure upon bonding of the device wafer and the cap wafer.

Abstract: A surface mountable electronic component free of connecting wires comprises a semiconductor substrate, wherein a plurality of solderable connection areas are arranged at the underside of the component. The component comprises at least one recess is formed in the region of the edges bounding the underside; and in that the recess is covered with an insulating layer. A method for the manufacture of such a component comprises the formation of corresponding recesses.

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, approaches for wafer dicing with wide kerf by using a laser scribing and plasma etching hybrid approach are described. For example, a method of dicing a semiconductor wafer including a plurality of integrated circuits separated by dicing streets involves forming a mask above the semiconductor wafer, the mask having a layer covering and protecting the integrated circuits. The method also involves patterning the mask with a laser scribing process to provide a patterned mask having a pair of parallel gaps for each dicing street, exposing regions of the semiconductor wafer between the integrated circuits. Each gap of each pair of parallel gaps is separated by a distance. The method also involves etching the semiconductor wafer through the gaps in the patterned mask to singulate the integrated circuits.

Abstract: A semiconductor structure less affected by stress and a method for forming the same are provided. The semiconductor structure includes a semiconductor chip. Stress-sensitive circuits are substantially excluded out of an exclusion zone to reduce the effects of the stress to the stress-sensitive circuits. The stress-sensitive circuits include analog circuits. The exclusion zone preferably includes corner regions of the semiconductor chip, wherein the corner regions preferably have a diagonal length of less than about one percent of the diagonal length of the semiconductor chip. The stress-sensitive analog circuits preferably include devices having channel lengths less than about five times the minimum channel length.

Abstract: Die structures for electronic devices and related fabrication methods are provided. An exemplary die structure includes a diced portion of a semiconductor substrate that includes a device region having one or more semiconductor devices fabricated thereon and an edge sealing structure within the semiconductor substrate that circumscribes the device region. In one or more embodiments, the edge sealing structure includes a conductive material that contacts a handle layer of semiconductor material, a crackstop structure is formed overlying the sealing structure, wherein the crackstop structure and the edge sealing structure provide an electrical connection between the handle layer and an active layer of semiconductor material that overlies a buried layer of dielectric material on the handle layer.

Abstract: A method of layout of pattern includes the following processes. A graphic data of a first wiring in a first area of a semiconductor wafer is extracted. The first area is a semiconductor chip forming area. The first area is surrounded by a scribed area of the semiconductor wafer. The first area includes a second area. The second area is bounded with the scribed area. The second area has a second distance from a boundary between the semiconductor chip forming area and the scribed area to an boundary between the first area and the second area. A first dummy pattern in the first area is laid out. The first dummy pattern has at least a first distance from the first wiring. A second dummy pattern in the second area is laid out. The second dummy pattern has at least the first distance from the first wiring. The second dummy pattern has at least a third distance from the first dummy pattern.

Abstract: Kerf areas are located between the integrated circuit chips on a wafer. Via chain test structures are located in the kerf areas or test chips. The via chain test structures comprise a first conductor in a first area of the wafer. First via chains are connected at individual points to the first conductor. Each of the first via chains comprises an open-ended electrical circuit beginning at the first conductor and ending in an insulated region of a second area of the wafer. The via chain test structures comprise a second conductor in the second area. Second via chains are connected at individual points to the second conductor. Each of the second via chains comprises an open-ended electrical circuit beginning at the second conductor and ending in an insulated region of the first area.

Abstract: A plurality of semiconductor die is mounted to a temporary carrier. An encapsulant is deposited over the semiconductor die and carrier. A portion of the encapsulant is designated as a saw street between the die, and a portion of the encapsulant is designated as a substrate edge around a perimeter of the encapsulant. The carrier is removed. A first insulating layer is formed over the die, saw street, and substrate edge. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first conductive layer and first insulating layer. The encapsulant is singulated through the first insulating layer and saw street to separate the semiconductor die. A channel or net pattern can be formed in the first insulating layer on opposing sides of the saw street, or the first insulating layer covers the entire saw street and molding area around the semiconductor die.

Abstract: Provided are a semiconductor device in which abrasive grain marks are formed in a surface of a semiconductor substrate, a dopant diffusion region has a portion extending in a direction which forms an angle included in a range of ?5° to +5° with a direction in which the abrasive grain marks extend, and the dopant diffusion region is formed by diffusing a dopant from a doping paste placed on one surface of the semiconductor substrate; and a method for manufacturing the semiconductor device.

Abstract: A method for manufacturing a semiconductor device includes forming at least one stripe-shaped protection film over a multilayer film in a scribe region of a semiconductor substrate having a plurality of semiconductor element regions formed therein, the protection film having a thickness larger in a center portion thereof than at an end surface thereof and being made of a member which transmits a laser beam, and removing the multilayer film in the scribe region by irradiating the protection film with a laser beam.

Abstract: A substrate dividing method which can thin and divide a substrate while preventing chipping and cracking from occurring. This substrate dividing method comprises the steps of irradiating a semiconductor substrate 1 having a front face 3 formed with functional devices 19 with laser light while positioning a light-converging point within the substrate, so as to form a modified region including a molten processed region due to multiphoton absorption within the semiconductor substrate 1, and causing the modified region including the molten processed region to form a starting point region for cutting; and grinding a rear face 21 of the semiconductor substrate 1 after the step of forming the starting point region for cutting such that the semiconductor substrate 1 attains a predetermined thickness.

Abstract: According to the invention, die shift is reduced or substantially eliminated, by cutting the wafer in two stages. In some embodiments a first wafer cutting procedure is carried out prior to thinning the wafer to the prescribed die thickness; and in other embodiments the wafer is thinned to the prescribed die thickness prior to carrying out a first wafer cutting procedure. The first wafer cutting procedure includes cutting along a first set of streets to a depth greater than the prescribed die thickness and optionally along a second set of streets to a depth less than the die thickness. The result of the first cutting procedure is an array of strips or blocks of die, each including a plurality of connected die, that are less subject to shift than are individual singulated die. In a second wafer cutting procedure the die are singulated by cutting through along the second set of streets.

Abstract: A die includes a first plurality of edges, and a semiconductor substrate in the die. The semiconductor substrate includes a first portion including a second plurality of edges misaligned with respective ones of the first plurality of edges. The semiconductor substrate further includes a second portion extending from one of the second plurality of edges to one of the first plurality of edges of the die. The second portion includes a first end connected to the one of the second plurality of edges, and a second end having an edge aligned to the one of the first plurality of edges of the die.

Abstract: A circuit layout structure includes a wafer having at least a cell region and a scribe line region defined thereon, a metal pattern formed in a first insulating layer in the scribe line region, a second insulating layer and a hard mask layer formed on the metal pattern and the first insulating layer, and at least a dummy pattern formed in the second insulating layer and the hard mask layer in the scribe line region. The dummy pattern has a transmission rate between 0% and 1%.

Abstract: A semiconductor circuit design includes an outer seal-ring and an inner seal-ring for each sub-section of the design that may potentially be cut into separate die. The use of multiple seal-rings permits a single circuit design and fabrication run to be used to support flexibly packaging different product releases having different numbers of integrated circuit blocks per packaged unit.

Abstract: An apparatus that comprises a device on a substrate and a crack stop in the substrate. Methods of forming a device are also disclosed. The methods may include providing a device, such as a semiconductor device, on a substrate having a first thickness, reducing the thickness of the substrate to a second thickness, and providing a crack stop in the substrate. Reducing the thickness of the substrate may include mounting the substrate to a carrier substrate for support and then removing the carrier substrate. The crack stop may prevent a crack from reaching the device.

Abstract: In one embodiment, a light-emitting device having a substrate, a casing, a plurality of light source dies, a plurality of spectral converters and a plurality of optical structures is disclosed. The spectral converters may be configured to spectrally adjust a portion of the light output of the light source die into a first and second converted spectral output that is substantially different from one another. In another embodiment, a system for illumination having a plurality of lighting assemblies has been disclosed. Each of the lighting assemblies comprises a light source die and a spectral converter. The spectral converter is configured to spectrally adjust the light output of the light source die so that the plurality of lighting assemblies are configured to emit substantially different spectral output. In yet another embodiment, a lighting apparatus having a primary spectral converter and a secondary spectral converter is disclosed.

Abstract: In one embodiment, semiconductor die are singulated from a semiconductor wafer by forming trenches along singulation lines and initiating a cracks from within the trenches, which propagate through the semiconductor wafer in a more controlled manner.

Abstract: The amount of signal propagation and moisture penetration and corresponding reliability problems due to moisture penetration degradation in an IC can be reduced by fabricating a wide seal ring with a channel having offset ingress and egress portions.

Abstract: A semiconductor may include several vias located in an active region and a die seal region. In the active region, a photoresist can be patterned with openings corresponding to the vias. In the die seal area however, the photoresist can be patterned to overlap the vias. With this configuration, an underlayer etch will not affect an underlayer resist in the die seal area allowing the die seal area to he disregarded for purposes of calculating a process window.

Abstract: The subject matter disclosed herein relates to structures formed on semiconductor chips that are used for at least partially addressing the thermally induced stresses and metallization system cracking problems in a semiconductor chip that may be caused by the presence of through-silicon vias (TSV's), and which may be due primarily to the significant differences in thermal expansion between the materials of the TSV's and the semiconductor-based materials that generally make up the remainder of the semiconductor chip. One device disclosed herein includes a substrate and a crack-arresting structure positioned above the substrate, the crack-arresting structure comprising a plurality of crack-arresting elements and having a perimeter when viewed from above.

Abstract: An electronic device manufacturing method includes a cutting step at which a wafer is cut to obtain chips before pattern formation and a polishing step at which cut surfaces of the obtained chips are subjected in one batch to barrel polishing. The method further includes an aligning step at which the polished chips are aligned so that front surfaces thereof face in an upward direction. The method further includes a bonding step at which the cut surfaces of the aligned chips are bonded together with an adhesive to thereby form a chip assembly. The method further includes a pattern forming step at which a circuit pattern is formed on each of the chips of the chip assembly and a melting step at which the adhesive on the chip assembly is melted to thereby separate the chip assembly into chips after pattern formation.

Abstract: A semiconductor package includes a lead frame including a chip mounting portion and a terminal portion, a semiconductor chip, which is mounted on the chip mounting portion and connected to the terminal portion, a through groove penetrating the terminal portion from one surface on a side of the semiconductor chip to another surface in a thickness direction of the terminal portion, a lid portion covering an end portion of the through groove on the side of the semiconductor chip, and a resin portion sealing the semiconductor chip, wherein the another surface of the terminal portion and a side surface of the terminal portion facing an outside of the semiconductor package are coated by a plating film.

Abstract: An integrated circuit structure including reflective metal pads is provided. The integrated circuit structure includes a semiconductor substrate; a first low-k dielectric layer overlying the semiconductor substrate, wherein the first low-k dielectric layer is a top low-k dielectric layer; a second low-k dielectric layer immediately underlying the first low-k dielectric layer; and a reflective metal pad in the second low-k dielectric layer.

Abstract: An insulating substrate includes: a transparent insulating layer; a first metal layer that is provided on a first face of the transparent insulating layer; and a second metal layer that is provided on a second face of the transparent insulating layer that is opposite from the first face. The first face of the transparent insulating layer is formed with an exposed section that is an area not provided with the first metal layer. The second metal layer includes an area that is overlapped with the exposed section when seen in an orthogonal direction to the first face.

Abstract: A method for manufacturing a plurality of chips comprises the step of providing a wafer comprising a plurality of chip areas separated by one or more dicing lines, wherein the chip areas are arranged on a first main surface, the step of providing a laser absorption layer on a second main surface opposite to the first main surface and the step of providing a backside metal stack on the laser absorption layer. After that a laser light is applied to the laser absorption layer along the dicing lines before the chips are singulated along the dicing lines by using stealth dicing.

Abstract: A semiconductor device includes: an interlayer insulating film formed on a substrate; a wiring formed in the interlayer insulating film in a chip region of the substrate; a seal ring formed in the interlayer insulating film in a periphery of the chip region and continuously surrounding the chip region; and a first protective film formed on the interlayer insulating film having the wiring and the seal ring formed therein. A first opening is formed in the first protective film in a region located outside the seal ring when viewed from the chip region, and the interlayer insulating film is exposed in the first opening.

Abstract: In one or more embodiments, a semiconductor structure is provided that includes a plurality of interposer dice on an un-singulated segment of a semiconductor wafer. Scribe lanes circumscribing each of the plurality of interposer dice have widths of at least 2.5% of the width of each interposer die. Each interposer die includes a first contact array formed on a first side of the interposer die, a plurality of vias formed through the interposer die, one or more wiring layers formed on the first side of the interposer die and electrically coupling the first contact array to the plurality of vias, and a second contact array formed on a second side of the interposer die and electrically coupled to the plurality of vias.

Abstract: Disclosed herein is a method of forming a stress relieved film stack, the method comprising forming a film stack on a first side of a substrate, the film stack comprising a plurality of film layers and creating a plurality of film stack openings according to a cutting pattern and along at least a portion of a buffer region. The plurality of film stack openings extend from a top surface of the film stack to the substrate. A deflection of the substrate may be determined, and the cutting pattern selected prior to creating the film stack openings based on the deflection of the substrate. The substrate may have a deflection of less than about 2 ?m after the creating the plurality of film stack openings. And at least one of the plurality of film layers may comprise one of titanium nitride, silicon carbide and silicon dioxide.

Abstract: The present invention provides a semiconductor wafer, semiconductor package and semiconductor process. The semiconductor wafer includes a substrate, at least one metal segment and a plurality of dielectric layers. The semiconductor wafer is defined as a plurality of die areas and a plurality of trench areas, each of the die areas has an integrated circuit including a plurality of patterned metal layers disposed between the dielectric layers. The trench areas are disposed between the die areas, and the at least one metal segment is disposed in the trench area and insulated from the integrated circuit of the die area.