Abstract: Embodiments relate to buried structures for silicon devices which can alter light paths and thereby form light traps. Embodiments of the lights traps can couple more light to a photosensitive surface of the device, rather than reflecting the light or absorbing it more deeply within the device, which can increase efficiency, improve device timing and provide other advantages appreciated by those skilled in the art.

Abstract: Disclosed is a method of fabricating a semiconductor chip. The method includes forming a silicon layer; forming a first layer formed on the silicon layer and including a first seal ring surrounding a first chip area and a second seal ring surrounding a second chip area; and forming a second layer formed on the first layer and including a metal interconnection connecting one of the first and second chip areas and an external terminal.

Abstract: In accordance with an embodiment of the present invention, a method of forming a semiconductor device includes forming a first cavity within a substrate. The first cavity is disposed under a portion of the substrate. The method further includes forming a first pillar within the first cavity to support the portion of the substrate.

Abstract: A method of forming an array of openings in a substrate. The method comprises forming a template structure comprising a plurality of parallel features and a plurality of additional parallel features perpendicularly intersecting the plurality of additional parallel features of the plurality over a substrate to define wells, each of the plurality of parallel features having substantially the same dimensions and relative spacing as each of the plurality of additional parallel features. A block copolymer material is formed in each of the wells. The block copolymer material is processed to form a patterned polymer material defining a pattern of openings. The pattern of openings is transferred to the substrate to form an array of openings in the substrate. A method of forming a semiconductor device structure, and a semiconductor device structure are also described.

Abstract: A semiconductor wafer and a method which are capable of reducing chippings or cracks generated during the die sawing process. The semiconductor wafer comprises a plurality of dies formed on the semiconductor wafer in row and column directions and separated from each other by scribe lane areas, and a passivation layer formed on the plurality of dies and the scribe lane areas, wherein a groove structure is formed in the passivation layer. The groove structure includes grooves formed along the scribe lane areas, and corners of the passivation layer at intersections of the grooves being removed.

Abstract: One embodiment for forming a shaped substrate for an electronic device can form a shaped perimeter to define the substrate shape on the surface of a substrate. The shaped perimeter can extend at least part way into the substrate. A subsequent thinning process can remove substrate material and expose the shaped perimeter effectively forming shaped dies from the substrate.

Abstract: A silicon carbide layer is epitaxially formed on a main surface of a substrate. The silicon carbide layer is provided with a trench having a side wall inclined relative to the main surface. The side wall has an off angle of not less than 50° and not more than 65° relative to a {0001} plane. A gate insulating film is provided on the side wall of the silicon carbide layer. The silicon carbide layer includes: a body region having a first conductivity type and facing a gate electrode with the gate insulating film being interposed therebetween; and a pair of regions separated from each other by the body region and having a second conductivity type. The body region has an impurity density of 5×1016 cm?3 or greater. This allows for an increased degree of freedom in setting a threshold voltage while suppressing decrease of channel mobility.

Abstract: A semiconductor device includes an element region and an end region, the element region having a semiconductor element formed therein, and the end region surrounding the element region. The semiconductor device includes a semiconductor substrate, a trench, an insulating layer, and a field plate conductive layer. The trench is formed in the semiconductor substrate so as to surround the element region in the end region. The field plate conductive layer is formed in the trench via the insulating layer.

Abstract: An apparatus (100) for fabricating a semiconductor thin film includes: substrate surface pretreatment means (101) for pretreating a surface of a substrate; organic layer coating means (102) for coating, with an organic layer, the substrate thus pretreated; focused light irradiation means (103) for irradiating, with focused light, the substrate coated with the organic layer, and for forming a growth-mask layer while controlling layer thickness; first thin film growth means (104) for selectively growing a semiconductor thin film over an area around the growth-mask layer; substrate surface treatment means (105) for, after exposing the surface of the substrate by removing the growth-mask layer, modifying the exposed surface of the substrate; and second thin film growth means (106) for further growing the semiconductor thin film and growing a semiconductor thin film over the modified surface of the substrate.

Abstract: A method of manufacturing a semiconductor device with an SON structure having a thick cavity inside a semiconductor substrate is disclosed. The method forms a plurality of trenches with a predetermined distance between adjacent trenches. Each trench has, at a middle portion between the trench top and bottom, an outwardly expanding sectional shape. High temperature annealing is conducted driving surface migration of silicon atoms in the surface region of the silicon substrate to close the top of the trench, resulting in formation of a plurality of small cavities composed of the trenches in the silicon substrate. Further high temperature annealing joins the plurality of small cavities to form a single cavity. Second opening width x2 at the middle portion ranges from 1.1 times to 1.5 times of first opening width x1 at the top of the trench. Aspect ratio of the trench is at least 8.

Abstract: Provided is a semiconductor device manufacturing method enabling miniaturization by forming a hole in a vertical shape, capable of reducing the number of processes as compared to conventional methods, and capable of increasing productivity. The semiconductor device manufacturing method includes: forming a hole in a substrate; forming a polyimide film within the hole; anisotropically etching the substrate without using a mask covering a sidewall portion of the polyimide film within the hole and removing at least a part of a bottom portion of the polyimide film within the hole while the sidewall portion of the polyimide film remains within the hole; and filling the hole with a conductive metal.

Abstract: A substrate for a light emitting diode (LED) can have one or more trenches formed therein so as to mitigate stress build up within the substrate due to mismatched thermal coefficients of expansion between the substrate and layers of material, e.g., semiconductor material, formed thereon. In this manner, the likelihood of damage to the substrate, such as cracking thereof, is substantially mitigated.

Abstract: A semiconductor memory device and a fabrication method thereof capable of improving electric contact characteristic between an access device and a lower electrode are provided. The semiconductor memory device includes an access device formed in a pillar shape on a semiconductor substrate, a first conductive layer formed over the access device, a protection layer formed on an edge of the first conductive layer to a predetermined thickness, and a lower electrode connected to the first conductive layer.

Abstract: The present disclosure provides a static random access memory (SRAM) cell. The SRAM cell includes a plurality of fin active regions formed on a semiconductor substrate, wherein the plurality of fin active regions include a pair adjacent fin active regions having a first spacing and a fin active region having a second spacing from adjacent fin active regions, the second spacing being greater than the first spacing; a plurality of fin field-effect transistors (FinFETs) formed on the plurality of fin active regions, wherein the plurality of FinFETs are configured to a first and second inverters cross-coupled for data storage and at least one port for data access; a first contact disposed between the first and second the fin active regions, electrically contacting both of the first and second the fin active regions; and a second contact disposed on and electrically contacting the third fin active region.

Abstract: A semiconductor device includes a semiconductor substrate. A first trench extends into or through the semiconductor substrate from a first side. A semiconductor layer adjoins the semiconductor substrate at the first side. The semiconductor layer caps the first trench at the first side. The semiconductor device further includes a contact at a second side of the semiconductor substrate opposite to the first side.

Abstract: There are provided a silicon substrate and a method of fabricating the same, the silicon substrate including: first and second silicon substrates having corresponding bonding surfaces; a silicon oxide film formed between the first and second silicon substrates and having at least one trench communicating with the outside; and a hermetic portion formed on an end portion of the trench according to oxidation of the silicon oxide film.

Abstract: A cavity is etched from a front surface into a semiconductor substrate. After providing an etch stop structure at the bottom of the cavity, the cavity is closed. From a back surface opposite to the front surface the semiconductor substrate is grinded at least up to an edge of the etch stop structure oriented to the back surface. Providing the etch stop structure at the bottom of an etched cavity allows for precisely adjusting a thickness of a semiconductor body of a semiconductor device.

Abstract: An MOS device includes a semiconductor layer of a first conductivity type and first and second source/drain regions of a second conductivity type formed in the semiconductor layer proximate an upper surface of the semiconductor layer. The first and second source/drain regions are spaced apart relative to one another. A gate is formed above and electrically isolated from the semiconductor layer, at least partially between the first and second source/drain regions. At least a given one of the first and second source/drain regions is configured having an effective width that is substantially greater than a width of a junction between the semiconductor layer and the given source/drain region.

Abstract: A method is described for filling cavities in wafers, the cavities being open to a predetermined surface of the wafer, including the following steps: applying a lacquer-like filling material to the predetermined surface of the wafer; heating the wafer at a first temperature; driving out gas bubbles enclosed in the filling material by heating the wafer under vacuum at a second temperature which is equal to or higher than the first temperature; and curing the filling material by heating the wafer at a third temperature which is higher than the second temperature. Furthermore, also described is a blind hole filled using such a method and general 3D cavities as well as a wafer having insulation trenches of a silicon via filled using such a method.

Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.

Abstract: The semiconductor device has insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a. A groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Defective filling of the buried conductor and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented.

Abstract: Semiconductor chips are provided. The semiconductor chip includes a semiconductor chip body having an arch-shaped groove in a backside thereof and a non-conductive material pattern filling the arch-shaped groove. Related methods are also provided.

Abstract: A semiconductor wafer with an assisting dicing structure. The wafer comprises a substrate having a front surface and a rear surface. The front surface of the substrate comprises at least two device regions separated by at least one dicing lane. The rear surface of the substrate comprises at least one pre-dicing trench formed therein and substantially aligned with the dicing lane. A method for dicing a semiconductor wafer is also disclosed.

Abstract: In order to form a more stable silicon pillar which can be used for the formation of vertical transistors in DRAM cells, a multi-step masking process is used. In a preferred embodiment, an oxide layer and a nitride layer are used as masks to define trenches, pillars, and active areas in a substrate. Preferably, two substrate etch processes use the masks to form three levels of bulk silicon.

Abstract: A device and method for forming nanostructures includes providing a monocrystalline semiconductor layer on a flexible substrate and stressing the substrate in accordance with a crystal cleave plane to initiate cracks in the semiconductor layer. The cracks are propagated on the crystal cleave plane through the semiconductor layer where the cracks are spaced by an intercrack distance as determined by applying a particular strain. The strain is released to provide parallel structures on the flexible substrate.

Abstract: A semiconductor substrate having a semiconductor device formable area, wherein a reinforcing part, which is thicker than the semiconductor device formable area and has a top part of which surface is flat, is formed on an outer circumference part of the semiconductor substrate, and an inner side surface connecting the top part of the reinforcing part and the semiconductor device formable area has a cross-sectional shape of which inner diameter becomes smaller as being closer to the semiconductor device formable area.

Abstract: Semiconductor structures are fabricated that include a semiconductor material bonded to a substrate with a layer of dielectric material between the semiconductor material and the substrate. At least one fluidic microchannel extends in a lateral direction through the layer of dielectric material between the semiconductor material and the substrate. The at least one fluidic microchannel includes at least one laterally extending section having a transverse cross-sectional shape entirely surrounded by the layer of dielectric material.

Abstract: In accordance with one or more embodiments, a flange package comprises a flange and an interposer having two or more fingers disposed in an interposer trench. The flange has a mold lock formed about a periphery of the interposer trench. A dielectric ring comprising a dielectric material is formed in the interposer trench, and in and around the periphery of the mold lock. A semiconductor die is disposed within the dielectric ring having gate pads and source pads formed on a first side, and having drain pads disposed on a second side of the die. The gate pads are coupled to the interposer and the source pads are coupled to the flange. A gate lead is coupled to the interposer and a drain lead is coupled to the drain pads. Other embodiments are disclosed.

Abstract: A method of forming a semiconductor device that includes providing a first strained layer of a first composition semiconductor material over a dielectric layer. A first portion of the layer of the first composition semiconductor material is etched or implanted to form relaxed islands of the first composition semiconductor material. A second composition semiconductor material is epitaxially formed over the relaxed island of the first composition semiconductor material. The second composition semiconductor material is intermixed with the relaxed islands of the first composition semiconductor material to provide a second strained layer having a different strain than the first strained layer.

Abstract: A technique for improving the characteristics of a semiconductor device (UMOSFET) is provided. In the UMOSFET in order to grow an epitaxial growth film on a trench side wall with an even film thickness, a channel is arranged in an optimum direction as a growth surface. For example, a trench is formed on an SiC substrate having a {0001} surface 4° off in a <11-20> direction as a main surface so that a channel surface becomes a {1-100} surface. With this configuration, an epitaxial growth with the even thickness can be conducted on the side wall from which the {1-100} surface of the trench is exposed. As a result, the unevenness of a channel resistance, and the insulation failure of a gate insulating film do not occur, and the yield is improved.

Abstract: A semiconductor device mounting structure includes: a substrate with an opening provided therein; a frame member with a frame body and a protruding portion that protrudes from the frame body, the frame body being formed and accommodated in a groove around the opening; a coreless substrate provided above the substrate and supported by the protruding portion of the frame member; and semiconductor elements provided on the coreless substrate.

Abstract: A method for forming a feature in an etch layer is provided. A photoresist layer is formed over the etch layer. The photoresist layer is patterned to form photoresist features with photoresist sidewalls. A control layer is formed over the photoresist layer and bottoms of the photoresist features. A conformal layer is deposited over the sidewalls of the photoresist features and control layer to reduce the critical dimensions of the photoresist features. Openings in the control layer are opened with a control layer breakthrough chemistry. Features are etched into the etch layer with an etch chemistry, which is different from the control layer break through chemistry, wherein the control layer is more etch resistant to the etch with the etch chemistry than the conformal layer.

Abstract: A hydrofluorocarbon gas is employed as a polymer deposition gas in an anisotropic etch process employing an alternation of an etchant gas and the polymer deposition gas to etch a deep trench in a semiconductor substrate. The hydrofluorocarbon gas can generate a thick carbon-rich and hydrogen-containing polymer on sidewalls of a trench at a thickness on par with the thickness of the polymer on a top surface of the semiconductor substrate. The thick carbon-rich and hydrogen-containing polymer protects sidewalls of a trench, thereby minimizing an undercut below a hard mask without degradation of the overall rate. In some embodiments, an improvement in the overall etch rate can be achieved.

Abstract: A photomask has a mask blank and a light shielding film formed on the mask blank. The light shielding film includes a plurality of opening traces extending in a first direction. An end of a first opening trace in the first direction and an end of a second opening trace in the first direction are in different positions in the first direction. The second opening trace adjoins the first opening trace.

Abstract: A groove structure formed on a surface of a substrate. The groove structure includes a lateral epitaxial pattern in a cross section perpendicular to the surface, which has: a first edge inclined to the surface; a second edge adjacent to first edge and parallel to the surface; a third edge parallel to the first edge, having a projection on the surface covering the second edge; and a fourth edge adjacent to the third edge. A first intersection between the second edge and the third edge on the second edge and an injection of a second intersection between the third edge and the fourth edge on the second edge are located on two sides of a third intersection between the first edge and the second edge, or the injection of the second intersection between the third edge and the fourth edge on the second edge coincides with the third intersection.

Abstract: A semiconductor device and manufacturing method are disclosed which prevent breakage and chipping of a semiconductor chip and improve device characteristics. A separation layer is in a side surface of an element end portion of the chip. An eave portion is formed by a depressed portion in the element end portion. A collector layer on the rear surface of the chip extends to a side wall and bottom surface of the depressed portion, and is connected to the separation layer. A collector electrode is over the whole surface of the collector layer, and is on the side wall of the depressed portion. The thickness of an outermost electrode film is 0.05 ?m or less. The collector electrode on the rear surface of the chip is joined onto an insulating substrate via a solder layer, which covers the collector electrode on a flat portion of the rear surface of the semiconductor chip.

Abstract: A method of forming a plurality of nanotubes is disclosed. Particularly, a substrate may be provided and a plurality of recesses may be formed therein. Further, a plurality of nanotubes may be formed generally within each of the plurality of recesses and the plurality of nanotubes may be substantially surrounded with a supporting material. Additionally, at least some of the plurality of nanotubes may be selectively shortened and at least a portion of the at least some of the plurality of nanotubes may be functionalized. Methods for forming semiconductor structures intermediate structures, and semiconductor devices are disclosed. An intermediate structure, intermediate semiconductor structure, and a system including nanotube structures are also disclosed.

Abstract: A method of making a transistor is disclosed. The method starts with applying a first photoresist and performing a first etching of the first side of a gate where the gate includes an oxide layer formed over a substrate and a conductive material formed over the oxide layer. The first etching is followed by implanting an impurity region into the substrate while using the first photoresist and the conductive material as a mask making the implantation of the impurity region self-aligned to the gate. The implantation is followed by applying a second photoresist and performing a second etching of the second side of the gate.

Abstract: A semiconductor structure includes a semiconductor substrate having a first region of a first polarity and a second region of a second polarity adjacent to the first region; and a first terminal including: a first deep trench located in the first region, a first node dielectric abutting all but an upper portion of sidewalls and a bottom of the first deep trench; a first conductive inner electrode inside the first node dielectric and electrically insulated from the first region by the first node dielectric; and a first electrical contact electrically coupling the first conductive inner electrode to the first region.

Abstract: A thinning method of a wafer is provided. The method includes the following steps. First, a wafer having a first surface, a second surface, and a side surface is provided, and the side surface is connected between the first surface and the second surface. At least one semiconductor device is formed on the first surface. Then, an anisotropy etching process is performed to the second surface with a mask to remove portions of the wafer while remaining the side surface thereby forming a number of grooves in the second surface and at least one reinforcing wall between the grooves. As a result, a thinned wafer is obtained.

Abstract: An active matrix substrate (20a) includes a plurality of pixel electrodes (18a) arranged in a matrix, and a plurality of TFTs (5) each connected to a corresponding one of the pixel electrodes (18a), and each including a gate electrode (11a) provided on an insulating substrate (10a), a gate insulating film (12a) covering the gate electrode (11a), a semiconductor layer (16a) provided on the gate insulating film (12a) and having a channel region (C) overlapping the gate electrode (11a), and a source electrode (15aa) and a drain electrode (15b) of copper or copper alloy provided on the gate insulating film (12a) and separated from each other by the channel region (C) of the semiconductor layer (16a). The semiconductor layer (16a) is formed of an oxide semiconductor and covers the source electrode (15aa) and the drain electrode (15b).

Abstract: The invention notably concerns a method for depositing nano-objects on a surface. The method includes: providing a substrate with surface patterns on one face thereof; providing a transfer layer on said face of the substrate; functionalizing areas on a surface of the transfer layer parallel to said face of the substrate, at locations defined with respect to said surface patterns, such as to exhibit enhanced binding interactions with nano-objects; depositing nano-objects and letting them get captured at the functionalized areas; and thinning down the transfer layer by energetic stimulation to decompose the polymer into evaporating units, until the nano-objects reach the surface of the substrate. The invention also provides a semiconductor device which includes a substrate and nano-objects accurately disposed on the substrate.

Abstract: Semiconductor structures and methods of fabrication are provided. One semiconductor structure includes a substrate, a semiconductor device layer supported by the substrate, and one or more buried through substrate vias (TSVs) disposed at least partially within the substrate. The buried through substrate via(s) is buried within the semiconductor substrate, and terminates below the semiconductor device layer of the semiconductor structure, and the semiconductor device layer extends over the buried through substrate via(s), thereby providing the buried through substrate via(s) without consuming space within the semiconductor device layer. A dielectric layer may be disposed between the substrate and the semiconductor device layer, with the TSV(s) terminating at a first end within the dielectric layer. Alternatively, the semiconductor device layer may be an epitaxially-grown layer extending over the TSV(s).

Abstract: An embodiment is a method and apparatus to induce flaw formation in nitride semiconductors. Regions of a thin film structure are selectively decomposed within a thin film layer at an interface with a substrate to form flaws in a pre-determined pattern within the thin film structure. The flaws locally concentrate stress in the pre-determined pattern during a stress-inducing operation. The stress-inducing operation is performed. The stress-inducing operation causes the thin film layer to fracture at the pre-determined pattern.

Abstract: Disclosed herein are various methods of forming spacers on FinFETs and other semiconductor devices. In one example, the method includes forming a plurality of spaced-apart trenches in a semiconducting substrate that defines a fin, forming a first layer of insulating material in the trenches that covers a lower portion of the fin but exposes an upper portion of the fin, and forming a second layer of insulating material on the exposed upper portion of the fin. The method further comprises selectively forming a dielectric material above an upper surface of the fin and in a bottom of the trench, depositing a layer of spacer material above a gate structure of the device and above the dielectric material above the fin and in the trench, and performing an etching process on the layer of spacer material to define sidewall spacers positioned adjacent the gate structure.

Abstract: A device including a surface layer of a selected material in a predetermined pattern on a substrate surface. A groove or ridge arranged in the substrate surface includes a bottom or top face, respectively, and at least one side face sloping relative to the bottom or top face. The surface layer is deposited on a part of the substrate including the groove or ridge by vacuum chamber sputtering the selected material from a sputtering source whilst moving the substrate past the sputtering source in a direction substantially perpendicular to a sputtering main lobe direction and with a normal to the substrate surface substantially in a predefined angle with the main lobe direction. By uniformly etching away surface layer material deposited on the substrate by the sputtering until freeing a substantial part of the side face, the predetermined pattern becomes defined substantially by the bottom face or the top face.

Abstract: A semiconductor device is provided. The device includes a semiconductor substrate, first and second projections extending upwardly from the substrate, the projections having respective first and second channel regions therein, and a first gate structure engaging the first projection adjacent the first channel region. The first gate structure includes a first dielectric material over the first channel region, a first opening over the first dielectric material and the first channel region, and a pure first metal with an n-type work function value conformally deposited in the first opening. The device also includes a second gate structure engaging the second projection adjacent the second channel region. The second gate structure includes a second dielectric material over the second channel region, a second opening over the second dielectric material and the second channel region, and a pure second metal with a p-type work function value conformally deposited in the second opening.

Abstract: A semiconductor device includes: a semiconductor chip including: a first main face having an edge portion, a second main face locating the opposite side to the first main face, a crystalline defect region present within a region including at least the edge portion being adjacent to the first main face, the crystalline defect region being configured to have lower stress than the stress in the other semiconductor region for the same strain; and a metallic substrate to be bonded via a bonding member to the first main face of the semiconductor chip.

Abstract: Methods for fabricating sublithographic, nanoscale microstructures in line arrays utilizing self-assembling block copolymers, and films and devices formed from these methods are provided. Semiconductor structures may include self-assembled block copolymer materials in the form of lines of half-cylinders of a minority block matrix of a majority block of the block copolymer. The lines of half-cylinders may be within trenches in the semiconductor structures.

Abstract: This invention relates to a dipping solution used in a process for producing a siliceous film. The present invention provides a dipping solution and a siliceous film-production process employing the solution. The dipping solution enables to form a homogeneous siliceous film even in concave portions of a substrate having concave portions and convex portions. The substrate is coated with a polysilazane composition, and then dipped in the solution before fire. The dipping solution comprises hydrogen peroxide, a foam-deposit inhibitor, and a solvent.