With Low Resistance Ohmic Connection Means Along Exposed Mesa Edge (e.g., Contact Or Heavily Doped Region Along Exposed Mesa To Reduce "skin Effect" Losses In Microwave Diode) Patents (Class 257/624)
  • Patent number: 10177269
    Abstract: A photovoltaic device includes a first contact layer formed on a substrate. An absorber layer includes Cu—Zn—Sn—S(Se) (CZTSSe) on the first contact layer. A buffer layer is formed in contact with the absorber layer. Metal dopants are dispersed in a junction region between the absorber layer and the buffer layer. The metal dopants have a valence between the absorber layer and the buffer layer to increase junction potential. A transparent conductive contact layer is formed over the buffer layer.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: January 8, 2019
    Assignee: International Business Machines Corporation
    Inventors: Talia S. Gershon, Jeehwan Kim, Yun Seog Lee, Teodor K. Todorov
  • Patent number: 8981557
    Abstract: A photovoltaic cell manufacturing method is disclosed. Methods include manufacturing a photovoltaic cell having a selective emitter and buried contact (electrode) structure utilizing nanoimprint technology. The methods include providing a semiconductor substrate having a first surface and a second surface opposite the first surface; forming a first doped region in the semiconductor substrate adjacent to the first surface; performing a nanoimprint process and an etching process to form a trench in the semiconductor substrate, the trench extending into the semiconductor substrate from the first surface; forming a second doped region in the semiconductor substrate within the trench, the second doped region having a greater doping concentration than the first doped region; and filling the trench with a conductive material. The nanoimprint process uses a mold to define a location of an electrode line layout.
    Type: Grant
    Filed: September 17, 2012
    Date of Patent: March 17, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Chiang Tu, Chun-Lang Chen
  • Patent number: 8951864
    Abstract: A semiconductor device includes a substrate; a storage element disposed over the substrate in a first region; a control gate disposed over the storage element; a high-k dielectric layer disposed on the substrate in a second region adjacent the first region; and a metal select gate disposed over the high-k dielectric layer and adjacent to the storage element and the control gate.
    Type: Grant
    Filed: February 13, 2012
    Date of Patent: February 10, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hsiung Wang, Chih-Ren Hsieh, Tung-Sheng Hsiao
  • Patent number: 8772911
    Abstract: A semiconductor diode has a first semiconductor layer (102) of a first conductivity type and a second semiconductor layer of a second conductivity type having a doping. The second semiconductor layer has a vertical electrical via region (106) which is connected to the first semiconductor layer and in which the doping is modified in such a way that the electrical via region (106) has the first conductivity type. A method for producing such a semiconductor diode is described.
    Type: Grant
    Filed: February 10, 2011
    Date of Patent: July 8, 2014
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Tony Albrecht, Markus Maute, Martin Reufer, Heribert Zull
  • Patent number: 8772930
    Abstract: A multilayer microelectronic device package includes one or more vertical electrical contacts. At least one semiconductor material layer is provided having one or more electrical devices fabricated therein. An electrical contact pad can be formed on or in the semiconductor material layer. Another material layer is positioned adjacent to the semiconductor material layer and includes a conductive material stud embedded in or bonded to the layer. A via is formed through at least a portion of the semiconductor material layer and the electrical contact pad and into the adjacent layer conducting material stud. The via is constructed such that the via tip terminates within the conducting material stud, exposing the conducting material. A metallization layer is disposed in the via such that the metallization layer contacts both the electrical contact pad and the conducting material stud exposed by the via tip.
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: July 8, 2014
    Assignee: Hong Kong Applied Science and Technology Research Institute Company Limited
    Inventors: Pui Chung Simon Law, Dan Yang, Xunqing Shi
  • Patent number: 8735941
    Abstract: Disclosed herein is a nitride based semiconductor device including: a base substrate; an epitaxial growth layer disposed on the base substrate and generating a 2-dimensional electron gas in an inner portion thereof; and an electrode structure disposed on the epitaxial growth layer, wherein the electrode structure includes: a gate electrode; a source electrode disposed at one side of the gate electrode; and a drain electrode disposed at the other side of the gate electrode and having an extension part extended to the inner portion of the epitaxial growth layer to contact the 2-dimensional electron gas.
    Type: Grant
    Filed: March 16, 2011
    Date of Patent: May 27, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Kiyeol Park, Woochul Jeon, Younghwan Park
  • Patent number: 8653565
    Abstract: Various aspects of the technology includes a quad semiconductor power and/or switching FET comprising a pair of control/sync FET devices. Current may be distributed in parallel along source and drain fingers. Gate fingers and pads may be arranged in a serpentine configuration for applying gate signals to both ends of gate fingers. A single continuous ohmic metal finger includes both source and drain regions and functions as a source-drain node. A set of electrodes for distributing the current may be arrayed along the width of the source and/or drain fingers and oriented to cross the fingers along the length of the source and drain fingers. Current may be conducted from the electrodes to the source and drain fingers through vias disposed along the surface of the fingers. Heat developed in the source, drain, and gate fingers may be conducted through the vias to the electrodes and out of the device.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: February 18, 2014
    Assignee: Sarda Technologies, Inc.
    Inventor: James L. Vorhaus
  • Patent number: 8592871
    Abstract: A nitride semiconductor device in which contact resistance between an ohmic electrode and an ohmic recess portion is reduced and a method of manufacturing the nitride semiconductor device are provided. The nitride semiconductor device includes: a first nitride semiconductor layer formed on a substrate; a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a bandgap wider than a bandgap of the first nitride semiconductor layer; an ohmic recess portion formed in at least the second nitride semiconductor layer; and an ohmic electrode provided in contact with the ohmic recess portion. The ohmic recess portion includes a corrugated structure in at least a part of a plane in contact with the ohmic electrode.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: November 26, 2013
    Assignee: Panasonic Corporation
    Inventor: Ryo Kajitani
  • Patent number: 8536042
    Abstract: A process for forming a vertically conducting semiconductor device includes providing a semiconductor substrate having a topside surface and a backside surface. The semiconductor substrate serves as a terminal of the vertically conducting device for biasing the vertically conducting device during operation. The process also includes forming an epitaxial layer extending over the topside surface of the semiconductor substrate but terminating prior to reaching an edge of the semiconductor substrate so as to form a recessed region along a periphery of the semiconductor substrate. The method also includes forming an interconnect layer extending into the recessed region but terminating prior to reaching an edge of the semiconductor substrate. The interconnect layer electrically contacts the topside surface of the semiconductor substrate in the recessed region to thereby provide a topside contact to the semiconductor substrate.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: September 17, 2013
    Assignee: Fairchild Semiconductor Corporation
    Inventors: John T. Andrews, Hamza Yilmaz, Bruce Marchant, Ihsiu Ho
  • Patent number: 8466555
    Abstract: A semiconductor structure is provided having: a semiconductor; a gold-free electrically conductive structure in ohmic contact with the semiconductor; and a pair of electrically conductive layers separated by a layer of silicon. The structure includes: a refractory metal layer disposed in contact with the semiconductor; and wherein one of the pair of electrically conductive layers separated by the layer of silicon is the refractory metal layer. A second layer of silicon is disposed on a second one of the pair of pair of electrically conductive layers and including a third electrically conducive layer on the second layer of silicon. In one embodiment, the semiconductor includes a III-V material.
    Type: Grant
    Filed: June 3, 2011
    Date of Patent: June 18, 2013
    Assignee: Raytheon Company
    Inventors: Ram V. Chelakara, Thomas E. Kazior, Jeffrey R. LaRoche
  • Patent number: 8368181
    Abstract: The invention provides a mesa semiconductor device and a method of manufacturing the same which enhance the yield and productivity. An N? type semiconductor layer is formed on a front surface of a semiconductor substrate, and a P type semiconductor layer is formed thereon. An anode electrode is further formed on the P type semiconductor layer so as to be connected to the P type semiconductor layer, and a mesa groove is formed from the front surface of the P type semiconductor layer deeper than the N? type semiconductor layer so as to surround the anode electrode. Then, a second insulation film is formed from inside the mesa groove onto the P type semiconductor layer on the outside of the mesa groove. The second insulation film is made of an organic insulator such as polyimide type resin or the like. The lamination body made of the semiconductor substrate and the layers laminated thereon is then diced along a scribe line.
    Type: Grant
    Filed: December 18, 2008
    Date of Patent: February 5, 2013
    Assignees: SANYO Semiconductor Co., Ltd., SANYO Semiconductor Manufacturing Co., Ltd., Semiconductor Components Industries, LLC
    Inventors: Akira Suzuki, Katsuyuki Seki, Keita Odajima
  • Patent number: 8293645
    Abstract: A photovoltaic cell manufacturing method is disclosed. Methods include manufacturing a photovoltaic cell having a selective emitter and buried contact (electrode) structure utilizing nanoimprint technology. The methods include providing a semiconductor substrate having a first surface and a second surface opposite the first surface; forming a first doped region in the semiconductor substrate adjacent to the first surface; performing a nanoimprint process and an etching process to form a trench in the semiconductor substrate, the trench extending into the semiconductor substrate from the first surface; forming a second doped region in the semiconductor substrate within the trench, the second doped region having a greater doping concentration than the first doped region; and filling the trench with a conductive material. The nanoimprint process uses a mold to define a location of an electrode line layout.
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: October 23, 2012
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Chiang Tu, Chun-Lang Chen
  • Patent number: 8278658
    Abstract: An device according to the present invention comprises: graphene; and a metal electrode, the metal electrode and the graphene being electrically connected, the following relationship of Eq. (1) being satisfied: coth ? ( r GP r C ? S ) < 1.3 , Eq . ? ( 1 ) where rGP (in units of ?/?m2) denotes the electrical resistance of a graphene layer per unit area, rC (in units of ??m2) denotes the contact resistance per unit area between the graphene layer and a metal electrode, and S denotes the contact area (in units of ?m2) between the graphene layer and the metal electrode.
    Type: Grant
    Filed: April 26, 2010
    Date of Patent: October 2, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Makoto Okai, Motoyuki Hirooka
  • Patent number: 8242539
    Abstract: A field effect transistor comprises a carrier transit layer in a stacked layer structure provided with a plurality of nitride semiconductor layers, a gate electrode provided on the stacked layer structure and a source electrode and a drain electrode placing the gate electrode in between.
    Type: Grant
    Filed: March 14, 2006
    Date of Patent: August 14, 2012
    Assignee: Nichia Corporation
    Inventor: Yuji Ohmaki
  • Patent number: 8173534
    Abstract: A semiconductor wafer with rear side identification and to a method for producing the same is disclosed. In one embodiment, the rear side identification has a multiplicity of information regarding the monocrystalline and surface and also rear side constitution. A multiplicity of semiconductor device positions arranged in rows and columns are provided on the top side of the semiconductor wafer, an information chip being arranged at an exposed semiconductor device position, the information chip having at least the information of the rear side identification.
    Type: Grant
    Filed: February 28, 2011
    Date of Patent: May 8, 2012
    Assignee: Infineon Technologies AG
    Inventors: Stephan Bradl, Rainer Holmer
  • Patent number: 8093688
    Abstract: Device comprising an ohmic via contact, and method of fabricating thereof. A preferred embodiment comprises forming a metal layer over a substrate, forming a conductive barrier layer over the metal layer, depositing an insulating layer over the conductive barrier layer, creating an opening in the insulating layer to expose the conductive barrier layer, and forming a via contact in the opening. The conductive barrier layer protects the metal layer by preventing the formation of an oxide layer, which could reduce conductivity.
    Type: Grant
    Filed: October 8, 2009
    Date of Patent: January 10, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: David A. Rothenbury, James D. Huffman
  • Patent number: 8084845
    Abstract: Novel etch techniques are provided for shaping silicon features below the photolithographic resolution limits. FinFET devices are defined by recessing oxide and exposing a silicon protrusion to an isotropic etch, at least in the channel region. In one implementation, the protrusion is contoured by a dry isotropic etch having excellent selectivity, using a downstream microwave plasma etch.
    Type: Grant
    Filed: February 25, 2010
    Date of Patent: December 27, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Kevin J. Torek, Mark Fischer, Robert J. Hanson
  • Patent number: 7936049
    Abstract: It is an object of the present invention to provide a nitride semiconductor device with low parasitic resistance by lowering barrier height to reduce contact resistance at an interface of semiconductor and metal. The nitride semiconductor device includes a GaN layer, a device isolation layer, an ohmic electrode, an n-type Al0.25Ga0.75N layer, a sapphire substrate, and a buffer layer. A main surface of the n-type Al0.25Ga0.75N layer is on (0 0 0 1) plane as a main surface, and concaves are arranged in a checkerboard pattern on the surface. The ohmic electrode contacts the sides of the concaves of the n-type Al0.25Ga0.75N layer, and the sides of the concaves are on non-polar surfaces such as (1 1 ?2 0) plane or (1 ?1 0 0) plane.
    Type: Grant
    Filed: June 25, 2010
    Date of Patent: May 3, 2011
    Assignee: Panasonic Corporation
    Inventors: Masayuki Kuroda, Tetsuzo Ueda
  • Patent number: 7911036
    Abstract: A semiconductor wafer with rear side identification and to a method for producing the same is disclosed. In one embodiment, the rear side identification has a multiplicity of information regarding the monocrystalline and surface and also rear side constitution. A multiplicity of semiconductor device positions arranged in rows and columns are provided on the top side of the semiconductor wafer, an information chip being arranged at an exposed semiconductor device position, the information chip having at least the information of the rear side identification.
    Type: Grant
    Filed: January 11, 2007
    Date of Patent: March 22, 2011
    Assignee: Infineon Technologies AG
    Inventors: Stephan Bradl, Rainer Holmer
  • Patent number: 7902639
    Abstract: Improved methods and articles providing conformal coatings for a variety of devices including electronic, semiconductor, and liquid crystal display devices. Peptide formulations which bind to nanoparticles and substrates, including substrates with trenches and vias, to provide conformal coverage as a seed layer. The seed layer can be further enhanced with use of metallic films deposited on the seed layer. Seed layers can be characterized by AFM measurements and improved seed layers provide for better enhancement layers including lower resistivity in the enhancement layer. Peptides can be identified by phage display.
    Type: Grant
    Filed: November 16, 2005
    Date of Patent: March 8, 2011
    Assignee: Siluria Technologies, Inc.
    Inventors: Philip E. Garrou, Michael R. Knapp, Hash Pakbaz, Florian Pschenitzka, Xina Quan, Michael A. Spaid
  • Patent number: 7888775
    Abstract: Some embodiments relate to an apparatus that exhibits vertical diode activity to occur between a semiconductive body and an epitaxial film that is disposed over a doping region of the semiconductive body. Some embodiments include an apparatus that causes both vertical and lateral diode activity. Some embodiments include a gated vertical diode for a finned semiconductor apparatus. Process embodiments include the formation of vertical-diode apparatus.
    Type: Grant
    Filed: September 27, 2007
    Date of Patent: February 15, 2011
    Assignee: Infineon Technologies AG
    Inventors: Christian Russ, Christian Pacha, Snezana Jenei, Klaus Schruefer
  • Patent number: 7786511
    Abstract: To provide a semiconductor device that has a sufficiently low on-resistance and excellent low-capacitance and high-speed characteristics as compared with conventional GaN-based diodes. The semiconductor device includes: a substrate (101); a buffer layer (102); a stack structure (103 and 104) including at least one heterojunction unit (103 and 104) that is a stack of a layer (GaN layer 103) made of a nitride semiconductor and a layer (AlGaN layer 104) made of another nitride semiconductor having a larger band gap than the nitride semiconductor (GaN layer 103); a Schottky electrode (106) that is placed at a first end of the stack structure (103 and 104) and forms a Schottky barrier contact with the heterojunction unit (103 and 104); and an ohmic electrode (107) that is placed at a second end of the stack structure (103 and 104) and forms an ohmic contact with the heterojunction unit (103 and 104).
    Type: Grant
    Filed: October 29, 2008
    Date of Patent: August 31, 2010
    Assignee: Panasonic Corporation
    Inventor: Hidetoshi Ishida
  • Patent number: 7777305
    Abstract: It is an object of the present invention to provide a nitride semiconductor device with low parasitic resistance by lowering barrier height to reduce contact resistance at an interface of semiconductor and metal. The nitride semiconductor device includes a GaN layer, a device isolation layer, an ohmic electrode, an n-type Al0.25Ga0.75N layer, a sapphire substrate, and a buffer layer. A main surface of the n-type Al0.25Ga0.75N layer is on (0 0 0 1) plane as a main surface, and concaves are arranged in a checkerboard pattern on the surface. The ohmic electrode contacts the sides of the concaves of the n-type Al0.25Ga0.75N layer, and the sides of the concaves are on non-polar surfaces such as (1 1 ?2 0) plane or (1 ?1 0 0) plane.
    Type: Grant
    Filed: March 4, 2008
    Date of Patent: August 17, 2010
    Assignee: Panasonic Corporation
    Inventors: Masayuki Kuroda, Tetsuzo Ueda
  • Patent number: 7705431
    Abstract: A method of improving adhesion between layers in the formation of a semiconductor device and integrated circuit, and the resultant intermediate semiconductor structure, which include a substrate layer with a low k insulating layer thereover. The low k insulating layer includes a treated surface area of adsorbed gaseous particles. This treated surface area is formed by flowing a gas, preferably, silane, disilane, dichlorosilane, germane or combinations thereof, over a surface of the heated low k insulating layer for adsorption of such gaseous particles onto the heated surface, wherein the insulating layer maintains its original thickness. A capping layer is then deposited directly over the insulating layer wherein the treated surface area of the insulating layer significantly improves adhesion between the insulating layers and the capping layers to prevent delamination therebetween during subsequent processing steps of forming the integrated circuit.
    Type: Grant
    Filed: April 1, 2008
    Date of Patent: April 27, 2010
    Assignee: Novellius Systems, Inc.
    Inventors: Mahesh Sanganeria, Bart van Schravendijk
  • Patent number: 7704874
    Abstract: According to an exemplary embodiment, a method for fabricating a frontside through-wafer via in a processed wafer includes forming a through-wafer via opening through at least one interlayer dielectric layer in a through-wafer via region of the processed wafer. The method further includes extending the through-wafer via opening through a substrate to a target depth. The method further includes forming a first conductive layer in the through-wafer via opening and over a through-wafer via pad, which is situated over the at least one interlayer dielectric layer. The first conductive layer in the through-wafer via opening forms an electrical connection between the substrate and the through-wafer via pad. The method further includes forming a second conductive layer on the backside surface of the processed wafer, where the second conductive layer is in electrical contact with the first conductive layer and the substrate.
    Type: Grant
    Filed: December 18, 2006
    Date of Patent: April 27, 2010
    Assignee: Newport Fab, LLC
    Inventors: Arjun Kar-Roy, Marco Racanelli, David J. Howard
  • Patent number: 7687889
    Abstract: The present invention relates to a light emitting display device, such as an organic electroluminescent device, and a method for manufacturing the same. Particularly, the present invention relates to reducing electrical resistance between the scan lines and the cathode electrode layers so that scan line signals do not degrade significantly degrade. One way to achieve this is to use materials to form the conducting layers of the scan line and the cathode electrode layers such that the conductivities of the conducting layers and the cathode electrode layer are as identical as possible. For example, if a same metal such as aluminum is used to form both the conducting layer and the cathode electrode layer, the resistance would be significantly lowered. In addition, a large contacting area may be provided.
    Type: Grant
    Filed: December 27, 2005
    Date of Patent: March 30, 2010
    Assignee: LG Electronics Inc.
    Inventor: Hak Su Kim
  • Patent number: 7687908
    Abstract: A thin film electrode for ohmic contact of a p-type GaN semiconductor includes first and second electrode layers sequentially stacked on a p-type GaN layer. The first electrode layer may include an Ni-based alloy, a Cu-based alloy, a Co-based alloy, or a solid solution capable of forming a p-type thermo-electronic oxide or may include a Ni-oxide doped with at least one selected from Al, Ga, and In. The second electrode layer may include at least one selected from the group consisting of Au, Pd, Pt, Ru, Re, Sc, Mg, Zn, V, Hf, Ta, Rh, Ir, W, Ti, Ag, Cr, Mo, Nb, Ca, Na, Sb, Li, In, Sn, Al, Ni, Cu, and Co. Furthermore, a method of fabricating the thin film electrode is provided.
    Type: Grant
    Filed: July 9, 2004
    Date of Patent: March 30, 2010
    Assignees: Samsung Electronics Co., Ltd., Gwangju Institute of Science and Technology
    Inventors: Dong-seok Leem, June-o Song, Sang-ho Kim, Tae-yeon Seong
  • Patent number: 7619282
    Abstract: There is disclosed a hybrid circuit in which a circuit formed of TFTs in integrated with an RF filter. The TFTs are fabricated on a quartz substrate. A ceramic filter forming the RF filter is fabricated on another substrate. Terminals extend through the quartz substrate. The TFTs are connected with the ceramic filter via the terminals. Thus, an RF module is constructed.
    Type: Grant
    Filed: February 28, 2006
    Date of Patent: November 17, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Satoshi Teramoto
  • Patent number: 7586131
    Abstract: A transistor array includes conductor lines, function lines, and transistors. Each of the conductor lines includes a core and a conductor layer that covers the core. Each of the function lines includes a core, at least the surface of which is electrically conductive, an insulating layer that covers the core, and a semiconductor layer that covers the insulating layer. Each of the function lines contacts with, and crosses, the conductor lines. Each of the transistors includes a first ohmic contact region, which is defined by a region where one of the conductor lines crosses one of the function lines and which makes an ohmic contact with the semiconductor layer, a second ohmic contact region, which also makes an ohmic contact with the semiconductor layer, and a channel region, which is defined in the semiconductor layer between the first and second ohmic contact regions.
    Type: Grant
    Filed: January 25, 2005
    Date of Patent: September 8, 2009
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hirohiko Nishiki, Kazuki Kobayashi
  • Patent number: 7544557
    Abstract: A Schottky diode exhibiting low series resistance is efficiently fabricated using a substantially standard CMOS process flow by forming the Schottky diode using substantially the same structures and processes that are used to form a field effect transistor (FET) of a CMOS IC device. Polycrystalline silicon, which is used to form the gate structure of the FET, is utilized to form an isolation structure between the Schottky barrier and backside structure of the Schottky diode. Silicide (e.g., cobalt silicide (CoSi2)) structures, which are utilized to form source and drain metal-to-silicon contacts in the FET, are used to form the Schottky barrier and backside Ohmic contact of the Schottky diode. Heavily doped drain (HDD) diffusions and lightly doped drain (LDD) diffusions, which are used to form source and drain diffusions of the FET, are utilized to form a suitable contact diffusion under the backside contact silicide.
    Type: Grant
    Filed: October 21, 2005
    Date of Patent: June 9, 2009
    Assignee: Tower Semiconductor Ltd.
    Inventors: Sharon Levin, Shye Shapira, Ira Naot, Robert J. Strain, Yossi Netzer
  • Patent number: 7381997
    Abstract: A structure and method of fabricating lateral diodes. The diodes include Schottky diodes and PIN diodes. The method of fabrication includes forming one or more doped regions and more trenches in a silicon substrate and forming metal silicides on the sidewalls of the trenches. The fabrication of lateral diodes may be integrated with the fabrication of field effect, bipolar and SiGe bipolar transistors.
    Type: Grant
    Filed: November 26, 2007
    Date of Patent: June 3, 2008
    Assignee: International Business Machines Corporation
    Inventors: Douglas Duane Coolbaugh, Jeffrey Bowman Johnson, Xuefeng Liu, Bradley Alan Orner, Robert Mark Rassel, David Charles Sheridan
  • Patent number: 7368822
    Abstract: The present invention provides an ohmic contact for a copper metallization whose heat diffusion is improved and cost is reduced. Therein, the ohmic contact is formed through a depositing and an annealing of three metal layers of Pd, Ge and Cu; and, the contact resistance of the ohmic contact is adjusted by the thicknesses of the three layers.
    Type: Grant
    Filed: March 17, 2006
    Date of Patent: May 6, 2008
    Assignee: National Chiao Tung University
    Inventors: Cheng-Shih Lee, Edward Yi Chang, Ke-Shian Chen
  • Patent number: 7335927
    Abstract: A structure and method of fabricating lateral diodes. The diodes include Schottky diodes and PIN diodes. The method of fabrication includes forming one or more doped regions and more trenches in a silicon substrate and forming metal silicides on the sidewalls of the trenches. The fabrication of lateral diodes may be integrated with the fabrication of field effect, bipolar and SiGe bipolar transistors.
    Type: Grant
    Filed: January 30, 2006
    Date of Patent: February 26, 2008
    Assignee: Internatioanl Business Machines Corporation
    Inventors: Douglas Duane Coolbaugh, Jeffrey Bowman Johnson, Xuefeng Liu, Bradley Alan Orner, Robert Mark Rassel, David Charles Sheridan
  • Patent number: 7208784
    Abstract: A single-electron transistor includes a projecting feature, such as a pyramid, that projects from a face of a substrate. A first electrode is provided on the substrate face that extends onto the projecting feature. A second electrode is provided on the substrate face that extends onto the projecting feature and that is spaced apart from the first electrode. Accordingly, the geometric configuration of the projecting feature can define the spacing between the first and second electrodes. At least one nanoparticle is provided on the projecting feature between the first and second electrodes.
    Type: Grant
    Filed: December 17, 2004
    Date of Patent: April 24, 2007
    Assignee: Quantum Logic Devices, Inc.
    Inventor: Louis C. Brousseau, III
  • Patent number: 7170101
    Abstract: A nitride-based semiconductor light-emitting device includes a light-emitting element having an n-GaN substrate and a nitride-based semiconductor multilayer film formed on the n-GaN substrate. The n-GaN substrate of the light-emitting element is fixed to a mount surface. The n-GaN substrate has one surface with the nitride-based semiconductor multilayer film formed thereon and an opposite surface with a metal layer and an ohmic electrode formed thereon. The metal layer contains a first metal and a second metal and the ohmic electrode is formed of the second metal. The adhesion between the ohmic electrode and the n-GaN substrate is thus improved. Accordingly, the semiconductor light-emitting device which is highly reliable with respect to the thermal strain from the mount surface can be provided.
    Type: Grant
    Filed: May 14, 2002
    Date of Patent: January 30, 2007
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masaki Tatsumi, Toshio Hata, Mayuko Fudeta
  • Patent number: 7154148
    Abstract: There is disclosed a hybrid circuit in which a circuit formed by TFTs is integrated with an RF filter. The TFTs are fabricated on a quartz substrate. A ceramic filter forming the RF filter is fabricated on another substrate. Terminals extend through the quartz substrate. The TFTs are connected with the ceramic filter via the terminals. Thus, an RF module is constructed.
    Type: Grant
    Filed: March 15, 2004
    Date of Patent: December 26, 2006
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Satoshi Teramoto
  • Patent number: 6906401
    Abstract: A method of forming a quasi-self-aligned heterojunction bipolar transistor (HBT) that exhibits high-performance is provided. The method includes the use of a patterned emitter landing pad stack which serves to improve the alignment for the emitter-opening lithography and as an etch stop layer for the emitter opening etch. The present invention also provides an HBT that includes a raised extrinsic base having monocrystalline regions located beneath the emitter landing pad stack.
    Type: Grant
    Filed: May 28, 2004
    Date of Patent: June 14, 2005
    Assignee: International Business Machines Corporation
    Inventors: James S. Dunn, Natalie B. Feilchenfeld, Qizhi Liu, Andreas D. Stricker
  • Patent number: 6888171
    Abstract: A semi-conductor light emitting diode includes closely spaced n and p electrodes formed on the same side of a substrate to form an LED with a small foot-print. A semi-transparent U shaped p contact layer is formed along three sides of the top surface of the underlying window layer. The p electrode is formed on the p contact layer centered on the closed end of the U shaped layer. An n contact layer is formed on an n cladding layer and centered in the open end of the U of the p contact layer. The n electrode is formed on the n contact layer. The n and p electrodes are electrically isolated from one another by either a trench or an insulator, situated between the electrodes.
    Type: Grant
    Filed: December 22, 2000
    Date of Patent: May 3, 2005
    Assignee: Dallan Luming Science & Technology Group Co., Ltd.
    Inventors: Heng Liu, Changhua Chen
  • Patent number: 6853079
    Abstract: The radio frequency (RF) impedance of a metal trace at gigahertz frequencies is reduced by forming the metal trace to have a base region and a number of fins that extend away from the base region. When formed in a spiral configuration having a number of loops, the metal trace forms an inductor with an increased quality factor (Q).
    Type: Grant
    Filed: August 15, 2002
    Date of Patent: February 8, 2005
    Assignee: National Semiconductor Corporation
    Inventors: Peter J. Hopper, Peter Johnson, Kyuwoon Hwang, Michael Mian, Robert Drury
  • Patent number: 6835967
    Abstract: A semiconductor diode structure is provided which includes a substrate; a fin formed of a semiconducting material positioned vertically on the substrate, the fin includes a first heavily-doped region of a first doping type on one side and a second heavily-doped region of a second doping type on an opposite side; and a first conductor contacting the first heavily-doped region and a second conductor contacting the second heavily-doped region.
    Type: Grant
    Filed: March 25, 2003
    Date of Patent: December 28, 2004
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yee-Chia Yeo, Fu-Liang Yang
  • Patent number: 6818952
    Abstract: A multi-mesa FET structure with doped sidewalls for source/drain regions and methods for forming the same are disclosed. The exposure of the source and drain sidewalls during the manufacture enables uniform doping of the entire sidewalls especially when geometry-independent doping methods, such as gas phase doping or plasma doping, is used. The resulting device has depth independent and precisely controlled threshold voltage and current density and can have very high current per unit area of silicon as the mesas can be very high compared with mesas that could be formed in prior arts. Methods of providing multi-mesa FET structures are provided which employ either a damascene gate process or a damascene replacement gate process instead of conventional subtractive etching methods.
    Type: Grant
    Filed: October 1, 2002
    Date of Patent: November 16, 2004
    Assignee: International Business Machines Corporation
    Inventors: Toshiharu Furukawa, Jack A. Mandelman, Byeongju Park
  • Patent number: 6794720
    Abstract: In a semiconductor device in which the gate electrode of a MISFET formed on a semiconductor substrate is electrically connected to a well region under the channel of the MISFET, the MISFET is formed in an island-shaped element region formed on the semiconductor substrate, and electrical connection between the gate electrode of the MISFET and the well region in the semiconductor substrate is done on the side surface of the island-shaped element region.
    Type: Grant
    Filed: July 23, 2002
    Date of Patent: September 21, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsushi Yagishita, Tomohiro Saito, Toshihiko Iinuma
  • Patent number: 6710410
    Abstract: There is disclosed a hybrid circuit in which a circuit formed by TFTs is integrated with an RF filter. The TFTs are fabricated on a quartz substrate. A ceramic filter forming the RF filter is fabricated on another substrate. Terminals extend through the quartz substrate. The TFTs are connected with the ceramic filter via the terminals. Thus, an RF module is constructed.
    Type: Grant
    Filed: January 27, 2003
    Date of Patent: March 23, 2004
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Satoshi Teramoto
  • Patent number: 6653653
    Abstract: A single-electron transistor includes a projecting feature, such as a pyramid, that projects from a face of a substrate. A first electrode is provided on the substrate face that extends onto the projecting feature. A second electrode is provided on the substrate face that extends onto the projecting feature and that is spaced apart from the first electrode. At least one nanoparticle is provided on the projecting feature between the first and second electrodes. Accordingly, the geometric configuration of the projecting feature can define the spacing between the first and second electrodes.
    Type: Grant
    Filed: July 13, 2001
    Date of Patent: November 25, 2003
    Assignee: Quantum Logic Devices, Inc.
    Inventor: Louis C. Brousseau, III
  • Patent number: 6515340
    Abstract: A semiconductor device having a device separation region and an active region includes a gate oxide film, a source/drain region, and an electrode which is electrically coupled to the source/drain region. The active region is in contact with the gate oxide film at a first face, a portion of the source/drain regions being located above the first face. The electrode is in contact with the source/drain region at a second face, the second face constituting an angle with respect to the first face.
    Type: Grant
    Filed: July 31, 2001
    Date of Patent: February 4, 2003
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hiroshi Iwata, Seizo Kakimoto, Masayuki Nakano, Kouichiro Adachi
  • Patent number: 6515348
    Abstract: A semiconductor device comprises one or more field effect devices (FD) having source and drain regions (5 and 6) spaced apart by a body region (3a). A gate structure (7a, 7b), preferably in a trench (4), controls a conduction channel in a portion (3b) of the body region (3a) between the source and drain regions. The device has one or more mesa structures (100) having end and side walls (100a to 100d). The body region (3a) extends between and meets at least the side walls (100c and 100d) of the mesa structure. The gate structure (7a, 7b) extends along and between the side walls such that the conduction channel accommodating portion (3b) extends along and between the side walls (100c and 100d). The source and drain regions (5 and 6) meet respective end walls (100a and 100b) of the mesa structure and/or its side walls (100c and 100d). At the mesa walls, a source electrode (S) contacts the source region (5) and a drain electrode (D) contacts the drain region (6). (FIGS.
    Type: Grant
    Filed: May 8, 2001
    Date of Patent: February 4, 2003
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Raymond J. E. Hueting, Erwin A. Hijzen
  • Patent number: 6515334
    Abstract: There is disclosed a hybrid circuit in which a circuit formed by TFTs is integrated with an RF filter. The TFTs are fabricated on a quartz substrate. A ceramic filter forming the RF filter is fabricated on another substrate. Terminals extend through the quartz substrate. The TFTs are connected with the ceramic filter via the terminals. Thus, an RF module is constructed.
    Type: Grant
    Filed: July 26, 2001
    Date of Patent: February 4, 2003
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Satoshi Teramoto
  • Publication number: 20020163059
    Abstract: A high voltage electrical device (20), having a substrate layer (22), base layer (24) and top layer (26), provides high voltage properties in excess of 1000V. Slicing a wafer (28) from an ingot (30) created in by monocrystalline growth forms the substrate layer (22), and this high quality crystal is used as the high resistivity layer in the device (20). The base layer (24) is a highly doped, low resistivity, epitaxial layer deposited on the lower surface (32) of the substrate layer (22) at a fast rate greater than approximately 2 microns/minute. The top layer (26) is a diffusion layer diffused into an upper surface (34) of the substrate layer (22). To control stress in the wafer (28), the epitaxial base is doped with germanium.
    Type: Application
    Filed: February 17, 2000
    Publication date: November 7, 2002
    Inventor: Roman J. Hamerski
  • Patent number: 6437423
    Abstract: A method for fabricating an interconnect with high aspect ratio contact members is provided. The interconnect is adapted to make electrical connections with a semiconductor component, such as a die, a wafer, or a chip scale package for testing. The method includes providing a substrate with projections, and forming a first conductive layer on the projections and substrate. The first conductive layer is then patterned using a resist mask having a thickness greater than a height of the projections. The resist mask can be a thick film resist that includes an epoxy resin, an organic solvent and a photo initiator. A second conductive layer is then formed on the projections, and patterned using a second resist mask having a thickness less than the height of the projections. Each contact member includes a projection with a tip portion having an exposed portion of the first conductive layer, and with a portion of the second conductive layer providing an electrical path to the projection.
    Type: Grant
    Filed: October 29, 1999
    Date of Patent: August 20, 2002
    Assignee: Micron Technology, Inc.
    Inventor: Salman Akram
  • Patent number: 6407443
    Abstract: A method for forming a platen useful for forming nanoscale wires for device applications comprises: (a) providing a substrate having a major surface; (b) forming a plurality of alternating layers of two dissimilar materials on the substrate to form a stack having a major surface parallel to that of the substrate; (c) cleaving the stack normal to its major surface to expose the plurality of alternating layers; and (d) etching the exposed plurality of alternating layers to a chosen depth using an etchant that etches one material at a different rate than the other material to thereby provide the surface with extensive strips of indentations and form the platen useful for molding masters for nano-imprinting technology. The pattern of the platen is then imprinted into a substrate comprising a softer material to form a negative of the pattern, which is then used in further processing to form nanowires.
    Type: Grant
    Filed: June 20, 2001
    Date of Patent: June 18, 2002
    Assignee: Hewlett-Packard Company
    Inventors: Yong Chen, R. Stanley Williams