Mesa Structure (e.g., Including Undercut Or Stepped Mesa Configuration Or Having Constant Slope Taper) Patents (Class 257/623)
  • Patent number: 10818494
    Abstract: The present disclosure relates to a structure which includes a first metal layer patterned as a mandrel, a dielectric spacer on the first metal layer, and a second metal layer on the dielectric spacer.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: October 27, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hsueh-Chung Chen, Ravi P. Srivastava, Somnath Ghosh, Nicholas V. Licausi, Terry A. Spooner, Sean Reidy
  • Patent number: 10803795
    Abstract: A display panel, a method for preparing the same, and a display device are provided. The display panel, comprises a base substrate; a first insulating layer and a second insulating layer which are sequentially disposed on the base substrate, wherein a direction of a film stress of the first insulating layer is the same as a direction of a film stress of the second insulating layer.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: October 13, 2020
    Assignees: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Liman Peng, Yan Wu, Qi Liu
  • Patent number: 10777635
    Abstract: Embodiments of the present disclosure provide a display substrate, a method for manufacturing the same, and a display device, and relate to the field of display technology. The contact area between a first conductive pattern and a second conductive pattern may be increased. The display substrate includes a display area and a peripheral area surrounding the display area. The peripheral area includes a first conductive pattern including at least two first hollow areas as alignment marks, an insulation layer disposed on the first conductive pattern, the insulation layer including a first insulating pattern, the first insulating pattern covering the first hollow area, and the first insulating pattern being incompletely covering space between adjacent first hollow areas, a second conductive pattern disposed on the insulating layer, the second conductive pattern penetrating through the hollow area on the first insulating pattern and electrically connected to the first conductive pattern.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: September 15, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventors: Fan Yang, Kun Guo, Jie Pu
  • Patent number: 10635052
    Abstract: The invention relates to an external part including a first portion based on photostructurable glass, at least one second portion based on at least one second material. According to the invention, one surface of the first portion is made integral with a surface of the second portion so as to form a one-piece external part.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: April 28, 2020
    Assignee: THE SWATCH GROUP RESEARCH AND DEVELOPMENT LTD.
    Inventors: Philippe Dubois, Thierry Hessler, Christian Charbon
  • Patent number: 10629485
    Abstract: A surface mountable electronic component free of connecting wires comprises a semiconductor substrate, wherein a plurality of solderable connection areas are arranged at the underside of the component. The component comprises at least one recess is formed in the region of the edges bounding the underside; and in that the recess is covered with an insulating layer. A method for the manufacture of such a component comprises the formation of corresponding recesses.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: April 21, 2020
    Assignee: Vishay Semiconductor GmbH
    Inventor: Claus Mähner
  • Patent number: 10573752
    Abstract: The present disclosure relates to the technical field of semiconductors, and discloses a semiconductor device and a manufacturing method therefor. The manufacturing method includes: providing a substrate; forming a source and a drain that are at least partially located in the substrate; forming a diffused layer on a surface of at least one of the source or the drain, where a conductivity type of the diffused layer is the same conductivity type as the source and the drain, and a doping density of a dopant contained in the diffused layer is separately greater than doping densities of dopants contained in the source and the drain; and performing an annealing processing after the diffused layer is formed. The present disclosure can increase a doping density at a surface of a source and/or a drain, helping to reduce a contact resistance, thereby improving performance of a device.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: February 25, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Yong Li
  • Patent number: 10535800
    Abstract: A micro-light emitting diode (LED) includes an epitaxial structure having a mesa and a top portion on the mesa. The epitaxial structure further includes quantum wells within the mesa configured to emit light, claddings surrounding the quantum wells, and a light emitting surface on a side opposite the mesa and top portion. A reflective contact is on the top portion of the epitaxial structure. Light emitted from the quantum wells are transmitted through the mesa and the top portion in first directions, and reflected by the reflective contact back through the top portion and the mesa in second directions toward the light emitting surface. The top portion allows the quantum wells to be positioned at a parabola focal point of the mesa without limiting cladding thickness.
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: January 14, 2020
    Assignee: Facebook Technologies, LLC
    Inventor: Celine Claire Oyer
  • Patent number: 10497690
    Abstract: A semiconductor package includes a first package component include a first side, a second side opposite to the first side, and a plurality of recessed corners over the first side. The semiconductor package further includes a plurality of first stress buffer structures disposed at the recessed corners, and each of the first stress buffer structures has a curved surface. The semiconductor package further includes a second package component connected to the first package component and a plurality of connectors disposed between the first package component and the second package component. The connectors are electrically coupled the first package component and the second package component. The semiconductor package further includes an underfill material between the first package component and the second package component, and at least a portion of the curved surface of the first stress buffer structures is in contact with and embedded in the underfill material.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: December 3, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hsien-Ju Tsou, Chih-Wei Wu, Pu Wang, Ying-Ching Shih, Szu-Wei Lu, Jing-Cheng Lin
  • Patent number: 10490599
    Abstract: Embodiments described herein provide for light field displays and methods of forming light field displays where micro-LED arrays are each configured to provide at least a macro-pixel of effective native hardware resolution, where each macro-pixel provides single pixel of spatial resolution and plurality of pixels of angular resolution, and where each pixel of angular resolution includes a plurality of sub-pixels each provided by a directional collimating micro-LED device described herein.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: November 26, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Manivannan Thothadri, Christopher Dennis Bencher, Robert Jan Visser, John M. White
  • Patent number: 10403678
    Abstract: A ?LED device comprising: a substrate and an epitaxial layer grown on the substrate and comprising a semiconductor material, wherein at least a portion of the substrate and the epitaxial layer define a mesa; an active layer within the mesa and configured, on application of an electrical current, to generate light for emission through a light emitting surface of the substrate opposite the mesa, wherein the crystal lattice structure of the substrate and the epitaxial layer is arranged such that a c-plane of the crystal lattice structure is misaligned with respect to the light emitting surface.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: September 3, 2019
    Assignee: Facebook Technologies, LLC
    Inventor: Christopher Percival
  • Patent number: 10230008
    Abstract: Provided are a semiconductor light receiving device, an optical receiver module, and a manufacturing method thereof in which characteristics of the device are improved when the device has a structure in which a mesa structure including layers formed of a common material is buried by a buried layer. The semiconductor light receiving device includes the mesa structure including the layers formed of a commonmaterial, the layers including an absorbing layer, the mesa structure being buried by the buried layer formed so as to surround side surfaces of the mesa structure. The mesa structure has a cross section having a forwardly tapered portion and a reversely tapered portion.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: March 12, 2019
    Assignee: Oclaro Japan, Inc.
    Inventors: Masahiro Ebisu, Hiroshi Hamada, Yasushi Sakuma, Shigenori Hayakawa
  • Patent number: 10205019
    Abstract: One embodiment of a semiconductor device includes a fin at a first side of a semiconductor body, a body region of a second conductivity type in at least a part of the fin, a drain extension region of a first conductivity type, a source region and a drain region of the first conductivity type, a source contact in contact with the source region, and a gate structure adjoining opposing walls of the fin. The source contact extends along a vertical direction along the source region. The source contact includes a conductive material and is disposed in a trench in the semiconductor body, adjacent to the source region. The body region and the drain extension region are arranged one after another between the source region and the drain region.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: February 12, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Andreas Meiser, Christian Kampen
  • Patent number: 10201091
    Abstract: The present invention includes compositions and methods of creating electrical isolation and ground plane structures, around electronic devices (inductors, antenna, resistors, capacitors, transmission lines and transformers) in photo definable glass ceramic substrates in order to prevent parasitic electronic signals, RF signals, differential voltage build up and floating grounds from disrupting and degrading the performance of isolated electronic devices by the fabrication of electrical isolation and ground plane structures on a photo-definable glass substrate.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: February 5, 2019
    Assignee: 3D Glass Solutions, Inc.
    Inventors: Jeb H. Flemming, Jeff A. Bullington, Roger Cook, Kyle McWethy
  • Patent number: 10068808
    Abstract: A semiconductor device includes: a fin-shaped structure on a substrate, in which the fin-shaped structure includes a top portion and a bottom portion; a doped layer around the bottom portion of the fin-shaped structure; a first liner on the doped layer, and a second liner on the top portion and the bottom portion of the fin-shaped structure. Preferably, the first liner and the second liner are made of different material.
    Type: Grant
    Filed: October 17, 2016
    Date of Patent: September 4, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Li-Wei Feng, Shih-Hung Tsai, Chao-Hung Lin, Hon-Huei Liu, Shih-Fang Hong, Jyh-Shyang Jenq
  • Patent number: 10070533
    Abstract: The present invention includes compositions and methods of creating electrical isolation and ground plane structures, around electronic devices (inductors, antenna, resistors, capacitors, transmission lines and transformers) in photo definable glass ceramic substrates in order to prevent parasitic electronic signals, RF signals, differential voltage build up and floating grounds from disrupting and degrading the performance of isolated electronic devices by the fabrication of electrical isolation and ground plane structures on a photo-definable glass substrate.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: September 4, 2018
    Assignee: 3D GLASS SOLUTIONS, INC.
    Inventors: Jeb H. Flemming, Jeff Bullington, Roger Cook, Kyle McWethy
  • Patent number: 9991264
    Abstract: An integrated circuit device includes a double-humped protrusion protruding from a surface of an inter-device isolation region. To manufacture the integrated circuit device, a plurality of grooves are formed in the inter-device isolation region of a substrate, a recess is formed by partially removing a surface of the substrate between the plurality of grooves, at least one fin-type active area is formed in a device region by etching the substrate in the device region and the inter-device isolation region, and the double-humped protrusion is formed from the surface of the substrate in the inter-device isolation region.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: June 5, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ki-Il Kim, Jung-gun You, Gi-gwan Park
  • Patent number: 9977855
    Abstract: According to one embodiment, a design method of layout formed by a sidewall method is provided. The method includes: preparing a base pattern on which a plurality of first patterns extending in a first direction and arranged at a first space in a second direction intersecting the first direction and a plurality of second patterns extending in the first direction and arranged at a center between the first patterns, respectively, are provided; and drawing a connecting portion which extends in the second direction and connects two neighboring first patterns sandwiching one of the second patterns, and separating the one of the second patterns into two patterns not contacting the connecting portion.
    Type: Grant
    Filed: January 15, 2014
    Date of Patent: May 22, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Chikaaki Kodama, Koichi Nakayama, Toshiya Kotani, Shigeki Nojima, Fumiharu Nakajima, Hirotaka Ichikawa
  • Patent number: 9958835
    Abstract: The invention relates to an external part including a first portion based on photostructurable glass, at least one second portion based on at least one second material. According to the invention, one surface of the first portion is made integral with a surface of the second portion so as to form a one-piece external part.
    Type: Grant
    Filed: June 3, 2015
    Date of Patent: May 1, 2018
    Assignee: The Swatch Group Research and Development Ltd
    Inventors: Philippe Dubois, Thierry Hessler, Christian Charbon
  • Patent number: 9953126
    Abstract: According to one embodiment, a design method of layout formed by a sidewall method is provided. The method includes: preparing a base pattern on which a plurality of first patterns extending in a first direction and arranged at a first space in a second direction intersecting the first direction and a plurality of second patterns extending in the first direction and arranged at a center between the first patterns, respectively, are provided; and drawing a connecting portion which extends in the second direction and connects two neighboring first patterns sandwiching one of the second patterns, and separating the one of the second patterns into two patterns not contacting the connecting portion.
    Type: Grant
    Filed: October 3, 2014
    Date of Patent: April 24, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Chikaaki Kodama, Koichi Nakayama, Toshiya Kotani, Shigeki Nojima, Fumiharu Nakajima, Hirotaka Ichikawa
  • Patent number: 9892918
    Abstract: A method of forming a pattern of a semiconductor device includes forming a lower film on a substrate having a first surface and a second surface at different levels, forming an upper film of hydrophobic material on the lower film, forming a block copolymer film on the upper film, phase-separating the block copolymer film to form first patterns spaced apart from one another and a second pattern spanning the first patterns and interposed between a bottom surface of each of the first patterns and the upper film, removing the first patterns, and performing an etch process using the second pattern or a residual part of the second pattern as an etch mask.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: February 13, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun-Sung Kim, Kyeong-Mi Lee, Seung-Chul Kwon, Jeong-Ju Park, Shi-Yong Yi
  • Patent number: 9893231
    Abstract: A compound semiconductor device comprises a substrate, comprising a top surface, a bottom surface, a side surface connecting the top surface and the bottom surface; and a semiconductor stack formed on the top surface, wherein the side surface comprises a first deteriorated surface, a second deteriorated surface, a first crack surface between the first and second deteriorated surfaces, a second crack surface between the first deteriorated surface and the top surface, and a third crack surface between the second deteriorated surface and the bottom surface, wherein the first and second deteriorated surfaces are rougher than at least one of the first crack surface, the second crack surface and the third crack surface; and wherein the second crack surface is about perpendicular to the top surface, and the third crack surface is about perpendicular to the bottom surface.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: February 13, 2018
    Assignee: EPISTAR CORPORATION
    Inventors: Chia Chen Tsai, Chen Ou, Chi Ling Lee, Chi Shiang Hsu
  • Patent number: 9837409
    Abstract: A method for integrating a vertical transistor and a three-dimensional channel transistor includes forming narrow fins and wide fins in a substrate; forming a first source/drain (S/D) region at a base of the narrow fin and forming a gate dielectric layer and a gate conductor layer over the narrow fin and the wide fin. The gate conductor layer and the gate dielectric layer are patterned to form a vertical gate structure and a three-dimensional (3D) gate structure. Gate spacers are formed over sidewalls of the gate structures. A planarizing layer is deposited over the vertical gate structure and the 3D gate structure. A top portion of the narrow fin is exposed. S/D regions are formed on opposite sides of the 3D gate structure to form a 3D transistor, and a second S/D region is formed on the top portion of the narrow fin to form a vertical transistor.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: December 5, 2017
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang
  • Patent number: 9812586
    Abstract: In a cross section in a channel width direction, a semiconductor layer includes a first region of which one end portion is in contact with an insulating layer and which is positioned at one side portion of the semiconductor layer; a second region of which one end portion is in contact with the other end portion of the first region and which is positioned at an upper portion of the semiconductor layer; and a third region of which one end portion is in contact with the other end portion of the second region and the other end portion is in contact with the insulating layer and which is positioned at the other side portion of the semiconductor layer. In the second region, an interface with a gate insulating film is convex and has three regions respectively having curvature radii R1, R2, and R3 that are connected in this order from the one end portion side toward the other. R2 is larger than R1 and R3.
    Type: Grant
    Filed: October 20, 2014
    Date of Patent: November 7, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 9735310
    Abstract: In accordance with embodiments disclosed herein, there are provided methods and systems for implementing damage-and-resist-free laser patterning of dielectric films on textured silicon. For example, in one embodiment, such means include means for depositing a Silicon nitride (SiNx) or SiOx (silicon oxide) layer onto a crystalline silicon (c-Si) substrate by a Plasma Enhanced Chemical Vapor Deposition (PECVD) processing; depositing an amorphous silicon (a-Si) film on top of the SiNx or SiOx layer; patterning the a-Si film to define an etch mask for the SiNx or SiOx layer; removing the SiNx or SiOx layer via a Buffered Oxide Etch (BOE) chemical etch to expose the c-Si surface; removing the a-Si mask with a hydrogen plasma etch in a PECVD tool to prevent current loss from the mask; and plating the exposed c-Si surface with metal contacts. Other related embodiments are disclosed.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: August 15, 2017
    Assignee: ARIZONA BOARD OF REGENTS ON BEHALF OF ARIZONA STATE UNIVERSITY
    Inventor: Mark Scott Bailly
  • Patent number: 9679819
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; forming a first bump on the first region and a second bump on the second region; forming a first doped layer on the first fin-shaped structure and the first bump; and forming a second doped layer on the second fin-shaped structure and the second bump.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: June 13, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Yu-Cheng Tung
  • Patent number: 9680032
    Abstract: In a cross section in a channel width direction, a semiconductor layer includes a first region of which one end portion is in contact with an insulating layer and which is positioned at one side portion of the semiconductor layer; a second region of which one end portion is in contact with the other end portion of the first region and which is positioned at an upper portion of the semiconductor layer; and a third region of which one end portion is in contact with the other end portion of the second region and the other end portion is in contact with the insulating layer and which is positioned at the other side portion of the semiconductor layer. In the second region, an interface with a gate insulating film is convex and has three regions respectively having curvature radii R1, R2, and R3 that are connected in this order from the one end portion side toward the other. R2 is larger than R1 and R3.
    Type: Grant
    Filed: October 20, 2014
    Date of Patent: June 13, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 9666555
    Abstract: A method of manufacturing a semiconductor structure includes providing a first wafer including a surface, removing some portions of the first wafer over the surface to form a plurality of recesses extended over at least a portion of the surface of the first wafer, providing a second wafer, and disposing the second wafer over the surface of the first wafer.
    Type: Grant
    Filed: July 6, 2016
    Date of Patent: May 30, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chen-Chun Chen, Chiu-Jung Chen, Fu-Tsun Tsai, Shiu-Ko Jangjian, Chi-Cherng Jeng, Hsin-Chi Chen
  • Patent number: 9653295
    Abstract: In a method of manufacturing an SRAM, first dummy patterns are formed over a substrate, on which a first to a third mask layer are formed. Intermediate dummy patterns are formed on sidewalls of the first dummy patterns. The first dummy patterns are removed, thereby leaving the intermediate dummy patterns. The third mask layer is patterned by using the intermediate dummy patterns, by which the second mask layer is patterned, thereby forming second dummy patterns. Sidewall spacer layers are formed on sidewalls of the second dummy patterns. The second dummy patterns are removed, thereby leaving the sidewall spacer layers as hard mask patterns over the substrate, by which the first mask layer is patterned. The substrate is patterned by using the patterned first mask layer. Each of the plurality of SRAM cells is defined by a cell boundary, within which only two first dummy patterns are included.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: May 16, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Han Huang, Chih-Hung Hsieh
  • Patent number: 9633982
    Abstract: Present disclosure provides a method for manufacturing a semiconductor device array, including (1) providing a temporary substrate; (2) forming a plurality of discrete semiconductor structures over the temporary substrate; and (3) removing a surface portion of the temporary substrate to expose a peripheral bottom surface of the discrete semiconductor structure. Present disclosure also provides a method for transferring discrete semiconductor device, including (1) detaching discrete semiconductor structures of a first type from a first temporary substrate supporting the discrete semiconductor structures of the first type by a transfer stamp; (2) carrying the discrete semiconductor structures over a target substrate by the transfer stamp; and (3) dismounting the discrete semiconductor structures of the first type from the transfer stamp to predetermined sites on the target substrate.
    Type: Grant
    Filed: February 17, 2015
    Date of Patent: April 25, 2017
    Assignees: GLOBALWAFERS CO., LTD.
    Inventor: Chun-Yen Chang
  • Patent number: 9620525
    Abstract: To reduce power consumption and suppress display degradation of a liquid crystal display device. To suppress display degradation due to an external factor such as temperature. A transistor whose channel formation region is formed using an oxide semiconductor layer is used for a transistor provided in each pixel. Note that with the use of a high-purity oxide semiconductor layer, off-state current of the transistor at a room temperature can be 10 aA/?m or less and off-state current at 85° C. can be 100 aA/?m or less. Consequently, power consumption of a liquid crystal display device can be reduced and display degradation can be suppressed. Further, as described above, off-state current of the transistor at a temperature as high as 85° C. can be 100 aA/?m or less. Thus, display degradation of a liquid crystal display device due to an external factor such as temperature can be suppressed.
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: April 11, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 9613820
    Abstract: A method of forming patterns includes the steps of providing a substrate having a target layer thereon; forming a plurality of first resist patterns on the target layer; depositing a directed self-assembly (DSA) material layer in a blanket manner on the first resist patterns, wherein the DSA material layer fills up a gap between the first resist patterns; subjecting the DSA material layer to a self-assembling process so as to form repeatedly arranged block copolymer patterns in the DSA material layer; and removing undesired portions from the DSA material layer to form second resist patterns on the target layer.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: April 4, 2017
    Assignee: INOTERA MEMORIES, INC.
    Inventor: Kuo-Yao Chou
  • Patent number: 9607899
    Abstract: A method for integrating a vertical transistor and a three-dimensional channel transistor includes forming narrow fins and wide fins in a substrate; forming a first source/drain (S/D) region at a base of the narrow fin and forming a gate dielectric layer and a gate conductor layer over the narrow fin and the wide fin. The gate conductor layer and the gate dielectric layer are patterned to form a vertical gate structure and a three-dimensional (3D) gate structure. Gate spacers are formed over sidewalls of the gate structures. A planarizing layer is deposited over the vertical gate structure and the 3D gate structure. A top portion of the narrow fin is exposed. S/D regions are formed on opposite sides of the 3D gate structure to form a 3D transistor, and a second S/D region is formed on the top portion of the narrow fin to form a vertical transistor.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: March 28, 2017
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang
  • Patent number: 9601578
    Abstract: A non-planar lateral drift MOS device eliminates the need for a field plate extension, which reduces gate width. In one example, two sources and two comparatively small gates in a raised structure allow for two channels and a dual current with mirrored flows, each traveling into and downward through a center region of a connecting well that connects the substrate with the drain areas and shallow wells containing the source areas, the current then traveling in opposite directions within the substrate region of the connecting well toward the two drains. The source and drain areas may be separate raised structures or isolated areas of a continuous raised structure.
    Type: Grant
    Filed: October 10, 2014
    Date of Patent: March 21, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jerome Ciavatti, Yanxiang Liu, Vara Govindeswara Reddy Vakada
  • Patent number: 9583489
    Abstract: A method of forming a semiconductor device comprises forming a first fin on a substrate, depositing an insulator layer on the substrate adjacent to the first fin, removing a first portion of the insulator layer to expose a first portion of a sidewall of the first fin, depositing a layer of spacer material over the first portion of the sidewall of the first fin, removing a second portion of the insulator layer to expose a second portion of the sidewall of the first fin, depositing a first glass layer including a first doping agent over the exposed second portion of the sidewall of the first fin, and performing a first annealing process to drive the first doping agent into the first fin.
    Type: Grant
    Filed: January 8, 2016
    Date of Patent: February 28, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent A. Anderson, Hemanth Jagannathan, Sanjay C. Mehta, Balasubramanian Pranatharthiharan
  • Patent number: 9502252
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having at least one fin-shaped structure thereon, in which the fin-shaped structure comprises a top portion and a bottom portion; and forming a doped layer and a first liner around the bottom portion of the fin-shaped structure.
    Type: Grant
    Filed: March 4, 2015
    Date of Patent: November 22, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Li-Wei Feng, Shih-Hung Tsai, Chao-Hung Lin, Hon-Huei Liu, Shih-Fang Hong, Jyh-Shyang Jenq
  • Patent number: 9402316
    Abstract: Various methods for forming a low profile assembly are described. The low profile assembly may include an integrated circuit. The integrated circuit as well as components associated with the integrated circuit may be positioned below a surface plane of a printed circuit board in which the integrated circuit is located. The integrated circuit may include bond wires configured to electrically connect the integrated circuits to other components. The low profile assembly may include forming various layers over a substrate and later removing some of the layers.
    Type: Grant
    Filed: April 24, 2015
    Date of Patent: July 26, 2016
    Assignee: Apple Inc.
    Inventors: Shawn X. Arnold, Terry L. Gilton, Matthew E. Last
  • Patent number: 9356023
    Abstract: Techniques are disclosed for forming a planar-like transistor device on a fin-based field-effect transistor (finFET) architecture during a finFET fabrication process flow. In some embodiments, the planar-like transistor can include, for example, a semiconductor layer which is grown to locally merge/bridge a plurality of adjacent fins of the finFET architecture and subsequently planarized to provide a high-quality planar surface on which the planar-like transistor can be formed. In some instances, the semiconductor merging layer can be a bridged-epi growth, for example, comprising epitaxial silicon. In some embodiments, such a planar-like device may assist, for example, with analog, high-voltage, wide-Z transistor fabrication.
    Type: Grant
    Filed: March 30, 2013
    Date of Patent: May 31, 2016
    Assignee: INTEL CORPORATION
    Inventors: Walid M. Hafez, Peter J. Vandervoorn, Chia-Hong Jan
  • Patent number: 9324866
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate; an isolation feature formed in the semiconductor substrate; a first active region and a second active region formed in the semiconductor substrate, wherein the first and second active regions extend in a first direction and are separated from each other by the isolation feature; and a dummy gate disposed on the isolation feature, wherein the dummy gate extends in the first direction to the first active region from one side and to the second active region from another side.
    Type: Grant
    Filed: January 23, 2012
    Date of Patent: April 26, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shao-Ming Yu, Chang-Yun Chang, Chih-Hao Chang, Hsin-Chih Chen, Kai-Tai Chang, Ming-Feng Shieh, Kuei-Liang Lu, Yi-Tang Lin
  • Patent number: 9306001
    Abstract: Embodiments are directed to a method of forming a leakage current stopper of a fin-type field effect transistor (FinFET). The method includes forming at least one fin having an active region, a non-active region and a channel region in the active region. The method further includes exposing a surface of the non-active region, wherein the exposed surface leads to a portion of the non-active region that is substantially underneath the channel region. The method further includes implanting dopants through the exposed surface of the non-active region to form the leakage current stopper region.
    Type: Grant
    Filed: April 14, 2015
    Date of Patent: April 5, 2016
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC., STMICROELECTRONICS, INC.
    Inventors: Xiuyu Cai, Qing Liu, Ruilong Xie, Chun-Chen Yeh
  • Patent number: 9269711
    Abstract: A semiconductor device includes a first ridge and a second ridge extending from a first main surface of a semiconductor substrate. The first and second ridges run in a first direction. The semiconductor device further includes a body region disposed in a portion of the semiconductor substrate between the first ridge and the second ridge, and a gate electrode adjacent to the body region. The first and second ridges are connected with the body region. A plurality of further ridges are formed in the body region, the further ridges extending in a second direction intersecting the first direction. The gate electrode runs in the first direction, and the gate electrode is disposed at at least two sides of the further ridges.
    Type: Grant
    Filed: July 1, 2013
    Date of Patent: February 23, 2016
    Assignee: Infineon Technologies Austria AG
    Inventor: Stefan Tegen
  • Patent number: 9208276
    Abstract: A method of generating a layout pattern including a FinFET structure layout includes the following processes. First, a layout pattern, which includes a sub-pattern having pitches in simple integer ratios, is provided to a computer system. The sub-pattern is then classified into a first sub-pattern and a second sub-pattern. Afterwards, first stripe patterns and at least one second stripe pattern are generated. The longitudinal edges of the first stripe patterns are aligned with the longitudinal edges of the first sub-pattern and the first stripe patterns have equal spacings and widths. The positions of the second stripe patterns correspond to the positions of the blank pattern, and spacings or widths of the second stripe patterns are different from the spacings or widths of the first stripe patterns. Finally, the first stripe patterns and the second stripe pattern are outputted to a photomask.
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: December 8, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Chao Tsao, Shih-Fang Hong, Chia-Wei Huang, Ming-Jui Chen, Shih-Fang Tzou, Ming-Te Wei
  • Patent number: 9196594
    Abstract: An embodiment of the invention provides a chip package which includes: a carrier substrate; a semiconductor substrate having an upper surface and a lower surface, disposed overlying the carrier substrate; a device region or sensing region located on the upper surface of the semiconductor substrate; a conducting pad located on the upper surface of the semiconductor substrate; a conducting layer electrically connected to the conducting pad and extending from the upper surface of the semiconductor substrate to a sidewall of the semiconductor substrate; and an insulating layer located between the conducting layer and the semiconductor substrate.
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: November 24, 2015
    Assignee: XINTEC INC.
    Inventors: Chao-Yen Lin, Yi-Hang Lin
  • Patent number: 9190269
    Abstract: Illustrative embodiments of power amplifiers and associated methods are disclosed. In at least one embodiment, a method may include fabricating a power amplifier in a first silicon layer of a silicon-on-insulator (SOI) substrate, wherein the SOI substrate comprises the first silicon layer, a second silicon layer, and a buried oxide layer disposed between the first and second silicon layers; removing at least some of the second silicon layer from the SOI substrate, after fabricating the power amplifier; and securing the SOI substrate, after removing at least some of the second silicon layer, to an electrically non-conductive and thermally conductive substrate.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: November 17, 2015
    Assignee: PURDUE RESEARCH FOUNDATION
    Inventors: Saeed Mohammadi, Sultan R. Helmi, Jing-Hwa Chen, Hossein Pajouhi
  • Patent number: 9165652
    Abstract: Split-gate non-volatile memory (NVM) cells having select-gate sidewall metal silicide regions are disclosed along with related manufacturing methods. Spacer etch processing steps are used to expose sidewall portions of select gates. Metal silicide regions are then formed within these sidewall portions of the select gates. Further, metal silicide regions can also be formed in top portions of the select gates. Further, the select gates can also be formed with one or more notches. By expanding the size of the metal silicide region to include the sidewall portion of the select gate, the select gate wordline (e.g., polysilicon) resistance is reduced for split-gate NVM arrays, the electrical contact to the select gate is improved, and performance of the select-gate NVN cell is improved.
    Type: Grant
    Filed: August 20, 2012
    Date of Patent: October 20, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Sung-Taeg Kang, Cheong M. Hong
  • Patent number: 9041165
    Abstract: A method for the formation of an at least partially relaxed strained material layer, comprises providing a seed substrate; patterning the seed substrate; growing a strained material layer on the patterned seed substrate; transferring the strained material layer from the patterned seed substrate to an intermediate substrate; and at least partially relaxing the strained material layer by a heat treatment.
    Type: Grant
    Filed: January 11, 2010
    Date of Patent: May 26, 2015
    Assignee: SOITEC
    Inventors: Fabrice Letertre, Bruce Faure, Pascal Guenard
  • Publication number: 20150137332
    Abstract: A carrier for carrying a semiconductor layer having a growth surface and at least one nano-patterned structure on the growth surface is provided. The at least one nano-patterned structure on the growth surface of the carrier has a plurality of mesas, a recess is formed between two adjacent mesas, in which a depth of the recess ranges from 10 nm to 500 nm, and a dimension of the mesa ranges from 10 nm to 800 nm.
    Type: Application
    Filed: December 29, 2014
    Publication date: May 21, 2015
    Inventors: Yi-Keng Fu, Rong Xuan, Hsun-Chih Liu
  • Publication number: 20150108616
    Abstract: A dielectric material layer is formed on a semiconductor-on-insulator (SOI) substrate including a top semiconductor layer containing a first semiconductor material. An opening is formed within the dielectric material layer, and a trench is formed in the top semiconductor layer within the area of the opening by an etch. A second semiconductor material is deposited to a height above the top surface of the top semiconductor layer employing a selective epitaxy process. Another dielectric material layer can be deposited, and another trench can be formed in the top semiconductor layer. Another semiconductor material can be deposited to a different height employing another selective epitaxy process. The various semiconductor material portions can be patterned to form semiconductor fins having different heights and/or different compositions.
    Type: Application
    Filed: October 22, 2013
    Publication date: April 23, 2015
    Applicant: International Business Machines Corporation
    Inventors: Brian J. Greene, Augustin J. Hong, Byeong Y. Kim, Dan M. Mocuta
  • Publication number: 20150108615
    Abstract: An assembly component and a technique for assembling a chip package using the assembly component are described. This chip package includes a set of semiconductor dies that are arranged in a stack in a vertical direction, which are offset from each other in a horizontal direction to define a stepped terrace at one side of the vertical stack. Moreover, the chip package may be assembled using the assembly component. In particular, the assembly component may include a pair of stepped terraces that approximately mirror the stepped terrace of the chip package and which provide vertical position references for an assembly tool that positions the set of semiconductor dies in the vertical stack during assembly of the chip package.
    Type: Application
    Filed: October 21, 2013
    Publication date: April 23, 2015
    Applicant: Oracle International Corporation
    Inventors: Michael H. S. Dayringer, R. David Hopkins, Alex Chow
  • Patent number: 9006010
    Abstract: Radiation detectors and methods of fabricating radiation detectors are provided. One method includes mechanically polishing at least a first surface of a semiconductor wafer using a polishing sequence including a plurality of polishing steps, wherein a last polishing step of the polishing sequence includes polishing with a slurry having a grain size smaller than about 0.1 ?m to create a polished first surface. The method also includes applying (i) an encapsulation layer on a top of the polished first surface to seal the polished first surface and (ii) a photoresist layer on top of the encapsulation layer on the polished first surface. The method further includes creating undercuts of the encapsulation layer under the photoresist layer. The method additionally includes partially etching the polished first surface of the semiconductor via the openings in the photoresist layer and in the encapsulation layer to partially etch the semiconductor creating etched regions.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: April 14, 2015
    Assignee: General Electric Company
    Inventors: Arie Shahar, Eliezer Traub, Diego Sclar, Peter Rusian
  • Publication number: 20150097275
    Abstract: A semiconductor device includes a substrate, a substrate-side electrode layer, an intermediate electrode layer, and a front-side electrode layer. The substrate includes a semiconductor layer and a projection portion, the projection portion being formed on a surface of the semiconductor layer. The substrate-side electrode layer is provided on the projection portion. The intermediate electrode layer extends from on a part of the substrate-side electrode layer, which part of the substrate-side electrode layer is located on the projection portion, to just above a region of the substrate in which region the projection portion is not provided. The front-side electrode layer is provided on a surface of the intermediate electrode layer. A Young's modulus E1 of the substrate-side electrode layer, a Young's modulus E2 of the intermediate electrode layer, and a Young's modulus E3 of the front-side electrode layer satisfy a relationship of E3>E1>E2.
    Type: Application
    Filed: September 29, 2014
    Publication date: April 9, 2015
    Inventors: Atsushi IMAI, Yoshiaki KOMINAMI, Takashi USHIJIMA