Semiconductor Body Including Mesa Is Intimately Bonded To Thick Electrical And/or Thermal Conductor Member Of Larger Lateral Extent Than Semiconductor Body (e.g., "plated Heat Sink" Microwave Diode) Patents (Class 257/625)
  • Patent number: 10741473
    Abstract: An integrated circuit has a substrate including semiconductor material and a resistor in an interconnect region, above a first level of interconnect lines. The integrated circuit further includes an electrically isolated thermal conduit having one or more interconnect lines in every interconnect level lower than the resistor. The interconnect lines of the thermal conduit are directly connected through one or more vertical interconnects, including contacts, and possibly vias, to a gate structure located on a dielectric material over the semiconductor material of the substrate. The thermal conduit is electrically isolated from the resistor, from all active components in the integrated circuit, and from the semiconductor material of the substrate.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: August 11, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Dhishan Kande, Archana Venugopal
  • Patent number: 10692804
    Abstract: A semiconductor device package includes an interposer and a semiconductor device. The interposer has a sidewall defining a space. The semiconductor device is disposed within the space and in contact with the sidewall. An interposer includes a first surface, a second surface and a third surface. The first surface has a first crystal orientation. The second surface is opposite the first surface and has the first crystal orientation. The third surface connects the first surface to the second surface, and defines a space. An angle defined by the third surface and the first surface ranges from about 90° to about 120°.
    Type: Grant
    Filed: August 15, 2018
    Date of Patent: June 23, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen-Long Lu
  • Patent number: 10686084
    Abstract: A photodiode device and method of manufacturing the same are disclosed. A stack of functional layers of the photodiode device, formed of crystalline semiconductor material, may be formed on a diamond substrate. The stack of functional layers may be in contact with or close proximity to the diamond substrate to thereby provide an efficient thermal conductive path between the functional layers and an external source, thereby mitigating problems that may result from overheating the photodiode device.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: June 16, 2020
    Assignee: Phase Sensitive Innovations, Inc.
    Inventor: Peng Yao
  • Patent number: 10672708
    Abstract: In some embodiments, the present disclosure relates to an integrated circuit (IC) having parallel conductive paths between a BEOL interconnect layer and a middle-end-of-the-line (MEOL) structure, which are configured to reduce a parasitic resistance and/or capacitance of the IC. The IC comprises source/drain regions arranged within a substrate and separated by a channel region. A gate structure is arranged over the channel region and a MEOL structure is arranged over one of the source/drain regions. A conductive structure is arranged over and in electrical contact with the MEOL structure. A first conductive contact is arranged between the MEOL structure and an overlying BEOL interconnect wire (e.g., a power rail). A second conductive contact is configured to electrically couple the BEOL interconnect wire and the MEOL structure along a conductive path extending through the conductive structure, thereby forming parallel conductive paths between the BEOL interconnect layer and the MEOL structure.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: June 2, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ni-Wan Fan, Ting-Wei Chiang, Cheng-I Huang, Jung-Chan Yang, Hsiang-Jen Tseng, Lipen Yuan, Chi-Yu Lu
  • Patent number: 10475725
    Abstract: An integrated circuit has a substrate including semiconductor material and a resistor in an interconnect region, above a first level of interconnect lines. The integrated circuit further includes an electrically isolated thermal conduit having one or more interconnect lines in every interconnect level lower than the resistor. The interconnect lines of the thermal conduit are directly connected through one or more vertical interconnects, including contacts, and possibly vias, to a gate structure located on a dielectric material over the semiconductor material of the substrate. The thermal conduit is electrically isolated from the resistor, from all active components in the integrated circuit, and from the semiconductor material of the substrate.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: November 12, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Dhishan Kande, Archana Venugopal
  • Patent number: 10426028
    Abstract: A power electronic device includes an Insulated Metal Substrate Printed Circuit Board (IMS PCB) and a power semiconductor device package. The power semiconductor device package includes a lead frame configured to electrically and mechanically couple the power semiconductor device package to the IMS PCB. The lead frame has a rigid configuration and is made of a lead frame material having a first thermal expansion coefficient. The IMS PCB includes an insulated metal substrate made of a substrate material having a second thermal expansion coefficient within a range of 60% to 140% of the first thermal expansion coefficient.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: September 24, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Elvir Kahrimanovic, Wai Keung Alan Lun
  • Patent number: 10211144
    Abstract: This semiconductor device includes a semiconductor element mounted on a metal layer, first to third connection terminals that are provided on the semiconductor element, a first bus bar bonded to the first connection terminal, and a second bus bar bonded to the second connection terminal. The semiconductor element is bonded to the metal layer, and the first to third connection terminals are disposed on a top surface of the semiconductor element. One end of the first bus bar is bonded to the first connection terminal, another end of the first bus bar is an output unit, one end of the second bus bar is bonded to the second connection terminal, and another end of the second bus bar is bonded to the metal layer. A first surface of the semiconductor element and the second bus bar are at an identical potential.
    Type: Grant
    Filed: July 4, 2016
    Date of Patent: February 19, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Shinichi Kohda, Junichi Kimura, Ryosuke Usui, Tomohide Ogura, Atsushi Watanabe
  • Patent number: 10002947
    Abstract: In a method for forming a device, a (110) silicon substrate is etched to form first trenches in the (110) silicon substrate, wherein remaining portions of the (110) silicon substrate between the first trenches form silicon strips. The sidewalls of the silicon strips have (111) surface orientations. The first trenches are filled with a dielectric material to from Shallow Trench Isolation (STI) regions. The silicon strips are removed to form second trenches between the STI regions. An epitaxy is performed to grow semiconductor strips in the second trenches. Top portions of the STI regions are recessed, and the top portions of the semiconductor strips between removed top portions of the STI regions form semiconductor fins.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: June 19, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Ming-Chyi Liu
  • Patent number: 9006082
    Abstract: A filmic circuit includes a circuit portion and a carrier layer. The circuit portion includes a logic circuit that includes, for example, plural logic gates configurable to receive an input and provide a corresponding logical output. The carrier layer is configured as a film. The circuit portion is affixed directly to the carrier layer or to an upper coat disposed adjacent to the carrier layer, and the carrier layer is configured to be releasable from the circuit portion after the filmic circuit assembly is affixed to a target. The circuit portion is configured to receive an adhesive layer configured to affix the filmic circuit assembly to the target.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: April 14, 2015
    Assignee: Illinois Tool Works Inc.
    Inventors: John H. Schneider, William A. Herring
  • Patent number: 8890217
    Abstract: An electronic device including an insulating substrate, a chip and a patterned conductive layer is provided. The insulating substrate has an upper surface and a lower surface opposite to each other. The chip is disposed above the upper surface of the insulating substrate. The patterned conductive layer is disposed between the upper surface of the insulating substrate and the chip. The chip is electrically connected to an external circuit via the patterned conductive layer. Heat generated by the chip is transferred to external surroundings via the patterned conductive layer and the insulating substrate.
    Type: Grant
    Filed: November 6, 2012
    Date of Patent: November 18, 2014
    Assignee: Genesis Photonics Inc.
    Inventors: Po-Jen Su, Yun-Li Li, Cheng-Yen Chen, Gwo-Jiun Sheu
  • Patent number: 8884411
    Abstract: A semiconductor device includes a first semiconductor element; a first thick plate portion that is electrically connected to an electrode on a lower surface side of the first semiconductor element, and is formed by a conductor; a second semiconductor element that is arranged such that a main surface of the second semiconductor element faces a main surface of the first semiconductor element; a second thick plate portion that is electrically connected to an electrode on a lower surface side of the second semiconductor element, and is formed by a conductor; a third thick plate portion that is electrically connected to an electrode on an upper surface side of the first semiconductor element, and is formed by a conductor; a fourth thick plate portion that is electrically connected to an electrode on an upper surface side of the second semiconductor element, and is formed by a conductor; a first thin plate portion that is provided on the second thick plate portion, is formed by a conductor, and is thinner than the
    Type: Grant
    Filed: April 18, 2012
    Date of Patent: November 11, 2014
    Assignees: Toyota Jidosha Kabushiki Kaisha, Denso Corporation
    Inventors: Takuya Kadoguchi, Shingo Iwasaki, Takanori Kawashima, Tomomi Okumura, Masayoshi Nishihata
  • Patent number: 8823145
    Abstract: Provided are a multilayer board and a light-emitting module having the same. The light-emitting module comprises a light-emitting diode chip and a multilayer board. The multilayer board is electrically connected to the light-emitting diode chip and comprises a nonconductive heat sink via and a thin copper layer.
    Type: Grant
    Filed: December 10, 2008
    Date of Patent: September 2, 2014
    Assignee: LG Innotek Co., Ltd.
    Inventor: Kyung Ho Shin
  • Patent number: 8772911
    Abstract: A semiconductor diode has a first semiconductor layer (102) of a first conductivity type and a second semiconductor layer of a second conductivity type having a doping. The second semiconductor layer has a vertical electrical via region (106) which is connected to the first semiconductor layer and in which the doping is modified in such a way that the electrical via region (106) has the first conductivity type. A method for producing such a semiconductor diode is described.
    Type: Grant
    Filed: February 10, 2011
    Date of Patent: July 8, 2014
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Tony Albrecht, Markus Maute, Martin Reufer, Heribert Zull
  • Patent number: 8754437
    Abstract: The invention relates to an LED module (1) comprising at least one light-emitting diode (LED) (3) and at least one heat sink (2) for active cooling, having at least one coolant channel (6) through which a cooling fluid flows. The dimensions of the at least one coolant channel (6) are selected so that a predominantly laminar flow of the fluid is set up in the at least one coolant channel (5) during operation of the LED module (1).
    Type: Grant
    Filed: June 12, 2009
    Date of Patent: June 17, 2014
    Assignee: OSRAM Gesellschaft mit beschraenkter Haftung
    Inventors: Alexander Faller, Moritz Kaiser, Martin Reuter
  • Patent number: 8748885
    Abstract: A semiconductor device including a first wafer assembly having a first substrate and a first oxide layer over the first substrate. The semiconductor device further includes a second wafer assembly having a second substrate and a second oxide layer over the second substrate. The first oxide layer and the second oxide layer are bonded together by van der Waals bonds or covalent bonds. A method of bonding a first wafer assembly and a second wafer assembly including forming a first oxide layer over a first substrate. The method further includes forming a second oxide layer over a second wafer assembly. The method further includes forming van der Waals bonds or covalent bonds between the first oxide layer and the second oxide layer.
    Type: Grant
    Filed: February 10, 2012
    Date of Patent: June 10, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tung-Ti Yeh, Chung-Yi Huang, Ya Wen Wu, Hui Mei Jao, Ting-Chun Wang, Shiu-Ko JangJian, Chia-Hung Chung
  • Patent number: 8749051
    Abstract: A semiconductor device which provides a small and simple design with efficient cooling. A first electrically conducting cooling element is in contact with first electrodes of semiconductor elements for forwarding a heat load from the semiconductor elements and for electrically connecting the first electrodes of the semiconductor elements to an external apparatus. A second electrically conducting cooling element is in contact with second electrodes of the semiconductor elements for forwarding a heat load from the semiconductor elements and for electrically connecting the second electrodes of the semiconductor elements to an external apparatus. The semiconductor device includes an interface which is electrically connected to gates of the semiconductor elements for external control of respective states of the semiconductor elements.
    Type: Grant
    Filed: February 7, 2012
    Date of Patent: June 10, 2014
    Assignee: ABB Research Ltd
    Inventors: Slavo Kicin, Nicola Schulz, Munaf Rahimo, Raffael Schnell
  • Patent number: 8742563
    Abstract: A component and a method for producing a component are disclosed. The component comprises an integrated circuit, a housing body, a wiring device overlapping the integrated circuit and the housing body, and one or more external contact devices in communication with the wiring device.
    Type: Grant
    Filed: November 29, 2010
    Date of Patent: June 3, 2014
    Assignee: Intel Mobile Communications GmbH
    Inventors: Thorsten Meyer, Harry Hedler, Markus Brunnbauer
  • Patent number: 8618585
    Abstract: A semiconductor apparatus according to embodiments of the invention can include a first semiconductor device made of silicon, the first semiconductor devices being arranged collectively, whereby to form a first device group, and a second semiconductor device made of silicon carbide, the second semiconductor devices being arranged collectively, whereby to form a second device group. The apparatus can also include a wiring conductor connecting the first semiconductor device and the second semiconductor device, a cooling fin base comprising a projection formed thereon, whereby to dissipate heat generated from the first and second semiconductor devices, and the projections arranged under the second device group being spaced apart from each other more widely than the projections arranged under the first device group.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: December 31, 2013
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Kenichiro Sato
  • Patent number: 8581385
    Abstract: A semiconductor chip includes a semiconductor chip body having a top surface, a bottom surface, and side surfaces. The bottom surface may have a groove pattern defined by removing a partial thickness of the semiconductor chip body to extend from one or more edges of the semiconductor chip body toward a center portion of the semiconductor chip body. Through electrodes may be formed to extend from the top surface of the semiconductor chip body and pass through the groove pattern defined on the bottom surface. A heat dissipation pattern may fill in the groove pattern defined on the bottom surface and may be connected with the through electrodes.
    Type: Grant
    Filed: December 27, 2010
    Date of Patent: November 12, 2013
    Assignee: SK Hynix Inc.
    Inventor: Jin Hui Lee
  • Patent number: 8547465
    Abstract: An imaging device module includes an imaging device including a light incident plane on which light is incident, and a reverse face disposed on an opposite side of the light incident plane; and a thermal conductive sheet provided on the reverse face for dissipating heat generated from the imaging device. The thermal conductive sheet contains a plate-like boron nitride particle, and the thermal conductive sheet has a thermal conductivity in a direction perpendicular to the thickness direction of 4 W/m·K or more.
    Type: Grant
    Filed: January 28, 2011
    Date of Patent: October 1, 2013
    Assignee: Nitto Denko Corporation
    Inventors: Seiji Izutani, Hisae Uchiyama, Takahiro Fukuoka, Kazutaka Hara
  • Patent number: 8476656
    Abstract: A light-emitting diode includes a circuit board, a pair of electrodes provided on the circuit board, at least one light-emitting diode element electrically connected to the pair of electrodes, a central electrode for heat-dissipation, provided between the pair of electrodes on the circuit board, and a heat-dissipation plate disposed on the central electrode for heat-dissipation and including a reflection surface. The central electrode for heat-dissipation includes an upper central electrode disposed on the upper surface of the circuit board and a lower central electrode disposed on the lower surface of the circuit board and the upper central electrode thermally connected to the lower central electrode.
    Type: Grant
    Filed: September 21, 2009
    Date of Patent: July 2, 2013
    Assignee: Citizen Electronics Co., Ltd.
    Inventor: Norikazu Kadotani
  • Patent number: 8466486
    Abstract: The present disclosure provides systems and methods for forming a semiconductor device. The semiconductor device includes a substrate having a first side and a second side opposite the first side. A first heat producing element is formed on the first side of the substrate. A second heat producing element is formed on the first side of substrate co-planar with, but not touching the first heat producing element. A heat spreader is coupled to the second side of the substrate using a thermal interface material. The heat spreader includes a first and second vapor chambers. The first vapor chamber is embedded in the heat spreader substantially opposite the first heat producing element. The second vapor chamber is embedded in the heat spreader substantially opposite the second heat producing element. As an example, the first heat producing element may be a light-emitting diode (LED) and the second heat producing element may be a driver circuit for the LED.
    Type: Grant
    Filed: August 27, 2010
    Date of Patent: June 18, 2013
    Assignee: TSMC Solid State Lighting Ltd.
    Inventor: Tsorng-Dih Yuan
  • Patent number: 8426945
    Abstract: To provide a semiconductor device in which a channel formation region can be thinned without adversely affecting a source region and a drain region through a simple process and a method for manufacturing the semiconductor device. In the method for manufacturing a semiconductor device, a semiconductor film, having a thickness smaller than a height of a projection of a substrate, is formed over a surface of the substrate having the projections; the semiconductor film is etched to have an island shape with a resist used as a mask; the resist is etched to expose a portion of the semiconductor film which covers a top surface of the projection; and the exposed portion of the semiconductor film is etched to be thin, while the adjacent portions of the semiconductor film on both sides of the projection remain covered with the resist.
    Type: Grant
    Filed: September 6, 2011
    Date of Patent: April 23, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masaharu Nagai, Takafumi Mizoguchi
  • Patent number: 8367521
    Abstract: The present invention relates to a method of forming a SOI structure having a thin silicon layer by forming a first etch stop layer on a donor substrate, forming a second etch stop layer on the first etch stop layer, wherein the material of the second etch stop layer differs from the material of the first etch stop layer, forming a thin silicon layer on the second etch stop layer, preferably by epitaxy, and bonding the intermediate structure to a target substrate, followed by detaching the donor substrate by splitting initiated in the first etch stop layer at a weakened region and removing the remaining material of the etch stop layers to produce a final ETSOI structure. The invention also relates to the ETSOI structure produces by the described method.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: February 5, 2013
    Assignee: Soitec
    Inventors: Nicolas Daval, Cecile Aulnette
  • Patent number: 8299630
    Abstract: A microstructure has at least one bonding substrate and a reactive multilayer system. The reactive multilayer system has at least one surface layer of the bonding substrate with vertically oriented nanostructures spaced apart from one another. Regions between the nanostructures are filled with at least one material constituting a reaction partner with respect to the material of the nanostructures. A method for producing at least one bonding substrate and a reactive multilayer system, includes, for forming the reactive multilayer system, at least one surface layer of the bonding substrate is patterned or deposited in patterned fashion with the formation of vertically oriented nanostructures spaced apart from one another, and regions between the nanostructures are filled with at least one material constituting a reaction partner with respect to the material of the nanostructures.
    Type: Grant
    Filed: January 26, 2010
    Date of Patent: October 30, 2012
    Assignees: Fraunhofer-Gesellschaft zur Foerderung der Angewandten Forschung E.V., Technische Universitaet Chemnitz
    Inventors: Joerg Braeuer, Thomas Gessner, Lutz Hofmann, Joerg Froemel, Maik Wiemer, Holger Letsch, Mario Baum
  • Patent number: 8288843
    Abstract: A semiconductor light-emitting device includes: a first semiconductor layer having a first major surface, a second major surface which is an opposite side from the first major surface, and a side surface; a second semiconductor layer provided on the second major surface of the first semiconductor layer and including a light-emitting layer; electrodes provided on the second major surface of the first semiconductor layer and on a surface of the second semiconductor layer on an opposite side from the first semiconductor layer; an insulating layer having a first surface formed on the second major surface side of the first semiconductor layer and a second surface which is an opposite side from the first surface; an external terminal which is a conductor provided on the second surface side of the insulating layer; and a phosphor layer provided on the first major surface of the first semiconductor layer and on a portion of the first surface of the insulating layer, the portion being adjacent to the side surface of t
    Type: Grant
    Filed: March 22, 2010
    Date of Patent: October 16, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akihiro Kojima, Yoshiaki Sugizaki
  • Patent number: 8247905
    Abstract: The present invention is related to a method for forming vertical conductive structures by electroplating. Specifically, a template structure is first formed, which includes a substrate, a discrete metal contact pad located on the substrate surface, an inter-level dielectric (ILD) layer over both the discrete metal contact pad and the substrate, and a metal via structure extending through the ILD layer onto the discrete metal contact pad. Next, a vertical via is formed in the template structure, which extends through the ILD layer onto the discrete metal contact pad. A vertical conductive structure is then formed in the vertical via by electroplating, which is conducted by applying an electroplating current to the discrete metal contact pad through the metal via structure. Preferably, the template structure comprises multiple discrete metal contact pads, multiple metal via structures, and multiple vertical vias for formation of multiple vertical conductive structures.
    Type: Grant
    Filed: August 10, 2009
    Date of Patent: August 21, 2012
    Assignee: International Business Machines Corporation
    Inventors: Hariklia Deligianni, Qiang Huang, John P. Hummel, Lubomyr T. Romankiw, Mary B. Rothwell
  • Patent number: 8217423
    Abstract: While embedded silicon germanium alloy and silicon carbon alloy provide many useful applications, especially for enhancing the mobility of MOSFETs through stress engineering, formation of alloyed silicide on these surfaces degrades device performance. The present invention provides structures and methods for providing unalloyed silicide on such silicon alloy surfaces placed on semiconductor substrates. This enables the formation of low resistance contacts for both mobility enhanced PFETs with embedded SiGe and mobility enhanced NFETs with embedded Si:C on the same semiconductor substrate. Furthermore, this invention provides methods for thick epitaxial silicon alloy, especially thick epitaxial Si:C alloy, above the level of the gate dielectric to increase the stress on the channel on the transistor devices.
    Type: Grant
    Filed: January 4, 2007
    Date of Patent: July 10, 2012
    Assignee: International Business Machines Corporation
    Inventors: Yaocheng Liu, Dureseti Chidambarrao, Oleg Gluschenkov, Judson R Holt, Renee T Mo, Kern Rim
  • Patent number: 8193553
    Abstract: The invention provides a semiconductor high-power light-emitting module including a heat-dissipating member, a heat-conducting device, and a diode light-emitting device. The heat-dissipating member includes an isolator member coupled to a first side of the heat-dissipating member. The heat-dissipating member has a second side opposite to the first side. The isolator member has a third side opposite to the first side. The environment temperature at the third side is higher than that at the second side. The heat-conducting device has a flat end and a contact portion tightly mounted on the heat-dissipating member. The diode light-emitting device is disposed on the flat end of the heat-conducting device. The semiconductor light-emitting module of the invention, applied to a headlamp of an automobile, has properties of saving electricity and long life, and furthermore the capability of integrating the heat-dissipating member into a shell of the automobile is both artistic and practical.
    Type: Grant
    Filed: October 10, 2006
    Date of Patent: June 5, 2012
    Assignee: Neobulb Technologies, Inc.
    Inventor: Jen-Shyan Chen
  • Patent number: 8193070
    Abstract: A method for bonding several layers, which comprise at least one thermally bondable material, by means of a joint layer produced with the aid of thermocompression at least one of the layers comprising a semiconductor material, as well as to a correspondingly manufactured device. Also disclosed is a method for manufacturing an organic light-emitting diode and an organic light-emitting diode that is encapsulated between two cover layers with the aid of thermocompression.
    Type: Grant
    Filed: September 22, 2006
    Date of Patent: June 5, 2012
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Vincent Grolier, Andreas Plössl, Marianne Renner
  • Patent number: 8174094
    Abstract: An electronic device comprises a substrate comprising a first surface and a second surface, a substrate carrier comprising a first surface and a second surface, and an inorganic material bonding the second surface of the substrate and the second surface of the substrate carrier.
    Type: Grant
    Filed: June 21, 2009
    Date of Patent: May 8, 2012
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Chien-Hua Chen, Barry C. Snyder, Ronald A. Hellekson
  • Patent number: 8106486
    Abstract: In a method of making an electronic apparatus, electronic devices and a mold are placed in a package such that pads of electronic devices are covered with the mold. An electrical insulator is poured into the package, in which the mold is placed, to fill the package. The mold is removed from the electrical insulator to form a space where the pads are exposed. An electrical conductor is placed in the space such that the pads are electrically connected together through the electrical conductor. The electrical conductor is in the form of a liquid or a solid having both fluidity and deformability.
    Type: Grant
    Filed: May 12, 2009
    Date of Patent: January 31, 2012
    Assignee: DENSO CORPORATION
    Inventors: Kouji Yamamoto, Hirofumi Higuchi, Masaki Inoue
  • Patent number: 8058736
    Abstract: The present invention provides a semiconductor device including: a semiconductor chip mounted on a substrate; a heat spreader provided above the semiconductor chip; and a sealing resin interposed between the semiconductor chip and the heat spreader and covering the semiconductor chip. The heat spreader is not in contact with any of the substrate and the semiconductor chip, and has an opening.
    Type: Grant
    Filed: June 8, 2007
    Date of Patent: November 15, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Masahiro Koike, Kenichi Kurihara
  • Patent number: 8017450
    Abstract: A method of forming an asymmetrical encapsulant bead on a series of wire bonds electrically connecting a micro-electronic device to a series of conductors, the micro-electronic device having a planar active surface. The method has the steps of positioning the die and the wire bonds beneath an encapsulant jetter that jets drops of encapsulant on to the wire bonds, the drops of encapsulant following a vertical trajectory, tilting the die such that the active surface is inclined to the horizontal and, jetting the drops of encapsulant to form a bead of encapsulant material covering the series of wire bonds, the bead having a cross sectional profile that is asymmetrical about an axis parallel to a normal to the active surface.
    Type: Grant
    Filed: February 3, 2009
    Date of Patent: September 13, 2011
    Assignee: Silverbrook Research Pty Ltd
    Inventors: Nadine Lee-Yen Chew, Elmer Dimaculangan Perez, Kiangkai Tankongchumruskul
  • Patent number: 7989839
    Abstract: The present invention provides a method and apparatus for using light emitting diodes for curing and various solid state lighting applications. The method includes a novel method for cooling the light emitting diodes and mounting the same on heat pipe in a manner which delivers ultra high power in UV, visible and IR regions. Furthermore, the unique LED packaging technology of the present invention utilizes heat pipes that perform very efficiently in very compact space. Much more closely spaced LEDs operating at higher power levels and brightness are possible because the thermal energy is transported in an axial direction down the heat pipe and away from the light-emitting direction rather than a radial direction in nearly the same plane as the “p-n” junction.
    Type: Grant
    Filed: March 1, 2010
    Date of Patent: August 2, 2011
    Assignee: Koninklijke Philips Electronics, N.V.
    Inventor: Jonathan S. Dahm
  • Patent number: 7982278
    Abstract: A thermoelectric module has a first substrate, a second substrate spaced from the first substrate, a plurality of P type thermoelectric elements and N type thermoelectric elements arranged in the space between the first and second substrates, and a plurality of electrodes which connect the P type and N type thermoelectric elements in series. Each electrode is connected to a respective one of the plurality of P type thermoelectric elements at a first connection and a respective one of the plurality of N type thermoelectric elements in the space, and a sealant is located at an edge portion of the space. Each one of a series of first or outer electrodes closest to the edge portion of the space has a concave portion that is concaved in a direction departing from the edge portion of the space and is at a position between the first connection and the second connection.
    Type: Grant
    Filed: January 27, 2009
    Date of Patent: July 19, 2011
    Assignee: Kyocera Corporation
    Inventors: Kouji Tokunaga, Kenichi Tajima
  • Patent number: 7952173
    Abstract: A nanometric device comprising a substrate; a plurality of conductive spacers of a conductive material, each conductive spacer being arranged on top of and transverse to the substrate, the conductive spacers including respective pairs of conductive spacers defining respective hosting seats each of less than 30 nm wide; and a plurality of nanometric elements respectively accommodated in the hosting seats.
    Type: Grant
    Filed: September 4, 2008
    Date of Patent: May 31, 2011
    Assignee: STMicroelectronics S.r.l.
    Inventors: Danilo Mascolo, Gianfranco Cerofolini, Gianguido Rizzotto
  • Patent number: 7936049
    Abstract: It is an object of the present invention to provide a nitride semiconductor device with low parasitic resistance by lowering barrier height to reduce contact resistance at an interface of semiconductor and metal. The nitride semiconductor device includes a GaN layer, a device isolation layer, an ohmic electrode, an n-type Al0.25Ga0.75N layer, a sapphire substrate, and a buffer layer. A main surface of the n-type Al0.25Ga0.75N layer is on (0 0 0 1) plane as a main surface, and concaves are arranged in a checkerboard pattern on the surface. The ohmic electrode contacts the sides of the concaves of the n-type Al0.25Ga0.75N layer, and the sides of the concaves are on non-polar surfaces such as (1 1 ?2 0) plane or (1 ?1 0 0) plane.
    Type: Grant
    Filed: June 25, 2010
    Date of Patent: May 3, 2011
    Assignee: Panasonic Corporation
    Inventors: Masayuki Kuroda, Tetsuzo Ueda
  • Patent number: 7902639
    Abstract: Improved methods and articles providing conformal coatings for a variety of devices including electronic, semiconductor, and liquid crystal display devices. Peptide formulations which bind to nanoparticles and substrates, including substrates with trenches and vias, to provide conformal coverage as a seed layer. The seed layer can be further enhanced with use of metallic films deposited on the seed layer. Seed layers can be characterized by AFM measurements and improved seed layers provide for better enhancement layers including lower resistivity in the enhancement layer. Peptides can be identified by phage display.
    Type: Grant
    Filed: November 16, 2005
    Date of Patent: March 8, 2011
    Assignee: Siluria Technologies, Inc.
    Inventors: Philip E. Garrou, Michael R. Knapp, Hash Pakbaz, Florian Pschenitzka, Xina Quan, Michael A. Spaid
  • Patent number: 7893432
    Abstract: Various embodiments include apparatus and method having a heat source, a thermal management device, and an interface disposed between the thermal management device and the heat source. The interface includes nanostructures to facilitate heat transfer and adhesion between the heat source and the thermal management device.
    Type: Grant
    Filed: September 16, 2008
    Date of Patent: February 22, 2011
    Assignee: Intel Corporation
    Inventors: Eric C. Hannah, Ralph M. Kling
  • Patent number: 7863641
    Abstract: The present invention provides a method and apparatus for using light emitting diodes for curing and various solid state lighting applications. The method includes a novel method for cooling the light emitting diodes and mounting the same on heat pipe in a manner which delivers ultra high power in UV, visible and IR regions. Furthermore, the unique LED packaging technology of the present invention utilizes heat pipes that perform very efficiently in very compact space. Much more closely spaced LEDs operating at higher power levels and brightness are possible because the thermal energy is transported in an axial direction down the heat pipe and away from the light-emitting direction rather than a radial direction in nearly the same plane as the “p-n” junction.
    Type: Grant
    Filed: October 12, 2007
    Date of Patent: January 4, 2011
    Inventor: Jonathan S. Dahm
  • Patent number: 7839908
    Abstract: Provided is a device capable of oscillating a plurality of oscillation modes within a laser medium for obtaining a fundamental wave output which is easy in output scaling and high in luminance, thereby enabling a second harmonic conversion which is high in efficiency. The device includes: a laser medium (5) that is planar, has a waveguide structure in a thickness direction of a cross-section that is perpendicular to an optical axis (6), and has a cyclic lens effect in a direction perpendicular to the optical axis (6) and the thickness direction; a clad (4) that is bonded onto one surface of the laser medium (5); and heat sink (3) that is bonded onto one surface side of the laser medium (5) through the clad (4), and in the device, a laser oscillation includes a laser oscillation that oscillates in a waveguide mode of the laser medium (5), and a laser oscillation that oscillates in a plurality of resonator modes that are generated by a cyclic lens effect of the laser medium (5).
    Type: Grant
    Filed: March 30, 2005
    Date of Patent: November 23, 2010
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takayuki Yanagisawa, Yoshihito Hirano, Syuhei Yamamoto, Masao Imaki, Kiyohide Sakai, Yasuharu Koyata
  • Patent number: 7834433
    Abstract: In one embodiment the present invention includes a semiconductor power device. The semiconductor power device includes a single gauge lead frame, a semiconductor die, and a heat sink. The semiconductor die is attached to a first level of the lead frame. The heat sink is attached to a second level of the lead frame. A molding compound encapsulates the semiconductor die and a portion of the lead frame, such that a portion of the heat sink is outside of the molding compound. The resulting device may be efficiently manufactured as compared to dual gauge lead frame devices or devices where the semiconductor die is not attached to the lead frame.
    Type: Grant
    Filed: July 16, 2007
    Date of Patent: November 16, 2010
    Assignee: Shanghai Kaihong Technology Co., Ltd.
    Inventors: Tan Xiaochun, Li Yunfang
  • Patent number: 7834434
    Abstract: The present invention is achieved with the object of providing an illumination system formed of an LED light emitting body and a socket which can appropriately release heat from LED chips. This object is achieved in the following manner. A heat conducting layer 12 made of diamond is provided on a substrate 11, and on top of this, a conductive layer 13 having a predetermined pattern is formed. LED chips 16 are mounted in predetermined positions on the conductive layer 13. Terminals of the conductive layer 13 and electrodes of the LED chips 16 are connected to each other. A connector part 14 for the connection to a socket is provided in an end portion of the substrate 11. The heat conducting layer 12 on the connector part 14 makes thermal contact with the heat conducting layer provided on the inner surface of the opening of the socket. A current is supplied to respective LED chips 16 through the conductive layer 13 from the socket, and respective LED chips 16 emit light.
    Type: Grant
    Filed: May 5, 2008
    Date of Patent: November 16, 2010
    Assignee: Yanchers Inc.
    Inventors: Junichi Shimada, Yoichi Kawakami
  • Patent number: 7786606
    Abstract: A resin-sealed semiconductor device includes a metal frame, an electronic substrate, an adhesive agent, a molded resin, and a bonding agent. The electronic substrate includes a first surface having a circuit element wiring part, a second surface facing the metal frame, and a side surface arranged approximately perpendicularly to the first surface and the second surface. The adhesive agent is disposed between the metal frame and the second surface to cover the second surface and a portion of the side surface adjacent to the second surface. The molded resin covers the metal frame and the electronic substrate, and holds the other portion of the side surface adjacent to the first surface. The bonding agent is disposed between the circuit element wiring part and the molded resin so that the molded resin holds the circuit element wiring part through the bonding agent.
    Type: Grant
    Filed: November 27, 2007
    Date of Patent: August 31, 2010
    Assignee: Denso Corporation
    Inventors: Mitsuyasu Enomoto, Haruo Kawakita, Takashi Ohno
  • Patent number: 7777305
    Abstract: It is an object of the present invention to provide a nitride semiconductor device with low parasitic resistance by lowering barrier height to reduce contact resistance at an interface of semiconductor and metal. The nitride semiconductor device includes a GaN layer, a device isolation layer, an ohmic electrode, an n-type Al0.25Ga0.75N layer, a sapphire substrate, and a buffer layer. A main surface of the n-type Al0.25Ga0.75N layer is on (0 0 0 1) plane as a main surface, and concaves are arranged in a checkerboard pattern on the surface. The ohmic electrode contacts the sides of the concaves of the n-type Al0.25Ga0.75N layer, and the sides of the concaves are on non-polar surfaces such as (1 1 ?2 0) plane or (1 ?1 0 0) plane.
    Type: Grant
    Filed: March 4, 2008
    Date of Patent: August 17, 2010
    Assignee: Panasonic Corporation
    Inventors: Masayuki Kuroda, Tetsuzo Ueda
  • Patent number: 7759761
    Abstract: In a semiconductor wafer substrate (20) for power semiconductor components (1) and in a method for producing the same, the semiconductor wafer substrate (20) has a large-area, buried rear side electrode (3) in form of a layer arranged between a self-supporting wafer substrate (4) and a non-self-supporting monocrystalline silicon wafer layer (5) arranged on the rear side electrode (3). The rear side electrode (3) has a ternary carbide and/or a ternary nitride and/or carbon.
    Type: Grant
    Filed: December 20, 2006
    Date of Patent: July 20, 2010
    Assignee: Infineon Technologies Austria AG
    Inventors: Hans-Joachim Schulze, Helmut Strack
  • Patent number: 7750442
    Abstract: A high-frequency switch includes a semiconductor body made of a semiconductor material having a first surface and a second surface, and two direct current terminals and two high-frequency terminals.
    Type: Grant
    Filed: February 23, 2005
    Date of Patent: July 6, 2010
    Assignee: Infineon Technologies AG
    Inventor: Reinhard Gabl
  • Patent number: 7701055
    Abstract: A plurality of disc-shaped substrates carry light emitters and are axially stacked, spaced apart, in a metal housing to dissipate the heat produced by the light emitters. The housing comprises mutually connected elongate planar ribs that abut the light emitters or substrates for thermally connecting the light emitters to the housing. The ribs have shoulders. The substrates are received between the ribs and abut the shoulders. The shoulders are positioned proximate each light emitter in intimate contact with the substrate for efficient heat dissipation.
    Type: Grant
    Filed: January 30, 2007
    Date of Patent: April 20, 2010
    Assignee: Hong Applied Science and Technology Research Institute Company Limited
    Inventors: Kai Chiu Wu, Ming Lu, Chak Hau Pang
  • Patent number: 7675143
    Abstract: A semiconductor element capable of reducing noises of a circuit propagating to another circuit through a seal ring is provided. A semiconductor element includes, on a surface of a semiconductor substrate: a plurality of circuits; a ring-shaped seal ring surrounding the plurality of circuits; and wiring connecting between the seal ring and an external low-impedance node.
    Type: Grant
    Filed: October 29, 2007
    Date of Patent: March 9, 2010
    Assignee: Sony Corporation
    Inventors: Takahide Kadoyama, Masayoshi Abe, Atsushi Kamo, Takaaki Yamada, Chihiro Arai