Abstract: The nitride semiconductor device includes: a substrate made of a III-V group compound semiconductor containing nitride; and a function region made of a III-V group compound semiconductor layer containing nitride formed on a main surface of the substrate. The main surface of the substrate is tilted from a {0001} plane by an angle in a range of 13° to 90° inclusive.

Abstract: A thermally coupling electrically decoupling cooling device is described. The cooling device may be thermally disposed between a self-heating electrically conductive line and a semiconductor substrate to cool the line by transferring heat from the line to the substrate while blocking flow of current from the line to the substrate. The cooling device may contain a thermally conductive structure, such as a stack of vias and lines, to conduct heat away from the electrically conductive line, and a current blocking structure, such as a reverse biased diode or a capacitor, to block current flow into the substrate. Specific current blocking structures include a reverse biased diode containing an n-doped region and a p-doped region disposed between the thermally conductive structure and the substrate, and a capacitor containing a dielectric layer disposed between the thermally conductive structure and the semiconductor substrate.

Abstract: A fuse (50, 150, 200) with a low fusing current includes a first contact element (51, 151, 201) and a second contact element (51, 151, 201). A fusing element (53, 153, 203) is coupled between the first and second contact elements (51, 151, 201). At least a majority of the fusing element (53, 153, 203) comprises silicided material.

Abstract: A diode for use in an under-the-hood automotive application has a TO 220 outline and consists of a diode die on a two piece lead frame which has a thick section to which the bottom of the die is soldered, and a thinner section which extends through a plastic housing as a connection tab and which has a forked end for easy connection to a node of a three phase bridge. The bottom of the thickened section is exposed through the insulation housing for easy connection to a d-c heat sink rail. The diode is particularly useful in applications greater than 2 KW.

Abstract: On a heat sink having a low thermal resistance, an Ni thin film layer is formed at a film thickness of 2 &mgr;m to 6 &mgr;m. On the face to which a semiconductor light emitting element is to be bonded and the face on the side from which light is to be emitted, a barrier metallic layer is formed at a film thickness of 50 nm to 150 nm in the region as wide as four times the area of the bonding face of the semiconductor light emitting element. A wettability improving metallic layer is formed at a film thickness of 50 nm to 150 nm. The semiconductor light emitting element stacks layers of AlGaAs, GaAs, GaAsP, and InGaAs, all on a GaAs substrate. An N electrode includes AuGe/Ni/Au , and a P electrode includes Au/Pt/Ti/Pt/Ti and is pressed and soldered against the bonding face of the heat sink.

Abstract: A thin-film heat sink comprises a heat sink film functioning as a heat sink and a bonding film for bonding the heat sink film to a base. The bonding film is an aluminum oxide (Al2O3) film formed using the CVD method and the heat sink film is an aluminum nitride (AlN) film. For the AlN film as the heat sink film, internal stress is compressive stress, whereas for the Al2O3 film as the bonding film, internal stress is tensile stress.

Abstract: A semiconductor package including at least one semiconductor chip disposed within a housing, the housing including a lid which overlies the at least one semiconductor chip and a heat-dissipating device coupled to the housing, the heat-dissipating device including at least one area formed of a material with a low coefficient of thermal expansion.

Abstract: A semiconductor device (50) includes a semiconductor die (52) having electronic circuitry that is connected to a substrate (54). The substrate (54) is used to interface the semiconductor die (52) to a printed circuit board (64). The substrate (54) includes a plurality of bonding pads (56, 58). A first portion of the plurality of bonding pads are soldermask defined (SMD) bonding pads (56) and a second portion of the plurality of bonding pads are non-soldermask defined (NSMD) bonding pads (58). Using a combination of SMD and NSMD bonding pads provides the advantages of good thermal cycling reliability and good bending reliability over devices that have only SMD bonding pads or NSMD bonding pads.

Abstract: A thermally coupling electrically decoupling cooling device is described. The cooling device may be thermally disposed between a self-heating electrically conductive line and a semiconductor substrate to cool the line by transferring heat from the line to the substrate while blocking flow of current from the line to the substrate. The cooling device may contain a thermally conductive structure, such as a stack of vias and lines, to conduct heat away from the electrically conductive line, and a current blocking structure, such as a reverse biased diode or a capacitor, to block current flow into the substrate. Specific current blocking structures include a reverse biased diode containing an n-doped region and a p-doped region disposed between the thermally conductive structure and the substrate, and a capacitor containing a dielectric layer disposed between the thermally conductive structure and the semiconductor substrate.

Abstract: Device quality, single crystal film of cubic zinc-blend aluminum nitride (AlN) is deposited on a cubic substrate, such as a silicon (100) wafer by plasma source molecular beam epitaxy (PSMBE). The metastable zinc-blend form of AlN is deposited on the substrate at a low temperature by a low energy plasma beam of high-energy activated aluminum ions and nitrogen ion species produced in a molecular beam epitaxy system by applying a pulsed d.c. power to a hollow cathode source. In this manner, films having a thickness of at least 800 Å were produced. The lattice parameter of as-deposited films was calculated to be approximately 4.373 Å which corresponds closely to the theoretical calculation (4.38 Å) for cubic zinc-blend AlN. An interfacial layer of silicon carbide, specifically the cubic 3C—SiC polytype, interposed between the epitaxial film of zinc-blend AlN and the Si(100) wafer provides a template for growth and a good lattice match.

Abstract: An electronic device includes a FET that is capable of operating in a negative differential resistance mode as well as in a conventional FET mode. The selection of the mode can be accomplished by providing a control signal to a body terminal of the FET as needed for a particular application. By providing two different operating modes a multi-function logic gate is effectuated that can perform two or more different logical functions on an input signal. Furthermore the device can be used as an element of a new logic family and synthesized into suitable configurations so that more sophisticated and complex functions are achieved with increased density, lower power, etc. over conventional semiconductor FETs.

Abstract: A high-speed bipolar transistor is provided which is improved in the effect of heat radiation without increasing the substrate capacitance. The heat radiation connection between a base region and a silicon substrate includes a p+ extrinsic base polysilicon electrode and a polysilicon layer buried in an isolation groove with a very thin silicon dioxide side wall. Accordingly, the heat generated at the base is radiated through this path to the silicon substrate. Further, the film thickness of the silicon dioxide on the inner wall of the isolation groove is sufficiently increased compared with previous structures to prevent an increase in the substrate capacitance. Consequently, there can be obtained a bipolar transistor which operates at high speed, and is improved in the effect of heat radiation without increasing the substrate capacitance.

Abstract: A semiconductor device having a polish preventing pattern that can improve the planarity of an element formation region after the CMP method polishing is provided. To the shape of an element formation region, a loop-shaped element formation region dummy is formed in a uniform width and at a uniform distance from the edge of the element formation region to have a loop shape. That can prevent formation of such a portion that is on a line extended from a gap between polish preventing patterns as well as a large gap between an element formation region and a polish preventing pattern. Accordingly, local application of large pressure to an end of an element formation region is suppressed which is caused when a polishing cloth bends. As a result, the semiconductor device does not have a locally substantially etched portion. The planarity of the surface of an element formation region is maintained in the semiconductor device.

Abstract: A laser system is disclosed. The system comprises laser emitters (102, 104, and 106) forming a laser stack (108). A heater resistor (110) coupled to the laser stack (108) stabilizes the temperature of the laser stack (108). A heat reservoir (112) coupled to the laser stack (108) stores the heat flow from and releases the heat flow to the laser stack (108). A temperature monitor (114) coupled to the laser stack (108) monitors the temperature of the laser stack (108).

Abstract: A semiconductor device such as a P-N or P-I-N junction diode, includes a first semiconductor layer having a first conductivity-type and being mounted over a metal address line, and a second semiconductor layer having a second conductivity-type and being mounted over the first semiconductor material. The diode preferably has a thickness of substantially no more than about 1 micron, and the diode includes a P-N junction confined to a thickness of less than about 0.1 micron. In the preferred embodiment the method comprises depositing a first semiconductor layer having a first conductivity type, depositing a second intrinsic layer, annealing to convert both layers to a polycrystalline layer, implanting ions of a second conductivity type into the second layer, and annealing to convert the second layer to a polycrystalline. The result is a diode having an ultra-sharp p-n junction.

Abstract: A semiconductor device comprises one or more field effect devices (FD) having source and drain regions (5 and 6) spaced apart by a body region (3a). A gate structure (7a, 7b), preferably in a trench (4), controls a conduction channel in a portion (3b) of the body region (3a) between the source and drain regions. The device has one or more mesa structures (100) having end and side walls (100a to 100d). The body region (3a) extends between and meets at least the side walls (100c and 100d) of the mesa structure. The gate structure (7a, 7b) extends along and between the side walls such that the conduction channel accommodating portion (3b) extends along and between the side walls (100c and 100d). The source and drain regions (5 and 6) meet respective end walls (100a and 100b) of the mesa structure and/or its side walls (100c and 100d). At the mesa walls, a source electrode (S) contacts the source region (5) and a drain electrode (D) contacts the drain region (6).

Abstract: Disclosed is a manufacturable silicon-based modular integrated circuit structure having performance characteristics comparable to high frequency GaAs-based integrated circuit structures, comprising materials and made in process steps which are compatible with existing low cost silicon-based integrated circuit processing.

Abstract: Provided is a method and composition for RF sputter cleaning of contact and via holes which provides substantially uniform charge distribution in the holes and minimizes electron shadowing. This is accomplished by isotropically depositing, such as by PVD, a layer of conductive material at the wafer surface surrounding a hole and down the sides of the hole. Isotropic deposition is such that in high aspect ratio trenches and holes deposition is heaviest at the top and minimal at the bottom (due to the deposition shadowing effect). The deposited conductive material is preferably a metal that is also used as a liner in the holes prior to depositing the plug material. The conductive material provides path for negative charge otherwise accumulating at the top of a hole during RF sputter cleaning to reach the bottom of the hole and thereby prevents accumulations of charge of one polarity in and around the hole. Thus, the stress on the gate oxide caused by conventional RF sputtering, described above, is relieved.

Abstract: A method and an apparatus for performing circuit edits through the back side of a flip-chip packaged integrated circuit die. In one embodiment, a circuit edit is achieved by exposing first and second circuit edit connection targets through a semiconductor substrate of the integrated circuit die from the back side. Next, an insulating layer is deposited over the first and second circuit edit connection targets and the exposed semiconductor substrate. Next, the circuit edit connection targets are re-exposed through the insulating layer and a conductor is deposited over the re-exposed circuit edit connection targets and the deposited insulating layer from the back side of the integrated circuit to couple together the circuit edit connection targets.

Abstract: A heterojunction bipolar transistor has a mesa including collector 604, base 603, and emitter 602 layers. The mesa has first and second sidewalls 606. An improved heat dissipation structure comprises a layer of electrically insulative and thermally conductive material 607 disposed on one of the sidewalls. A thermal path metal 600 is electrically connected to the emitter 602 and is disposed on the layer of electrically insulative and thermally conductive material 607. The thermal path metal 600 extends from the emitter 602 to the substrate 608 providing for efficient dissipation of heat that is generated by the HBT device.

Abstract: A low cost highly integrated method of fabricating a heat sink on the backside of a power semiconductor device maintains device performance, improves thermal transfer, and enables reliable planar connections without having to dice the wafer or package the discrete device-heat sink assembly. An etch stop layer is formed between the wafer and the frontside power devices to protect them during backside processing and to reduce the contact resistance between the device and its heat sink. The heat sinks are formed by thinning, patterning and then plating the wafer in such a manner that the devices can be released without dicing. The heat sinks are preferably oversized so that a vacuum tool can grasp the heat sink from above without damaging the device and then compression bond the heat sink onto a planar microstrip circuit assembly, which is designed and packaged to facilitate easy replacement of failed devices.

Abstract: The microwave hybrid integrated circuit comprises a dielectric board (1) provided with a topological metallization pattern (2) on its face side, a shield grounding metallization (3) on the back side thereof, a hole (4), and a metal base (5) having a projection (6). The hole (4) in the board (1) has a constriction (9) situated at a height of 1 to 300 .mu.m from the face surface of the board (1). The projection (6) is located in a wide section (10) of the hole (4). Bonding pads (8) of a chip (7) which are to be grounded are electrically connected to the projection (6) through the constricted portion (9) of the hole (4) which is filled with an electrically and heat conducting material (11). The wide section (10) of the hole (4) is from 0.2.times.0.2 mm to the size of the chip (7), and the distance between the side walls of the projection (6) and the side walls of the wide section (10) of the hole (4) is 0.001 to 1.0 mm.

Abstract: A microwave monolithic integrated circuit includes a coplanar waveguide (CPW) formed by a composite silicon structure constituted by a relatively high resistivity substrate, a first oxide layer on the upper surface thereof, a relatively thin silicon layer formed on the surface of the first oxide layer, and a very thin second oxide layer formed on the surface of the thin silicon layer. The silicon layer and the first oxide layer on which it is formed constitutes a silicon-on-insulator or SOI structure. A metallic signal line and ground planes are bonded to the surface of the second oxide layer. The zone of the thin silicon layer which extends between the ground planes is doped with an active impurity to produce high conductivity therein. As a result, the electric component of a quasi-TEM wave traversing the waveguide is substantially restricted to the thin silicon layer and does not penetrate to the underlying bulk silicon substrate.

Abstract: A fusible link device disposed on a semiconductor substrate for providing discretionary electrical connections. The fusible link device of the invention includes a silicide layer and a polysilicon layer formed on the silicide layer and has a first unprogrammed resistance.

Abstract: A laser diode package includes a laser diode, a heat sink and a lid. The laser diode has an emitting surface, a reflective surface opposing the emitting surface, and first and second surfaces between the emitting surface and the reflective surface. The laser diode has a diode height defined between the emitting surface and the reflective surface. The heat sink has an interior surface, an exterior surface opposing the interior surface, a top surface and a base surface. The height of the heat sink is defined between the top surface and the base surface and is approximately less than four times the laser diode height. The first surface of the diode is attached to the interior surface of the heat sink with a first solder. The base surface of the heat sink is coupled to a thermal reservoir. The lid is attached to the second surface of the laser diode via a second solder. An upper end of the lid is near the emitting surface of the laser diode.

Abstract: A surface-protected composite article, such as a missile component, is prepared with a heat-sink substrate, a first composite layer of an pre-ceramic-matrix structural composite material, and a second composite layer of a reinforced silicone pre-ceramic material. The silicone material is co-curable with the organic matrix of the first composite layer. The silicone at the surface of the article is thereafter converted to a silica refractory by an appropriate treatment such as exposure to an oxygen-rich plasma or a high-surface temperature. The silica protects the surface of the composite material.

Abstract: A semiconductor component that could be a power transistor type of component comprises mesa-structured elementary bipolar transistors. This component has a thick, metal heat sink of which a part (PI) takes the form of a bridge and a part is in contact with the substrate. The legs of the bridge lie on the entire unit constituted by the mesas. The heat sink made on the front face of the substrate may be connected to the rear face of the substrate comprising a ground plate. The discharging of the heat is thus appreciably fostered.

Abstract: A semiconductor body (2) has an active region (6) of n conductivity type formed of a material having a relatively low mass, high mobility conduction band main minimum and at least one relatively high mass, low mobility conduction band satellite minimum and an injector region (9) defining a potential barrier (P) to the flow of electrons into the active region (6) of a height such that, in operation of the device, electrons with sufficient energy to surmount the barrier (P) provided by the injector region (9) are emitted into the active region (6) with an energy comparable to that of the at least one relatively high mass, low mobility conduction band satellite minimum. An electron containing well region (10a, 10b) of a material different from that of the active region (6) and of the injector region (9) is provided between the injector region (9) and the active region (6) for inhibiting the spread of a depletion region into the active region (6) during operation of the device.

Abstract: A heat tolerant, frequency responsive transistor for use in the microwave region includes a collector region, a base region overlying the collector region, and an emitter region including an AlGaN layer overlying at least part of said base region, forming a heterojunction between said base region and said emitter region. The emitter region may include two layers. The HBT may be mounted on a SiC or sapphire substrate. The HBT may include a buffer layer between the substrate and the collector region.

Abstract: Multiple quantum wells within an impact avalanche transit time device (IMPATT) utilizing a plurality of gallium arsenide/aluminum gallium arsenide heterojunctions are used to provide a high power, high frequency, high efficiency device operating at 50 GHz and up. The multiple quantum wells defined by the heterojunctions between pairs of gallium arsenide quantum wells and aluminum gallium arsenide barrier layers improves the nonlinearity of the avalanche process within the gallium arsenide quantum wells and reduces the ionization rate saturation limitations. Optical injection locking of the current through the IMPATT device is achieved by irradiating the active layer of the IMPATT device with modulated laser light.

Abstract: A silicon-based monolithic microwave integrated circuit architecture is described. This architecture, called MICROX.TM., is a combination of silicon material growth and wafer processing technologies. A wafer is fabricated using a substrate of high resistivity silicon material. An insulating layer is formed in the wafer below the surface area of active silicon, preferably using the SIMOX process. A monolithic circuit is fabricated on the wafer. A ground plane electrode is formed on the back of the wafer. Direct current and rf capacitive losses under microstrip interconnections and transistor source and drain electrodes are thereby minimized. Reduction in the resistivity of the substrate material as a result of CMOS processing can be minimized by maintaining a shielding layer over the bottom surface of the wafer. Microstrip and airbridge connectors, salicide processing and nitride side wall spacing can be used to further enhance device performance.

Abstract: A semiconductor structure having an active layer formed over a first surface of a substrate. The semiconductor structure includes an electrode formed over a first surface of the structure. A conductive layer is formed over a second surface of the substrate. A conductor section passes through the semiconductor structure between the electrode and the conductive layer. The conductor section includes two conductive elements, one having a first end connected to the electrode and a second end terminating in the semiconductor structure; and the other conductive element having a first end connected to the conductive layer and a second end connected to the second end of the first conductive element. The second end terminates at, or in, an etch resistant layer disposed in the semiconductor structure between the active layer and the substrate. The method for forming the conductive sections includes etching the second via hole from the second surface of the substrate until the etching reaches an etch resistant layer.

Abstract: An optoelectric switch is disclosed that utilizes a cylindrically shaped and contoured GaAs medium or other optically active semiconductor medium to couple two cylindrically shaped metal conductors with flat and flared termination points each having an ovoid prominence centrally extending there from. Coupling the truncated ovoid prominence of each conductor with the cylindrically shaped optically active semiconductor causes the semiconductor to cylindrically taper to a triple junction circular line at the base of each prominence where the metal conductor conjoins with the semiconductor and a third medium such as epoxy or air. Tapering the semiconductor at the triple junction inhibits carrier formation and injection at the triple junction and thereby enables greater current carrying capacity through and greater sensitivity of the bulk area of the optically active medium.

Abstract: A heat dissipation apparatus for dissipation of thermal energy from an isolated active silicon region to an underlying supportive substrate is disclosed. Such an apparatus comprises a diamond filled trench having walls extending through the isolated active silicon region, an underlying insulative layer, and into the supportive substrate, whereby said diamond filled trench provides a high thermal conductive path from said active silicon region to said substrate.

Abstract: A semiconductor device of vertical arrangement includes an anode region formed of a first semiconductor substrate and a second semiconductor substrate joined with the first semiconductor substrate. The first semiconductor substrate forms a high-resistance layer with a predetermined impurity density, and the second semiconductor substrate forms a low-resistance layer whose impurity density is higher than that of the high-resistance layer. A PN junction is formed inside the first semiconductor substrate. The periphery of the first semiconductor substrate including the PN junction is configured in an inverted mesa structure and coated with an insulation material. With this arrangement, the semiconductor device has a high withstand voltage and enables an employment of a large diameter wafer.

Abstract: Modified laser submounts are positioned in grooves in the surface of a monolithic substrate permitting not only relatively high packing diversities, but also pretesting and easy replacement of any submounts which may later become defective in the field. The assembly may be connected directly to a heat sink or may include an integral microchannel cooler.

Abstract: A transferred electron effect device (1) has adjacent its cathode contact region (3) an injection zone (60) defining a potential barrier (P) for causing electrons to be emitted, under the influence of an electric field applied between the cathode and anode contact regions (3 and 4), into the active region (5) of the device with an energy comparable to that of a relatively high mass, low mobility satellite minimum (L) of the active region (5). The anode contact region (4), active region (5), injection zone (60) and cathode contact region (3) are grown sequentially, for example using molecular beam epitaxy, on a substrate which is then selectively removed to expose the anode contact region. A heat sink (70) is provided in thermal contact with the anode contact region (4). Providing the heat sink (70) in thermal contact with the anode contact region (4) rather than the cathode contact region (3) enables a significant increase in rf output power.