Abstract: In one embodiment, a method of fabricating a transistor for a memory cell includes the steps of performing a counter doping implant before or after a source/drain implant. The counter doping implant may comprise one or more implant steps that move a metallurgical junction formed by a well and a highly doped region closer to a surface of the substrate. The counter doping implant may also increase the concentration of the dopant of the well. The counter doping implant and the source/drain implant may be performed using the same mask. Transistors fabricated using embodiments of the present invention may be employed in memory cells to reduce soft error rates.

Abstract: A method for forming a high-luminescence Si electroluminescence (EL) phosphor is provided, with an EL device made from the Si phosphor. The method comprises: depositing a silicon-rich oxide (SRO) film, with Si nanocrystals, having a refractive index in the range of 1.5 to 2.1, and a porosity in the range of 5 to 20%; and, post-annealing the SRO film in an oxygen atmosphere. DC-sputtering or PECVD processes can be used to deposit the SRO film. In one aspect the method further comprises: HF buffered oxide etching (BOE) the SRO film; and, re-oxidizing the SRO film, to form a SiO2 layer around the Si nanocrystals in the SRO film. In one aspect, the SRO film is re-oxidized by annealing in an oxygen atmosphere. In this manner, a layer of SiO2 is formed around the Si nanocrystals having a thickness in the range of 1 to 5 nanometers (nm).

Abstract: A nonvolatile memory element is formed by layering a lower electrode, a variable resistor and an upper electrode in sequence. The variable resistor is formed in which crystallinity and amorphism are mixed. Thus, the nonvolatile memory element is formed. More preferably, the variable resistor is a praseodymium-calcium-manganese oxide represented by a general formula, Pr1-xCaxMnO3, that has been formed at a film forming temperature from 350° C. to 500° C. Alternatively, the variable resistor is formed as a film at a film forming temperature that allows the variable resistor to become of an amorphous state or a state where crystallinity and amorphism are mixed and, then, is subjected to an annealing process at a temperature higher than the film forming temperature, in a temperature range where the variable resistor can maintain the state where crystallinity and amorphism are mixed.

Abstract: A method of making a memory device and a memory device is described. In one embodiment, a method of manufacturing a memory device is described. The method includes providing a substrate having a tunneling layer deposited on a main surface and having a first conductive lines arranged on the tunneling layer running in a first direction. A layer of dielectric material is deposited on the first conductive lines. A control gate layer is deposited. The first conductive lines are patterned to produce gate stacks. Dielectric material is deposited in between the gate stacks. The gate stacks are partially removed to uncover floating gate electrodes in region of selection transistor lines to be prepared creating selection transistor line recesses running in the second direction. The selection transistor line recesses are filled with a conductive material to create the selection transistor lines.

Abstract: In the fabrication of integrated circuits, one specific technique for making surfaces flat is chemical-mechanical planarization. However, this technique is quite time consuming and expensive, particularly as applied to the numerous intermetal dielectric layers—the insulative layers sandwiched between layers of metal wiring—in integrated circuits. Accordingly, the inventor devised several methods for making nearly planar intermetal dielectric layers without the use of chemical-mechanical planarization and methods of modifying metal layout patterns to facilitate formation of dielectric layers with more uniform thickness. These methods of modifying metal layouts and making dielectric layers can be used in sequence to yield nearly planar intermetal dielectric layers with more uniform thickness.

Abstract: A thin film transistor device structure and a method for fabricating the thin film transistor device structure each comprise a thin film transistor device formed over a substrate. The thin film transistor device structure also comprises a passivation layer formed of a silicon rich silicon oxide material formed over the thin film transistor device. The passivation layer formed of the silicon rich silicon oxide material provides the thin film transistor device with enhanced performance.

Abstract: A method and apparatus for preventing plasma induced damage resulting from high density plasma deposition processes. In the present embodiment, Un-doped Silica Glass(USG) is deposited so as to form a USG liner. In the present embodiment, the USG liner directly overlies a conductive interconnect structure that couples to semiconductor devices that are susceptible to plasma-induced damage during high density plasma deposition processes. A silicon-rich oxide is deposited in-situ immediately following the deposition of the USG liner so as to form a silicon-rich oxide liner that directly overlies the USG liner. The silicon-rich oxide liner protects the interconnect structure during the subsequent high density plasma deposition process, preventing damage resulting from plasma charge to the interconnect structure.

Abstract: In an inverse-stagger MOSFET (1), a gate insulating layer (4) made of amorphous aluminum oxide is so formed as to face a channel layer (5) which serves as the semiconductor layer, and which is made of zinc oxide. With this arrangement, a defect level at an interface between the channel layer (5) and the gate insulating layer (4) is reduced, thereby obtaining performance equivalent to that of a semiconductor apparatus in which all the layered films are crystalline. This technique is applicable to a staggered MOSFET and the like, and has high versatility.

Abstract: A process for producing an integrated electronic circuit. The process begins with the production of a first electronic component and a second electronic component that are superposed on top of a substrate. A volume of temporary material is formed on the substrate at the position of the second electronic component. The first electronic component is then produced above the volume of temporary material relative to the substrate, and then the second electronic component is produced using at least one shaft for access to the temporary material. The first electronic component may be an active component and the second electronic component may be a passive component.

Abstract: The invention relates to a semiconductor component having a semiconductor body (100) and at least one pn junction present in the semiconductor body (100) and an amorphous passivation layer (70) arranged at least in sections on a surface (101) of the semiconductor body (100), the following holding true for the minimum Ds,min of an interface state density Ds at the junction between the passivation layer (70) and the semiconductor body (100): D s , min ? N S , Bd E g where NS,Bd is the breakdown charge and Eg is the band gap of the semiconductor material used for the semiconductor body (100).

Abstract: A thin film transistor array substrate of a thin film transistor liquid crystal display (TFT-LCD) is provided. The gate dielectric layer of the TFT includes a silicon nitride layer, a dielectric layer and a silicon nitride layer, and the etching selectivity of the amorphous silicon layer over the dielectric layer is not less than about 5.0. Therefore, the dielectric layer can be an etching stop layer when doped and undoped amorphous silicon layers are etched to form source/drain stacked layers or a conductive layer is etched to form a gate on the gate dielectric layer. Hence, the dielectric layer thickness can be controlled, and thereby the capacitance of the storage capacitor can be controlled.

Abstract: A method for producing an insulating or barrier layer (FIG. 1B), useful for semiconductor devices, comprises depositing a layer of silicon and at least one additional element on a silicon substrate whereby said deposited layer is substantially free of defects such that epitaxial silicon substantially free of defects can be deposited on said deposited layer. Alternatively, a monolayer of one or more elements, preferably comprising oxygen, is absorbed on a silicon substrate. A plurality of insulating layers sandwiched between epitaxial silicon forms a barrier composite. Semiconductor devices are disclosed which comprise said barrier composite.

Abstract: Structures are provided which improve performance in integrated circuits. The structures include a diffusion barrier and a seed layer in an integrated circuit both formed using a low energy ion implantation followed by a selective deposition of metal lines for the integrated circuit. The low energy ion implantation allows for the distinct placement of both the diffusion barrier and the seed layer. Structures are formed with a barrier/adhesion layer deposited in the number of trenches using a low energy ion implantation, e.g. a 100 to 800 electron volt (eV) ion implantation. A seed layer is deposited on the barrier/adhesion layer in the number of trenches also using the low energy ion implantation. Such structures include aluminum, copper, gold, and silver metal interconnects.

Abstract: Dielectric materials including elements of Si, C, O and H having specific values of mechanical properties (tensile stress, elastic modulus, hardness cohesive strength, crack velocity in water) that result in a stable ultra low k film which is not degraded by water vapor or integration processing are provided. The dielectric materials have a dielectric constant of about 2.8 or less, a tensile stress of less than 45 MPa, an elastic modulus from about 2 to about 15 GPa, and a hardness from about 0.2 to about 2 GPa. Electronic structures including the dielectric materials of the present invention as well as various methods of fabricating the dielectric materials are also provided.

Abstract: This invention provides a hetero-junction bipolar transistor with a new structure that prevent the corrector resistance from increasing as shrinking the size of the transistor. The bipolar transistor according to the invention comprises a substrate 2, a collector layer 6a, a base layer 10a and an emitter layer 12a. The collector layer 6a is formed on a first region of the substrate. The base layer 10a is formed on a second region of the substrate and has band gap energy smaller than that of the collector layer 6a and that of the emitter layer 12a. The plan shape of the first region is substantially same as that of the second region.

Abstract: The invention provides a process for forming a low k fluorine and carbon-containing silicon oxide dielectric material by reacting with an oxidizing agent one or more silanes containing one or more organofluoro silanes having the formula SiR1R2R3R4, where: (a) R1 is selected from H, a 3 to 10 carbon alkyl, and an alkoxy; (b) R2 contains at least one C atom bonded to at least one F atom, and no aliphatic C—H bonds; and (c) R3 and R4 are selected from H, alkyl, alkoxy, a moiety containing at least one C atom bonded to at least one F atom, and ((L)Si(R5)(R6))n(R7); where n ranges from 1 to 10; L is O or CFR8; each n R5 and R6 is selected from H, alkyl, alkoxy, and a moiety containing at least one C atom bonded to at least one F atom; R7 is selected from H, alkyl, alkoxy, and a moiety containing at least one C atom bonded to at least one F atom; and each R8 is selected from H, alkyl, alkoxy, and a moiety containing at least one C atom bonded to at least one F atom.

Abstract: A board for an electronic device is provide comprising a substrate having an amorphous layer, a buffer layer formed on the amorphous layer, the buffer layer having an orientation at least in the direction of its thickness, and a conductive oxide layer formed on the buffer layer by means of epitaxial growth, the conductive oxide layer having a metal oxide of a perovskite structure. The buffer layer contains at least one of the group consisting of a metal oxide of a NaCl structure and a metal oxide of a fluorite structure. Furthermore, the buffer layer 12 is formed by epitaxial growth in the cubic crystal (100) orientation.

Abstract: A method of providing even nucleation between silicon and oxide surfaces for growing uniformly thin silicon nitride layers used in semiconductor devices. First, a nonconductive nitride-nucleation enhancing monolayer is formed over a semiconductor assembly having both nitridation receptive and resistive materials. For purposes of the present invention, a nitride-nucleation enhancing monolayer is a material that will readily accept the bonding of nitrogen atoms to the material itself. Next, a silicon nitride layer is formed over the nonconductive nitride-nucleation enhancing monolayer. The nonconductive nitride-nucleation enhancing monolayer provides even nucleation over both the nitridation receptive material and the nitridation resistive material for silicon nitride, thereby allowing for the growth of a uniformly thin nitride layer.

Abstract: A pre-metal dielectric structure of a SONOS memory structure includes a UV light-absorbing film, which prevents the ONO structure from being electronically charged in response to UV irradiation. In one embodiment, the pre-metal dielectric structure includes a first pre-metal dielectric layer located over the SONOS memory structure, a light-absorbing structure located over the first pre-metal dielectric layer, and a second pre-metal dielectric layer located over the light-absorbing structure. The light-absorbing structure can be a continuous polysilicon or amorphous silicon layer. Alternately, the light-absorbing structure can include one or more patterned polysilicon layers. In another embodiment, the SONOS transistors include UV light absorbing polysilicon spacers.

Abstract: The termination of a MOSgated device is formed by a trench bevel which surrounds the active device area. The trench bevel has flat walls which extend into and through the epitaxial layer containing the active area which has a lateral extend equal to or less than the thickness of the epitaxial layer. The surface of the bevel is coated with a resistive film, preferably, an amorphous silicon which connects the device source to the device drain to cause the electric field in the epitaxial silicon to the linearly distributed over the length of the bevel.

Abstract: This invention provides a hetero-junction bipolar transistor (HBT) having a large base-collector breakdown voltage. The HBT has a collector, a base and an emitter. The emitter is made of a semiconductor material whose band gap energy is greater than that of the base. An passivation layer made of a semiconductor material cover the collector, the base and the emitter and the band gap energy of the passivation layer is greater than that of the collector and the base.

Abstract: In the fabrication of semiconductor devices such as active matrix displays, the need to pattern resist masks in photolithography increases the number of steps in the fabrication process and the time required to complete them and consequently represents a substantial cost. This invention provides a method for forming an impurity region in a semiconductor layer 303 by doping an impurity element into the semiconductor layer self-aligningly using as a mask the upper layer (a second conducting film 306) of a gate electrode formed in two layers. The impurity element is doped into the semiconductor layer through the lower layer of the gate electrode (a first conducting film 305), and through a gate insulating film 304. By this means, an LDD region 313 of a GOLD structure is formed in the semiconductor layer 303.

Abstract: A leadframe for use with integrated circuit chips comprising a base metal having a plated layer of nickel fully covering said base metal; a plated layer of pure tin on said nickel layer, selectively covering areas of said leadframe intended for attachment to other parts; and a plated layer of palladium on said nickel layer, selectively covering areas of said leadframe intended for bonding wire attachment.

Abstract: An improved method for producing a semiconductor device with a fluorine-doped silicon oxide interlayer insulating film. In one embodiment, the fluorine-doped silicon oxide layer (FSG layer) is formed in a process chamber. Thereafter, a silicon oxide layer is formed in the same process chamber over the FSG layer at a higher temperature than the FSG layer formation temperature. In another embodiment, after the FSG layer is formed, a surface layer of the FSG layer is selectively sputtered away before the silicon oxide layer is formed.

Abstract: A high-voltage diode and a method for producing the high-voltage diode involve only three masking steps. Only three masking steps are required due to the use of adjustment structures and of a chipping stopper with an edge passivation containing a-C:H or a-Si. In this manner, the high-voltage diode is inexpensive to manufacture. The diode has a rating for reverse voltages of, in particular, above about 400 V and preferably above about 500 V, and can be fabricated with the least possible process complexity and thus a small number of photo technologies and, in the edge region, can readily be equipped with a channel stopper for avoiding leakage currents and a chipping stopper for limiting the extent of saving defects.

Abstract: The present invention provides a semiconductor device comprising a single-crystal silicon substrate; and a single-crystal oxide thin film having a perovskite structure formed through epitaxial growth on the single-crystal silicon. substrate. The single-crystal oxide thin film is directly in contact with a surface of the single-crystal silicon substrate, and contains a bivalent metal that is reactive to silicon.

Abstract: According to one exemplary embodiment, a structure comprises a substrate. The structure further comprises at least one memory cell situated on the substrate. The at least one memory cell may be, for example, a flash memory cell, such as a SONOS flash memory cell. The structure further comprises an interlayer dielectric layer situated over the at least one memory cell and over the substrate. According to this exemplary embodiment, the structure further comprises a UV radiation blocking layer which comprises silicon-rich TCS nitride. Further, an oxide cap layer is situated over the UV radiation blocking layer. The structure might further comprise an antireflective coating layer over the oxide cap layer. The interlayer dielectric may comprise BPSG and the oxide cap layer may comprise TEOS oxide.

Abstract: A semiconductor package is provided. In one embodiment, the semiconductor package includes a lead frame having a die pad and a plurality of leads disposed around the die pad. One or more semiconductor integrated circuit chips are mounted on the die pad and electrically connected to the plurality of leads. The semiconductor further includes a molding part for encapsulating the lead frame and the one or more chips. The molding part includes an upper molding portion having a first width, and a lower molding portion having a second width smaller than the first width to expose a portion of said leads from the lower molding portion. With the semiconductor package of the present invention, the mounting area and the mounting height on a substrate can be reduced. Also, the mounting reliability of a package on a substrate and electrical characteristics of the package can be improved.

Abstract: Gate and storage dielectric systems and methods of their fabrication are presented. A passivated overlayer deposited between a layer of dielectric material and a gate or first storage plate maintains a high K (dielectric constant) value of the dielectric material. The high K dielectric material forms an improved interface with a substrate or second plate. This improves dielectric system reliability and uniformity and permits greater scalability, dielectric interface compatibility, structural stability, charge control, and stoichiometric reproducibility. Furthermore, etch selectivity, low leakage current, uniform dielectric breakdown, and improved high temperature chemical passivity also result.

Abstract: A method of manufacturing a semiconductor device is obtained which is capable of evading generation of a short circuit between wirings in an upper wiring layer even if a part of an upper surface of an FSG film is exposed by variations in a production step. After a USG film (4) is deposited to a thickness of 1 &mgr;m over an entire surface of an FSG film (3), the USG film (4) is polished and removed by a thickness of 900 nm from an upper surface thereof by the CMP method. At this time, a part of an upper surface of the FSG film (3) is exposed by variations in a production step. Next, the surface of the interlayer dielectric film (50) is cleaned with a cleaning liquid whose etching rate to the FSG film (3) and etching rate to the USG film (5) are substantially the same. Such a cleaning liquid may be, for example, an ammonia hydrogen peroxide mixture of NH4OH:H2O2:H2O=1:1:20. The structure shown in FIG.

Abstract: A power semiconductor component having a mesa edge termination is described. The component has a semiconductor body with first and second surfaces. An inner zone of a first conductivity type is disposed in the semiconductor body. A first zone is disposed in the semiconductor body and is connected to the inner zone. An edge area outside of the first zone has areas etched out. A second zone of a second conductivity type is disposed in the semiconductor body and is connected to the inner zone, and a boundary area between the second zone and the inner zone defines a pn junction. A field stop zone is adjacent the first surface in the edge area. The field stop zone is formed of the first conductivity type and is embedded in the semiconductor body, and the field stop zone is connected to the first zone and to the inner zone.

Abstract: An anti-reflection layer and method of manufacture. A silicon substrate has a conductive layer formed thereon. Plasma-enhanced chemical vapor deposition is performed to form a graded silicon oxynitride layer over the conductive layer. During silicon oxynitride deposition, concentration of one of the reactive gases nitrous oxide is gradually reduced so that the graded silicon oxynitride layer is oxygen-rich near bottom but nitrogen-rich near the top.

Abstract: An anti-reflection layer and method of manufacture. A silicon substrate has a conductive layer formed thereon. Plasma-enhanced chemical vapor deposition is performed to form a graded silicon oxynitride layer over the conductive layer. During silicon oxynitride deposition, concentration of one of the reactive gases nitrous oxide is gradually reduced so that the graded silicon oxynitride layer is oxygen-rich near bottom but nitrogen-rich near the top.

Abstract: The present invention is a dielectric film and its method of fabrication. The dielectric film of the present invention includes silicon oxygen fluorine and nitrogen wherein the interlayer dielectric comprises between 0.01-0.1 atomic percent nitrogen.

Abstract: An optical device having a high reflector tunable stress coating includes a micro-electromechanical system (MEMS) platform, a mirror disposed on the MEMS platform, and a multiple layer coating disposed on the mirror. The multiple layer coating includes a layer of silver (Ag), a layer of silicon dioxide (SiO2) deposited on the layer of Ag, a layer of intrinsic silicon (Si) deposited on the layer of SiO2, and a layer of silicon oxynitride (SiOxNy) deposited on the layer of Si. The concentration of nitrogen is increased and/or decreased to tune the stress (e.g., tensile, none, compressive).

Abstract: The performance of high-voltage devices is often influenced by charge-creep effects in the package. In order to avoid the resultant degradation, a bleeder may be used between the device and the package. However, it has been found in practice that the use of a high-resistive bleeder may lead to a certain instability of the device during operation. According to the invention, the bleeder (8) is provided with a plurality of conductive regions (12, 13) which are distributed in such a way that, when a high voltage is applied across the bleeder, a non-linear potential profile across the bleeder is obtained, which harmonizes with the ideal potential profile without the bleeder, instead of a linear profile which would have been obtained in the absence of said conductive regions due to charge-loading effects, and which would result in the above-mentioned instability effects.

Abstract: A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer.

Abstract: An interconnect structure having reduced fringing fields of bottom corners of said interconnect structure and a method of fabricating the same is provided. The interconnect structure includes one or more interconnect levels one on top of each other, wherein each interconnect level is separated by a diffusion barrier and includes a dielectric stack of at least one low-k interlayer dielectric on at least one hybrid dielectric, said dielectrics having planar interfaces therebetween, each interconnect level further comprising metallic lines formed in said low-k interlayer dielectric, with the proviso that bottom horizontal portions of said metallic lines are not coincident with said interface, and said metallic lines are contained within said low-k interlayer dielectric. The interconnect structures may be fabricated such that top horizontal portions of the metallic lines are coplanar with a top surface of the low-k interlayer dielectric.

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicone oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy, epitaxial growth of single crystal silicon onto single crystal oxide, and epitaxial growth of Zintl phase materials.

Abstract: A leadframe for use with integrated circuit chips, comprising a leadframe base made of aluminum or aluminum alloy having a surface layer of zinc; a first layer of nickel on said zinc layer, said first nickel layer deposited to be compatible with aluminum and zinc; a layer of an alloy of nickel and a noble metal on said first nickel layer; a second layer of nickel on said alloy layer, said second nickel layer deposited to be suitable for lead bending and solder attachment; and an outermost layer of noble metal, whereby said leadframe is suitable for solder attachment to other parts, for wire bonding, and for corrosion protection.

Abstract: In an aspect, an apparatus is provided that sets and reprograms the state of programmable devices. In an aspect, a method is provided such that an adhesive is formed on a dielectric and on an electrode, the adhesive is patterned exposing the electrode, and a programmable material is formed on the adhesive and on the electrode. In an aspect, a method is provided such that an adhesive is formed on a dielectric, an opening is formed through the dielectric exposing a contact formed on a substrate, and a programmable material is formed on the adhesive and on a portion of the contact. A conductor is formed on the programmable material and the contact transmits to a signal line.

Abstract: A dual-die packaging technology is proposed to pack two semiconductor chips in one single package module, so that one single package module is capable of offering a doubled level of functionality or data storage capacity. The proposed dual-die packaging technology is characterized in the use of a face-to-face stacked dual-die construction to pack two integrated circuit chips, such as flash memory chips, in one single package module. The first semiconductor die has its non-circuit surface attached to the front side of the die pad of the leadframe, while the second semiconductor die has its circuit surface attached by means of adhesive layer to the circuit surface of the first semiconductor die, thus forming a face-to-face stacked dual-die construction over the die pad of the leadframe, allowing one single package module to offer a doubled level of functionality or data storage capacity.

Abstract: Lateral bipolar transistor, in which a thin diffusion barrier (4) is applied to a base region (10) between an emitter region (9) and a collector region (11), and there is present, on said barrier, a base electrode (8) which is provided for low-resistance supply, is connected to a heavily doped base terminal region and consists of polysilicon, for example, into which dopant is diffused out from said base terminal region.

Abstract: An integrated circuit has a guard ring for shielding a first area 14 (eg. high voltage area) from a second area 15 (eg. low voltage). The guard ring comprises a conductive guard ring 6, (eg. metal), which is partially exposed through a passivation layer 13 in the integrated circuit 1. A semiconductor guard ring 8, (eg. silicon), is isolated from the first and second areas of semiconductor by at least two trench rings 16, one located on each side of the semiconductor guard ring 8. A plurality of conductive elements (comprising a metal connection plate 18 and via 19) connect the conductive guard ring 6 and the semiconductor guard ring 8 at spaced apart intervals. The conductive guard ring 6, semiconductor guard ring 8 and conductive elements are all connected to a ground source. If high energy particles move from the first area towards the second area, they are attracted to the exposed metal, and their charge is conducted to ground.

Abstract: High quality epitaxial layers of compound semiconductor materials can be grown overlying large silicon wafers by first growing an accommodating buffer layer on a silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline compound semiconductor layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer.

Abstract: A plurality of lower-level metal interconnects are formed over a semiconductor substrate. A first fluorine-containing insulating film, made of a fluorine-doped insulator, is formed to fill in gaps between adjacent ones of the lower-level metal interconnects over the semiconductor substrate. An interlevel insulating film is formed over the lower-level metal interconnects and the first fluorine-containing insulating film. And a plurality of upper-level metal interconnects are formed on the interlevel insulating film. The interlevel insulating film includes: a second fluorine-containing insulating film made of a fluorine-doped insulator; and a silicon-rich insulating film containing a larger quantity of silicon than a quantity defined by stoichiometry.

Abstract: The present invention includes integrated circuit devices, synchronous-link dynamic random access memory devices, methods of forming an integrated circuit device and methods of forming a synchronous-link dynamic random access memory edge-mounted device. According to one aspect of the present invention, an integrated circuit device includes a semiconductor die and a first housing encapsulating the semiconductor die. A heat sink is positioned proximate the first housing and a second housing is formed to encapsulate at least a portion of the heat sink. The heat sink is preferably thermally coupled with the semiconductor die and configured to expel heat therefrom. Another aspect provides a method of forming an integrated circuit device including the steps of providing a semiconductor die; forming a first housing about the semiconductor die; thermally coupling a heat sink with the first housing; and forming a second housing about at least a portion of the heat sink following the thermally coupling.

Abstract: A plurality of lower-level metal interconnects are formed over a semiconductor substrate. A first fluorine-containing insulating film, made of a fluorine-doped insulator, is formed to fill in gaps between adjacent ones of the lower-level metal interconnects over the semiconductor substrate. An interlevel insulating film is formed over the lower-level metal interconnects and the first fluorine-containing insulating film. And a plurality of upper-level metal interconnects are formed on the interlevel insulating film. The interlevel insulating film includes: a second fluorine-containing insulating film made of a fluorine-doped insulator; and a silicon-rich insulating film containing a larger quantity of silicon than a quantity defined by stoichiometry.

Abstract: A flash memory structure and fabrication process whereby stacks of a first poly-crystalline or of an amorphous silicon material (polysilicon), having a bottom layer member of an interpoly dielectric stack, are processed for formation of a post-treatment layer over the bottom interpoly dielectric layer member. The post-treatment layer is essentially a solid material formed by a chemical reaction for purposes of improving the reliability of an interpoly dielectric stack and results in changes to the capacitor coupling ratio of the flash memory element and allows the use of new power supply and programming voltages. The post-treatment layer is formed by exposing the polysilicon stacks with the bottom interpoly dielectric layer member to a selected one of at least three ambient reagent gases. The selected ambient reagent gases and exposure of the semiconductor structure being performed in either a batch furnace, a single wafer rapid thermal anneal tool, or a plasma chamber.

Abstract: A first HSQ film composed of a Si—O-based film with a low dielectric constant is formed on a first wiring via a protective insulation film, and the surface of this first HSQ film is reformed to form a first SRO layer. Then, a second HSQ film is formed on this first SRO layer, and the surface of the second HSQ film is reformed to form a second SRO layer. Next, a via-hole is formed within a predetermined region, which reaches the protective insulation film on the first wiring. Then, wiring trenches forming a second wiring are formed within predetermined regions of the second HSQ film and the second SRO film while using the first SRO film as an etching stopper film. Thereafter, the protective insulation film at the bottom of the via-hole is etched and removed, and the wiring trenches and the via-hole are embedded with a conductive film. Then, the conductive film on the second SRO layer is removed while using the second SRO layer as a CMP stopper film.