With Specified Shape Of Pn Junction Patents (Class 257/653)
  • Patent number: 11843039
    Abstract: A semiconductor device includes a gate stack including a gate insulating layer and a gate electrode on the gate insulating layer. The gate insulating layer includes a first dielectric layer and a second dielectric layer on the first dielectric layer, and a dielectric constant of the second dielectric layer is greater than a dielectric constant of the first dielectric layer. The semiconductor device also includes a first spacer on a side surface of the gate stack, and a second spacer on the first spacer, wherein the second spacer includes a protruding portion extending from a level lower than a lower surface of the first spacer towards the first dielectric layer, and a dielectric constant of the second spacer is greater than the dielectric constant of the first dielectric layer and less than a dielectric constant of the first spacer.
    Type: Grant
    Filed: December 2, 2022
    Date of Patent: December 12, 2023
    Inventors: Doosan Back, Dongoh Kim, Gyuhyun Kil, Jung-Hoon Han
  • Patent number: 11842665
    Abstract: The present disclosure provides a display panel and a display device. The display panel includes: a base substrate including a display area and a peripheral area surrounding the display area; a plurality of sub-pixels; a plurality of data signal lines; a plurality of data wires located in the peripheral area and electrically connected to the plurality of data signal lines; an electrostatic discharge circuit located in the peripheral area on the base substrate, and electrically connected to the plurality of data wires; and an encapsulation layer located on a side of the plurality of sub-pixels and the electrostatic discharge circuit away from the base substrate, wherein an orthographic projection of the electrostatic discharge circuit on the base substrate is located within an orthographic projection of the encapsulation layer on the base substrate.
    Type: Grant
    Filed: November 25, 2020
    Date of Patent: December 12, 2023
    Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Cong Liu, Hongjun Zhou, Lili Du, Feng Wei
  • Patent number: 11705448
    Abstract: A number of monolithic diode limiter semiconductor structures are described. The diode limiters can include a hybrid arrangement of diodes with different intrinsic regions, all formed over the same semiconductor substrate. In one example, a method of manufacture of a monolithic diode limiter includes providing an N-type semiconductor substrate, providing an intrinsic layer on the N-type semiconductor substrate, implanting a first P-type region to a first depth into the intrinsic layer, implanting a second P-type region to a second depth into the intrinsic layer, and forming at least one passive circuit element over the intrinsic layer. The method can also include forming an insulating layer on the intrinsic layer, forming a first opening in the insulating layer, and forming a second opening in the insulating layer. The method can also include implanting the first P-type region through the first opening and implanting the second P-type region through the second opening.
    Type: Grant
    Filed: July 13, 2021
    Date of Patent: July 18, 2023
    Assignee: MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC.
    Inventors: James Joseph Brogle, Joseph Gerard Bukowski, Margaret Mary Barter, Timothy Edward Boles
  • Patent number: 11211382
    Abstract: Apparatuses and methods are disclosed. One such apparatus includes a well having a first type of conductivity formed within a semiconductor structure having a second type of conductivity. A boundary of the well has an edge that is substantially beneath an edge of an active area of a tap to the well.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: December 28, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Michael Smith
  • Patent number: 11069868
    Abstract: The present invention relates to a semiconductor structure. The semiconductor structure comprises a semiconductor layer, at least one metallic carbon nanotube, and at least one graphene layer. The semiconductor layer defines a first surface and a second surface opposite to the first surface. The at least one metallic carbon nanotube is located on the first surface of the semiconductor layer. The at least one graphene layer is located on the second surface of the semiconductor layer. The at least one metallic carbon nanotube, the semiconductor layer and the at least one graphene layer are stacked with each other to form at least one three-layered stereoscopic structure. The present invention also relates a semiconductor device, and a photodetector.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: July 20, 2021
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Ke Zhang, Yang Wei, Shou-Shan Fan
  • Patent number: 11063144
    Abstract: A semiconductor component includes a SiC semiconductor body. A drift zone of a first conductivity type and a semiconductor region are formed in the SiC semiconductor body. Barrier structures extending from the semiconductor region into the drift zone differ from the gate structures.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: July 13, 2021
    Assignee: Infineon Technologies AG
    Inventors: Roland Rupp, Larissa Wehrhahn-Kilian, Bernd Zippelius
  • Patent number: 10553735
    Abstract: A light sensor includes an N-type semiconductor. The light sensor further includes a P-type semiconductor stacked on at least a portion of the N-type semiconductor, partially defining a trench extending into the P-type semiconductor, and having a trench portion aligned with the trench and extending farther into the N-type semiconductor than other portions of the P-type semiconductor. The light sensor also includes a passivation layer stacked on and contacting the P-type semiconductor and partially defining the trench that extends through the passivation layer and into the P-type semiconductor. The light sensor further includes an electrical contact stacked on the passivation layer, positioned within the trench, and extending through the passivation layer into the P-type semiconductor such that photons received by the N-type semiconductor generate photocurrent resulting in a voltage at the electrical contact.
    Type: Grant
    Filed: October 9, 2017
    Date of Patent: February 4, 2020
    Assignee: TELEDYNE SCIENTIFIC & IMAGING, LLC
    Inventor: Majid Zandian
  • Patent number: 10197439
    Abstract: An optoelectronic sensor for recognizing objects or object properties comprises a light transmitter for transmitting transmitted light into a detection zone, a light receiver for receiving received light and an evaluation unit which is configured to detect an object located in or projecting into a detection zone and/or to determine a property of such an object with reference to the received light received by the light receiver. The light transmitter comprises a monolithic semi-conductor component having a first light emitting layer and a second light emitting layer, with the first light emitting layer being configured for emitting red light and the second light emitting layer being configured for emitting infrared light, and with the second light emitting layer defining a central light emitting surface and the first light emitting layer defining an outer light emitting surface surrounding the central light emitting surface.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: February 5, 2019
    Assignee: SICK AG
    Inventors: Ingolf Horsch, Gerhard Merettig, Roland Bergbach, Felix Lang, Gunter Leuker
  • Patent number: 10109718
    Abstract: A semiconductor component and a method for manufacturing the semiconductor component, wherein the semiconductor component includes a transient voltage suppression structure that includes at least two diodes and a Zener diode. In accordance with embodiments, a semiconductor material is provided that includes an epitaxial layer. The at least two diodes and the Zener diode are created at the surface of the epitaxial layer, where the at least two diodes may be adjacent to the Zener diode.
    Type: Grant
    Filed: May 1, 2014
    Date of Patent: October 23, 2018
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Umesh Sharma, Harry Yue Gee, Der Min Liou, David D Marreiro, Sudhama C Shastri
  • Patent number: 10020190
    Abstract: The present disclosure relates to a nano-heterostructure. The nano-heterostructure includes a semiconductor layer, a first metallic carbon nanotube, a semiconducting carbon nanotube and a second metallic carbon nanotube. The semiconductor layer comprises a first surface and a second surface. The first metallic carbon nanotube is located on the first surface and extends in a first direction. The semiconducting carbon nanotube is located on the first surface and extends in the first direction. The semiconducting carbon nanotube is parallel and spaced away from the first metallic carbon nanotube. The second metallic carbon nanotube is located on the second surface and extends in a second direction. An angle forms between the first direction and the second direction.
    Type: Grant
    Filed: April 14, 2017
    Date of Patent: July 10, 2018
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Jin Zhang, Yang Wei, Kai-Li Jiang, Shou-Shan Fan
  • Patent number: 9873824
    Abstract: A polishing material including polishing abrasive grains, the polishing abrasive grain having a core material that includes a metal oxide, and a cover layer that is provided on a surface of the core material and includes an oxide of a metal, that is different from the core material, or an oxide of a semimetal. When the polishing abrasive grains are observed with a scanning electron microscope after boiling a slurry including the polishing abrasive grains for 5 hours, a ratio of a longitudinal axis to a lateral axis of the polishing abrasive grain is 1.0 or greater and less than 1.5. The polishing abrasive grain preferably has a mass ratio of the cover layer to the core material, cover layer/core material, of from 0.3 mass % to 30 mass % inclusive. The cover layer preferably has a thickness of from 0.2 nm to 500 nm inclusive.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: January 23, 2018
    Assignee: MITSUI MINING & SMELTING CO., LTD.
    Inventors: Sumikazu Ogata, Shigeki Tokuchi, Yohei Maruyama, Motomi Oshika
  • Patent number: 9293553
    Abstract: A laminated graphene device is demonstrated as a cathode. In one example the devices include organic photovoltaic devices. The measured properties demonstrate work-function matching via contact doping. Devices and method shown also provide increased power conversion efficiency due to transparency. These findings indicate that flexible, light-weight all carbon devices, such as solar cells, can be constructed using graphene as the cathode material.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: March 22, 2016
    Assignee: The Trustees of Columbia University in the City of New York
    Inventors: Marshall Cox, Ioannis Kymissis, Alon Gorodetsky, Melinda Y. Han, Colin P. Nuckolls, Philip Kim
  • Patent number: 9006863
    Abstract: A diode string voltage adapter includes diodes formed in a substrate of a first conductive type. Each diode includes a deep well region of a second conductive type formed in the substrate. A first well region of the first conductive type formed on the deep well region. A first heavily doped region of the first conductive type formed on the first well region. A second heavily doped region of the second conductive type formed on the first well region. The diodes are serially coupled to each other. A first heavily doped region of a beginning diode is coupled to a first voltage. A second heavily doped region of each diode is coupled to a first heavily doped region of a next diode. A second heavily doped region of an ending diode provides a second voltage. The deep well region is configured to be electrically floated.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: April 14, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Peng Hsieh, Jaw-Juinn Horng
  • Patent number: 9000481
    Abstract: A low capacitance transient voltage suppressor with reduced clamping voltage includes an n+ type substrate, a first epitaxial layer on the substrate, a buried layer formed within the first epitaxial layer, a second epitaxial layer on the first epitaxial layer, and an implant layer formed within the first epitaxial layer below the buried layer. The implant layer extends beyond the buried layer. A first trench is at an edge of the buried layer and an edge of the implant layer. A second trench is at another edge of the buried layer and extends into the implant layer. Each trench is lined with a dielectric layer. A set of source regions is formed within a top surface of the second epitaxial layer. The trenches and source regions alternate. A pair of implant regions is formed in the second epitaxial layer.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: April 7, 2015
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Lingpeng Guan, Madhur Bobde, Anup Bhalla, Jun Hu, Wayne F. Eng
  • Patent number: 9000479
    Abstract: According to one embodiment, a semiconductor device includes a base layer, a second conductivity type semiconductor layer, a first insulating film, and a first electrode. The first insulating film is provided on an inner wall of a plurality of first trenches extending from a surface of the second conductivity type semiconductor layer toward the base layer side, but not reaching the base layer. The first electrode is provided in the first trench via the first insulating film, and provided in contact with a surface of the second conductivity type semiconductor layer. The second conductivity type semiconductor layer includes a first second conductivity type region, and a second second conductivity type region. The first second conductivity type region is provided between the first trenches. The second second conductivity type region is provided between the first second conductivity type region and the base layer, and between a bottom part of the first trench and the base layer.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: April 7, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Mitsuhiko Kitagawa
  • Patent number: 8981347
    Abstract: A method of forming a memory cell is provided. The method includes forming a steering element pillar having a first stiffness and a sidewall, forming a sidewall collar along at least a portion of the sidewall of the steering element pillar, the sidewall collar having a second stiffness, wherein the second stiffness is greater than the first stiffness, and forming a memory element coupled to the steering element pillar. Numerous other aspects are provided.
    Type: Grant
    Filed: February 17, 2014
    Date of Patent: March 17, 2015
    Assignee: SanDisk 3D LLC
    Inventor: Scott Brad Herner
  • Patent number: 8963296
    Abstract: A high power density or low forward voltage rectifier which utilizes at least one trench in both the anode and cathode. The trenches are formed in opposing surfaces of the substrate, to increase the junction surface area per unit surface area of the semiconductor die. This structure allows for increased current loads without increased horizontal die space. The increased current handling capability allows for the rectifier to operate at lower forward voltages. Furthermore, the present structure provides for increased substrate usage by up to 30 percent.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: February 24, 2015
    Assignee: Vishay General Semiconductor, LLC
    Inventors: Hung-Ping Tsai, Shih-Kuan Chen, Lung-Ching Kao
  • Patent number: 8896084
    Abstract: A semiconductor device includes a first semiconductor region of a first conductivity type and formed of a material having a band gap wider than that of silicon; a first layer selectively disposed on a surface of and forming a first junction with the first semiconductor region; a second layer selectively disposed on the first semiconductor region and forming a second junction with the first semiconductor region; a first diode formed by a region including the first junction; a second diode formed by a region including the second junction; and a fourth semiconductor region of a second conductivity type and disposed in the first semiconductor region, between and contacting the first and second junctions. A recess and elevated portion are disposed on the first semiconductor region. The first and the second junctions are formed at different depths. The second diode has a lower built-in potential than the first diode.
    Type: Grant
    Filed: February 23, 2011
    Date of Patent: November 25, 2014
    Assignees: Fuji Electric Co., Ltd.
    Inventor: Yoshitaka Sugawara
  • Publication number: 20140327118
    Abstract: A method of fabricating a power semiconductor device includes the following steps. Firstly, a substrate is provided. A first epitaxial layer is formed over the substrate. A first trench is formed in the first epitaxial layer. A second epitaxial layer is refilled into the first trench. The first epitaxial layer and the second epitaxial layer are collaboratively defined as a first semiconductor layer. A third epitaxial layer is formed over the substrate, and a second trench is formed in the third epitaxial layer. A first doping region is formed in a sidewall of the second trench. An insulation layer is refilled into the second trench. The insulation layer, the first doping region and the third epitaxial layer are collaboratively defined as a second semiconductor layer. The power semiconductor device fabricated by the fabricating method can withstand high voltage and has low on-resistance.
    Type: Application
    Filed: August 14, 2013
    Publication date: November 6, 2014
    Applicant: MOSEL VITELIC INC.
    Inventors: Chien-Ping Chang, Chien-Chung Chu
  • Patent number: 8836090
    Abstract: A power device (such as a power diode) has a peripheral die area and a central area. The main PN junction of the device is formed by a P+ type region that extends down into an N? type layer. The central portion of the P+ type region has a plurality of openings so mesa structures of the underlying N? type material extend up to the semiconductor surface through the openings. Due to the mesa structures being located in the central portion of the die, there are vertically extending extensions of the PN junction in the central portion of the die. Minority carrier charge storage is more uniform per unit area across the surface of the die. Due to the form of the P+ type region and the mesa structures, the reverse recovery of the PN junction exhibits a soft characteristic.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: September 16, 2014
    Assignee: IXYS Corporation
    Inventor: Subhas Chandra Bose Jayappa Veeramma
  • Publication number: 20140246761
    Abstract: A power device (such as a power diode) has a peripheral die area and a central area. The main PN junction of the device is formed by a P+ type region that extends down into an N? type layer. The central portion of the P+ type region has a plurality of openings so mesa structures of the underlying N? type material extend up to the semiconductor surface through the openings. Due to the mesa structures being located in the central portion of the die, there are vertically extending extensions of the PN junction in the central portion of the die. Minority carrier charge storage is more uniform per unit area across the surface of the die. Due to the form of the P+ type region and the mesa structures, the reverse recovery of the PN junction exhibits a soft characteristic.
    Type: Application
    Filed: March 1, 2013
    Publication date: September 4, 2014
    Applicant: IXYS Corporation
    Inventor: Subhas Chandra Bose Jayappa Veeramma
  • Publication number: 20140246762
    Abstract: Semiconductor devices and methods of fabricating the same are provided. An insulating film can be disposed on a semiconductor substrate, and insulating film patterns can be formed opening a plurality of areas with predetermined widths by patterning the insulating film. A plurality of ion implantation areas having a first conductivity type can be formed by implanting impurities into the plurality of open areas, and an oxide film pattern can be formed on each of the ion implantation areas. The insulating film patterns can be removed, and ion implantation areas having a second conductivity type can be formed by implanting impurities using the oxide film pattern as a mask. The semiconductor substrate can be annealed at a high temperature to form deep wells.
    Type: Application
    Filed: March 12, 2013
    Publication date: September 4, 2014
    Applicant: DONGBU HITEK CO., LTD.
    Inventor: Kyung Wook KWON
  • Patent number: 8810010
    Abstract: An exemplary semiconductor device comprises a through silicon via penetrating a semiconductor substrate including a circuit pattern on one side of the substrate, a first doped layer formed in the other side, and a bump connected with the through silicon via.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: August 19, 2014
    Assignee: SK Hynix Inc.
    Inventor: Jae Bum Kim
  • Patent number: 8796806
    Abstract: A diode and memory device including the diode, where the diode includes a conductive portion and another portion formed of a first material that has characteristics allowing a first decrease in a resistivity of the material upon application of a voltage to the material, thereby allowing current to flow there through, and has further characteristics allowing a second decrease in the resistivity of the first material in response to an increase in temperature of the first material.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: August 5, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej Sandhu, Bhaskar Srinivasan
  • Patent number: 8794501
    Abstract: A micro light emitting diode (LED) and a method of forming an array of micro LEDs for transfer to a receiving substrate are described. The micro LED structure may include a micro p-n diode and a metallization layer, with the metallization layer between the micro p-n diode and a bonding layer. A conformal dielectric barrier layer may span sidewalls of the micro p-n diode. The micro LED structure and micro LED array may be picked up and transferred to a receiving substrate.
    Type: Grant
    Filed: February 13, 2012
    Date of Patent: August 5, 2014
    Assignee: LuxVue Technology Corporation
    Inventors: Andreas Bibl, John A. Higginson, Hung-Fai Stephen Law, Hsin-Hua Hu
  • Patent number: 8729667
    Abstract: According to one embodiment, a second electrode layer is formed on first structures where a first electrode layer and a first memory cell layer sequentially stacked above a substrate are patterned in a line-and-space shape extending in a first direction and a first interlayer insulating film embedded between the first structures. Etching is performed from the second electrode layer to a predetermined position in an inner portion of the first memory cell layer by using a first mask layer having a line-and-space pattern extending in a second direction, so that a first trench is formed. A first modifying film is formed on a side surface of the first trench, anisotropic etching is performed on the first memory cell layer by using the first mask layer, and after that, isotropic etching is performed.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: May 20, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takuji Kuniya
  • Publication number: 20140124903
    Abstract: Structures and methods are provided for nanosecond electrical pulse anneal processes. The method of forming an electrostatic discharge (ESD) N+/P+ structure includes forming an N+ diffusion on a substrate and a P+ diffusion on the substrate. The P+ diffusion is in electrical contact with the N+ diffusion. The method further includes forming a device between the N+ diffusion and the P+ diffusion. A method of annealing a structure or material includes applying an electrical pulse across an electrostatic discharge (ESD) N+/P+ structure for a plurality of nanoseconds.
    Type: Application
    Filed: January 14, 2014
    Publication date: May 8, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michel J. ABOU-KHALIL, Robert J. GAUTHIER, JR., Tom C. LEE, Junjun LI, Souvick MITRA, Christopher S. PUTNAM, Robert R. ROBISON
  • Patent number: 8710633
    Abstract: The present invention discloses a semiconductor overlapped PN structure and manufacturing method thereof. The method includes: providing a substrate; providing a first mask to define a P (or N) type well and at least one overlapped region in the substrate; implanting P (or N) type impurities into the P (or N) type well and the at least one overlapped region; providing a second mask having at least one opening to define an N (or P) type well in the substrate, and to define at least one dual-implanted region in the at least one overlapped region; implanting N (or P) type impurities into the N (or P) type well and the at least one dual-implanted region such that the at least one dual-implanted region has P type and N type impurities.
    Type: Grant
    Filed: April 16, 2013
    Date of Patent: April 29, 2014
    Assignee: Richtek Technology Corporation
    Inventors: Tsung-Yi Huang, Chien-Hao Huang, Ying-Shiou Lin
  • Patent number: 8710542
    Abstract: A semiconductor device includes a base layer, a second conductivity type semiconductor layer, a first insulating film, and a first electrode. The first insulating film is provided on an inner wall of a plurality of first trenches extending from a surface of the second conductivity type semiconductor layer toward the base layer side, but not reaching the base layer. The first electrode is provided in the first trench via the first insulating film, and provided in contact with a surface of the second conductivity type semiconductor layer. The second conductivity type semiconductor layer includes first and second regions. The first region is provided between the first trenches. The second region is provided between the first second conductivity type region and the base layer, and between a bottom part of the first trench and the base layer. The second region has less second conductivity type impurities than the first region.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: April 29, 2014
    Assignee: Kabushiki Kaisha Tosiba
    Inventor: Mitsuhiko Kitagawa
  • Patent number: 8698196
    Abstract: A low capacitance transient voltage suppressor with reduced clamping voltage includes an n+ type substrate, a first epitaxial layer on the substrate, a buried layer formed within the first epitaxial layer, a second epitaxial layer on the first epitaxial layer, and an implant layer formed within the first epitaxial layer below the buried layer. The implant layer extends beyond the buried layer. A first trench is at an edge of the buried layer and an edge of the implant layer. A second trench is at another edge of the buried layer and extends into the implant layer. A third trench is at another edge of the implant layer. Each trench is lined with a dielectric layer. A set of source regions is formed within a top surface of the second epitaxial layer. The trenches and source regions alternate. A pair of implant regions is formed in the second epitaxial layer.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: April 15, 2014
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Lingpeng Guan, Madhur Bobde, Anup Bhalla, Jun Hu, Wayne F. Eng
  • Publication number: 20140061874
    Abstract: An exemplary semiconductor device comprises a through silicon via penetrating a semiconductor substrate including a circuit pattern on one side of the substrate, a first doped layer formed in the other side, and a bump connected with the through silicon via.
    Type: Application
    Filed: December 18, 2012
    Publication date: March 6, 2014
    Applicant: SK hynix Inc.
    Inventor: Jae Bum KIM
  • Patent number: 8653593
    Abstract: A semiconductor device includes a semiconductor layer provided with a gate trench, a first conductivity type source region exposed on a surface side of the semiconductor layer, a second conductivity type channel region formed on a side of the source region closer to aback surface of the semiconductor layer to be in contact with the source region, a first conductivity type drain region formed on a side of the channel region to be in contact with the channel region, a gate insulating film formed on an inner surface of the gate trench, and agate electrode embedded inside the gate insulating film in the gate trench, while the channel region includes a channel portion formed along the side surface of the gate trench and a projection projecting from an end portion of the channel portion closer to the back surface of the semiconductor layer toward the back surface.
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: February 18, 2014
    Assignee: Rohm Co., Ltd.
    Inventor: Kengo Omori
  • Patent number: 8643152
    Abstract: A high power density or low forward voltage rectifier which utilizes at least one trench in both the anode and cathode. The trenches are formed in opposing surfaces of the substrate, to increase the junction surface area per unit surface area of the semiconductor die. This structure allows for increased current loads without increased horizontal die space. The increased current handling capability allows for the rectifier to operate at lower forward voltages. Furthermore, the present structure provides for increased substrate usage by up to 30 percent.
    Type: Grant
    Filed: February 27, 2012
    Date of Patent: February 4, 2014
    Assignee: Vishay General Semiconductor, LLC
    Inventors: Hung-Ping Tsai, Shih-Kuan Chen, Lung-Ching Kao
  • Patent number: 8633560
    Abstract: A semiconductor device capable of decreasing a reverse leakage current and a forward voltage is provided. In the semiconductor device, an anode electrode undergoes Schottky junction by being connected to a surface of an SiC epitaxial layer that has the surface, a back surface, and trapezoidal trenches formed on the side of the surface each having side walls and a bottom wall. Furthermore, an edge portion of the bottom wall of each of the trapezoidal trenches is formed to be in the shape bent towards the outside of the trapezoidal trench in the manner that a radius of curvature R satisfies 0.01<L<R<10 L (1) (in the expression (1), L represents the straight-line distance between the edge portions opposite to each other in a width direction of the trench).
    Type: Grant
    Filed: April 6, 2012
    Date of Patent: January 21, 2014
    Assignee: Rohm Co., Ltd.
    Inventor: Masatoshi Aketa
  • Publication number: 20130328120
    Abstract: A device comprises a substrate, an n-layer and a p-layer, an n-electrode, and a p-electrode. A step is formed at an outer circumference of the device. A protective film is formed so as to continuously cover a side surface and a bottom surface of the step. A field plate electrode connected with the p-electrode is formed on the protective film. When a distance from the pn junction interface to the surface of the protective film on the bottom surface of the step is defined as h (?m), a dielectric constant of the protective film is defined as ?s, and a thickness of the protective film at the pn junction interface on the side surface of the step is defined as d (?m), (?s·h)/d is 4 or more, and ?s/d is 3 (1/?m) or more.
    Type: Application
    Filed: June 7, 2013
    Publication date: December 12, 2013
    Applicant: TOYODA GOSEI CO., LTD.
    Inventors: Yukihisa UENO, Toru OKA
  • Patent number: 8581365
    Abstract: The present technology discloses a bipolar junction transistor (BJT) device integrated into a semiconductor substrate. The BJT device comprises a collector, a base and an emitter. The collector is of a first doping type on the substrate; the base is of a second doping type in the collector from the top surface of the semiconductor device and the base has a base depth; and the emitter is of a first doping type in the base from the top surface of the semiconductor device. The base depth is controlled by adjusting a layout width in forming the base.
    Type: Grant
    Filed: April 22, 2011
    Date of Patent: November 12, 2013
    Assignee: Monolithic Power Systems, Inc.
    Inventor: Jeesung Jung
  • Patent number: 8501598
    Abstract: A semiconductor substrate which allows desired electrical characteristics to be more easily acquired, a semiconductor device of the same, and a method of producing the semiconductor substrate. The method of producing this semiconductor substrate is provided with: a first epitaxial layer forming step (S1) of forming a first epitaxial layer; a trench forming step (S2) of forming trenches in the first epitaxial layer; and epitaxial layer forming steps (S3, S4, S5) of forming epitaxial layers on the first epitaxial layer and inside the trenches, using a plurality of growth conditions including differing growth rates, so as to fill the trenches, and keeping the concentration of dopant taken into the epitaxial layers constant in the plurality of growth conditions.
    Type: Grant
    Filed: March 25, 2010
    Date of Patent: August 6, 2013
    Assignees: Sumco Corporation, Denso Corporation
    Inventors: Syouji Nogami, Hitoshi Goto, Takumi Shibata, Tsuyoshi Yamamoto
  • Patent number: 8486798
    Abstract: A replaceable chamber element for use in a plasma processing system, such as a plasma etching system, is described. The replaceable chamber element includes a chamber component configured to be exposed to plasma in a plasma processing system, wherein the chamber component is fabricated to include a semiconductor junction, and wherein a capacitance of the chamber component is varied when a voltage is applied across the semiconductor junction.
    Type: Grant
    Filed: February 5, 2012
    Date of Patent: July 16, 2013
    Assignee: Tokyo Electron Limited
    Inventors: Zhiying Chen, Jianping Zhao, Lee Chen, Merritt Funk, Radha Sundararajan
  • Patent number: 8373255
    Abstract: A diode comprises a P-type well formed in a semiconductor substrate, at least one N-type impurity doping area formed in the P-type well, an isolation area formed to surround the N-type impurity doping area, a P-type impurity doping area formed to surround the isolation area, first contacts formed in the N-type impurity doping area in a single row or a plurality of rows, and second contacts formed in the P-type impurity doping area in a single row or a plurality of rows, wherein pin resistance can be adjusted through changing any one of a distance between the N-type impurity doping area and the P-type impurity doping area, a contact pitch between the first contacts, and a contact pitch between the second contacts.
    Type: Grant
    Filed: August 3, 2012
    Date of Patent: February 12, 2013
    Assignee: SK Hynix Inc.
    Inventor: Kook Whee Kwak
  • Patent number: 8368145
    Abstract: A semiconductor device has a structure including the first semiconductor region 103 which is provided in the first terminal portion 100 and includes the first n-type impurity region 106, the first resistance region 107 provided at an inner periphery portion of the first n-type impurity region 106 in a plane view, and the first p-type impurity region 108 provided at an inner periphery portion of the first resistance region 107 in the plane view, and the second semiconductor region 104 which is provided in the second terminal portion 101 and includes the second p-type impurity region 109, the second resistance region 110 provided at an inner periphery portion of the second p-type impurity region 109 in the plane view, and the second n-type impurity region 111 provided at an inner periphery portion of the second resistance region 110 in the plane view.
    Type: Grant
    Filed: June 5, 2009
    Date of Patent: February 5, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Osamu Fukuoka, Masahiko Hayakawa, Hideaki Shishido
  • Publication number: 20130009125
    Abstract: A semiconductor device includes an insulation layer including a cell contact hole, and a switching device in the cell contact hole, at least a part of a top surface of the switching device being inclined with respect to an axial direction of the cell contact hole.
    Type: Application
    Filed: June 26, 2012
    Publication date: January 10, 2013
    Inventors: Jong-hyun PARK, Jae-hee Oh, Kyu-sul Park
  • Patent number: 8350366
    Abstract: A power semiconductor component having a pn junction, a body with a first basic conductivity, a well-like region with a second conductivity which is arranged horizontally centrally in the body, has a first two-level doping profile and has a first penetration depth from the first main surface into the body. In addition, this power semiconductor component has an edge structure which is arranged between the well-like region and the edge of the power semiconductor component and which comprises a plurality of field rings with a single-level doping profile, a second conductivity and a second penetration depth, wherein the first penetration depth is no more than about 50% of the second penetration depth.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: January 8, 2013
    Assignee: Semikron Elektronik GmbH & Co., KG
    Inventor: Bernhard Koenig
  • Publication number: 20120313212
    Abstract: A semiconductor device includes a first semiconductor region of a first conductivity type and formed of a material having a band gap wider than that of silicon; a first layer selectively disposed on a surface of and forming a first junction with the first semiconductor region; a second layer selectively disposed on the first semiconductor region and forming a second junction with the first semiconductor region; a first diode formed by a region including the first junction; a second diode formed by a region including the second junction; and a fourth semiconductor region of a second conductivity type and disposed in the first semiconductor region, between and contacting the first and second junctions. A recess and elevated portion are disposed on the first semiconductor region. The first and the second junctions are formed at different depths. The second diode has a lower built-in potential than the first diode.
    Type: Application
    Filed: February 23, 2011
    Publication date: December 13, 2012
    Applicants: FUJI ELECTRIC CO., LTD.
    Inventor: Yoshitaka Sugawara
  • Patent number: 8309958
    Abstract: According to one embodiment, a semiconductor memory device includes a word line interconnection layer, a bit line interconnection layer and a pillar. The word line interconnection layer includes a plurality of word lines which extend in a first direction. The bit line interconnection layer includes a plurality of bit lines which extend in a second direction crossing over the first direction. The pillar is arranged between each of the word lines and each of the bit lines. The pillar includes a silicon diode and a variable resistance film, and the silicon diode includes a p-type portion and an n-type portion. The word line interconnection layer and the bit line interconnection layer are alternately stacked, and a compressive force is applied to the silicon diode in a direction in which the p-type portion and the n-type portion become closer to each other.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: November 13, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Jun Hirota, Yoko Iwakaji, Moto Yabuki
  • Publication number: 20120261804
    Abstract: A diode structure, formed under a buried dielectric layer of a silicon on insulator (SOI), method of manufacturing the same and design structure thereof are provided. In an embodiment the p-n junction of the diode structure can be advantageously arranged in a vertical orientation. The cathode comprises an N+ epitaxial layer formed upon a P-type substrate. The anode comprises an active region of the P-substrate. Contacts to the cathode and anode are formed through the buried dielectric layer. Contact to the anode is accomplished via a deep trench filled with a conductive plug. The deep trench also provides electrical isolation for the cathode (as well as p-n junction). Advantageously, embodiments of the present invention may be formed during formation of other structures which also include trenches (for example, deep trench capacitors) in order to reduce process steps required to form the diode structure under the buried dielectric layer of the SOI substrate.
    Type: Application
    Filed: April 15, 2011
    Publication date: October 18, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Junjun Li, Zhengwen Li, Chengwen Pei, Jian Yu
  • Publication number: 20120248584
    Abstract: A nano/micro-sized diode and a method of preparing the same, the diode including: a first electrode; a second electrode; and a diode layer that is disposed between the first electrode and the second electrode. The diode layer includes a first layer and a second layer. The first layer is disposed on the first electrode and has a first surface that is electrically connected to the first electrode, and an opposing second surface that has a protrusion. The second layer is disposed between the first layer and the second electrode and has a first surface having a recess that corresponds to the protrusion, and an opposing second surface that is electrically connected to the second electrode.
    Type: Application
    Filed: June 6, 2012
    Publication date: October 4, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jinhwan PARK, Sungho PARK
  • Patent number: 8278728
    Abstract: An octagonal structure of photodiodes using standard CMOS technology has been developed to serve as a de-multiplexer for spatially multiplexed fiber optic communication systems.
    Type: Grant
    Filed: October 17, 2009
    Date of Patent: October 2, 2012
    Assignee: Florida Institute of Technology
    Inventor: Syed Murshid
  • Publication number: 20120223421
    Abstract: A high power density or low forward voltage rectifier which utilizes at least one trench in both the anode and cathode. The trenches are formed in opposing surfaces of the substrate, to increase the junction surface area per unit surface area of the semiconductor die. This structure allows for increased current loads without increased horizontal die space. The increased current handling capability allows for the rectifier to operate at lower forward voltages. Furthermore, the present structure provides for increased substrate usage by up to 30 percent.
    Type: Application
    Filed: February 27, 2012
    Publication date: September 6, 2012
    Applicant: VISHAY GENERAL SEMICONDUCTOR, LLC
    Inventors: Hung-Ping Tsai, Shih-Kuan Chen, Lung-Ching Kao
  • Patent number: 8253223
    Abstract: A diode comprises a P-type well formed in a semiconductor substrate, at least one N-type impurity doping area formed in the P-type well, an isolation area formed to surround the N-type impurity doping area, a P-type impurity doping area formed to surround the isolation area, first contacts formed in the N-type impurity doping area in a single row or a plurality of rows, and second contacts formed in the P-type impurity doping area in a single row or a plurality of rows, wherein pin resistance can be adjusted through changing any one of a distance between the N-type impurity doping area and the P-type impurity doping area, a contact pitch between the first contacts, and a contact pitch between the second contacts.
    Type: Grant
    Filed: January 27, 2012
    Date of Patent: August 28, 2012
    Assignee: SK hynix Inc.
    Inventor: Kook Whee Kwak
  • Publication number: 20120133031
    Abstract: Consistent with an example embodiment, there is a semiconductor device with nanowire-type interconnect elements. The semiconductor device comprises a semiconductor substrate with a pn junction formed by a first doped substrate region of a first conductivity type, and a second doped substrate region of an opposite second conductivity type. There is a layer structure on the semiconductor substrate, the layer structure includes a first metal structure which is conductively connected with the first doped substrate region, and further comprising a second metal structure, which is conductively connected with the second doped substrate region. The layer structure allows the transmission of photons with an energy suitable for creating free charge carriers in the first and second doped substrate regions. A third metal structure comprising at least one self-assembled metal dendrite forms an interconnect element between the first and second metal structures.
    Type: Application
    Filed: November 30, 2011
    Publication date: May 31, 2012
    Applicant: NXP B.V.
    Inventors: Kevin COOPER, Srdjan KORDIC