Abstract: A circuit utilizable for protecting an integrated circuit feature from electrostatic discharge is disclosed. A first bipolar transistor has its emitter connected to the IC feature and its collector connected to ground. A second bipolar transistor has its emitter connected to the IC feature and its collector connected to its base and to the base of the first bipolar transistor. A field effect transistor has its gate and drain connected to the IC feature and its body connected to its source and to the collector and base of the second bipolar transistor and to the base of the first bipolar transistor. A diode has its cathode connected to the body and the source of the field effect transistor and to the collector and base of the second bipolar transistor and to the base of the first bipolar transistor.

Abstract: A bidirectional two-terminal ungated thyristor (9) having two wide-base portions (25, 27). The bidirectional two-terminal ungated thyristor (9) has a first semiconductor device having a first narrow-base portion (28) in series with a first wide-base portion (25), and a second semiconductor device having a second narrow-base portion (26) in series with a second wide-base portion (27). A width of the first wide base portion (25) and a width of the second wide base portion (27) are decreased to decrease a total base width. The first and second wide-base portions (25, 27) having a decreased width produce a low forward voltage drop across the bidirectional two-terminal ungated thyristor (9); thus, improving a power dissipation capability of the bidirectional two-terminal ungated thyristor (9).

Abstract: According to this present invention, a semiconductor device includes source and drain diffusion layers, and a gate electrode formed on a substrate between the source diffusion layer and the drain diffusion layer. In addition, antioxidant films are respectively formed on the source diffusion layer and the drain diffusion layer. These antioxidant films are used for controlling a diffusion rate of an impurity contained in the source diffusion layer and the drain diffusion layer.

Abstract: A p.sup.- semiconductor substrate has a surface which is high in a memory cell region and low in a peripheral circuit region. An n.sup.+ buried semiconductor layer of uniform thickness is formed on the substrate. An n.sup.- epitaxial layer formed on the buried semiconductor layer is thin in the memory cell region and thick in the peripheral circuit region, so that the surface of the epitaxial layer can be flat. A concave or convex step is formed on the surface of the epitaxial layer in a boundary portion between the memory cell region and the peripheral circuit region in order to use it as an alignment mark in a later processing step.

Abstract: A BiMOS integrated circuit device comprises a bipolar transistor and at least one MOSFET. The collector and emitter of the bipolar transistor are connected to a high potential source and a low potential source, respectively. The MOSFET has two gate electrodes, a source, and a drain. The source is connected to the high potential source, and the drain is the base of the bipolar transistor by a diffusion layer. The diffusion layer is located between the gate electrodes, and serves as both the base of the bipolar transistor and the drain of the MOSFET. Therefore, the MOSFET has a great channel width, and a large current can be supplied to the base of the bipolar transistor. In other words, the MOSFET has a great driving capability, and the bipolar transistor has a high amplification factor.

Abstract: An optical signal receiver module having: a light receiver unit adapted to be mounted in a receptacle, the receptacle coupling the end portion of an optical fiber, the light receiver unit having a light receiver element for converting light from the optical fiber into an electric signal, the light being incident to one side face of the light receiver unit in the axial direction of the light receiver unit, the light receiver unit having an output terminal extending out of the light receiver unit in the axial direction on the other side face, and the output terminal outputting the electric signal from the light receiver element; and an amplifier unit having an amplifier element for amplifying the electric signal outputted from the light receiver element, the amplifier element being fixedly mounted on an amplifier substrate, the output terminal being adapted to be inserted into a hole formed in the amplifier substrate to mechanically fix the light receiver unit and the amplifier unit, and the output terminal bei

Abstract: A vertical bipolar transistor arrangement in which the distance between the emitter and the isolation region is kept within a range determined by the sum of emitter depth and base width (i.e., the thickness of the base in the depth direction). This keeps the carriers given by the emitter from getting trapped inside, thereby preventing the cut-off frequency from dropping.

Abstract: A photosensitive device includes a semiconductor body (1) having a first region (2) of one conductivity type adjacent a given surface (3) of the body with a second region (4) of the opposite conductivity type surrounding the first region (2) so as to form with the first region a main pn junction (5) terminating at the given surface (3), the main pn junction (5) being reverse-biassed in operation of the device. One or more further regions (6) of the one conductivity type surround the main pn junction (5) adjacent the given surface (3) so that each further region (6) forms a photosensitive pn junction (17) with the second region (4), the further region(s) (6) lying within the spread of the depletion region of the main pn junction (5) when the main pn junction (5) is reverse-biassed in operation of the device so as to increase the breakdown voltage of the main pn junction (5).

Abstract: A semiconductor body (100) has a first device region (20) of one conductivity type forming with a second device region (13) of the opposite conductivity type provided adjacent one major surface (11) of the semiconductor body (100) a first pn junction (40) which is reverse-biassed in at least one mode of operation. A floating further region (50) of the opposite conductivity type is provided within the first device region (20) remote from the major surfaces (11 and 12) of the semiconductor body (100) and spaced from the second device region (13) so that, in the one mode, the depletion region of the first pn junction (40) reaches the floating further region (50) before the first pn junction (40) breaks down.

Abstract: A memory cell layout achieves a reduced cell area. In one embodiment, a six transitor (6T) SRAM cell has two vertical thin-film transistors (18 and 20) as load transistors, two transfer transistors (10 and 12), two latch transistors (14 and 16), and two storage nodes. NODE 1 and NODE 2 of the cell each have a minimum feature defined by trenches (60). Four of five interconnects associated with each node are located within the respective trench. For example in NODE 1, a drain of latch transistor (14), a gate of latch transistor (16), a drain of load transistor (18), and a current electrode of transfer transistor (10) are electrically coupled within or beneath one trench (60). A remaining interconnection of NODE 1, a gate of load transistor 20, is located within the trench associated with NODE 2. Thus, ten interconnects of the memory cell are contained within areas defined by two minimum features.

Abstract: A MOS type semiconductor device comprising a plurality of second conductivity type channel regions having a predetermined impurity density selectively formed in the surface of a first conductivity type semiconductor layer. A channel in the semiconductor layer is formed between adjacent ones of the channel regions, and source regions of the first conductivity type are selectively formed in a surface of each one of the channel regions. A well region of the second conductivity type is formed with a predetermined depth in a middle portion of each one of the plurality of channel regions and has an impurity density higher than that of the channel regions. An insulating layer is formed on the surface of the semiconductor layer, gate electrodes are formed on the insulating layer and overlaying the channel in the first conductivity type semiconductor layer, and a main electrode is formed in contact with at least one of the source region and the well region.