Abstract: A method for manufacturing a diode having a relatively improved on-off ratio. The diode is formed in a container in an insulative structure layered on a substrate of an integrated circuit. The container is then partially filled with a polysilicon material, by methods such as conformal deposition, leaving a generally vertical seam in the middle of the polysilicon material. An insulative material is deposited in the seam. The polysilicon material is appropriately doped and electrical contacts and conductors are added as required. The diode can be coupled to a chalcogenide resistive element to create a chalcogenide memory cell.

Abstract: The present invention relates to a pinned photodiode used in a CMOS image sensor. The pinned photodiode according to the present invention has an uneven surface for increasing an area of a PN junction of the photodiode. So, the increased PN junction area improves a light sensitivity of the photodiode. That is, the epitaxial layer, in which the photodiode is formed, has a trench or a protrusion. Also, in the pinned photodiode, since the P0 diffusion layer is directly in contact with the P-epi layer, the two P-type layers have the same potential and then it may operate in a low voltage.

Abstract: A plurality of optimized diode chips are connected in series with each other to provide a high-voltage silicon diode rectifying device. Each chip has an improved withstand voltage and inverse surge resistance which improves the overall usefulness and efficiency of high-voltage silicon diodes. This invention also reduces costs by requiring fewer individual diode chips. The specific resistance of the (n)-type silicon substrate is in a critical range of between 20 to 50 &OHgr;cm. The diffusion depth of the p+ anode layer is in a critical range of between 30 to 200 &mgr;m. The thickness of the n− base layer is 0.54×(&rgr;·Vsr)½ or greater. In another embodiment, the specific resistance of the silicon substrate is in the range of 32 to 40 &OHgr;cm, and diffusion depth of the p+ anode layer is in the range of 70 to 200 &mgr;m. In yet another embodiment, a cathode layer is diffused on the semiconductor base material.

Abstract: An edge termination for a semiconductor component containing a semiconductor body formed of silicon carbide. The edge termination has at least one diode chain that is insulated from the semiconductor body and provided with a plurality of semiconductor layers having alternating conductivity types.

Abstract: A multilayer ZnO polycrystalline diode that protects against electrostatic discharges, over-current, and voltage surges is provided. The polycrystalline diode includes a block having a plurality of polycrystalline layers in parallel having a first lateral side and a second lateral side. A polycrystalline system is formed by a network of the ZnO diodes. Each diode further includes a plurality of inner electrodes, wherein each inner electrode includes metal and is placed among the plurality of parallel polycrystalline layers, and wherein one end of each inner electrode is placed to alternately terminate at one of the first lateral side and the second lateral side of the block, and wherein the remainder of each inner electrode is surrounded by the parallel polycrystalline layers. A pair of outer electrodes, each including metal and covering each of the first lateral side and the second lateral side of the block are also provided.

Abstract: A face down bonding PIN diode having a semiconductor main body; a first region of a conductivity type, a surface of the first region being exposed at a first surface of a semiconductor main body; a third region of a conductivity type opposite that of the first region, the third region being positioned under the first region; a fifth region of substantially intrinsic semiconductor, the fifth region being positioned between the first region and the third region; a fourth region of the same conductivity type, the fourth region being extended vertically from the first surface to the third surface; a first electrode provided on a predetermined surface of the semiconductor main body connected to the first region; and a second electrode provided on the predetermined surface of the semiconductor main body, the second electrode being connected to the fourth region and connected to the third region through the fourth region.

Abstract: A planar slice (1) of semiconductor substrate material of a first conductivity type is provided on one face with a first region (13a) of a second conductivity type having a higher dopant concentration than that of the substrate and on the opposite face a second region (13b) of said second conductivity type having a higher dopant concentration than that of the substrate. Each of the faces has had removed from part of it a depth of material which increases gradually as the outer edge is approached so that the junction between each of the regions (13a, 13b) and the substrate is exposed along a path following the shape of the perimeter of the slice but so that the removal of material ceases at a distance outwardly beyond the exposure of the junction to leave a rim (11) of the original planar faces of the slice at its perimeter.

Abstract: A semiconductor device has a planar PN junction formed in a semiconductor substrate immediately below bonding pads subjected to mechanical stress. The P- and N-type semiconductor regions that form the PN junction have their respective width and impurity concentration set so that they are completely depleted when a given reverse voltage lower than an inherent breakdown voltage is applied across the PN junction. The PN junction is formed such that the P- and N-type semiconductor regions are each patterned into the shape of a comb and the fingers of one comb-shaped region are interleaved with those of the other comb-shaped region. Paired testing pads are provided which are electrically connected to the P- and N-type semiconductor regions of the PN junction. Application of a reverse voltage across the PN junction through the paired testing pads allows internal damage to the substrate due to mechanical stress to be detected with accuracy as a leakage current resulting from a soft breakdown of the PN junction.

Abstract: An electron emitting apparatus that can realize a convergence of electron trajectories and an improved electron emission efficiency. The apparatus comprises a substrate having a first primary surface that is substantially planar, an electron emitting device comprising first and second electroconductive members disposed on the primary surface and at an interval from one another, and an anode electrode having a substantially planar surface opposite to the first primary surface. A voltage applying means of the apparatus applies a potential higher than a potential applied to the first electroconductive member to the second electroconductive member to irradiate electrons emitted from the electron emitting device onto the anode electrode.

Abstract: A depletion type MOS semiconductor device is provided which includes a p− well region formed in a surface layer of an n− drift layer, an n+ emitter region formed in a surface layer of the p− well region, an n− depletion region formed in the surface layer of the p well region, to extend from the n+ emitter region to a surface layer of the n drift layer, a gate electrode layer formed on a gate insulating film, over the n− depletion region, an emitter electrode formed in contact with surfaces of both of the n+ emitter region and the p− well region, and a collector electrode formed on a rear surface of the n− drift layer. Also provided is a MOS power IC in which the depletion type MOS semiconductor device is integrated with a vertical MOSFET or IGBT. The MOS power IC has a high breakdown voltage, and includes a circuit for feeding back an increase in the potential of the C terminal to the gate (gm) of the MOSFET or IGBT.

Abstract: A method for manufacturing a diode having a relatively improved on-off ratio. The diode is formed in a container in an insulative structure layered on a substrate of an integrated circuit. The container is then partially filled with a polysilicon material, by methods such as conformal deposition, leaving a generally vertical seam in the middle of the polysilicon material. An insulative material is deposited in the seam. The polysilicon material is appropriately doped and electrical contacts and conductors are added as required. The diode can be coupled to a chalcogenide resistive element to create a chalcogenide memory cell.

Abstract: A semiconductor diode device having the characteristic of soft recovery and a method for manufacturing the same. A first N+ layer contacts with a cathode electrode. An N- epitaxial layer is formed on the first N+ layer. A P- layer is formed to have an undulating junction with the N- epitaxial layer. A second N+ layer is embedded in the P- layer. An anode electrode is attached to the P- layer, wherein the anode contact to the P- layer includes the second N+ layer. A channel stop region and insulating layer are also added to the structure.

Abstract: A diode is formed by forming a PN junction region 6 with a p region 5 formed on a buried oxide film 19 side and an n region 7 formed on the surface side in a surface silicon layer 3 which is isolated by the buried oxide film 19 of an SOI substrate 1, providing a lightly doped p region 33 on one end side of the PN junction region 6 and a lightly doped n region 31 on an other end side, forming a heavily doped p region 13 and a heavily doped n region 9 at the respective surface portions of the lightly doped p region 33 and the lightly doped n region 31 in such a manner as not to contact the PN junction region 6, and providing two metal plates which respectively connect to the heavily doped p region 13 and the heavily doped n region 9.

Abstract: In an input protection circuit having an SOI structure for protecting a MOSFET against breaking caused by a high voltage such as static electricity, a trench is provided in an SOI substrate to vertically pass through a silicon layer and a buried oxide film and reach the interior of a P-type silicon substrate. An n.sup.+ polysilicon layer is buried in the trench, to be connected with the silicon substrate by a P-N junction. A wire is connected to the n.sup.+ polysilicon layer. An end of the wire is connected to an input pad, and another end thereof is connected to an internal circuit. An input voltage is limited by an avalanche breakdown at the P-N junction in the interface between the n.sup.+ polysilicon layer and the P-type silicon substrate.

Abstract: A semiconductor device structure and method are presented for increasing a breakdown voltage of a junction between a substrate of first conductivity type and a device region. The structure includes a region of second conductivity type in the substrate completely buried in the substrate below and separated from the device region. The region of second conductivity type is located a predetermined distance away from the device region. The distance is sufficient to permit a depletion region to form between the region of second conductivity type and the device region, when a first voltage is applied between the device region and the substrate. The distance also is determined to produce a radius of curvature of the depletion region, when a second voltage that is larger than the first voltage is applied between the device region and the substrate, that is larger than a radius of curvature of the depletion region about the device region that would be formed if the region of second conductivity type were not present.

Abstract: An n.sup.+ drain layer 2 and an n.sup.- layer 1 on n.sup.+ drain layer 2 constitute a substrate for the semiconductor arrangement. A p-type base region 3 is in the surface portion of n.sup.- layer 1. An n.sup.+ source region 6 is formed in the surface portion of p-type base region 3. A p.sup.+ region 5, deeper than n.sup.+ source region 6 and shallower than p-type base region 3, partially overlaps n.sup.+ source region 6 and extends thoroughly into the portion of p-type base region 3 surrounded by n.sup.+ source region 6. A channel portion 7 is in the surface portion of p-type base region 3 extending between n.sup.- layer 1 and n.sup.+ source regions 6. A gate electrode 8 is disposed above channel portion 7 with a gate insulation film 9 interposed therebetween. A source electrode 11 contacts with p.sup.+ region 5 and n.sup.+ source region 6. An inter-layer insulation film 10 on gate electrode 8 insulates source electrode 11 from gate electrode 8. A drain electrode 12 is on the surface of n.sup.

Abstract: An n.sup.+ drain layer 2 and an n.sup.- layer 1 on n.sup.+ drain layer 2 constitute a substrate for the semiconductor arrangement. A p-type base region 3 is in the surface portion of n.sup.- layer 1. An n.sup.+ source region 6 is formed in the surface portion of p-type base region 3. A p.sup.+ region 5, deeper than n.sup.+ source region 6 and shallower than p-type base region 3, partially overlaps n.sup.+ source region 6 and extends thoroughly into the portion of p-type base region 3 surrounded by n.sup.+ source region 6. A channel portion 7 is in the surface portion of p-type base region 3 extending between n.sup.- layer 1 and n.sup.+ source regions 6. A gate electrode 8 is disposed above channel portion 7 with a gate insulation film 9 interposed therebetween. A source electrode 11 contacts with p.sup.+ region 5 and n.sup.+ source region 6. An inter-layer insulation film 10 on gate electrode 8 insulates source electrode 11 from gate electrode 8. A drain electrode 12 is on the surface of n.sup.

Abstract: A pn-diode of SiC has a first emitter layer part doped with first dopants having a low ionization energy and a second part designed as a grid and having portions extending vertically from above and past the junction between the drift layer and the first part and being laterally separated from each other by drift layer regions for forming a pn-junction by the first part and the drift layer adjacent such portions at a vertical distance from a lower end of the grid portions. The different parameters of the device are selected to allow a depletion of the drift layer in the blocking state form a continuous depleted region between the grid portions, to thereby screen off the high electric field at the pn-junction so that it will not be exposed to high electrical fields.

Abstract: An antifuse is described that can be formed without masks or mask steps beyond those required for a conventional CMOS process. The antifuse includes adjacent p-type and n-type diffusion regions that together form a P-N junction. The diffusion regions are tapered toward one another such that the P-N junction is located at a necked-down region of the antifuse. The diffusion regions are connected to respective terminals of a programming-voltage source via first and second metal electrical contacts, typically of aluminum metal. Each of the first and second electrical contacts includes a point directed toward the other of the first and second electrical contacts. The antifuse is programmed by providing a reverse-bias programming voltage across the electrical contacts. This programming voltage exceeds the breakdown voltage of the P-N junction so that current flows through the necked-down region of the antifuse between the points on the respective first and second electrical contacts.

Abstract: In an input protection circuit having an SOI structure for protecting a MOSFET against breaking caused by a high voltage such as static electricity, a trench is provided in an SOI substrate to vertically pass through a silicon layer and a buried oxide film and reach the interior of a P-type silicon substrate. An n.sup.+ polysilicon layer is buried in the trench, to be connected with the silicon substrate by a P-N junction. A wire is connected to the n.sup.+ polysilicon layer. An end of the wire is connected to an input pad, and another end thereof is connected to an internal circuit. An input voltage is limited by an avalanche breakdown at the P-N junction in the interface between the n.sup.+ polysilicon layer and the P-type silicon substrate.

Abstract: Semiconductor diodes having a low forward voltage conduction drop, a low reverse leakage current and a high voltage capability suitable for use in integrated circuits as well as for discrete devices. The semiconductor diodes are fabricated as field effect devices having a common gate and drain connection by a process which provides very short channels, shallow drain regions and longitudinally graded junctions. Continuation of the gate/drain contact layer over specially located, tapered edge field oxide maximizes the breakdown voltage of the devices. The preferred fabrication technique utilizes four masking steps, all without any critical mask alignment requirements. Various embodiments are disclosed.

Abstract: A power diode includes at least one semiconductor body having an inner zone f a first conductivity type and a given doping level, a cathode zone of the first conductivity type and a doping level higher than the given doping level, and an anode zone of a second conductivity type opposite the first conductivity type and a doping level higher than the given doping level. The inner zone has at least a first region with a first predetermined thickness being dimensioned for a required blocking voltage and a second region with a second thickness being greater than the first predetermined thickness by at least a factor of 1.4. The area and/or the minority carrier life of first and second partial diodes is dimensioned for causing a current flowing through the first partial diode in a conductive phase to be greater than a current flowing through the second partial diode by at least a factor of 2.

Abstract: An integrated CMOS diode with an injection ring which enables construction of an integrated CMOS diode that has the performance characteristics of a high impedance value, when the diode is in the off state, and low impedance, when the diode is in the on state in addition to high breakdown voltages using standard CMOS processing techniques to construct the integrated circuit diode.

Abstract: A method for forming a diode for use within an integrated circuit, and a diode formed through the method. There is first provided a semiconductor substrate. There is then formed over the semiconductor substrate a dielectric layer. There is then formed upon the dielectric layer a first polysilicon layer, where the first polysilicon layer has a first dopant polarity and a first dopant concentration. There is then formed at least in part overlapping and at least in part in contact with the first polysilicon layer a second polysilicon layer. The second polysilicon layer has a second dopant polarity and a second dopant concentration, where the second dopant polarity is opposite to the first dopant polarity. A first portion of the second polysilicon layer overlapping and in contact within a first portion of the first polysilicon layer forms a junction diode.

Abstract: An integrated circuit device comprising: a body of a semiconductor material having an upper surface and a bottom major surface; wall means defining in said semiconductor material body a microscopically precise depression or groove of a selected shape and size and extending for a selected length or depth from a selected position on said upper surface toward without reaching said bottom major surface; and a material chemically different from said semiconductor material and introduced into said semiconductor material through ?a selected portion of an exposed wall of! said groove to modify, in a predetermined manner, a selected electronic property of said semiconductor material the vicinity of said exposed wall.

Abstract: A diode integrated on semiconductor material with BCD technology and of the type provided on a substrate having a first type of conductivity inside an isolation region having a second type of conductivity. The diode comprises also a buried anode region having a first type of conductivity and a cathode region having a second type of conductivity. The cathode region comprises an epitaxial layer located above the buried anode region and a highly doped region provided inside the epitaxial layer. The buried anode region comprises depressions opposite which is located the highly doped region with the depressions being achieved by the intersection of lateral diffusions of distinct and adjacent portions of the buried anode region.

Abstract: A semiconductor device comprising a source region, a channel region, and a drain region, provided that one or both of the phase boundary between the channel forming region and the source region and that between the channel forming region and the drain region are shaped into an uneven shape, and optionally, periodically. Also claimed is a process for fabricating the same.

Abstract: A low-noise Zener diode that enables to improve the surge resistance performance without degeneration of its low-noise characteristic is provided. The diode contains a semiconductor substrate of a first conductivity type and a first impurity doped region of a second conductivity type formed in a surface area of the substrate. The first impurity doped region has spaces into which no impurity of the second conductivity type is doped. The diode further contains a second impurity doped region of the second conductivity type formed in the first impurity doped region. The second impurity doped region has a depth less than that of the first impurity doped region. The second impurity doped region is contacted with the substrate in the spaces, producing main p-n junctions of the diode at respective interfaces of the second impurity doped regions and the substrate. The second impurity doped region is contacted with the first impurity doped region other than in the spaces.

Abstract: The present invention is directed to an improved base-collector junction transistor structure capable of higher junction breakdown voltages and lower junction capacitances than bipolar transistors of the prior art. A narrow trench is used to positively affect junction breakdown voltage and junction capacitance. The trench allows the beneficial characteristics of both depletion ring and mesa structures to be utilized. Depletion zone profiles that negatively affect junction breakdown voltage are minimized by using the trench and a depletion enhancing channel.

Abstract: A high voltage MIS field effect transistor includes a semiconductor substrate of a first conductivity type; a semiconductor layer of a second conductivity type formed on an obverse surface side of the semiconductor substrate; a base layer of the first conductivity type formed in the semiconductor layer; a source layer of the second conductivity type formed in the base layer; a source electrode abutting the source layer; a gate electrode formed in such a manner as to extend from the source layer to the semiconductor layer via an insulating gate film; a drain section including a drain layer of the second conductivity type formed in the semiconductor layer in such a manner as to be spaced apart from the source layer; and a low-concentration region of the first conductivity type being formed in a vicinity of a periphery of a base corner portion of said base layer.

Abstract: The high-voltage semiconductor device includes a single chip having a plurality of semiconductor elements connected in series with each other which includes an insulating substrate (2); a monocrystalline semiconductor carrier (1) of a first conductivity type applied to the insulating substrate (2); at least two terminals (5,6) located on opposite sides of the chip; strip-like areas (3) of a second conductivity type formed in the monocrystalline semiconductor carrier (1), the strip-like areas (3) each extending across the semiconductor carrier (1) at right angles to a longitudinal direction between the at least two terminals, forming pn junctions in the semiconductor carrier (1), being spaced from each other in the longitudinal direction over the single chip and penetrating an entire thickness of the semiconductor carrier; at least one doped region (7) in the strip-like areas (3) forming an at least four layered component in the single chip; and a light responsive device for reducing a switching voltage of the

Abstract: A semiconductor device with a semiconductor body (1) includes a surface region (3) of a first conductivity type which adjoins a surface and in which a field effect transistor is provided which includes a channel region (7) with a gate electrode (8) above it, and a source region (4), a drain region (5) and a drain extension region (6). The drain extension region (6) serves to improve the drain breakdown voltage of the field effect transistor. In practice, a high breakdown voltage is accompanied by a comparatively high on-resistance of the transistor. According to the invention, the drain extension region (6) has a geometry different from that in known transistors, i.e.

Abstract: A reference diode is formed in an N-type insulated well. An avalanche diode includes a P-type deep region having a high doping level, beneath which is formed an N-type overlapping buried layer, a P-type deep diffused region contacting a central portion of the deep region, a second, P-type, deep diffused region contacting the periphery of the deep region, an N-type highly doped surface region coating the surface of the first deep diffused region and forming therewith an avalanche junction. At least another structure identical to the avalanche diode structure, without the N-type surface region, forms a resistor between its electrodes.

Abstract: A semiconductor rectifying module has a metal base, a dielectric heat conducting spacer arranged on the metal base and rectifying elements of anode and cathode groups arranged with their cathodes and anodes on the spacer, the rectifying elements being composed of a semiconductor with at least two layers having alternating conductivity types, each of the rectifying elements being surrounded by its side surface by a side layer of a first type conductivity semiconductor material while an original material is a second type conductivity semiconductor material, and being provided with an upper closed separating groove with an external part bordering at least the side layer.

Abstract: A MOS transistor for protection against electrostatic discharge includes a semiconductor substrate; an island including a source region and a drain region provided in the semiconductor substrate; an isolation region provided in the semiconductor substrate so as to surround the island; a gate insulating layer provided on the semiconductor substrate; a gate electrode provided on the gate insulating layer; and a distributing device for distributing an electric current generated by an electrostatic voltage applied to the drain region into the drain region.

Abstract: A semiconductor diode characterized by an anode electrode structure connected to a double diffusion of P-type impurities in a major surface of an N.sup.- semiconductor. The first diffusion forming a first plurality of P.sup.- well regions and the second diffusion selectively forming a second plurality of P.sup.+ well regions within the first well region.

Abstract: A source/drain structural configuration suitable for metal-oxide semiconductor field-effect transistors is provided, having a wedge-shaped configuration with a thickness that increases in the direction from its end near to one the channel of the transistor toward the other end. The source/drain configuration includes a shallow junction advantageously formed to reduce sheet resistance and prevent the hot carrier punchthrough effect. The wedge-shaped source/drain configuration is fabricated by depositing a dielectric layer, which is flowable under thermal treatment, after the formation of a polysilicon gate electrode. After annealing, the dielectric layer is etched to form a wedge-shaped mask. The resulting mask has a thickness that decreases in the direction from its one end near the gate electrode toward the other end. The presence of the wedge-shaped shielding masks facilitates the formation of a pair of wedge-shaped source/drain regions on the substrate via implementation of an ion implantation procedure.

Abstract: A reference diode is formed in an N-type insulated well. An avalanche diode includes a P-type deep region having a high doping level, beneath which is formed an N-type overlapping buried layer, a P-type deep diffused region contacting a central portion of the deep region, a second, P-type, deep diffused region contacting the periphery of the deep region, an N-type highly doped surface region coating the surface of the first deep diffused region and forming therewith an avalanche junction. At least another structure identical to the avalanche diode structure, without the N-type surface region, forms a resistor between its electrodes.

Abstract: A thin film transistor is provided with a semiconductor layer disposed on an insulating layer region having a channel region and a plurality of main electrode regions having an impurity concentration higher than an impurity concentration of the channel region. A second insulating layer region is disposed on the semiconductor region layer, and a control electrode is disposed on the second insulating layer. An interface is defined between at least one of the main electrode regions and the channel regions through a thickness of the semiconductor layer becoming increasing remote from its side of the control electrode in the direction from the second insulating layer region toward the first insulating layer region. An original point is defined as a position of the interface immediately beneath the insulating layer region. When a layer thickness of the semiconductor region is defined as T.sub.SOI and a maximum distance of the semiconductor layer region in the direction normal to a layer thickness is defined as L.

Abstract: An electrical junction is precisely located between a highly p doped semiconductor material and a more lightly n doped semiconductor material by providing a lightly p doped buffer region between the two materials, with a doping level on the order of the n doped material's. The buffer region is made wide enough to establish an electrical junction at approximately its interface with the n doped material, despite a diffusion of dopant from the p doped material. When applied to a heterojunction bipolar transistor (HBT), the transistor's base serves as the heavily p doped material and its emitter as the more lightly n doped material. The buffer region is preferably employed in conjunction with a graded superlattice, located between the buffer and emitter, which inhibits dopant diffusion from the base into the emitter.

Abstract: A semiconductor device having at least one symmetrical pair of MOSFETs is provided. The device includes a semiconductor layer having an upper surface, an active region formed in the upper surface, an isolation region formed in the upper surface and enclosing the active region, and a pair of MOSFETs formed in the active region, wherein the pair of MOSFETs are symmetrical with respect to a first symmetric plane substantially vertical to the upper surface and also with respect to a second symmetric plane vertical both to the upper surface and to the first symmetric plane, each of the pair of MOSFETs includes a source region, a drain region, and a channel region formed in an upper surface of the active region, the source region is shared by the pair of MOSFETs, and the drain region is spatially isolated from the source region by the channel region.

Abstract: A field effect transistor includes a polycrystalline silicon gate having a semiconductor junction therein. The semiconductor junction is formed of first and second oppositely doped polycrystalline silicon layers, and extends parallel to the substrate face. The polycrystalline silicon gate including the semiconductor junction therein is perfectly formed by implanting ions into the top of the polycrystalline silicon gate simultaneous with implantation of the source and drain regions. The semiconductor junction thus formed does not adversely impact the performance of the field effect transistor, and provides a low resistance ohmic gate contact. The gate need not be masked during source and drain implant, resulting in simplified fabrication.

Abstract: A semiconductor device includes a semiconductor substrate and channel and electron supply layers epitaxially grown on the semiconductor substrate. Source, drain, and gate electrodes are disposed on the electron supply layer. At least the gate electrode and the electron supply layer are structured such that an electron gas within the channel layer is one-dimensional to prevent scattering of electrons in the channel layer.

Abstract: A high voltage semiconductor structure (10) includes a semiconductor substrate (11) of a first conductivity type. The structure (10) also includes a first region (12) providing a main rectifying junction, a second region (13, 17, 21) of a second conductivity type formed in the semiconductor substrate and surrounding the first region ( 12 ) and a third region (14, 18, 22) of the second conductivity type. The third region (14, 18, 22) has reduced conductivity and greater junction depth compared to the second region (13, 17, 21). The third region (14, 18, 22) surrounds and is in contact with the second region (13, 17, 21) to form field rings which improve (increase) breakdown voltage of the high voltage semiconductor structure (10).

Abstract: An electronic switch, in particularly a transistor, has at least one barrier layer extending between regions of different doping concentrations within a semiconductor and is characterized in that the barrier layer has at least one voltage limiting zone (Z) having a radius of curvature (R) less than or at most equal to the diffusion depth (x.sub.JB) of the diffused junction.

Abstract: A semiconductor device includes a MISFET which has a gate polysilicon between source and drain regions, the gate polysilicon being covered with a gate insulator film. The gate polysilicon with the gate insulator film thereon has a protruded curved bottom portion extending in the substrate direction. The source and drain regions have their respective bottom surfaces located above the location where the bottom of the gate insulator film is most protruded toward the substrate. At least the drain region has in the vicinity of the protruded bottom portion of the gate polysilicon, a sidewall portion having a bottom portion projecting laterally towards the protruded portion of the gate polysilicon and an upper portion bent into a concave shape to form a pocket between that upper portion and the gate insulator film.

Abstract: A CMIS transistor suitable for device miniaturization, elimination of degradation of operational characteristics by hot carrier effect, and elimination of decrease of threshold voltage caused by short channel effect, includes a laterally spreading N-type diffusion region having an impurity concentration level higher than P-type and N-type wells but lower than source and drain regions, such that the N-type diffusion region extends laterally into a part located immediately below an edge of an insulating gate and has a depth smaller than a depth of the source and drain regions. The device is thereby capable of increasing the width of depletion layer at the bottom of the source and drain regions while maintaining effectiveness as a punch-through stopper. Thereby, the junction capacitance at the source and drain regions is reduced and the operational speed of the device improved in the P-channel transistor part in the device.

Abstract: A vertical power field effect transistor is liable to be destroyed due to a large amount of current backwardly flowing from the drain region through the base region into the source region when a parasitic bipolar transistor fabricated therefrom turns on, and base contacts radially and inwardly project from the four corners a rectangular base region into a rectangular source region so that the resistance of the base region is decreased, thereby effectively preventing the parasitic bipolar transistor from turn-on.

Abstract: A process for producing a compound semiconductor comprises applying a crystal forming treatment on a substrate having a free surface comprising a nonnucleation surface (S.sub.NDS) with smaller nucleation density and a nucleation surface (S.sub.NDL) arranged adjacent thereto having a sufficiently small area for a crystal to grow only from a single nucleus and a larger nucleation density (ND.sub.L) than the nucleation density (ND.sub.S) of said nonnucleation surface (S.sub.NDS), by exposing the substrate to either of the gas phases:(a) gas phase (a) containing a starting material (II) for feeding the group II atoms of the periodic table and a starting material (VI) for feeding the group VI atoms of the periodic table and(b) gas phase (b) containing a starting material (III) for feeding the group III atoms of the periodic table and a starting material (V) for feeding the group V atoms of the periodic table, thereby forming only a single nucleus on said nucleation surface (S.sub.

Abstract: A monolithic structure comprises two sets of bidirectional diodes having distinct characteristics constituted from a substrate (1) of a first (N.sup.-) conductivity type. First regions (10, 11, 12) of the second conductivity type constitute the first set of diodes between a first metallization (30) coating one of the first regions and second metallizations (31, 32) coating the other first regions. In a well (15) of the second conductivity type, second regions (20, 21, 22) of the first conductivity type constitute the second set of diodes between a third metallization (40) coating one of the second regions and fourth metallizations (41, 42) coating the other second regions.