Abstract: An electronic device includes: a support member that has a metallic placement surface joined to the conductive bonding layer, and a metallic sealing surface provided on an outer side of the placement surface in an in-plane direction of the placement surface to adjoin the placement surface and to surround the placement surface; and a resin member, which is a synthetic resin molded article, joined to the sealing surface and covering the electronic component. The sealing surface includes a rough surface having a plurality of laser irradiation marks having a substantially circular shape. The rough surface includes a first region and a second region. The second region has a higher density of the laser irradiation marks in the in-plane direction than the first region.

Abstract: A packaged semiconductor device includes a semiconductor die having a top side including a semiconductor surface layer having circuitry configured for a function coupled to bond pads, and a bottom side. A leadframe includes a die pad and leads or lead terminals on at least two sides of the die pad. At least one non-through hole for delamination prevention is in at least one of the die pad and the lead or the lead terminals. The semiconductor die is mounted by a die attach material with the bottom side down on the die pad. A mold compound provides encapsulation for the package semiconductor device except for at least a bottom side of the lead terminals or sidewalls of the package for the leads. The non-through hole is a filled hole filled with either the die attach material or the mold compound.

Abstract: An electronic device includes a package substrate, at least one integrated circuit (IC) die including a substrate having a semiconductor surface including circuitry electrically coupled to bond pads positioned onto contact pads on a top surface of a package substrate. At least one surface mount device (SMD) component including at least a first terminal and a second terminal is on the package substrate positioned lateral to the IC die. There is at least one SMD interconnect electrically connecting to at least one of the first terminal and the second terminal to the bond pads. The SMD interconnect includes a portion of a tie bar that extends to an outer edge of the electronic device.

Abstract: A semiconductor package includes a base substrate, a first semiconductor chip on the base substrate, a dam structure on the base substrate and surrounding the first semiconductor chip, a second semiconductor chip on the first semiconductor chip, a non-conductive film, and a molding member. The non-conductive film may be between the base substrate, the first semiconductor chip, and the second semiconductor chip. The molding member may cover the base substrate, the first semiconductor chip, and the second semiconductor chip. A level of an upper surface of the first semiconductor chip and a level of an upper surface of the dam structure may be at a same level.

Abstract: An optoelectronic assembly and methods of fabrication thereof are provided. The assembly includes a sub-mount, one or more micro-devices attached to the sub-mount, and a lid attached to the sub-mount. The lid includes a dispense channel and a gel groove which allows for a thermal gel to be dispensed between the lid and the micro-device in a manner that mitigates the thermal gel dispersing and/or flowing onto components of the micro-devices.

Abstract: In some embodiments, the present application provides a method for manufacture a memory device. The method includes forming a multilayer stack including a first magnetic layer and a first dielectric layer and forming another magnetic layer. The multilayer stack and the another magnetic layer are tailored to meet dimensions of a package structure. The package structure includes a chip having a memory cell and an insulating material enveloping the chip, where an outer surface of the package structure comprises the insulating material. The tailored multilayer stack and the tailored another magnetic layer are attached to the outer surface of the package structure.

Abstract: An electronic assembly that includes a substrate having an upper surface and a bridge that includes an upper surface. The bridge is within a cavity in the upper surface of the substrate. A first electronic component is attached to the upper surface of the bridge and the upper surface of the substrate and a second electronic component is attached to the upper surface of the bridge and the upper surface of the substrate, wherein the bridge electrically connects the first electronic component to the second electronic component.

Abstract: In some examples, a sensor package includes a semiconductor die having a sensor; a mold compound covering a portion of the semiconductor die; and a cavity formed in a top surface of the mold compound, the sensor being in the cavity. The sensor package includes an adhesive abutting the top surface of the mold compound, and a semi-permeable film abutting the adhesive and covering the cavity. The semi-permeable film is approximately flush with at least four edges of the top surface of the mold compound.

Abstract: A lead frame used to assemble a semiconductor device, such as a smart card, has a first major surface including exposed leads and a second major surface including a die receiving area and one or more connection pads surrounding the die receiving area. The connection pads enable electrical connection of an Integrated Circuit (IC) die to the exposed leads. A molding tape sized and shaped like the lead frame is adhered to and covers the second major surface of the lead frame. The molding tape has a die receiving area cut-out that exposes the die receiving area and the connection pads on the second major surface of the lead frame and forms a cavity for receiving an encapsulant. The cut-out has an elevated sidewall for retaining the encapsulant within the cavity.

Abstract: Semiconductor devices having flow controllers configured to reduce mitigation of mold material between stacked layers, and associated systems and methods, are disclosed herein. In some embodiments, the semiconductor device includes a package substrate that has first and second surfaces. First and second die stacks are formed on the first surface and are adjacent to each other. A portion of the first surface extends between the first and second die stacks. A layer of material is adhered to top surfaces of the first and second die stacks and extends at a distance above the package substrate to form a tunnel between the layer of material, opposing sidewalls of the die stacks, and the package substrate. The semiconductor device further includes a flow controller that is adhered to at least a portion of the first surface inside the tunnel that reduces a cross-sectional surface area of at least a portion of the tunnel.

Abstract: An electronic-part-reinforcing thermosetting resin composition has: a viscosity of 5 Pa·s or less at 140° C.; a temperature of 150° C. to 170° C. as a temperature corresponding to a maximum peak of an exothermic curve representing a curing reaction; and a difference of 20° C. or less between the temperature corresponding to the maximum peak and a temperature corresponding to one half of the height of the maximum peak in a temperature rising range of the exothermic curve.

Abstract: A semiconductor device includes: semiconductor elements and; a lead frame including a mount having an upper surface over which the semiconductor elements and are mounted; a sealing resin sealing the lead frame and the semiconductor elements and so that outer leads and of the lead frame protrude outwardly; and a resin wall located on an inner lead between the outer lead and the mount of the lead frame. A vertical thickness of the resin wall is greater than a vertical thickness from a lower surface of the sealing resin to a lower end of the lead frame.

Abstract: A semiconductor package includes a base substrate, a first semiconductor chip on the base substrate, a dam structure on the base substrate and surrounding the first semiconductor chip, a second semiconductor chip on the first semiconductor chip, a non-conductive film, and a molding member. The non-conductive film may be between the base substrate, the first semiconductor chip, and the second semiconductor chip. The molding member may cover the base substrate, the first semiconductor chip, and the second semiconductor chip. A level of an upper surface of the first semiconductor chip and a level of an upper surface of the dam structure may be at a same level.

Abstract: A linear image sensor includes first and second sensor chips, first and second substrates, a common support substrate, a support portion, a dam portion, and a sealing portion. The first sensor chip is mounted to partially protrude on one end side of the first substrate. The second sensor chip is mounted to partially protrude on one end side of the second substrate. The first and second substrates are mounted on the common support substrate. The support portion is provided in a gap between the end faces of the first and second substrates. The dam portion is provided annularly to surround the sensor chips. The sealing portion seals the sensor chips, in a region surrounded by the dam portion.

Abstract: A method includes attaching semiconductor dies to die attach pads of first and second columns of the lead frame; enclosing the semiconductor dies of the respective columns in respective first and second package structures; trimming the lead frame to separate respective first and second lead portions of adjacent ones of the first and second columns of the lead frame; moving the first columns along a column direction relative to the second columns; and separating individual packaged electronic devices of the respective first and second columns from one another.

Abstract: A display device and a method of manufacturing the display device are provided. The method includes disposing a display panel, including side areas, a front display area, and a sub-region, on a carrier film including first, second, and third release portions; removing the first release portion to expose the side areas; disposing a cover window above the display panel; attaching the front display area to the cover window by pressing the second release portion toward the cover window, and attaching the side areas to the cover window by pressing the side areas exposed by removing the first release portion toward the cover window; removing the second release portion and the third release portion to expose the front display area and the sub-region; and bending the display panel to attach a bottom portion of the sub-region to a bottom portion of the front display area.

Abstract: A chip package and method for fabricating the same are provided which utilize a cover having one or more windows formed through one or more sidewalls to provide excellent resistance to warpage while allowing access to an internal volume of the chip package. In one example, the chip package includes a package substrate, an integrated circuit (IC) die, and a cover disposed over the IC die. The cover includes a lower surface facing the IC die, an upper surface facing away from the IC die, a lip extending from the lower surface, and a first sidewall extending from a first edge of the upper surface to the bottom of the lip. The lip is secured to the package substrate and encloses a volume between the lower surface and the package substrate. The IC die resides in the volume. A first elongated window is formed through the first sidewall and exposes the volume through the cover.

Abstract: In a semiconductor device, lead frame includes a die pad. The die pad includes a mounting surface and a back surface. The mounting surface includes first and second mounting regions. The back surface includes first and second back regions. The first and second semiconductor elements are mounted on the first and second mounting regions, respectively. The first and second back regions are located on opposite sides from the first and second mounting regions, respectively. The mold resin has the first semiconductor element, the second semiconductor element, and the die pad encapsulated therein and is in direct contact with the second back region. The insulation sheet is disposed on the first back region to be exposed outside the mold resin, the insulation sheet having a thermal conductivity higher than a thermal conductivity of the mold resin.

Abstract: An LED filament is disclosed.

Abstract: An interposer may comprise a metal layer above a substrate. A dam or a plurality of dams may be formed above the metal layer. A dam surrounds an area of a size larger than a size of a die which may be connected to a contact pad above the metal layer within the area. A dam may comprise a conductive material, or a non-conductive material, or both. An underfill may be formed under the die, above the metal layer, and contained within the area surrounded by the dam, so that no underfill may overflow outside the area surrounded by the dam. Additional package may be placed above the die connected to the interposer to form a package-on-package structure.

Abstract: A method of making a semiconductor device may include providing a carrier and forming a first photoresist over the carrier with first openings through the first photoresist. A non-planar conductive seed layer may be formed over the first photoresist and conformally extend into the first openings through the first photoresist. A second photoresist may be formed over the first photoresist and over the non-planar conductive seed layer. The second photoresist layer may be patterned to form second openings through the second photoresist that extend to the non-planar conductive seed layer. Conductive posts may be plated over the non-planar conductive seed layer and within the second openings. The second photoresist may be removed while leaving in place the first photoresist. A semiconductor die may be coupled to the carrier. The semiconductor die, the conductive posts, and the first photoresist may be encapsulated with mold compound.

Abstract: The method of the present invention improves quality and reliability of resin mold-type semiconductor devices. The method includes the steps of placing a lead frame such that cavities of a mold match with device formation regions of the lead frame, respectively, and forming encapsulation bodies that encapsulate semiconductor chips by flowing encapsulating resin into the cavities. The mold with an upper mold half and a lower mold half clamped together has a plurality of first gates that allow the cavities to communicate with a runner, and a dummy-cavity gate that allows a dummy cavity to communicate with the runner. During a resin molding process, from the time when the resin starts flowing into the mold to the time when the encapsulation bodies are formed, an orifice of each cavity gate is larger in size than an orifice of the dummy-cavity gate.

Abstract: Development of smart objects with electronic functions requires integration of printed components with IC chips or dies. Conventional chip or die bonding including wire bonding, flip chip bonding, and soldering may not be applicable to chip or die attachment on low temperature plastic surfaces used in physical objects. Printing conductive connection traces requires a smooth interface between contact pads of a chip and the surface of the physical object. In order to address this issue of chip/die attachment to a physical object, this disclosure provides embodiments to construct a fixture on a chip or die for attachment and electrical connection onto a physical object by printing operations and/or ACF bonding methods.

Abstract: A plated hole with a sidewall plating. The plated hole has a vent opening that has a sidewall of non-conductive material that is not plated. During attachment of a joint conductive material such as solder to the sidewall plating, gasses generated from the attachment process are outgassed through the vent opening.

Abstract: A semiconductor device includes two or more semiconductor elements, a lead with island portions on which the semiconductor elements are mounted, a heat dissipation member for dissipating heat from the island portions, a bonding layer bonding the island portions and the heat dissipation member, and a sealing resin covering the semiconductor elements, the island portions and a part of the heat dissipation member. The bonding layer includes mutually spaced individual regions provided for the island portions, respectively.

Abstract: A leadframe includes a die pad for mounting a semiconductor die with its top side facing up using a die attach resin material including a resin, the leadframe having leads or lead terminals beyond the die pad. The die pad includes slots including a first slot and at least a second slot on at least a first side of the die pad that penetrate a full thickness of the die pad. At least one non-penetrating groove is in the die pad for providing a fluid connection including between the first and second slots for providing a flow channel for guiding the resin when received by the grooves after bleeding out from under the semiconductor die to flow to at least one of the first slot and the second slot.

Abstract: According to one embodiment, a magnetic memory device includes a magnetic memory chip having a magnetoresistive element, a magnetic layer having first and second portions spacing out each other, the first portion covering a first main surface of the magnetic memory chip, the second portion covering a second main surface facing the first main surface of the magnetic memory chip, a circuit board on which the magnetic layer is mounted, and a bonding wire connecting between the magnetic memory chip and the circuit board in a first direction parallel to the first and second main surfaces.

Abstract: An electromagnetic interference (EMI) shielding structure and a method for manufacturing are provided. The EMI shielding structure includes a printed circuit board (PCB) on which a plurality of elements are mounted, an insulation molding member configured to cover the plurality of elements, a conductive shielding dam formed along a side surface of the insulation molding member, and a conductive shielding member formed on a top surface of the insulation molding member.

Abstract: The present disclosure relates to an enclosed electronic module with single/multiple active components and an integrated heat dissipation system, including a top housing formed with one or more openings, a heat sink mounted on an outer surface of the top housing over the opening(s) thereof, a bottom housing coupled with the top housing, one or more active components mounted on a PCB between the top and bottom housings, and at least one thermal block or vapor chamber thermally connected between the heat sink and the active component(s), thereby forming one or more thermal dissipation paths extending from the active component(s), through the at least one thermal block or vapor chamber, and to the heat sink.

Abstract: A lead frame includes a first electrode, a second electrode, two hanger leads, and an outer frame, and partially forms a box-shaped package which has a first recess for mounting a light emitting element as combined with a support member that supports the first electrode and the second electrode. At least a portion of lower faces of the electrodes, at least a portion of lower faces of the hanger leads, and at least a portion of a lower face of the planned formation area for the support member are coplanarly formed. Lower face corners of the first electrode and the second electrode are rounded while upper face corners of the first electrode and the second electrode are not rounded, and upper face corners of the hanger leads are rounded while lower face corners of the hanger leads are not rounded.

Abstract: Method of making an integrated circuit package, by a) providing a plurality of die members (4a, 4b) connected to respective electrical contact members (8a, 8b) in a mould; b) providing a mould insert in contact with at least a part of a first upper surface (6a) of a first die member (4a); c) encasing the plurality of die members (4a, 4b) and the respective electrical contact members (8a, 8b) into a package collection body (3); and d) cutting the package collection body (3) into at least two separate integrated circuit packages (3a, 3b) along a first cutting line (S1) extending through the package collection body (3) and separating the plurality of die members (4a, 4b). The mould insert as provided in step b) extends across a part of the first cutting line (S1).

Abstract: An LED module, including a carrier having high reflectivity, wherein a metal layer, preferably a silver layer or a layer of high-purity aluminum, is applied to the carrier. Also disclosed is an LED module, including a carrier having high reflectivity, wherein a metal layer is applied to the carrier, at least one LED chip, and a dam, wherein the metal layer partially covers the surface of the carrier lying under the dam.

Abstract: A semiconductor device includes an interposer having a first side and a second side opposite to the first side, at least one active chip mounted on the first side within a chip mounting area through a plurality of first bumps, at least one dummy chip mounted on the first side within a peripheral area being adjacent to the chip mounting area, a molding compound disposed on the first side. The molding compound covers the at least one active chip and the at least one dummy chip. A plurality of solder bumps is mounted on the second side.

Abstract: A sensor package structure includes a substrate, a sensor chip, a plurality of wires, a supporting frame, a transparent cover, and a molding compound. The substrate includes a chip bonding region and a plurality of first pads outside the chip bonding region. The sensor chip is disposed on the chip bonding region, and includes a sensing region and a plurality of second pads. Each wire has two opposite ends respectively connected to one of the first pads and one of the second pads. The supporting frame is arranged above the substrate and/or the sensor chip and includes a positioning portion. The transparent cover is fixed in position above the sensor chip by the positioning portion so as to maintain a vertical distance there-between. The molding compound fills the space in-between the substrate and the supporting frame and covers a part of an upper surface of the supporting frame.

Abstract: A semiconductor package includes a semiconductor chip, an encapsulant encapsulating the semiconductor chip, and a connection member disposed on at least one surface of the semiconductor chip and including an insulating layer and a plurality of redistribution layers electrically connected to the semiconductor chip. At least one of the plurality of redistribution layers includes a plurality of degassing holes penetrating therethrough in a thickness direction.

Abstract: Semiconductor packages and methods for forming a semiconductor package are presented. The semiconductor package includes a package substrate having a die region on a first surface thereof. The package includes a die having a sensing element. The die is disposed in the die region and is electrically coupled to contact pads disposed on the first surface of the package substrate by insulated wire bonds. A cap is disposed over the first surface of the package substrate. The cap and the first surface of the package substrate define an inner cavity which accommodates the die and the insulated wire bonds. The insulated wire bonds are directly exposed to an environment through at least one access port of the package.

Abstract: A semiconductor device includes a semiconductor element, a lead on which the semiconductor element is mounted, a bonding member fixing the semiconductor element to the lead, and a resin package enclosing the semiconductor element and a portion of the lead. This lead is formed with a groove recessed at a location spaced from the semiconductor element. The groove has first and second inner surfaces, where the first inner surface is closer to the semiconductor element than is the second inner surface. The angle the first inner surface forms with respect to the thickness direction of the semiconductor element is smaller than the angle the second inner surface forms with respect to the thickness direction.

Abstract: A substrate includes a substrate body and an interconnection layer disposed on a bearing surface of the substrate body and having an annular portion and a plurality of protrusions extending outward from an outer periphery of the annular portion. A package module is formed by the substrate, a chip mounted on the bearing surface of the substrate body, and a cap enclosing the chip and having a bottom thereof adhered to the interconnection layer of the substrate by an adhesive. By means of the protrusions of the interconnection layer, the bonding area of the adhesive is increased and the spread of the adhesive is effectively concentrated.

Abstract: Methods of magnetically shielding an MRAM structure on all six sides in a thin wire or thin flip chip bonding package and the resulting devices are provided. Embodiments include forming a first metal layer embedded between an upper and a lower portion of a PCB substrate, the first metal layer having a pair of metal filled vias laterally separated; attaching a semiconductor die to the upper portion of the PCB substrate between the pair of metal filled vias; connecting the semiconductor die electrically to the PCB substrate through the pair of metal filled vias; removing a portion of the upper portion of the PCB substrate outside of the pair of metal filled vias down to the first metal layer; and forming a second metal layer over and on four opposing sides of the semiconductor die, the second metal layer landed on the first metal layer.

Abstract: An aluminum foil includes a first main surface and a second main surface located opposite to the first main surface. In at least one of the first main surface and the second main surface, a surface roughness Ra is not more than 10 nm, a surface roughness Rz is not more than 40 nm in each of a rolling direction and a direction perpendicular to the rolling direction, and the number of peak counts is not less than 10 when a reference length is 40 ?m, the number of peak counts being determined from a roughness curve in at least one of the rolling direction and the direction perpendicular to the rolling direction.

Abstract: An electronic component package includes a frame having a cavity, an electronic component disposed in the cavity of the frame, a first metal layer disposed on an inner wall of the cavity of the frame, an encapsulant encapsulating the electronic component, and a redistribution layer disposed below the frame and the electronic component.

Abstract: An integrated circuit package assembly includes a first integrated circuit package and a second integrated circuit package. The first integrated circuit package includes a first integrated circuit die mounted on a first substrate. The second integrated circuit package includes a second integrated circuit die mounted on a second substrate. The second integrated circuit package is disposed under the first integrated circuit package. Solder bumps are disposed between the first integrated circuit package and the second integrated circuit package and provide electrical signal connections between the first integrated circuit die and the second integrated circuit die. A buffer layer is disposed between the first substrate and the second integrated circuit die to facilitate thermal conduction between the first integrated circuit package and the second integrated circuit package.

Abstract: An integrated circuit (IC) includes a lead frame that has a set of leads coupled to a corresponding set of pins. A semiconductor die with contacts is coupled to the set of leads. Encapsulating material encloses the semiconductor die, such that the set of pins extend beyond the encapsulating material. An additive coating covers one or more of the plurality of pins.

Abstract: An electromagnetic interference shielding structure is disclosed. The electromagnetic interference shielding structure includes an insulating member covering at least one circuit element mounted on a printed circuit board (PCB), a shielding member covering the insulating member, and a heat dissipator having a surface adhering to the shielding member to transfer heat emitted from the at least one circuit element to a place where temperature is relatively low.

Abstract: An adhesive composition for semiconductors, an adhesive film, and a semiconductor device, wherein, in a curing process including a first stage at a temperature ranging from 120° C. to 130° C. for 1 to 20 minutes, a second stage at a temperature ranging from 140° C. to 150° C. for 1 to 10 minutes, a third stage at a temperature ranging from 160° C. to 180° C. for 30 seconds to 10 minutes, and a fourth stage at a temperature ranging from 160° C. to 180° C. for 10 minutes to 2 hours, the adhesive film has a DSC curing rate in the first stage that is 40% or less of a total curing rate, a DSC curing rate in the fourth stage that is 30% to 60% higher than a DSC curing rate in the third stage, and DSC curing rates in each of the second and third stages that are 5% or more higher than a DSC curing rate of a preceding stage thereof.

Abstract: A gas sensor package comprises a gas sensor chip with a layer sensitive to a gas, and with a heater for heating the sensitive layer. Contact pads are provided for electrically contacting the gas sensor package and a die pad is provided for mounting the gas sensor chip to. Electrical connections connect the gas sensor chip and the contact pads. A molding compound at least partially encloses the gas sensor chip. An opening in the molding compound provides access to the sensitive layer of the gas sensor chip. One of the contact pads serves as a pin for supplying electrical current to the heater of the gas sensor chip.

Abstract: An electronic component package that includes a heat spreader with a die pad. An electronic component is attached to each side of the die pad where each electronic component includes conductive terminals on a side facing away from the die pad. Conductive terminals of the top electronic component are wirebonded to conductive surfaces of a package substrate and conductive terminals of the bottom electronic component are physically and electrically attached to conductive surfaces of the package substrate. The heat spreader structure includes tie structures that extend in a direction away from the second electronic component.

Abstract: A device comprises a package component comprising a plurality of bumps formed on a first side of the package component, a semiconductor die mounted on the first side of the package component, a dielectric material formed over the first side of the package component, wherein four corners of the top surface of the package component are free from the dielectric material and a top package bonded on the first side of the package component, wherein the semiconductor die is located between the top package and the package component.

Abstract: A semiconductor package and a manufacturing method thereof are disclosed. The semiconductor package includes a device carrier and a stiffener structure. The device carrier includes at least one insulating layer and at least conductive layer defining at least one trace layout unit. The stiffener structure is disposed on the device carrier, surrounding the periphery of the at least one trace layout unit. The stiffener structure is disposed away from the periphery of the at least one trace layout unit, forming a cavity with the device carrier. The shape and disposition of the stiffener structure enhance the strength of the semiconductor package, impeding flexure to the semiconductor package.

Abstract: An electronic component package includes a frame having a cavity, an electronic component disposed in the cavity of the frame, a first metal layer disposed on an inner wall of the cavity of the frame, an encapsulant encapsulating the electronic component, and a redistribution layer disposed below the frame and the electronic component.