With Dam Or Vent For Encapsulant Patents (Class 257/667)
  • Patent number: 10644225
    Abstract: According to one embodiment, a magnetic memory device includes a magnetic memory chip having a magnetoresistive element, a magnetic layer having first and second portions spacing out each other, the first portion covering a first main surface of the magnetic memory chip, the second portion covering a second main surface facing the first main surface of the magnetic memory chip, a circuit board on which the magnetic layer is mounted, and a bonding wire connecting between the magnetic memory chip and the circuit board in a first direction parallel to the first and second main surfaces.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: May 5, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Takeshi Fujimori
  • Patent number: 10624248
    Abstract: An electromagnetic interference (EMI) shielding structure and a method for manufacturing are provided. The EMI shielding structure includes a printed circuit board (PCB) on which a plurality of elements are mounted, an insulation molding member configured to cover the plurality of elements, a conductive shielding dam formed along a side surface of the insulation molding member, and a conductive shielding member formed on a top surface of the insulation molding member.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: April 14, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyong-il Kim, Keon Kuk, Il-ju Mun, O-hyun Beak
  • Patent number: 10617034
    Abstract: The present disclosure relates to an enclosed electronic module with single/multiple active components and an integrated heat dissipation system, including a top housing formed with one or more openings, a heat sink mounted on an outer surface of the top housing over the opening(s) thereof, a bottom housing coupled with the top housing, one or more active components mounted on a PCB between the top and bottom housings, and at least one thermal block or vapor chamber thermally connected between the heat sink and the active component(s), thereby forming one or more thermal dissipation paths extending from the active component(s), through the at least one thermal block or vapor chamber, and to the heat sink.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: April 7, 2020
    Assignee: CLOUD LIGHT TECHNOLOGY LIMITED
    Inventors: Gad Joseph Hubahib Gaviola, Vincent Wai Hung, Margarito P. Banal, Jr., Vivian Wei Ma
  • Patent number: 10600944
    Abstract: A lead frame includes a first electrode, a second electrode, two hanger leads, and an outer frame, and partially forms a box-shaped package which has a first recess for mounting a light emitting element as combined with a support member that supports the first electrode and the second electrode. At least a portion of lower faces of the electrodes, at least a portion of lower faces of the hanger leads, and at least a portion of a lower face of the planned formation area for the support member are coplanarly formed. Lower face corners of the first electrode and the second electrode are rounded while upper face corners of the first electrode and the second electrode are not rounded, and upper face corners of the hanger leads are rounded while lower face corners of the hanger leads are not rounded.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: March 24, 2020
    Assignee: NICHIA CORPORATION
    Inventor: Mayumi Fukuda
  • Patent number: 10593567
    Abstract: Method of making an integrated circuit package, by a) providing a plurality of die members (4a, 4b) connected to respective electrical contact members (8a, 8b) in a mould; b) providing a mould insert in contact with at least a part of a first upper surface (6a) of a first die member (4a); c) encasing the plurality of die members (4a, 4b) and the respective electrical contact members (8a, 8b) into a package collection body (3); and d) cutting the package collection body (3) into at least two separate integrated circuit packages (3a, 3b) along a first cutting line (S1) extending through the package collection body (3) and separating the plurality of die members (4a, 4b). The mould insert as provided in step b) extends across a part of the first cutting line (S1).
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: March 17, 2020
    Assignee: Sencio B.V.
    Inventors: Ignatius Josephus van Dommelen, Johannes Stephanus Jansen
  • Patent number: 10586901
    Abstract: An LED module, including a carrier having high reflectivity, wherein a metal layer, preferably a silver layer or a layer of high-purity aluminum, is applied to the carrier. Also disclosed is an LED module, including a carrier having high reflectivity, wherein a metal layer is applied to the carrier, at least one LED chip, and a dam, wherein the metal layer partially covers the surface of the carrier lying under the dam.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: March 10, 2020
    Assignee: TRIDONIC JENNERSDORF GMBH
    Inventors: Florian Wimmer, Peter Pachler, Norbert Reitinger, Juergen Gumhold
  • Patent number: 10446509
    Abstract: A semiconductor device includes an interposer having a first side and a second side opposite to the first side, at least one active chip mounted on the first side within a chip mounting area through a plurality of first bumps, at least one dummy chip mounted on the first side within a peripheral area being adjacent to the chip mounting area, a molding compound disposed on the first side. The molding compound covers the at least one active chip and the at least one dummy chip. A plurality of solder bumps is mounted on the second side.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: October 15, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Shing-Yih Shih, Neng-Tai Shih
  • Patent number: 10411055
    Abstract: A sensor package structure includes a substrate, a sensor chip, a plurality of wires, a supporting frame, a transparent cover, and a molding compound. The substrate includes a chip bonding region and a plurality of first pads outside the chip bonding region. The sensor chip is disposed on the chip bonding region, and includes a sensing region and a plurality of second pads. Each wire has two opposite ends respectively connected to one of the first pads and one of the second pads. The supporting frame is arranged above the substrate and/or the sensor chip and includes a positioning portion. The transparent cover is fixed in position above the sensor chip by the positioning portion so as to maintain a vertical distance there-between. The molding compound fills the space in-between the substrate and the supporting frame and covers a part of an upper surface of the supporting frame.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: September 10, 2019
    Assignee: KINGPAK TECHNOLOGY INC.
    Inventors: Chun-Hua Chuang, Wen-Chung Huang, Chung-Hsien Hsin, Chen-Pin Peng, Li-Chun Hung
  • Patent number: 10396005
    Abstract: A semiconductor package includes a semiconductor chip, an encapsulant encapsulating the semiconductor chip, and a connection member disposed on at least one surface of the semiconductor chip and including an insulating layer and a plurality of redistribution layers electrically connected to the semiconductor chip. At least one of the plurality of redistribution layers includes a plurality of degassing holes penetrating therethrough in a thickness direction.
    Type: Grant
    Filed: May 2, 2018
    Date of Patent: August 27, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Min Kyu Kim
  • Patent number: 10381280
    Abstract: Semiconductor packages and methods for forming a semiconductor package are presented. The semiconductor package includes a package substrate having a die region on a first surface thereof. The package includes a die having a sensing element. The die is disposed in the die region and is electrically coupled to contact pads disposed on the first surface of the package substrate by insulated wire bonds. A cap is disposed over the first surface of the package substrate. The cap and the first surface of the package substrate define an inner cavity which accommodates the die and the insulated wire bonds. The insulated wire bonds are directly exposed to an environment through at least one access port of the package.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: August 13, 2019
    Assignee: UTAC HEADQUARTERS PTE. LTD.
    Inventors: Nathapong Suthiwongsunthorn, John Ducyao Beleran, Serafin Padilla Pedron, Jr.
  • Patent number: 10340208
    Abstract: A semiconductor device includes a semiconductor element, a lead on which the semiconductor element is mounted, a bonding member fixing the semiconductor element to the lead, and a resin package enclosing the semiconductor element and a portion of the lead. This lead is formed with a groove recessed at a location spaced from the semiconductor element. The groove has first and second inner surfaces, where the first inner surface is closer to the semiconductor element than is the second inner surface. The angle the first inner surface forms with respect to the thickness direction of the semiconductor element is smaller than the angle the second inner surface forms with respect to the thickness direction.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: July 2, 2019
    Assignee: ROHM CO., LTD.
    Inventor: Motoharu Haga
  • Patent number: 10312169
    Abstract: A substrate includes a substrate body and an interconnection layer disposed on a bearing surface of the substrate body and having an annular portion and a plurality of protrusions extending outward from an outer periphery of the annular portion. A package module is formed by the substrate, a chip mounted on the bearing surface of the substrate body, and a cap enclosing the chip and having a bottom thereof adhered to the interconnection layer of the substrate by an adhesive. By means of the protrusions of the interconnection layer, the bonding area of the adhesive is increased and the spread of the adhesive is effectively concentrated.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: June 4, 2019
    Assignee: LINGSEN PRECISION INDUSTRIES, LTD.
    Inventors: Yu-Shiang Chen, Chao-Wei Yu, Yu-Lin Hsiao, Ming-Te Tu
  • Patent number: 10290678
    Abstract: Methods of magnetically shielding an MRAM structure on all six sides in a thin wire or thin flip chip bonding package and the resulting devices are provided. Embodiments include forming a first metal layer embedded between an upper and a lower portion of a PCB substrate, the first metal layer having a pair of metal filled vias laterally separated; attaching a semiconductor die to the upper portion of the PCB substrate between the pair of metal filled vias; connecting the semiconductor die electrically to the PCB substrate through the pair of metal filled vias; removing a portion of the upper portion of the PCB substrate outside of the pair of metal filled vias down to the first metal layer; and forming a second metal layer over and on four opposing sides of the semiconductor die, the second metal layer landed on the first metal layer.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: May 14, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Shan Gao, Boo Yang Jung
  • Patent number: 10166580
    Abstract: An aluminum foil includes a first main surface and a second main surface located opposite to the first main surface. In at least one of the first main surface and the second main surface, a surface roughness Ra is not more than 10 nm, a surface roughness Rz is not more than 40 nm in each of a rolling direction and a direction perpendicular to the rolling direction, and the number of peak counts is not less than 10 when a reference length is 40 ?m, the number of peak counts being determined from a roughness curve in at least one of the rolling direction and the direction perpendicular to the rolling direction.
    Type: Grant
    Filed: January 22, 2016
    Date of Patent: January 1, 2019
    Assignee: TOYO ALUMINIUM KABUSHIKI KAISHA
    Inventors: Akira Shingu, Mitsunari Ooyagi
  • Patent number: 10170386
    Abstract: An electronic component package includes a frame having a cavity, an electronic component disposed in the cavity of the frame, a first metal layer disposed on an inner wall of the cavity of the frame, an encapsulant encapsulating the electronic component, and a redistribution layer disposed below the frame and the electronic component.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: January 1, 2019
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Seung On Kang, Woo Sung Han, Young Gwan Ko, Chul Kyu Kim, Han Kim
  • Patent number: 10163865
    Abstract: An integrated circuit package assembly includes a first integrated circuit package and a second integrated circuit package. The first integrated circuit package includes a first integrated circuit die mounted on a first substrate. The second integrated circuit package includes a second integrated circuit die mounted on a second substrate. The second integrated circuit package is disposed under the first integrated circuit package. Solder bumps are disposed between the first integrated circuit package and the second integrated circuit package and provide electrical signal connections between the first integrated circuit die and the second integrated circuit die. A buffer layer is disposed between the first substrate and the second integrated circuit die to facilitate thermal conduction between the first integrated circuit package and the second integrated circuit package.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Hsien-Wei Chen
  • Patent number: 10147672
    Abstract: An integrated circuit (IC) includes a lead frame that has a set of leads coupled to a corresponding set of pins. A semiconductor die with contacts is coupled to the set of leads. Encapsulating material encloses the semiconductor die, such that the set of pins extend beyond the encapsulating material. An additive coating covers one or more of the plurality of pins.
    Type: Grant
    Filed: April 20, 2016
    Date of Patent: December 4, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Yong Lin, Sadia Arefin Khan, Benjamin Stassen Cook
  • Patent number: 10068832
    Abstract: An electromagnetic interference shielding structure is disclosed. The electromagnetic interference shielding structure includes an insulating member covering at least one circuit element mounted on a printed circuit board (PCB), a shielding member covering the insulating member, and a heat dissipator having a surface adhering to the shielding member to transfer heat emitted from the at least one circuit element to a place where temperature is relatively low.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: September 4, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun-bong Han, Hyeon-hyang Kim
  • Patent number: 9957425
    Abstract: An adhesive composition for semiconductors, an adhesive film, and a semiconductor device, wherein, in a curing process including a first stage at a temperature ranging from 120° C. to 130° C. for 1 to 20 minutes, a second stage at a temperature ranging from 140° C. to 150° C. for 1 to 10 minutes, a third stage at a temperature ranging from 160° C. to 180° C. for 30 seconds to 10 minutes, and a fourth stage at a temperature ranging from 160° C. to 180° C. for 10 minutes to 2 hours, the adhesive film has a DSC curing rate in the first stage that is 40% or less of a total curing rate, a DSC curing rate in the fourth stage that is 30% to 60% higher than a DSC curing rate in the third stage, and DSC curing rates in each of the second and third stages that are 5% or more higher than a DSC curing rate of a preceding stage thereof.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: May 1, 2018
    Assignee: CHEIL INDUSTRIES, INC.
    Inventors: Jun Woo Lee, Sung Min Kim, In Hwan Kim, Baek Soung Park, Su Mi Lim, Jae Won Choi
  • Patent number: 9952171
    Abstract: A gas sensor package comprises a gas sensor chip with a layer sensitive to a gas, and with a heater for heating the sensitive layer. Contact pads are provided for electrically contacting the gas sensor package and a die pad is provided for mounting the gas sensor chip to. Electrical connections connect the gas sensor chip and the contact pads. A molding compound at least partially encloses the gas sensor chip. An opening in the molding compound provides access to the sensitive layer of the gas sensor chip. One of the contact pads serves as a pin for supplying electrical current to the heater of the gas sensor chip.
    Type: Grant
    Filed: June 2, 2015
    Date of Patent: April 24, 2018
    Assignee: Sensirion AG
    Inventors: Werner Hunziker, David Pustan, Stephen Braun
  • Patent number: 9953904
    Abstract: An electronic component package that includes a heat spreader with a die pad. An electronic component is attached to each side of the die pad where each electronic component includes conductive terminals on a side facing away from the die pad. Conductive terminals of the top electronic component are wirebonded to conductive surfaces of a package substrate and conductive terminals of the bottom electronic component are physically and electrically attached to conductive surfaces of the package substrate. The heat spreader structure includes tie structures that extend in a direction away from the second electronic component.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: April 24, 2018
    Assignee: NXP USA, INC.
    Inventors: Navas Khan Oratti Kalandar, Akhilesh Kumar Singh, Nishant Lakhera
  • Patent number: 9911687
    Abstract: A device comprises a package component comprising a plurality of bumps formed on a first side of the package component, a semiconductor die mounted on the first side of the package component, a dielectric material formed over the first side of the package component, wherein four corners of the top surface of the package component are free from the dielectric material and a top package bonded on the first side of the package component, wherein the semiconductor die is located between the top package and the package component.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: March 6, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Hsien-Wei Chen
  • Patent number: 9847268
    Abstract: A semiconductor package and a manufacturing method thereof are disclosed. The semiconductor package includes a device carrier and a stiffener structure. The device carrier includes at least one insulating layer and at least conductive layer defining at least one trace layout unit. The stiffener structure is disposed on the device carrier, surrounding the periphery of the at least one trace layout unit. The stiffener structure is disposed away from the periphery of the at least one trace layout unit, forming a cavity with the device carrier. The shape and disposition of the stiffener structure enhance the strength of the semiconductor package, impeding flexure to the semiconductor package.
    Type: Grant
    Filed: November 20, 2009
    Date of Patent: December 19, 2017
    Assignee: ADVANPACK SOLUTIONS PTE. LTD.
    Inventors: Shoa Siong Lim, Kian Hock Lim
  • Patent number: 9842789
    Abstract: An electronic component package includes a frame having a cavity, an electronic component disposed in the cavity of the frame, a first metal layer disposed on an inner wall of the cavity of the frame, an encapsulant encapsulating the electronic component, and a redistribution layer disposed below the frame and the electronic component.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: December 12, 2017
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Seung On Kang, Woo Sung Han, Young Gwan Ko, Chul Kyu Kim, Han Kim
  • Patent number: 9812385
    Abstract: An electronic component package according to one aspect of the present disclosure includes a metal pattern layer having a first principal surface and a second principal surface, an electronic component disposed on the first principal surface and electrically connected to the metal pattern layer, at least one metal member disposed on the first principal surface and electrically connected to the metal pattern layer, a sealing resin layer disposed on the first principal surface, the electronic component and the at least one metal member, and an insulating layer disposed on the second principal surface. The at least one metal member is thicker than the electronic component. In plan view, the at least one metal member is disposed on an area of the first principal surface, the area including an end of the first principal surface. The at least a part of the metal pattern layer is exposed from the insulating layer.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: November 7, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Koji Kawakita, Takashi Ichiryu, Masanori Nomura
  • Patent number: 9806035
    Abstract: A non-leaded semiconductor device comprises a sealing body for sealing a semiconductor chip, a tab in the interior of the sealing body, suspension leads for supporting the tab, leads having respective surfaces exposed to outer edge portions of a back surface of the sealing body, and wires connecting pads formed on the semiconductor chip and the leads. End portions of the suspension leads positioned in an outer periphery portion of the sealing body are unexposed to the back surface of the sealing body, but are covered with the sealing body. Stand-off portions of the suspending leads are not formed in resin molding. When cutting the suspending leads, corner portions of the back surface of the sealing body are supported by a flat portion of a holder portion in a cutting die having an area wider than a cutting allowance of the suspending leads, whereby chipping of the resin is prevented.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: October 31, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Tadatoshi Danno, Hiroyoshi Taya, Yoshiharu Shimizu
  • Patent number: 9742968
    Abstract: An image acquisition system, in particular for automotive applications, includes: a substrate; an image sensor mounted on the substrate and contacted via contact points; an optically transparent sealing compound that covers the image sensor, the contact points, and a portion of the upper substrate side; an optical device being arranged or secured in or on the sealing compound. The optical device can be placed into the sealing compound after shaping of the sealing compound or directly. Furthermore, the optical device can also be arranged directly by shaping the sealing compound. Manufacture of the image acquisition system can be incorporated into a board populating process.
    Type: Grant
    Filed: January 26, 2007
    Date of Patent: August 22, 2017
    Assignee: ROBERT BOSCH GMBH
    Inventors: Ulrich Seger, Gerald Franz
  • Patent number: 9661745
    Abstract: In accordance with disclosed embodiments, there are provided methods, systems, and apparatuses for vacuum lamination of a depth-sensing camera module PCB to a stiffener using built-in vacuum channels.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: May 23, 2017
    Assignee: Intel Corporation
    Inventors: Kyle Yazzie, Pramod Malatkar
  • Patent number: 9640501
    Abstract: A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar has at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: May 2, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Virendra R. Jadhav, Krystyna W. Semkow, Kamalesh K. Srivastava, Brian R. Sundlof
  • Patent number: 9640492
    Abstract: A laminate includes a core, a buildup layer having a top and a bottom, the bottom contacting the core and a solder mask contacting the top, the solder mask including at least one warpage control region formed on a top surface of the solder mask.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: May 2, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Charles L. Arvin, Brian M. Erwin, Brian W. Quinlan
  • Patent number: 9627302
    Abstract: An object is to provide a technique in which a cost reduction in a power semiconductor device can be achieved while maintaining heat dissipation performance as much as possible. A power semiconductor device includes a leadframe, a power semiconductor element disposed on an upper surface of the leadframe, and an insulating layer disposed on a lower surface of the leadframe. At least a partial line of a peripheral line of a region where the insulating layer is disposed, on the lower surface, is aligned, in top view, with at least a partial line of an expanded peripheral line obtained by shifting outwardly, by the amount corresponding to the thickness of the leadframe, the peripheral line of the region where the power semiconductor element is disposed, on the upper surface.
    Type: Grant
    Filed: January 10, 2014
    Date of Patent: April 18, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventors: Keitaro Ichikawa, Taketoshi Shikano
  • Patent number: 9627305
    Abstract: A semiconductor package includes a support substrate having opposing first and second main surfaces and sides between the first and second main surfaces, a semiconductor die attached to one of the main surfaces of the support substrate, and an encapsulation material at least partly covering the support substrate and the semiconductor die. A protrusion extends outward from a side of the support substrate and terminates in the encapsulation material. The protrusion forms an interlocked connection with the encapsulation material. The interlocked connection increases the tensile strength of the interface between the encapsulation material and the side of the support substrate with the protrusion.
    Type: Grant
    Filed: July 11, 2013
    Date of Patent: April 18, 2017
    Assignee: Infineon Technologies AG
    Inventors: Georg Meyer-Berg, Reinhard Pufall, Michael Goroll, Rainer Dudek
  • Patent number: 9620557
    Abstract: A semiconductor device has a substrate containing a transparent or translucent material. A spacer is mounted to the substrate. A first semiconductor die has an active region and first conductive vias electrically connected to the active region. The active region can include a sensor responsive to light received through the substrate. The first die is mounted to the spacer with the active region positioned over an opening in the spacer and oriented toward the substrate. An encapsulant is deposited over the first die and substrate. An interconnect structure is formed over the encapsulant and first die. The interconnect structure is electrically connected through the first conductive vias to the active region. A second semiconductor die having second conductive vias can be mounted to the first die with the first conductive vias electrically connected to the second conductive vias.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: April 11, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Seng Guan Chow, Lee Sun Lim, Rui Huang, Xu Sheng Bao, Ma Phoo Pwint Hlaing
  • Patent number: 9620438
    Abstract: An electronic device includes an integrated circuit chip mounted to a heat slug. The heat slug has a peripheral region having first thickness along a first direction, the peripheral region surrounding a recess region (having a second, smaller, thickness along the first direction) that defines a chip mounting surface along a second direction perpendicular to the first direction. The recess region defines side borders and a nook extends into the heat slug along the side borders. An insulating body embeds the integrated circuit one chip and heat slug. Material of the insulating body fills the nook.
    Type: Grant
    Filed: February 6, 2015
    Date of Patent: April 11, 2017
    Assignees: STMICROELECTRONICS (MALTA) LTD, STMICROELECTRONICS S.R.L., STMICROELECTRONICS PTE LTD
    Inventors: Roseanne Duca, Valter Motta, Xueren Zhang, Kim-Yong Goh
  • Patent number: 9601415
    Abstract: In a method of manufacturing a semiconductor device according to an embodiment, a lead frame is provided, the lead frame having a trench part formed thereon so as to communicate bottom surfaces of a first lead and a second lead, which are coupled to each other between device regions adjacent to each other. Then, after a part of a coupling part between the first and second leads is cut by using a first blade, metal wastes formed inside the trench part are removed. Then, after the metal wastes are removed, a metal film is formed on exposed surfaces of the first and second leads by a plating method, and then, a remaining part of the coupling part between the first and second leads is cut by using a second blade. At this time, the cutting is performed so that the second blade does not contact the trench part.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: March 21, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yasutomo Makino
  • Patent number: 9573800
    Abstract: A MEMS lead frame package body encloses a MEMS device enclosed in an internal cavity formed by the mold body and cover. To accommodate a MEMS microphone, an acoustic aperture extends through the mold body. In some embodiments, a conductive column extends through the pre-molded body to allow electrical connection from a partially encapsulated lead frame to the conductive cover. Some embodiments may include a multi-tiered cavity within the mold body for mounting an integrated circuit separated by a gap above the MEMS device.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: February 21, 2017
    Assignee: INVENSENSE, INC.
    Inventor: Thomas M. Goida
  • Patent number: 9502342
    Abstract: A method of fabricating a package-on-package (PoP) type of semiconductor package may include providing a lower package with a lower substrate, a lower semiconductor chip, and a lower mold layer and providing an upper package with an upper substrate, an upper semiconductor chip, and an upper mold layer. A through hole is formed to penetrate the upper package, and the upper package and lower package are electrically connected. A thermal interface material is injected into the through hole to form a first heat transmission part between, and in contact with, the upper package and the lower package.
    Type: Grant
    Filed: July 16, 2015
    Date of Patent: November 22, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Ilho Kim
  • Patent number: 9425161
    Abstract: An embodiment of a method of attaching a semiconductor die to a substrate includes placing a bottom surface of the die over a top surface of the substrate with an intervening die attach material. The method further includes contacting a top surface of the semiconductor die and the top surface of the substrate with a conformal structure that includes a non-solid, pressure transmissive material, and applying a pressure to the conformal structure. The pressure is transmitted by the non-solid, pressure transmissive material to the top surface of the semiconductor die. The method further includes, while applying the pressure, exposing the assembly to a temperature that is sufficient to cause the die attach material to sinter. Before placing the die over the substrate, conductive mechanical lock features may be formed on the top surface of the substrate, and/or on the bottom surface of the semiconductor die.
    Type: Grant
    Filed: July 24, 2015
    Date of Patent: August 23, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Lakshminarayan Viswanathan, L. M. Mahalingam, David F. Abdo, Jaynal A. Molla
  • Patent number: 9397033
    Abstract: The semiconductor device in accordance with one mode comprises a semiconductor chip; a chip mounting substrate on which the semiconductor chip is mounted; a chip container that is provided on the chip mounting substrate and contains the semiconductor chip; and a seal part that seals the chip container containing the semiconductor chip and the chip mounting substrate. The chip container has a frame part surrounding a periphery of the semiconductor chip. The height of the frame part is greater than that of the semiconductor chip. The inside of the frame part in the chip container is provided with a chip coating material that protects the semiconductor chip.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: July 19, 2016
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Masaki Furumai
  • Patent number: 9349674
    Abstract: A wiring board unit includes: a polygonal wiring board having three or more sides in top view, a product insulating part comprising a plurality of external terminals, and a dummy insulating part at an outer edge of one of the at least three sides; and a lead frame including a frame having an inner edge defining an opening within which the wiring board is disposed in top view, and a plurality of leads, one end of each of the plurality of leads connected to the inner edge of the frame and the other end of each of the plurality of leads respectively connected to one of the plurality of external terminals of the wiring board, wherein a connection unit for connecting the frame of the lead frame and the dummy insulating part of the wiring board is arranged therebetween.
    Type: Grant
    Filed: May 21, 2014
    Date of Patent: May 24, 2016
    Assignee: NGK SPARK PLUG CO., LTD.
    Inventors: Kensuke Matsuhashi, Sadahiro Nishimura
  • Patent number: 9279902
    Abstract: An optical module for an optical unit associated with forming a light curtain for monitoring a protective or surveillance field. The optical module includes at least one radiation emitting and/or radiation receiving element for transmitting and/or receiving a radiation beam associated with forming a light curtain. The optical module includes a module body for mounting a radiation transmitter/receiver carrier that carries the at least one transmitting and/or receiving element associated with the radiation beam. The module body has at least one alignment element for aligning the optical module within a support element that forms an outer housing of the optical unit.
    Type: Grant
    Filed: May 2, 2013
    Date of Patent: March 8, 2016
    Assignee: Rockwell Automation Safety AG
    Inventors: Carl Meinherz, Richard Casty, Danilo Dorizzi, Martin Hardegger, Manfred Norbert Stein, Clau Lombriser, Guido Baumgartner
  • Patent number: 9257372
    Abstract: A surface mount package of a semiconductor device, has: an encapsulation, housing at least one die including semiconductor material; and electrical contact leads, protruding from the encapsulation to be electrically coupled to contact pads of a circuit board; the encapsulation has a main face designed to face a top surface of the circuit board, which is provided with coupling features designed for mechanical coupling to the circuit board to increase a resonant frequency of the mounted package. The coupling features envisage at least a first coupling recess defined within the encapsulation starting from the main face, designed to be engaged by a corresponding coupling element fixed to the circuit board, thereby restricting movements of the mounted package.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: February 9, 2016
    Assignees: STMicroelectronics (Mala) Ltd, STMicroelectronics Pte Ltd
    Inventors: Roseanne Duca, Kim-Yong Goh, Xueren Zhang, Kevin Formosa
  • Patent number: 9224676
    Abstract: Packages for an integrated circuit die and methods and leadframes for making such packages are disclosed. The package includes a die, a die pad, peripheral metal contacts, bond wires, and an encapsulant. The die pad and contacts are located at a lower surface of the package. The die pad and the contacts have side surfaces which include reentrant portions and asperities to engage the encapsulant. A method of making a package includes providing a metal leadframe having a die pad in a rectangular frame. Tabs extend from the frame toward the die pad. The die pad and tabs have side surfaces with reentrant portions and asperities. A die is attached to the die pad. The die is electrically connected to the tabs. An encapsulant is applied to the upper and side surfaces of the leadframe. Finally, the leadframe is cut in situ so that the die pad and tabs are severed from the frame, the sides of the package are formed, and the package is severed from the leadframe.
    Type: Grant
    Filed: January 8, 2015
    Date of Patent: December 29, 2015
    Inventor: Thomas P. Glenn
  • Patent number: 9196576
    Abstract: A semiconductor device has a die mounted on a die paddle that is elevated above and thermally connected via tie bars to a heat sink structure. Heat generated by the die flows from the die to the die paddle to the tie bars to the heat sink structure and then to either the external environment or to an external heat sink. By elevating the die/paddle sub-assembly above the heat sink structure, the packaged device is less susceptible to delamination between the die and die attach adhesive and/or the die attach adhesive and the die paddle. An optional heat sink ring can surround the die paddle.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: November 24, 2015
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Kai Yun Yow, Poh Leng Eu, Meng Kong Lye, You Ge, Penglin Mei
  • Patent number: 9130064
    Abstract: A semiconductor package and a method for fabricating the same are provided. A leadframe including a die pad and a plurality of peripheral leads is provided. A carrier, having a plurality of connecting pads formed thereon, is attached to the die pad, wherein a planar size of the carrier s greater than that of the die pad, allowing the connecting pads on the carrier to be exposed from the die pad. At least a semiconductor chip is attached to a side of an assembly including the die pad and the carrier, and is electrically connected to the connecting pads of the carrier and the leads via bonding wires. A package encapsulant encapsulates the semiconductor chip, the bonding wires, a part of the carrier and a part of the leadframe, allowing a bottom surface of the carrier and a part of the leads to be exposed from the package encapsulant.
    Type: Grant
    Filed: November 21, 2013
    Date of Patent: September 8, 2015
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chang-Yueh Chan, Chih-Ming Huang, Chun-Yuan Li, Chih-Hsin Lai
  • Patent number: 9082777
    Abstract: Embodiments of the present invention disclose a method for encapsulating a component with plastic and its encapsulation structure, which belong to the plastic encapsulation technology field. The method includes: processing, by using the surface mounting technology, a first surface of a part to be encapsulated with plastic and/or performing die bonding on the first surface; encapsulating, with plastic, the first surface of the part to be encapsulated with plastic a second surface of the part to be encapsulated with plastic the first surface and/or performing die bonding in the second face; and encapsulating, with plastic, the second surface of the part to be encapsulated with plastic. This encapsulation structure includes a substrate, where components are fixed on an upper surface and a lower surface of the substrate, and the components on the upper surface and lower surface are all encapsulated with plastic in seal.
    Type: Grant
    Filed: December 11, 2012
    Date of Patent: July 14, 2015
    Assignee: HUAWEI DEVICE CO., LTD.
    Inventor: Xiong Yang
  • Patent number: 9070679
    Abstract: Embodiments of the present disclosure provide configurations for a semiconductor package and associated methods of fabricating the semiconductor package. A method of fabricating a semiconductor package includes attaching a semiconductor die to a first substrate, attaching a second substrate to the first substrate, wherein the semiconductor die is embedded in between the first substrate and the second substrate, and forming an electrically insulative structure to substantially encapsulate the semiconductor die, wherein forming the electrically insulative structure is performed subsequent to the second substrate being attached to the first substrate. Additional embodiments may be described and/or claimed.
    Type: Grant
    Filed: November 9, 2010
    Date of Patent: June 30, 2015
    Assignee: Marvell World Trade Ltd.
    Inventors: Albert Wu, Shiann-Ming Liou, Scott Wu
  • Patent number: 9035432
    Abstract: A method for producing a component having a semiconductor substrate with through-hole plating is provided, the through-plating being surrounded by a recess, and the semiconductor substrate having a first layer on one side, which covers the recess on the first side. The semiconductor substrate has a second layer on a second side, which covers the recess on the second side, and the through-hole plating is surrounded by a ring structure which is produced from the semiconductor substrate. The recess surrounding the ring structure is produced in the same process step or at the same time as the recess for the through-hole plating.
    Type: Grant
    Filed: June 11, 2013
    Date of Patent: May 19, 2015
    Assignee: ROBERT BOSCH GMBH
    Inventors: Jochen Reinmuth, Heribert Weber, Timo Schary, Yvonne Bergmann
  • Patent number: 9029992
    Abstract: In one embodiment, a semiconductor device includes a leadframe structure. A semiconductor die is attached to a die pad. Land connect bars are spaced apart from the die pad and a plurality of lands are between the land connect bars and the die pad and are spaced apart therefrom. Insulation members are adhered to the land connect bars and the plurality of lands to hold the land connect bars and the plurality of lands together and to electrically isolate them. An encapsulant covers the semiconductor die and at least portions of the plurality of lands, the die pad, and the land connect bars and further fills spaces between the land connect bars and the plurality of lands.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: May 12, 2015
    Assignee: Amkor Technology, Inc.
    Inventors: Sung Gyu Kim, Byong Jin Kim, Gi Jeong Kim
  • Publication number: 20150115421
    Abstract: A method and apparatus of minimizing resin bleed and mold flash on integrated lead finishes by providing groves on the external leads that can control the length of resin bleed.
    Type: Application
    Filed: October 28, 2013
    Publication date: April 30, 2015
    Inventors: Bernardo Gallegos, Yong Lin