Abstract: A method of manufacturing a semiconductor package system including: forming a leadframe having a passive device; encapsulating the passive device to form an encapsulant interposer; attaching a first die to the encapsulant interposer; forming a substrate interposer having a second die; and stacking the encapsulant interposer over the substrate interposer.

Abstract: A structure of a lead-frame matrix of photoelectron devices is provided. The lead-frame matrix is used to fabricate a first lead-frame array and a second lead-frame array. In the structure of the lead-frame matrix of the photoelectron devices, pins of the first lead-frame array and pins of the second lead-frame array are alternatively inserted.

Abstract: While a semiconductor device is provided with a plurality of element electrodes 5 formed on a semiconductor element 4 and a plurality of lead terminal electrodes 6 formed on a lead frame, the semiconductor device is equipped with a coupling conductor which electrically connects at least one electrode among the above-described element electrodes 5 to at least one electrode among the above-described lead terminal electrodes 6; the above-described coupling conductor is manufactured by a first conductor 1 and a second conductor 2, the major components of which are metals; the first conductor 1 has been electrically connected to the second conductor 2; and the element electrodes 5 and the lead terminal electrodes 6 have been electrically connected to the second conductor 2 respectively.

Abstract: A chip package having asymmetric molding includes a lead frame, a chip, an adhesive layer, bonding wires and a molding compound. The lead frame includes a turbulent plate and a frame body having inner lead portions and outer lead portions. The turbulent plate is bended downwards to form a concave portion. The first end of the turbulent plate is connected to the frame body, and the second end is lower than the inner lead portions. The chip is fixed under the inner lead portions through the adhesive layer. The bonding wires are connected between the chip and the inner lead portions. The molding compound encapsulates the chip, the bonding wires, and the turbulent plate. The ratio between the thickness of the molding compound over and under the concave portion is larger than 1. The thickness of the molding compound under and over the outer lead portions is not equal.

Abstract: A packaged electronic device (20) includes a die pad (30), leads (32) arranged around the die pad (30), and a die (24) attached to an upper surface (34) of the die pad (30) and electrically connected to the leads (32). A packaging material (28) encapsulates the die pad (30), the die (24), and the leads (32). The die pad (30) includes indentations (42) formed in the upper surface (34) along a sidewall (38) of the die pad (30). The die pad (30) further includes indentations (44) formed in a lower surface (36) of the die pad (30) along the sidewall. The packaging material (28) fills the indentations (42, 44) thereby promoting adhesion between the die pad (30) and the packaging material (28) so that the die pad (30) and packaging material (28) cannot readily delaminate.

Abstract: A lead frame includes a frame body defining an internal region, a plurality of leads extending from the frame body, and first and second stages that are disposed in the internal region. The first and second stages are sloped and are parallel to a first line along which a primary stream of a molten resin runs, so that slope angles of the stages are not substantially changed by the injection of the molten resin into the cavity.

Abstract: A semiconductor device according to the present invention includes an island provided on one surface of a resin substrate, an external terminal provided on the other surface of the substrate, a thermal pad provided on the other surface of the substrate in opposed relation to the island, a heat conduction portion extending through the substrate from the one surface to the other surface to connect the island to the thermal pad in a thermally conductive manner, and a solder resist portion provided on the other surface of the substrate and having a heat dissipation opening which defines a gap with respect to an outer periphery of the thermal pad and a terminal opening which exposes the external terminal.

Abstract: A semiconductor package 60 in which a region where a land pad 18 is formed is provided on an outer side of a region in which a flip-chip connecting pad 16 is formed, wherein a protecting member 39 is formed to expose the land pad 18 in the region in which the land pad 18 is formed, and the protecting member 39 includes a frame-shaped structure portion 39A disposed to surround the flip-chip connecting pad 16 and a support film portion 39B disposed on an outer side of the frame-shaped structure portion 39A, and a semiconductor device 70 using the semiconductor package 60.

Abstract: A semiconductor device having linear zigzag(s) for wire bonding is revealed, primarily comprising a chip, a plurality of leads made of a lead frame and a plurality of bonding wires electrically connecting the chip and the leads. At least one of the leads has a linear zigzag including a first finger and a second finger connected each other in a zigzag form. One end of one of the bonding wire is bonded to a bonding pad on the chip and the other end is selectively bonded to either the first finger or the second finger but not both in a manner that the wire-bonding direction of the bonding wire is parallel to or in a sharp angle with the direction of the connected fingers for easy wire bonding processes. Therefore, the semiconductor device can assemble chips with diverse dimensions or with diverse bonding pads layouts by flexible wire-bonding angles at linear zigzag to avoid electrical short between the adjacent leads.

Abstract: A redistributed lead frame for use in a molded plastic semiconductor package (38) is formed from an electrically conductive substrate by a sequential metal removal process. The process includes: (a) patterning a first side of an electrically conductive substrate to form an array of lands separated by channels, (b) disposing a first molding compound (18) within these channels, (c) patterning a second side of the electrically conductive substrate to form an array of chip attach sites (24) and routing circuits (26) electrically interconnecting the array of lands and the array of chip attach sites (24), (d) directly electrically interconnecting input/output pads on the at least one semiconductor device (28) to chip attach site members (24) of the array of chip attach sites (24), and (e) encapsulating the at least one semiconductor device (28), the array of chip attach sites (24) and the routing circuits (26) with a second molding compound (36).

Abstract: A leadframe includes a die pad and a plurality of leads corresponding to the die pad. The die pad for supporting a die is formed with a plurality of sides, each of the sides having at least one recess portion and at least one protrusion portion. The leads are substantially coplanar to the die pad. The leads include a plurality of first leads and a plurality of second leads. The first leads extend into the recess portions respectively, and the second leads are aligned with the protrusion portions. The length of the first leads is greater than that of the second leads. The length of wires electrically connecting the die to the leads or the die pad can be adjusted by the sides of the leadframe with the recess portion and the protrusion portion having a dimension corresponding to the leads, so as to save the manufacture cost of the leadframe.

Abstract: One aspect of the invention pertains to a semiconductor package having a die and a die attach pad with a plurality of spaced apart pedestals supported by a web. A die is mounted on the die attach pad such that the die is supported by at least a plurality of the pedestals. Selected edge regions of the die are arranged to overlie recessed regions of the die attach pad between adjacent pedestals. The die is electrically connected to at least some of the contact leads. An adhesive is arranged to secure the die to the die attach pad, with the thickness of the adhesive between the web of the die attach pad and the die being greater than the thickness of the adhesive between the die and the top surfaces of the pedestals that support the die. The die attach pad may have rounded peripheral corners between adjacent edge surfaces of the die attach pad.

Abstract: A semiconductor device includes a pair of power chips, an IC chip, a plurality of leads one of which having a die pad on which the power chips are mounted and another one having a die attach portion on which the IC chip is mounted, a resin sheet firmly adhered to one side of the die pad, and a resin casing made by molding operation to encapsulate the power chips, the IC chip and the resin sheet by a resin in such a manner that one surface of the resin sheet opposite the die pad is exposed to the exterior of the resin casing. The resin casing has a groove formed in one surface opposite the exposed surface of the resin sheet, the groove extending parallel to the resin sheet and perpendicular to a runner through which the resin was supplied in the molding operation.

Abstract: The invention provides a semiconductor device including a rectangular chip provided on a mounting region of a substrate, a liquid resin layer provided under the rectangular chip and on a side surface of the chip, and a plurality of dams formed on the substrate so as to extend along the side surface of the rectangular chip. The configuration allows the semiconductor device to be provided with the substrate having a reduced size which is achieved by preventing a liquid resin from flowing out.

Abstract: A redistributed lead frame for use in molded plastic semiconductor package (38) is formed from an electrically conductive substrate by a sequential metal removal process. The process includes: (a) patterning a first side of an electrically conductive substrate to form an array of lands separated by channels, (b) disposing a first molding compound (18) within these channels, (c) patterning a second side of the electrically conductive substrate to form an array of chip attach sites (24) and routing circuits (26) electrically interconnecting the array of lands and the array of chip attached sites (24), (d) directly electrically interconnecting input/output pads on the at least one semiconductor device (28) to chip attach site members (24) of the array of chip attach sites (24), and (e) encapsulating the at least one semiconductor device (28), the array of chip attach sites (24) and the routing circuits (26) with a second molding compound (36).

Abstract: A semiconductor package and a manufacturing method thereof are provided. The package element has a first insulating layer, and a plurality of holes are disposed on the first surface of the first insulating layer. Besides, a plurality of package traces are embedded in the insulating layer and connected to the other end of the holes. The holes function as a positioning setting for connecting the solder balls to the package traces, such that the signal of the semiconductor chip is connected to the package trace via conductor of the chip, and further transmitted externally via solder ball. The elastic modulus of the material of the first insulating layer is preferably larger than 1.0 GPa.

Abstract: A leadframe for supporting a semiconductor chip, the leadframe including a die pad having a first major surface and an opposing second major surface defining a thickness and having at least one perimeter edge, and an opening spaced from the at least one perimeter edge and extending through the thickness of the die pad between the first and second major surfaces. A vent extends from the at least one perimeter edge to the opening so that the opening is in communication with the at least one perimeter edge.

Abstract: A semiconductor device is disclosed which includes a tab (5) for use in supporting a semiconductor chip (8), a seal section (12) as formed by sealing the semiconductor chip (8) with a resin material, more than one tab suspension lead (4) for support of the tab (5), a plurality of electrical leads (2) which have a to-be-connected portion as exposed to outer periphery on the back surface of the seal section (12) and a thickness reduced portion as formed to be thinner than said to-be-connected portion and which are provided with an inner groove (2e) and outer groove (2f) in a wire bonding surface (2d) as disposed within the seal section (12) of said to-be-connected portion, and wires (10) for electrical connection between the leads (2) and pads (7) of the semiconductor chip (8), wherein said thickness reduced portion of the leads (2) is covered by or coated with a sealing resin material while causing the wires (10) to be contacted with said to-be-connected portion at specified part lying midway between the outer

Abstract: Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.

Abstract: A surface of a lead frame of a semiconductor device package, on which a semiconductor chip is mounted, is formed to have a mesh structure, whereby a connecting area between the lead frame and a molding resin can be increased to have strong bonding. Further, only filler particles having a small diameter than the mesh are taken into the vicinity of the lead frame, suppressing the effect of stresses to reduce deformation of the lead frame.

Abstract: A semiconductor package includes a semiconductor device having a first main surface and a second main surface, a first electrode plate provided on the first main surface, a second electrode plate provided on the second main surface, and a wiring substrate provided between the semiconductor device and the first electrode plate, in which a plurality of opening portions in the side surface of a protruding portion provided on the first electrode plate are engaged respectively with a plurality of engaging portions which face the opening portions and which are provided on the inner side surface of an intrusion opening portion in the wiring substrate into which the protruding portion is intruded.

Abstract: An interference interlock between leadframe features and a mold compound is provided in a packaged semiconductor device by exposing at least one predetermined surface area to an etching process prior to a molding step. This produces an etched recess with a recessed wall delimited by a step wall, generally perpendicular and adjacent to the recessed wall. The step wall is partially undercut by etching. During the molding step, the recessed wall and the step wall are both contacted by and embedded in the molding compound.

Abstract: A method for structured application of a laminatable intermediate layer (9) to a substrate (1) for a semiconductor module, wherein a separating layer is indirectly or directly applied to the substrate (1) over a large surface, the intermediate layer (9) is applied to the substrate (1), including the separating layer(s), by lamination, over a large surface, the intermediate layer (9) is opened in places on the substrate (1), where recesses are provided for the intermediate layer (9), and the separating layer (8) is removed in these places.

Abstract: A semiconductor package system includes providing a die having a plurality of contact pads. A leadframe is formed having a plurality of lead fingers with the plurality of lead fingers having a fine pitch and each having a substantially trapezoidal cross-section. A plurality of bumps is formed on the plurality of lead fingers, the plurality of bumps are on the tops and extend down the sides of the plurality of lead fingers. A plurality of bond wires is attached to the plurality of contact pads and to the plurality of bumps. An encapsulant is formed over the plurality of lead fingers, the die, and the plurality of bond wires, the encapsulant leaving lower surfaces of the plurality of lead fingers exposed.

Abstract: A semiconductor package including a leadframe having first and second major surfaces and a mold lock opening extending between the first and second major surfaces. The semiconductor package includes a semiconductor die coupled to the first major surface, and an encapsulating material formed about the semiconductor chip and a portion of the first major surface of the leadframe and filling all but a portion of the mold lock opening, the unfilled portion of the mold lock opening forming a vent extending from the second major surface to the first major surface, the vent providing a pathway for air to escape from between the second major surface and a surface to which the second major surface is to be attached.

Abstract: Embodiments of the present invention include a method of packaging semiconductor devices. The method comprises the steps of molding a surface of a wafer, sawing the wafer into individual devices, attaching the individual semiconductor device to an adhesive surface, molding the exposed surface, and sawing the wafer into individual semiconductor devices. The step of molding forms a continuous molded layer. The step of sawing results in each individual semiconductor having a molded layer. This molded layer corresponds to a portion of the continuous molded layer. The step of attaching includes attaching the molded layer of the individual semiconductor devices to the adhesive surface. The step of molding the exposed area includes molding an exposed area above the adhesive surface. This forms a solid expanse of material. The step of sawing the wafer into individual semiconductor devices includes sawing the solid expanse of material.

Abstract: A semiconductor device in which a semiconductor chip, a lead frame and metal wires for electrically connecting the lead frame are sealed with sealing resin. The lead frame has a plurality of lead terminal portions, a supporting portion for supporting the semiconductor chip, and hanging lead portions supporting the supporting portion. Each of the lead terminal portions adjacent to the hanging lead portion is a chamfered lead terminal portion having, at its head, a chamfered portion formed substantially in parallel with the hanging lead portion so as to avoid interference with the hanging lead portion.

Abstract: A manufacturing process of a leadframe-based BGA package is disclosed. A leadless leadframe with an upper layer and a lower layer is provided for the package. The upper layer includes a plurality of ball pads, and the lower layer includes a plurality of sacrificial pads aligning and connecting with the ball pads. A plurality of leads are formed in either the upper layer or the lower layer to interconnect the ball pads or the sacrificial pads. An encapsulant is formed to embed the ball pads after chip attachment and electrical connections. During manufacturing process, a half-etching process is performed after encapsulation to remove the sacrificial pads to make the ball pads electrically isolated and exposed from the encapsulant for solder ball placement where the soldering areas of the ball pads are defined without the need of solder mask(s) to solve the problem of solder bleeding of the solder balls on the leads or the undesired spots during reflow. Moreover, mold flash can easily be detected and removed.

Abstract: A semiconductor device with an inductor device is small, thin, and low-cost. A laminated inductor is adhered fixedly onto a supporting conductive plate by Ag paste, and a semiconductor chip is adhered fixedly onto the laminated inductor via an insulating DAF tape. One end of the supporting conductive plate and a terminal electrode of the semiconductor chip are connected by a metal wire, and a plurality of terminal electrodes of the semiconductor chip and a plurality of external lead-out terminals are connected respectively by laterally extending metal wires. The entire structure is then sealed by a resin mold. By employing a laminated inductor and forming the metal wires to extend laterally in this manner, the thickness of the semiconductor device with an inductor can be reduced.

Abstract: A method of manufacture of an integrated circuit die packaging system includes: providing a lead frame having a die attach paddle, an isolated pad, and a connector; attaching an integrated circuit die to the die attach paddle and the connector; forming an encapsulation over the integrated circuit die, the connector, the die attach paddle, and the isolated pad; and singulating the connector and the die attach paddle whereby the isolated pads are electrically isolated.

Abstract: An integrated circuit package system comprised by providing a leadframe including leads configured to provide electrical contact between an integrated circuit chip and an external electrical source. Configuring the leads to include outer leads, down set transitional leads, and down set inner leads. Connecting the integrated circuit chip electrically to the down set inner leads. Depositing an encapsulating material to prevent exposure of the down set inner leads.

Abstract: A chip package having asymmetric molding includes a lead frame, a chip, an adhesive layer, bonding wires and a molding compound. The lead frame includes a turbulent plate and a frame body having inner lead portions and outer lead portions. The turbulent plate is bended downwards to form a concave portion. The first end of the turbulent plate is connected to the frame body, and the second end is lower than the inner lead portions. The chip is fixed under the inner lead portions through the adhesive layer. The bonding wires are connected between the chip and the inner lead portions. The molding compound encapsulates the chip, the bonding wires, and the turbulent plate. The ratio between the thickness of the molding compound over and under the concave portion is larger than 1. The thickness of the molding compound under and over the outer lead portions is not equal.

Abstract: A structure of a lead-frame matrix of photoelectron devices is provided. The lead-frame matrix is used to fabricate a first lead-frame array and a second lead-frame array. In the structure of the lead-frame matrix of the photoelectron devices, pins of the first lead-frame array and pins of the second lead-frame array are alternatively inserted.

Abstract: A leadframe for supporting a semiconductor chip, the leadframe including a die pad having a first major surface and an opposing second major surface defining a thickness and having at least one perimeter edge, and an opening spaced from the at least one perimeter edge and extending through the thickness of the die pad between the first and second major surfaces. A vent extends from the at least one perimeter edge to the opening so that the opening is in communication with the at least one perimeter edge.

Abstract: A chip package having asymmetric molding includes a lead frame, a chip, an adhesive layer, bonding wires and a molding compound. The lead frame includes a turbulent plate and a frame body having inner lead portions and outer lead portions. The turbulent plate is bended downwards to form a concave portion. The first end of the turbulent plate is connected to the frame body, and the second end is lower than the inner lead portions. The chip is fixed under the inner lead portions through the adhesive layer. The bonding wires are connected between the chip and the inner lead portions. The molding compound encapsulates the chip, the bonding wires, and the turbulent plate. The ratio between the thickness of the molding compound over and under the concave portion is larger than 1. The thickness of the molding compound under and over the outer lead portions is not equal.

Abstract: In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package.

Abstract: The specification describes a plastic overmolded package for high power devices that has a very low lead count, typically fewer than eight, and in a preferred embodiment, only two. The leads occupy essentially the same linear space as the multiple leads in a conventional package and thus have a wide-blade configuration. To improve mechanical integrity, the leads in the package are provided with retention slots to add back the equivalent of the plastic joints in the spaces that were eliminated due to the wide-blade design. The retention slots extend in the width dimension of the leads.

Abstract: A method of fabricating a memory card. The method comprises the initial step of providing a leadframe which has a dambar and a plurality of contacts, each of the contacts being attached to the dambar by at least one tie bar. A layer of tape is applied to the leadframe such that the tape the bottom contact surfaces of the contacts, at least portions of the bottom dambar surface of the dambar. Thereafter, the tie bars are removed from the leadframe. At least one semiconductor die is electrically connected to the leadframe, with a body thereafter being formed on the leadframe such that the bottom contact surfaces are exposed in an exterior surface thereof.

Abstract: A semiconductor package includes a leadframe. A first lead finger has a lower portion, a connecting portion extending vertically upward from the lower portion, and a substantially flat, top portion. The top portion forms a top terminal lead structure. A second lead finger is electrically connected to the first lead finger. A portion of the second lead finger forms a bottom terminal lead structure. A portion of the second lead finger corresponds to a bottom surface of the semiconductor package. A surface of the substantially flat, top portion corresponds to a top surface of the semiconductor package.

Abstract: One aspect of the invention pertains to a semiconductor package having a die and a die attach pad with a plurality of spaced apart pedestals supported by a web. A die is mounted on the die attach pad such that the die is supported by at least a plurality of the pedestals. Selected edge regions of the die are arranged to overlie recessed regions of the die attach pad between adjacent pedestals. The die is electrically connected to at least some of the contact leads. An adhesive is arranged to secure the die to the die attach pad, with the thickness of the adhesive between the web of the die attach pad and the die being greater than the thickness of the adhesive between the die and the top surfaces of the pedestals that support the die. The die attach pad may have rounded peripheral corners between adjacent edge surfaces of the die attach pad.

Abstract: A structure of a lead-frame matrix of photoelectron devices is provided. The lead-frame matrix is used to fabricate a first lead-frame array and a second lead-frame array. In the structure of the lead-frame matrix of the photoelectron devices, pins of the first lead-frame array and pins of the second lead-frame array are alternatively inserted.

Abstract: A semiconductor package having improved adhesiveness between the chip paddle and the package body and having improved ground-bonding of the chip paddle. A plurality of through-holes are formed in the chip paddle for increasing the bonding strength of encapsulation material in the package body. A plurality of tabs are formed in the chip paddle may also be used alone or in conjunction with the through-holes to further increase the bonding strength of the encapsulation material in the package body. The tabs provide additional area for the bonding site to ground wires from the semiconductor chip by increasing the length of the chip paddle.

Abstract: In a circuit device having a circuit element housed in a case, a rise of air pressure and occurrence of condensation in the case are prevented. A circuit device of the present invention includes a case formed of a bottom part and a side part, and a cover part covering an upper surface of the side part. In an internal space of the case, a circuit element such as a semiconductor element is housed. In a bottom part of the case, a land and leads are buried. A communicating part which causes the internal space of the case to communicate with an outside of the case is provided in the land. By providing the communicating part, the rise of air pressure and occurrence of condensation in the internal space due to change in temperature are suppressed. Furthermore, in the land made of metal, the communicating part can be easily formed by etching or the like.

Abstract: Segments formed on a wiring substrate are arranged in a staggered array, and tie bars are provided between the segments.

Abstract: A semiconductor package is revealed with a special designed substrate. The substrate has a plurality of fingers, a dummy metal pattern, and at least a peripheral slot penetrating through the substrate. The dummy metal pattern is aligned to two opposing sides of the peripheral slot and is electrically isolated from the fingers. A chip is disposed on the substrate and is electrically connected to the fingers. An encapsulant is completely filled the peripheral slot. The peripheral slot can enhance the mold flow and eliminate the mold flash. The shape of the dummy metal pattern aligned to the peripheral slot is used to offer stiffening edges to prevent the substrate from warpage and from breakage at peripheries, to enhance the thermal stress resistance due to thermal cycles, and to avoid damages to the chip.

Abstract: Means for forming a package is disclosed on which is mounted a semiconductor chip with a high-speed LSI formed thereon, using a wire bonding method. The package comprises a semiconductor chip, a die pad smaller than a main surface of the semiconductor chip, a sealing member, plural leads each comprising an outer terminal portion and an inner lead portion, and plural bonding wires for connection between bonding pads formed on the semiconductor chip and the inner lead portions of the leads, each of the inner lead portions being bent in a direction away from a mounting surface of the sealing member, thereby approximating the height of the chip-side bonding pads and that of a bonding position of the inner lead portions to each other, whereby the wire length can be made shorter and it is possible to suppress an increase in inductance of the wire portions and attain impedance matching at various portion of a high-frequency signal input/output transmission path.

Abstract: A chip package with asymmetric molding including a lead frame, a chip, an adhesive layer, bonding wires and an encapsulant, is provided. The lead frame includes a frame body and at least a turbulent plate. The frame body has inner lead portions and outer lead portions. The turbulent plate is bended upwards to form a bulge portion and the first end of the turbulent plate is connected to the frame body. The chip is fixed under the inner lead portions and the turbulent plate is located at one side of the chip. The adhesive layer is disposed between the chip and the inner lead portions, and the bonding wires are electrically connected between the chip and the corresponding inner lead portions, respectively. The encapsulant encapsulates at least the chip, the bonding wires, the inner lead portions, the adhesive layer and the turbulent plate.

Abstract: The present invention is directed to an interposer for packaging a microchip device, which includes a plurality of electrical contacts on an outer side of the interposer, for electrically contacting the packaged microchip device and to be electrically connected with the microchip device. There is an aperture extending from the outer side into the interposer. The aperture may be divided into at least two openings, and at least a first of the openings may extend from the outer side through the interposer in order to allow connection to the microchip device.

Abstract: Methods and structures for die packages are described. The die package includes an integrated circuit die connected to and elevated above a substrate. In an embodiment, wire bonds connects pads on the die to pads on the substrate. The substrate pads are closely adjacent the die due to the die support being positioned inwardly of the peripheral surface of the die. In an embodiment, the die support includes a paste that flows outwardly when connecting the die to the substrate. The outward paste flow extends from beneath the die support but does not extend outwardly of the die so as to not interfere or contact the substrate pads.

Abstract: A memory card comprising a leadframe having a plurality of contacts, at least one die pad, and a plurality of conductive traces extending from respective ones of the contacts toward the die pad. Also included in the leadframe are at least two bumpers. Attached to the die pad is a semiconductor die which is electrically connected to at least one of the traces. A body defining at least two corner regions at least partially encapsulates the leadframe and the semiconductor die such that the contacts are exposed in a bottom surface defined by the body, and the bumpers are located at respective ones of the corner regions thereof.