Abstract: A semiconductor light-emitting device includes a lead frame, a semiconductor light-emitting element mounted on the top surface of the bonding region, and a case covering part of the lead frame. The bottom surface of the bonding region is exposed to the outside of the case. The lead frame includes a thin extension extending from the bonding region and having a top surface which is flush with the top surface of the bonding region. The thin extension has a bottom surface which is offset from the bottom surface of the bonding region toward the top surface of the bonding region.

Abstract: A method comprises removing a portion of molding compound from a side of a package structure by a laser ablation process to create an opening that exposes a portion of a conductive clip, depositing solder paste on the exposed portion of the conductive clip, and reflowing the solder paste. The laser ablation process in one example is a pulsed laser ablation process that includes raster scanning a laser along a portion of the side of the package structure to create the opening. Depositing the solder paste in one example includes performing a dispense process or a screening process that deposits solder paste in the opening onto the exposed portion of the conductive clip.

Abstract: An object of the present invention is to provide a power semiconductor device capable of improving seismic resistance while suppressing a decrease in assembly efficiency. According to the present invention, a power semiconductor device 1 includes an element installation conductor 2 including a first conductor portion 20a that is made of metal and is used for installing a power semiconductor element 300, a second conductor portion 20b that is made of metal and forms one or more main terminals 2a for transmitting a current to the power semiconductor element 300, and one or more control terminals 2b for transmitting a switching control signal to the power semiconductor element 300, and a third conductor portion 20c that is made of metal and is provided at a tip portion of the control terminal 2b.

Abstract: A semiconductor device includes a semiconductor element, a first lead including a mounting portion for the semiconductor element and a first terminal portion connected to the mounting portion, and a sealing resin covering the semiconductor element and a portion of the first lead. The mounting portion has a mounting-portion front surface and a mounting-portion back surface opposite to each other in a thickness direction, with the semiconductor element mounted on the mounting-portion front surface. The sealing resin includes a resin front surface, a resin back surface and a resin side surface connecting the resin front surface and the resin back surface. The mounting-portion back surface of the first lead is flush with the resin back surface. The first terminal portion includes a first-terminal-portion back surface exposed from the resin back surface, in a manner such that the first-terminal-portion back surface extends to the resin side surface.

Abstract: Implementations of a method of forming a plurality of semiconductor devices on a semiconductor substrate may include: providing a semiconductor substrate having a first surface, a second surface, a size, and a thickness where the second surface opposes the first surface and the thickness is between the first surface and the second surface. The method may include processing the semiconductor substrate through a plurality of semiconductor device fabrication processes to form a plurality of semiconductor devices on the first surface. The thickness may be between 100 microns and 575 microns and the size may be 150 mm. The semiconductor substrate may not be coupled with a carrier or support.

Abstract: Method for manufacturing an electronic semiconductor package, in which method an electronic chip (100) is coupled to a carrier, the electronic chip is at least partially encapsulated by means of an encapsulation structure having a discontinuity, and the carrier is partially encapsulated, and at least one part of the discontinuity and a volume connected thereto adjoining an exposed surface section of the carrier are covered by an electrically insulating thermal interface structure, which electrically decouples at least one part of the carrier with respect to its surroundings.

Abstract: A lead frame includes a lead portion having a first surface and a second surface, a connecting bar that has a first surface and a second surface and to which the lead portion is connected, and a raised portion provided on the first surface of the connecting bar. The first surface of the connecting bar is positioned between the first and the second surfaces of the lead portion. The tip of the raised portion is positioned between the first surface of the lead portion and the first surface of the connecting bar.

Abstract: The present invention relates to a power semiconductor chip module, comprising a substrate having a top side and a bottom side; at least one first power semiconductor device attached to the top side of the substrate; at least one first conductive structure thermally and electrically connecting the first power semiconductor device to the top side of the substrate; at least one second power semiconductor device attached to the bottom side of the substrate; and at least one second conductive structure connecting the second power semiconductor device to the bottom side of the substrate.

Abstract: A semiconductor device includes a semiconductor chip and a plurality of leads. The leads include a first lead including a supporting portion for mounting the semiconductor chip, and a projecting portion which projects in a first direction from the supporting portion. A second lead extends in a second direction non-parallel with the first direction, and one or more third leads extends in the second direction, such that a line extending in a third direction perpendicular to the first direction passes through the second lead and the one or more third leads. The second lead includes a first portion and a second portion, the first portion having a width larger than the second portion, the first portion having one side parallel to the first direction, and the first portion located between the second portion and the first lead.

Abstract: A copper lead frame used in the assembly of a semiconductor device includes a die flag and lead fingers extending away from the die flag. Each lead finger has a proximal end near the die flag and a distal end further away from the die flag. Metal plating is formed on the lead fingers, where first lead fingers have the metal plating on their proximal ends and second lead fingers have the metal plating on their distal ends. The first and second lead fingers are arranged alternately around the die flag.

Abstract: The present invention relates to a microphone, and more particularly, to a microphone with a mechanical switch function. A microphone with a mechanical switch function according to the present invention comprises a microphone body, wherein the microphone body comprises a circuit substrate above which a metal cover is disposed, an acoustic cavity formed by the metal cover and the circuit substrate; and a metal elastic piece, wherein a gap is formed between the metal elastic piece and the metal cover, and the metal elastic piece electrically contacts with the metal cover under an effect of a pressing force. By adopting the above-mentioned technical solutions, the present invention provides a microphone with functions of a mechanical switch, and the new type of microphone occupies less space, has a lower cost and is convenient to use.

Abstract: A semiconductor device is presented. The semiconductor device comprises a semiconductor body coupled to a first load terminal and to a second load terminal and configured to carry a load current between the first load terminal and the second load terminal. The first load terminal comprises a contiguous metal layer coupled to the semiconductor body; and at least one metal island arranged on top of and in contact with the contiguous metal layer and configured to be contacted by an end of a bond wire and to receive at least a part of the load current by means of the bond wire, wherein the contiguous metal layer and the metal island are composed of the same metal.

Abstract: In a manufacturing method of a semiconductor device, by arranging a lead in the vicinity of a gate portion serving as a resin injection port of a mold, a void is prevented from remaining within an encapsulation body when two semiconductor chips arranged so as to overlap in the Y direction are encapsulated with resin. Further, a length of an inner lead portion of the lead in the Y direction is greater than a length of an inner lead portion of another lead overlapping a chip mounting portion in the Y direction.

Abstract: The semiconductor device includes a semiconductor element, a main lead and a resin package. The semiconductor element includes an obverse surface and a reverse surface spaced apart from each other in a thickness direction. The main lead supports the semiconductor element via the reverse surface of the semiconductor element. The resin package covers the entirety of the semiconductor element. The resin package covers the main lead in such a manner that a part of the main lead is exposed from the resin package. The semiconductor element includes a part that does not overlap the main lead as viewed in the thickness direction.

Abstract: Provided is a semiconductor device including an insulating plate; a first conducting portion formed on a first surface of the insulating plate; a semiconductor element mounted on the first conducting portion; and a mold material that seals the first conducting portion and the semiconductor element on the first surface side of the insulating plate. A material of the insulating plate has higher adhesion with respect to the mold material than a material of the first conducting portion, and the first conducting portion includes a gap that is filled with the mold material between the first conducting portion and the insulating plate in a portion thereof.

Abstract: A semiconductor package or device includes a leadframe defining a plurality of leads which are arranged and partially etched in a manner facilitating a substantial reduction in burr formation resulting from a saw singulation process used to complete the fabrication of the semiconductor device. In one embodiment, the semiconductor device includes a die pad defining multiple peripheral edge segments. In addition, the semiconductor device includes a plurality of leads that are provided in a prescribed arrangement. At least one semiconductor die is connected to the top surface of the die pad and further electrically connected to at least some of the leads. At least portions of the die pad, the leads, the lands, and the semiconductor die are encapsulated by the package body, with at least portions of the bottom surfaces of the die pad and the leads being exposed in a common exterior surface of the package body.

Abstract: Disclosed examples include a method of making a semiconductor die package comprising arranging at least one preformed die attach pad and at least two preformed leads on a lead frame carrier in a predetermined configuration to form a lead frame, attaching a semiconductor die to the at least one preformed die attach pad, wire bonding the semiconductor die to the at least two preformed leads, forming a molding structure including at least part of the semiconductor die and the at least two preformed leads, and removing the molding structure from the lead frame carrier.

Abstract: Methods and apparatuses for transferring heat from stacked microfeature devices are disclosed herein. In one embodiment, a microfeature device assembly comprises a support member having terminals and a first microelectronic die having first external contacts carried by the support member. The first external contacts are operatively coupled to the terminals on the support member. The assembly also includes a second microelectronic die having integrated circuitry and second external contacts electrically coupled to the first external contacts. The first die is between the support member and the second die. The assembly can further include a heat transfer unit between the first die and the second die. The heat transfer unit includes a first heat transfer portion, a second heat transfer portion, and a gap between the first and second heat transfer portions such that the first external contacts and the second external contacts are aligned with the gap.

Abstract: A lead frame has a first sink, an island, and a control terminal. The lead frame is bent, and at a rear surface, the island is positioned closer to one surface of a resin molded body than the first sink and a passive component mounting portion of the control terminal. A passive component is mounted on the passive component mounting portion of the control terminal through a bonding material, the passive component mounting portion being a part of one surface.

Abstract: A microphone package includes a housing; a control circuit chip accommodated in the housing; a micro-electromechanical chip accommodated in the housing; and a circuit board forming an accommodation space with the housing. The circuit board includes a substrate, a rigid conductive layer disposed on the substrate and a plurality of conductive pads on the substrate for connecting to the control circuit chip. The micro-electromechanical chip and the control circuit chip are mounted on the rigid conductive layer, and the rigid conductive layer is provided with a number of isolation holes for receiving the conductive pads.

Abstract: Embodiments of the present invention are directed to a semiconductor package with partial plating on contact side surfaces. The semiconductor package includes a top surface, a bottom surface opposite the top surface, and side surfaces between the top and bottom surfaces. Contacts are located on peripheral edges of the bottom surface. Each of the contacts includes a first surface that is flush with the bottom surface, a second surface that is flush with one of the side surfaces, and a third surface between the first surface and the second surface. Each of the side surfaces can include a step such that the area of the bottom surface is differently sized from the area of the top surface and the third surface is located at the step. The first surface is plated, while the second surface is exposed (not plated). At least a portion of the third surface is plated.

Abstract: An improvement is achieved in the reliability of a semiconductor device. Over a die pad, first and second semiconductor chips are mounted. The first and second semiconductor chips and a part of the die pad are sealed in a sealing portion. The first semiconductor chip includes a power transistor. The second semiconductor chip controls the first semiconductor chip. The thickness of the portion of the die pad over which the first semiconductor chip is mounted is smaller than the thickness of the portion of the die pad over which the second semiconductor chip is mounted.

Abstract: A method of processing a leadframe strip having opposite first and second longitudinal ends and a plurality of leadframe panels positioned between the first and second longitudinal ends, each of the leadframe panels including an array of leadframe portions. The method includes saw cutting the leadframe rails and panels with a plurality of laterally extending saw cuts that each extend through the first and second rails and a panel connector portion of the leadframe strip positioned between adjacent panels of the leadframe strip. A method of reducing blade heating during leadframe strip singulation is described. Leadframe strip assemblies are also described.

Abstract: A method of making electronic packages includes providing a leadframe strip that includes a plurality of leadframes, wherein the leadframes comprise a plurality of leads, etching a surface of each of the leadframes to form an opening, wherein each of the leads has a lead tip that connects to a die paddle within the opening, isolating each of the leads from the die paddle, adhering a tape to a bottom side of the leadframe strips, leads, and die paddle, attaching a die to the die paddle, placing ball bumps on each of the lead tips, and connecting the die to the ball bumps.

Abstract: A lead frame strip has a plurality of unit lead frames. Each of the unit lead frames has a periphery structure connecting adjacent ones of the unit lead frames, a die paddle inside of the periphery structure, a plurality of leads connected to the periphery structure and extending towards the die paddle, and a molding compound channel in the periphery structure configured to guide liquefied molding material. The lead frame strip is processed by attaching a semiconductor die to each of the die paddles, electrically connecting each of the semiconductor dies to the leads, and forming a liquefied molding compound on each of the unit lead frames. The liquefied molding compound is formed such that the liquefied molding compound encapsulates the semiconductor dies and flows into the molding compound channels thereby forming molding extensions that extend onto the periphery structures.

Abstract: Terminal portions are arrayed at regular widths and regular intervals, and each face any enable terminal, and are electrically connected to the enable terminals by conductive particles. A lead portion is connected to the other terminal portion except for a pair of terminal portions which is a pair of terminal portions adjacent to each other, and extends from an overlap region to a lead region. A connection portion connects the respective terminal portions that are not connected with the lead portion to the adjacent terminal portions that are connected to the lead portion within an area of the overlap region. An interval between a pair of lead portions extending from a pair of connection portions located to sandwich a pair of terminal portions that are not connected with the lead portion therebetween is larger than an interval between the other adjacent lead portions.

Abstract: A semiconductor package includes a first lead frame type having a first type of package leads and a pre-molded portion, and a second lead frame type having a second type of package leads that surround a die pad and are supported by the pre-molded portion. An integrated circuit is attached to the die pad and electrically connected to the first and second types of leads with bond wires. A mold compound, which forms a mold cap, covers the first and second lead frame types, the integrated circuit and the bond wires. The first lead frame type may be a QFP type and the second lead frame type may be a QFN type.

Abstract: Power electronics devices having thermal stress reduction elements are disclosed. A power electronics device includes a heat source having a heat source perimeter, a first conduction member coupled to the heat source, and a substrate coupled to the first conduction member. The first conduction member includes a support portion that extends to at least the heat source perimeter and a plurality of finger portions extending from the support portion and separated from one another by web regions, where the plurality of finger portions have a finger thickness that is greater than a web thickness of the web regions.

Abstract: A semiconductor package that includes a substrate having a metallic back plate, an insulation body and a plurality of conductive pads on the insulation body, and a semiconductor die coupled to said conductive pads, the conductive pads including regions readied for direct connection to pads external to the package using a conductive adhesive.

Abstract: Method for manufacturing an electronic semiconductor package, in which method an electronic chip (100) is coupled to a carrier, the electronic chip is at least partially encapsulated by means of an encapsulation structure having a discontinuity, and the carrier is partially encapsulated, and at least one part of the discontinuity and a volume connected thereto adjoining an exposed surface section of the carrier are covered by an electrically insulating thermal interface structure, which electrically decouples at least one part of the carrier with respect to its surroundings.

Abstract: There is disclosed a lead for connection to a semiconductor device die, the lead comprising a clip portion. The clip portion comprises a major surface having two or more protrusions extending therefrom for connection to a bond pad of the semiconductor device die.

Abstract: An apparatus includes a temperature measuring device within a thermally conductive package. A crystal within the package is thermally coupled to the temperature measuring device and subjected to a same temperature as the temperature measuring device. A controller external to the package is configured to receive a signal from the crystal and a temperature measurement from the temperature measuring device. The controller is configured to estimate a frequency error of the crystal based on the temperature measurement and to provide a frequency error estimate to an external system.

Abstract: There is provided a technology enabling the improvement of the reliability of a semiconductor device manufactured by physically fixing separately formed chip mounting portion and lead frame. A feature of an embodiment resides in that, a second junction portion formed in a suspension lead is fitted into a first junction portion formed in a chip mounting portion, thereby to physically fix the chip mounting portion and the suspension lead. Specifically, the first junction portion is formed of a concave part disposed in the surface of the chip mounting portion. The second junction portion forms a part of the suspension lead.

Abstract: A semiconductor device includes a semiconductor die encapsulated in a package casing and having four main side walls each oriented generally parallel with one of first or second orthogonal directions. Signal leads are electrically coupled to the die and each has an exposed portion that extends from one of the main side walls parallel with one of the first or second directions. One or more power bars are electrically coupled to the die and each has at least one power bar lead extending at a non-zero angle with respect to the first and second directions. The power bars and associated power bar leads are electrically isolated from the signal leads. One or more tie bars extends at a generally non-zero angle with respect to the first and second directions and is electrically isolated from the signal leads and the power bars and associated power bar leads.

Abstract: There are provided semiconductor packages having corner pins and methods for their fabrication. Such a semiconductor package includes a leadframe and a die paddle, the leadframe having first and second edge sides meeting to form a first corner. The semiconductor package also includes edge pins arrayed substantially parallel to the first edge side and edge pins arrayed substantially parallel to the second edge side. In addition, the semiconductor package includes a first corner pin situated at the first corner, the first corner pin being electrically isolated from the die paddle.

Abstract: A mount includes a terminal, and a resin portion. The terminal includes a first surface, a second surface, and an end surface having first and second recessed areas that are extend from the first and second surfaces, respectively. The resin portion is integrally formed with the terminal, and at least partially covers the end surface so that the first and second surfaces are at least partially exposed. The resin portion forms a recessed part to accommodate the light emitting device. The second recessed area includes a closest point that is positioned closest to the first surface, and an extension part that extends outward of the closest point and toward the second surface side. The extension part is formed at least on opposing end surfaces of the pair of positive and negative lead terminal. The first recessed area is arranged on the exterior side relative to the closest point.

Abstract: A connecting contact for SM D-components includes a metal material and the metal material at least partially comprises a coating with a different metal material. The connecting contact has a substantially laminar contact area for solderable contact to a board and comprises edge regions. At least one segment of the edge region is at a distance from the laminar contact area, so that a soldered fillet is formed for a soldered contact to a board. Also, a method for producing connecting contacts for SM D-components for solderably contacting a board includes the steps of punching metal strips, bending the metal strips so that a conducting region and a laminar contact area are produced, and forming the edge areas at the laminar contact area. At least one segment of the edge area is at a distance from the laminar contact area.

Abstract: A semiconductor device is disclosed. The semiconductor device has a semiconductor chip, an island having an upper surface to which the semiconductor chip is bonded, a lead disposed around the island, a bonding wire extended between the surface of the semiconductor chip and the upper surface of the lead, and a resin package sealing the semiconductor chip, the island, the lead, and the bonding wire, while the lower surface of the island and the lower surface of the lead are exposed on the rear surface of the resin package, and the lead is provided with a recess concaved from the lower surface side and opened on a side surface thereof.

Abstract: In one embodiment, a semiconductor device includes a leadframe structure. A semiconductor die is attached to a die pad. Land connect bars are spaced apart from the die pad and a plurality of lands are between the land connect bars and the die pad and are spaced apart therefrom. Insulation members are adhered to the land connect bars and the plurality of lands to hold the land connect bars and the plurality of lands together and to electrically isolate them. An encapsulant covers the semiconductor die and at least portions of the plurality of lands, the die pad, and the land connect bars and further fills spaces between the land connect bars and the plurality of lands.

Abstract: A trench portion (trench) is formed at each of four corner portions of a chip bonding region having a quadrangular planar shape smaller than an outer-shape size of a die pad included in a semiconductor device. Each trench is formed along a direction of intersecting with a diagonal line which connects between the corner portions where the trench portions are arranged, and both ends of each trench portion are extended to an outside of the chip bonding region. The semiconductor chip is mounted on the chip bonding region so as to interpose a die-bond material. In this manner, peel-off of the die-bond material in a reflow step upon mounting of the semiconductor device on a mounting substrate can be suppressed. Also, even if the peel-off occurs, expansion of the peel-off can be suppressed.

Abstract: A surface mount semiconductor device is assembled by positioning an array of semiconductor dies with an array of metallic ground plane members between and beside the semiconductor dies. The arrays of dies and ground plane members are encapsulated in a molding compound. A redistribution layer is formed on the arrays of dies and ground plane members. The redistribution layer has an array of sets of redistribution conductors within a layer of insulating material. The redistribution conductors interconnect electrical contacts of the dies with external electrical contact elements of the device. As multiple devices are formed at the same time, adjacent devices are separated (singulated) by cutting along saw streets between the dies. The molding compound is interposed between tie bars of the ground plane members and the insulating material of the redistribution layer in the saw streets, and at the side surfaces of the singulated devices.

Abstract: A Quad Flat Pack (QFP) type semiconductor device includes four corner tie bars that, instead of being trimmed, are used for power and/or ground connections, and alternatively, to control mold flow during the encapsulation step of the assembly process.

Abstract: Systems, methods, and other embodiments associated with an etched hybrid die package are described. According to one embodiment, a method includes electrically connecting a semiconductor die to at least one of a plurality of primary leads and at least one feature. The method includes applying an encapsulant material to a lead-frame that includes the plurality of primary leads to form a package body. Portions of the primary leads protrude from the package body and portions of the at least one feature are exposed within the package body. The method includes chemically etching a die pad exposed within the package body to form and electrically isolate the at least one feature from the die pad. Chemically etching includes fully etching the at least one feature from the die pad.

Abstract: An integrated circuit device includes a support for supporting electrical circuitry, an integrated circuit having electrical circuitry disposed on the support, and a magnetic portion attached to the support around the integrated circuit. The integrated circuit and the magnetic portion are interconnected for converting a power input signal having a first characteristic to a power output signal having a second characteristic different from the first characteristic.

Abstract: A semiconductor device has a die mounted on a die paddle that is elevated above and thermally connected via tie bars to a heat sink structure. Heat generated by the die flows from the die to the die paddle to the tie bars to the heat sink structure and then to either the external environment or to an external heat sink. By elevating the die/paddle sub-assembly above the heat sink structure, the packaged device is less susceptible to delamination between the die and die attach adhesive and/or the die attach adhesive and the die paddle. An optional heat sink ring can surround the die paddle.

Abstract: A package structure is disclosed, which includes: a carrier having a recessed portion formed on a lower side thereof and filled with a dielectric material; a semiconductor element disposed on an upper side of the carrier and electrically connected to the carrier; and an encapsulant formed on the upper side of the carrier for encapsulating the semiconductor element. Therein, the dielectric material is exposed from the encapsulant. As such, when the carrier is disposed on a circuit board, the dielectric material is sandwiched between the lower side of the carrier and the circuit board to form a decoupling capacitor, thereby improving the power integrity.

Abstract: A printed wiring board includes a circuit substrate on which sheets are laminated, a wireless IC element provided on the sheet, a radiator provided on the sheet, and a loop-shaped electrode defined by first planar conductors, via hole conductors, and one side of the radiator, coupled to the wireless IC element. The first planar conductors are coupled to the radiator and the second planar conductors by auxiliary electrodes.

Abstract: A cavity package is disclosed comprising a metal leadframe, a metal ring connected to the metal leadframe, a plastic body molded to the metal leadframe forming a substrate cavity including an exposed die attach pad of the leadframe for affixing a semiconductor device, exposed lead fingers of the leadframe for wire bonding to the semiconductor device and an external circuit, and an exposed top surface of the metal ring, and a metal cap for closing and encapsulating the substrate cavity. The metal ring is integrated into the pre-molded cavity leadframe for providing an electrical ground path from the metal cap to the die attach pad and permitting attachment of the metal cap to the pre-molded leadframe using solder reflow.

Abstract: A 3D stacked multichip module comprises a stack of W IC die. Each die has a patterned conductor layer, including an electrical contact region with electrical conductors and, in some examples, device circuitry over a substrate. The electrical conductors of the stacked die are aligned. Electrical connectors extend into the stack to contact landing pads on the electrical conductors to create a 3D stacked multichip module. The electrical connectors may pass through vertical vias in the electrical contact regions. The landing pads may be arranged in a stair stepped arrangement. The stacked multichip module may be made using a set of N etch masks with 2N-1 being less than W and 2N being greater than or equal to W, with the etch masks alternatingly covering and exposing 2n-1 landing pads for each mask n=1, 2 . . . N.

Abstract: One exemplary disclosed embodiment comprises a two-terminal stacked-die package including a diode, such as a silicon diode, stacked atop a III-nitride transistor, such that a cathode of the diode resides on and is electrically coupled to a source of the III-nitride transistor. A first terminal of the package is coupled to a drain of the III-nitride transistor, and a second terminal of the package is coupled to an anode of the diode. In this manner, devices such as cascoded rectifiers may be packaged in a stacked-die form, resulting in reduced parasitic inductance and resistance, improved thermal dissipation, smaller form factor, and lower manufacturing cost compared to conventional packages.