With Separate Tie Bar Element Or Plural Tie Bars Patents (Class 257/670)
  • Patent number: 10403513
    Abstract: In a manufacturing method of a semiconductor device, by arranging a lead in the vicinity of a gate portion serving as a resin injection port of a mold, a void is prevented from remaining within an encapsulation body when two semiconductor chips arranged so as to overlap in the Y direction are encapsulated with resin. Further, a length of an inner lead portion of the lead in the Y direction is greater than a length of an inner lead portion of another lead overlapping a chip mounting portion in the Y direction.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: September 3, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shoji Hashizume, Keita Takada
  • Patent number: 10312171
    Abstract: The semiconductor device includes a semiconductor element, a main lead and a resin package. The semiconductor element includes an obverse surface and a reverse surface spaced apart from each other in a thickness direction. The main lead supports the semiconductor element via the reverse surface of the semiconductor element. The resin package covers the entirety of the semiconductor element. The resin package covers the main lead in such a manner that a part of the main lead is exposed from the resin package. The semiconductor element includes a part that does not overlap the main lead as viewed in the thickness direction.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: June 4, 2019
    Assignee: ROHM CO., LTD.
    Inventors: Kensuke Mikado, Makoto Shibuya, Yasufumi Matsuoka
  • Patent number: 10204871
    Abstract: Provided is a semiconductor device including an insulating plate; a first conducting portion formed on a first surface of the insulating plate; a semiconductor element mounted on the first conducting portion; and a mold material that seals the first conducting portion and the semiconductor element on the first surface side of the insulating plate. A material of the insulating plate has higher adhesion with respect to the mold material than a material of the first conducting portion, and the first conducting portion includes a gap that is filled with the mold material between the first conducting portion and the insulating plate in a portion thereof.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: February 12, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Yuichiro Hinata
  • Patent number: 10090228
    Abstract: A semiconductor package or device includes a leadframe defining a plurality of leads which are arranged and partially etched in a manner facilitating a substantial reduction in burr formation resulting from a saw singulation process used to complete the fabrication of the semiconductor device. In one embodiment, the semiconductor device includes a die pad defining multiple peripheral edge segments. In addition, the semiconductor device includes a plurality of leads that are provided in a prescribed arrangement. At least one semiconductor die is connected to the top surface of the die pad and further electrically connected to at least some of the leads. At least portions of the die pad, the leads, the lands, and the semiconductor die are encapsulated by the package body, with at least portions of the bottom surfaces of the die pad and the leads being exposed in a common exterior surface of the package body.
    Type: Grant
    Filed: April 4, 2017
    Date of Patent: October 2, 2018
    Assignee: Amkor Technology, Inc.
    Inventors: Hong Bae Kim, Hyun Jun Kim, Hyung Kook Chung
  • Patent number: 9978613
    Abstract: Disclosed examples include a method of making a semiconductor die package comprising arranging at least one preformed die attach pad and at least two preformed leads on a lead frame carrier in a predetermined configuration to form a lead frame, attaching a semiconductor die to the at least one preformed die attach pad, wire bonding the semiconductor die to the at least two preformed leads, forming a molding structure including at least part of the semiconductor die and the at least two preformed leads, and removing the molding structure from the lead frame carrier.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: May 22, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: You Chye How
  • Patent number: 9960148
    Abstract: Methods and apparatuses for transferring heat from stacked microfeature devices are disclosed herein. In one embodiment, a microfeature device assembly comprises a support member having terminals and a first microelectronic die having first external contacts carried by the support member. The first external contacts are operatively coupled to the terminals on the support member. The assembly also includes a second microelectronic die having integrated circuitry and second external contacts electrically coupled to the first external contacts. The first die is between the support member and the second die. The assembly can further include a heat transfer unit between the first die and the second die. The heat transfer unit includes a first heat transfer portion, a second heat transfer portion, and a gap between the first and second heat transfer portions such that the first external contacts and the second external contacts are aligned with the gap.
    Type: Grant
    Filed: February 6, 2012
    Date of Patent: May 1, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Salman Akram, David R. Hembree
  • Patent number: 9935074
    Abstract: A lead frame has a first sink, an island, and a control terminal. The lead frame is bent, and at a rear surface, the island is positioned closer to one surface of a resin molded body than the first sink and a passive component mounting portion of the control terminal. A passive component is mounted on the passive component mounting portion of the control terminal through a bonding material, the passive component mounting portion being a part of one surface.
    Type: Grant
    Filed: March 23, 2015
    Date of Patent: April 3, 2018
    Assignee: DENSO CORPORATION
    Inventors: Syoichirou Oomae, Akira Iwabuchi
  • Patent number: 9813790
    Abstract: A microphone package includes a housing; a control circuit chip accommodated in the housing; a micro-electromechanical chip accommodated in the housing; and a circuit board forming an accommodation space with the housing. The circuit board includes a substrate, a rigid conductive layer disposed on the substrate and a plurality of conductive pads on the substrate for connecting to the control circuit chip. The micro-electromechanical chip and the control circuit chip are mounted on the rigid conductive layer, and the rigid conductive layer is provided with a number of isolation holes for receiving the conductive pads.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: November 7, 2017
    Assignee: AAC TECHNOLOGIES PTE. LTD.
    Inventors: Rui Zhang, Ting Kang
  • Patent number: 9741642
    Abstract: Embodiments of the present invention are directed to a semiconductor package with partial plating on contact side surfaces. The semiconductor package includes a top surface, a bottom surface opposite the top surface, and side surfaces between the top and bottom surfaces. Contacts are located on peripheral edges of the bottom surface. Each of the contacts includes a first surface that is flush with the bottom surface, a second surface that is flush with one of the side surfaces, and a third surface between the first surface and the second surface. Each of the side surfaces can include a step such that the area of the bottom surface is differently sized from the area of the top surface and the third surface is located at the step. The first surface is plated, while the second surface is exposed (not plated). At least a portion of the third surface is plated.
    Type: Grant
    Filed: February 11, 2016
    Date of Patent: August 22, 2017
    Assignee: UTAC HEADQUARTERS PTE. LTD.
    Inventors: Somchai Nondhasitthichai, Saravuth Sirinorakul, Woraya Benjasukul
  • Patent number: 9735127
    Abstract: An improvement is achieved in the reliability of a semiconductor device. Over a die pad, first and second semiconductor chips are mounted. The first and second semiconductor chips and a part of the die pad are sealed in a sealing portion. The first semiconductor chip includes a power transistor. The second semiconductor chip controls the first semiconductor chip. The thickness of the portion of the die pad over which the first semiconductor chip is mounted is smaller than the thickness of the portion of the die pad over which the second semiconductor chip is mounted.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: August 15, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tadatoshi Danno, Atsushi Nishikizawa
  • Patent number: 9698085
    Abstract: A method of processing a leadframe strip having opposite first and second longitudinal ends and a plurality of leadframe panels positioned between the first and second longitudinal ends, each of the leadframe panels including an array of leadframe portions. The method includes saw cutting the leadframe rails and panels with a plurality of laterally extending saw cuts that each extend through the first and second rails and a panel connector portion of the leadframe strip positioned between adjacent panels of the leadframe strip. A method of reducing blade heating during leadframe strip singulation is described. Leadframe strip assemblies are also described.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: July 4, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Rex Araneta Cari-an, Ruby Ann Merto Camenforte, Roxanna Bauzon Samson, Glenn Juan Morado
  • Patent number: 9691688
    Abstract: A method of making electronic packages includes providing a leadframe strip that includes a plurality of leadframes, wherein the leadframes comprise a plurality of leads, etching a surface of each of the leadframes to form an opening, wherein each of the leads has a lead tip that connects to a die paddle within the opening, isolating each of the leads from the die paddle, adhering a tape to a bottom side of the leadframe strips, leads, and die paddle, attaching a die to the die paddle, placing ball bumps on each of the lead tips, and connecting the die to the ball bumps.
    Type: Grant
    Filed: October 26, 2015
    Date of Patent: June 27, 2017
    Assignee: CARSEM (M) SDN. BHD.
    Inventors: Mow Lum Yee, Kam Chuan Lau, Kok Siang Goh, Shang Yan Choong, Voon Joon Liew, Chee Sang Yip
  • Patent number: 9659843
    Abstract: A lead frame strip has a plurality of unit lead frames. Each of the unit lead frames has a periphery structure connecting adjacent ones of the unit lead frames, a die paddle inside of the periphery structure, a plurality of leads connected to the periphery structure and extending towards the die paddle, and a molding compound channel in the periphery structure configured to guide liquefied molding material. The lead frame strip is processed by attaching a semiconductor die to each of the die paddles, electrically connecting each of the semiconductor dies to the leads, and forming a liquefied molding compound on each of the unit lead frames. The liquefied molding compound is formed such that the liquefied molding compound encapsulates the semiconductor dies and flows into the molding compound channels thereby forming molding extensions that extend onto the periphery structures.
    Type: Grant
    Filed: November 5, 2014
    Date of Patent: May 23, 2017
    Assignee: Infineon Technologies AG
    Inventors: Boon Teik Tee, Tiam Sen Ong
  • Patent number: 9596760
    Abstract: Terminal portions are arrayed at regular widths and regular intervals, and each face any enable terminal, and are electrically connected to the enable terminals by conductive particles. A lead portion is connected to the other terminal portion except for a pair of terminal portions which is a pair of terminal portions adjacent to each other, and extends from an overlap region to a lead region. A connection portion connects the respective terminal portions that are not connected with the lead portion to the adjacent terminal portions that are connected to the lead portion within an area of the overlap region. An interval between a pair of lead portions extending from a pair of connection portions located to sandwich a pair of terminal portions that are not connected with the lead portion therebetween is larger than an interval between the other adjacent lead portions.
    Type: Grant
    Filed: October 8, 2014
    Date of Patent: March 14, 2017
    Assignee: Japan Display Inc.
    Inventors: Hideaki Abe, Yasushi Nakano, Hitoshi Kawaguchi, Ryouhei Suzuki
  • Patent number: 9589928
    Abstract: A semiconductor package includes a first lead frame type having a first type of package leads and a pre-molded portion, and a second lead frame type having a second type of package leads that surround a die pad and are supported by the pre-molded portion. An integrated circuit is attached to the die pad and electrically connected to the first and second types of leads with bond wires. A mold compound, which forms a mold cap, covers the first and second lead frame types, the integrated circuit and the bond wires. The first lead frame type may be a QFP type and the second lead frame type may be a QFN type.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: March 7, 2017
    Assignee: NXP USA, INC.
    Inventors: Zhigang Bai, Jinzhong Yao, Lan Chu Tan
  • Patent number: 9496214
    Abstract: Power electronics devices having thermal stress reduction elements are disclosed. A power electronics device includes a heat source having a heat source perimeter, a first conduction member coupled to the heat source, and a substrate coupled to the first conduction member. The first conduction member includes a support portion that extends to at least the heat source perimeter and a plurality of finger portions extending from the support portion and separated from one another by web regions, where the plurality of finger portions have a finger thickness that is greater than a web thickness of the web regions.
    Type: Grant
    Filed: May 22, 2013
    Date of Patent: November 15, 2016
    Assignee: Toyota Motor Engineering & Manufacturing North American, Inc.
    Inventors: Tsuyoshi Nomura, Sang Won Yoon, Ercan Mehmet Dede, Shuhei Horimoto
  • Patent number: 9496205
    Abstract: A semiconductor package that includes a substrate having a metallic back plate, an insulation body and a plurality of conductive pads on the insulation body, and a semiconductor die coupled to said conductive pads, the conductive pads including regions readied for direct connection to pads external to the package using a conductive adhesive.
    Type: Grant
    Filed: June 3, 2015
    Date of Patent: November 15, 2016
    Assignee: Infineon Technologies Americas Corp.
    Inventor: Martin Standing
  • Patent number: 9437513
    Abstract: Method for manufacturing an electronic semiconductor package, in which method an electronic chip (100) is coupled to a carrier, the electronic chip is at least partially encapsulated by means of an encapsulation structure having a discontinuity, and the carrier is partially encapsulated, and at least one part of the discontinuity and a volume connected thereto adjoining an exposed surface section of the carrier are covered by an electrically insulating thermal interface structure, which electrically decouples at least one part of the carrier with respect to its surroundings.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: September 6, 2016
    Assignee: Infineon Technologies AG
    Inventors: Edward Fuergut, Manfred Mengel
  • Patent number: 9418918
    Abstract: There is disclosed a lead for connection to a semiconductor device die, the lead comprising a clip portion. The clip portion comprises a major surface having two or more protrusions extending therefrom for connection to a bond pad of the semiconductor device die.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: August 16, 2016
    Assignee: NXP B.V.
    Inventors: Roelf Anco Jacob Groenhuis, Tim Boettcher
  • Patent number: 9252782
    Abstract: An apparatus includes a temperature measuring device within a thermally conductive package. A crystal within the package is thermally coupled to the temperature measuring device and subjected to a same temperature as the temperature measuring device. A controller external to the package is configured to receive a signal from the crystal and a temperature measurement from the temperature measuring device. The controller is configured to estimate a frequency error of the crystal based on the temperature measurement and to provide a frequency error estimate to an external system.
    Type: Grant
    Filed: January 9, 2012
    Date of Patent: February 2, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Rick A. Wilcox, Daniel F. Filipovic, Xu Mike Chi, Chris M. Rosolowski
  • Patent number: 9230831
    Abstract: There is provided a technology enabling the improvement of the reliability of a semiconductor device manufactured by physically fixing separately formed chip mounting portion and lead frame. A feature of an embodiment resides in that, a second junction portion formed in a suspension lead is fitted into a first junction portion formed in a chip mounting portion, thereby to physically fix the chip mounting portion and the suspension lead. Specifically, the first junction portion is formed of a concave part disposed in the surface of the chip mounting portion. The second junction portion forms a part of the suspension lead.
    Type: Grant
    Filed: February 3, 2015
    Date of Patent: January 5, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Yukihiro Sato, Nobuya Koike
  • Patent number: 9177834
    Abstract: A semiconductor device includes a semiconductor die encapsulated in a package casing and having four main side walls each oriented generally parallel with one of first or second orthogonal directions. Signal leads are electrically coupled to the die and each has an exposed portion that extends from one of the main side walls parallel with one of the first or second directions. One or more power bars are electrically coupled to the die and each has at least one power bar lead extending at a non-zero angle with respect to the first and second directions. The power bars and associated power bar leads are electrically isolated from the signal leads. One or more tie bars extends at a generally non-zero angle with respect to the first and second directions and is electrically isolated from the signal leads and the power bars and associated power bar leads.
    Type: Grant
    Filed: February 19, 2014
    Date of Patent: November 3, 2015
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Chee Seng Foong, Meng Kong Lye, Lan Chu Tan, Seng Kiong Teng
  • Patent number: 9142491
    Abstract: There are provided semiconductor packages having corner pins and methods for their fabrication. Such a semiconductor package includes a leadframe and a die paddle, the leadframe having first and second edge sides meeting to form a first corner. The semiconductor package also includes edge pins arrayed substantially parallel to the first edge side and edge pins arrayed substantially parallel to the second edge side. In addition, the semiconductor package includes a first corner pin situated at the first corner, the first corner pin being electrically isolated from the die paddle.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: September 22, 2015
    Assignee: CONEXANT SYSTEMS, INC.
    Inventors: Robert W. Warren, Hyun Jane Lee, Nic Rossi
  • Patent number: 9117806
    Abstract: A mount includes a terminal, and a resin portion. The terminal includes a first surface, a second surface, and an end surface having first and second recessed areas that are extend from the first and second surfaces, respectively. The resin portion is integrally formed with the terminal, and at least partially covers the end surface so that the first and second surfaces are at least partially exposed. The resin portion forms a recessed part to accommodate the light emitting device. The second recessed area includes a closest point that is positioned closest to the first surface, and an extension part that extends outward of the closest point and toward the second surface side. The extension part is formed at least on opposing end surfaces of the pair of positive and negative lead terminal. The first recessed area is arranged on the exterior side relative to the closest point.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: August 25, 2015
    Assignee: NICHIA CORPORATION
    Inventors: Ryohei Yamashita, Ryoichi Yoshimoto
  • Patent number: 9065234
    Abstract: A connecting contact for SM D-components includes a metal material and the metal material at least partially comprises a coating with a different metal material. The connecting contact has a substantially laminar contact area for solderable contact to a board and comprises edge regions. At least one segment of the edge region is at a distance from the laminar contact area, so that a soldered fillet is formed for a soldered contact to a board. Also, a method for producing connecting contacts for SM D-components for solderably contacting a board includes the steps of punching metal strips, bending the metal strips so that a conducting region and a laminar contact area are produced, and forming the edge areas at the laminar contact area. At least one segment of the edge area is at a distance from the laminar contact area.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: June 23, 2015
    Assignee: PHOENIX CONTACT GMBH & CO. KG
    Inventors: Dieter Holste, Ulrich Rosemeyer
  • Patent number: 9035436
    Abstract: A semiconductor device is disclosed. The semiconductor device has a semiconductor chip, an island having an upper surface to which the semiconductor chip is bonded, a lead disposed around the island, a bonding wire extended between the surface of the semiconductor chip and the upper surface of the lead, and a resin package sealing the semiconductor chip, the island, the lead, and the bonding wire, while the lower surface of the island and the lower surface of the lead are exposed on the rear surface of the resin package, and the lead is provided with a recess concaved from the lower surface side and opened on a side surface thereof.
    Type: Grant
    Filed: April 21, 2014
    Date of Patent: May 19, 2015
    Assignee: ROHM CO., LTD.
    Inventors: Akihiro Koga, Taro Nishioka
  • Patent number: 9029992
    Abstract: In one embodiment, a semiconductor device includes a leadframe structure. A semiconductor die is attached to a die pad. Land connect bars are spaced apart from the die pad and a plurality of lands are between the land connect bars and the die pad and are spaced apart therefrom. Insulation members are adhered to the land connect bars and the plurality of lands to hold the land connect bars and the plurality of lands together and to electrically isolate them. An encapsulant covers the semiconductor die and at least portions of the plurality of lands, the die pad, and the land connect bars and further fills spaces between the land connect bars and the plurality of lands.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: May 12, 2015
    Assignee: Amkor Technology, Inc.
    Inventors: Sung Gyu Kim, Byong Jin Kim, Gi Jeong Kim
  • Patent number: 9006871
    Abstract: A trench portion (trench) is formed at each of four corner portions of a chip bonding region having a quadrangular planar shape smaller than an outer-shape size of a die pad included in a semiconductor device. Each trench is formed along a direction of intersecting with a diagonal line which connects between the corner portions where the trench portions are arranged, and both ends of each trench portion are extended to an outside of the chip bonding region. The semiconductor chip is mounted on the chip bonding region so as to interpose a die-bond material. In this manner, peel-off of the die-bond material in a reflow step upon mounting of the semiconductor device on a mounting substrate can be suppressed. Also, even if the peel-off occurs, expansion of the peel-off can be suppressed.
    Type: Grant
    Filed: May 12, 2010
    Date of Patent: April 14, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Atsushi Fujisawa
  • Patent number: 9000589
    Abstract: A surface mount semiconductor device is assembled by positioning an array of semiconductor dies with an array of metallic ground plane members between and beside the semiconductor dies. The arrays of dies and ground plane members are encapsulated in a molding compound. A redistribution layer is formed on the arrays of dies and ground plane members. The redistribution layer has an array of sets of redistribution conductors within a layer of insulating material. The redistribution conductors interconnect electrical contacts of the dies with external electrical contact elements of the device. As multiple devices are formed at the same time, adjacent devices are separated (singulated) by cutting along saw streets between the dies. The molding compound is interposed between tie bars of the ground plane members and the insulating material of the redistribution layer in the saw streets, and at the side surfaces of the singulated devices.
    Type: Grant
    Filed: May 30, 2012
    Date of Patent: April 7, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Dominic Poh Meng Koey, Zhiwei Gong
  • Patent number: 9000570
    Abstract: A Quad Flat Pack (QFP) type semiconductor device includes four corner tie bars that, instead of being trimmed, are used for power and/or ground connections, and alternatively, to control mold flow during the encapsulation step of the assembly process.
    Type: Grant
    Filed: July 11, 2013
    Date of Patent: April 7, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Weng Hoong Chan, Ly Hoon Khoo, Boon Yew Low
  • Patent number: 9001524
    Abstract: An integrated circuit device includes a support for supporting electrical circuitry, an integrated circuit having electrical circuitry disposed on the support, and a magnetic portion attached to the support around the integrated circuit. The integrated circuit and the magnetic portion are interconnected for converting a power input signal having a first characteristic to a power output signal having a second characteristic different from the first characteristic.
    Type: Grant
    Filed: August 1, 2011
    Date of Patent: April 7, 2015
    Assignee: Maxim Integrated Products, Inc.
    Inventor: Sunil M. Akre
  • Patent number: 8999755
    Abstract: Systems, methods, and other embodiments associated with an etched hybrid die package are described. According to one embodiment, a method includes electrically connecting a semiconductor die to at least one of a plurality of primary leads and at least one feature. The method includes applying an encapsulant material to a lead-frame that includes the plurality of primary leads to form a package body. Portions of the primary leads protrude from the package body and portions of the at least one feature are exposed within the package body. The method includes chemically etching a die pad exposed within the package body to form and electrically isolate the at least one feature from the die pad. Chemically etching includes fully etching the at least one feature from the die pad.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: April 7, 2015
    Assignee: Marvell International Ltd.
    Inventors: Chenglin Liu, Shiann-Ming Liou
  • Publication number: 20150084169
    Abstract: A semiconductor device has a die mounted on a die paddle that is elevated above and thermally connected via tie bars to a heat sink structure. Heat generated by the die flows from the die to the die paddle to the tie bars to the heat sink structure and then to either the external environment or to an external heat sink. By elevating the die/paddle sub-assembly above the heat sink structure, the packaged device is less susceptible to delamination between the die and die attach adhesive and/or the die attach adhesive and the die paddle. An optional heat sink ring can surround the die paddle.
    Type: Application
    Filed: May 15, 2014
    Publication date: March 26, 2015
    Inventors: Kai Yun Yow, Poh Leng Eu, Meng Kong Lye, You Ge, Penglin Mei
  • Patent number: 8981540
    Abstract: A package structure is disclosed, which includes: a carrier having a recessed portion formed on a lower side thereof and filled with a dielectric material; a semiconductor element disposed on an upper side of the carrier and electrically connected to the carrier; and an encapsulant formed on the upper side of the carrier for encapsulating the semiconductor element. Therein, the dielectric material is exposed from the encapsulant. As such, when the carrier is disposed on a circuit board, the dielectric material is sandwiched between the lower side of the carrier and the circuit board to form a decoupling capacitor, thereby improving the power integrity.
    Type: Grant
    Filed: June 20, 2013
    Date of Patent: March 17, 2015
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Cheng-Yu Chiang, Wen-Jung Chiang, Hsing-Hung Lee
  • Patent number: 8981906
    Abstract: A printed wiring board includes a circuit substrate on which sheets are laminated, a wireless IC element provided on the sheet, a radiator provided on the sheet, and a loop-shaped electrode defined by first planar conductors, via hole conductors, and one side of the radiator, coupled to the wireless IC element. The first planar conductors are coupled to the radiator and the second planar conductors by auxiliary electrodes.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: March 17, 2015
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Makoto Takeoka, Koji Shiroki
  • Publication number: 20150061094
    Abstract: A cavity package is disclosed comprising a metal leadframe, a metal ring connected to the metal leadframe, a plastic body molded to the metal leadframe forming a substrate cavity including an exposed die attach pad of the leadframe for affixing a semiconductor device, exposed lead fingers of the leadframe for wire bonding to the semiconductor device and an external circuit, and an exposed top surface of the metal ring, and a metal cap for closing and encapsulating the substrate cavity. The metal ring is integrated into the pre-molded cavity leadframe for providing an electrical ground path from the metal cap to the die attach pad and permitting attachment of the metal cap to the pre-molded leadframe using solder reflow.
    Type: Application
    Filed: July 30, 2014
    Publication date: March 5, 2015
    Inventor: Chun Ho FAN
  • Patent number: 8970047
    Abstract: A 3D stacked multichip module comprises a stack of W IC die. Each die has a patterned conductor layer, including an electrical contact region with electrical conductors and, in some examples, device circuitry over a substrate. The electrical conductors of the stacked die are aligned. Electrical connectors extend into the stack to contact landing pads on the electrical conductors to create a 3D stacked multichip module. The electrical connectors may pass through vertical vias in the electrical contact regions. The landing pads may be arranged in a stair stepped arrangement. The stacked multichip module may be made using a set of N etch masks with 2N-1 being less than W and 2N being greater than or equal to W, with the etch masks alternatingly covering and exposing 2n-1 landing pads for each mask n=1, 2 . . . N.
    Type: Grant
    Filed: August 21, 2014
    Date of Patent: March 3, 2015
    Assignee: Macronix International Co., Ltd.
    Inventor: Shih-Hung Chen
  • Patent number: 8963338
    Abstract: One exemplary disclosed embodiment comprises a two-terminal stacked-die package including a diode, such as a silicon diode, stacked atop a III-nitride transistor, such that a cathode of the diode resides on and is electrically coupled to a source of the III-nitride transistor. A first terminal of the package is coupled to a drain of the III-nitride transistor, and a second terminal of the package is coupled to an anode of the diode. In this manner, devices such as cascoded rectifiers may be packaged in a stacked-die form, resulting in reduced parasitic inductance and resistance, improved thermal dissipation, smaller form factor, and lower manufacturing cost compared to conventional packages.
    Type: Grant
    Filed: March 22, 2011
    Date of Patent: February 24, 2015
    Assignee: International Rectifier Corporation
    Inventors: Heny Lin, Jason Zhang, Alberto Guerra
  • Patent number: 8952508
    Abstract: According to one embodiment, a lead frame includes a die pad having a mounting surface on which a semiconductor chip is mounted, plural leads having inner leads and outer leads, and a connecting member that extends from the die pad to both ends of a plurality of leads and connects the die pad and the plurality leads so that the ends of the inner leads are positioned above of the mounting surface.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: February 10, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Eitaro Miyake
  • Patent number: 8951841
    Abstract: In one embodiment, a semiconductor package includes a clip frame with a first clip having a first support structure, a first lever, and a first contact portion, which is disposed on a front side of the semiconductor package. The first support structure is adjacent an opposite back side of the semiconductor package. The first lever joins the first contact portion and the first support structure. A first die is disposed over the first support structure of the first clip. The first die has a first contact pad on the front side of the semiconductor package. An encapsulant material surrounds the first die and the first clip.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: February 10, 2015
    Assignee: Infineon Technologies AG
    Inventors: Melissa Mei Ching Ng, Mei Chin Ng, Peng Soon Lim
  • Patent number: 8941219
    Abstract: An integrated circuit package system includes: interconnection pads; a first device mounted below the interconnection pads; a bond wire, or a solder ball connecting the first device to the interconnection pads; a lead connected to the interconnection pad or to the first device; an encapsulation having a top surface encapsulating the first device; and a recess in the top surface of the encapsulation with the interconnection pads exposed therefrom.
    Type: Grant
    Filed: April 5, 2011
    Date of Patent: January 27, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Lionel Chien Hui Tay, Jairus Legaspi Pisigan
  • Patent number: 8937376
    Abstract: Semiconductor packages including a die pad, at least one connecting bar, at least one supporting portion, a plurality of leads, a semiconductor chip, a heat sink and a molding compound. The connecting bar connects the die pad and the supporting portion. The leads are electrically isolated from each other and the die pad. The semiconductor chip is disposed on the die pad and electrically connected to the leads. The heat sink is supported by the supporting portion. The molding compound encapsulates the semiconductor chip and the heat sink. Heat from the semiconductor chip is efficiently dissipated from the die pad through the connecting bar, through the supporting portion, and through the heat sink.
    Type: Grant
    Filed: April 16, 2012
    Date of Patent: January 20, 2015
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventor: Fu-Yung Tsai
  • Publication number: 20150014831
    Abstract: A Quad Flat Pack (QFP) type semiconductor device includes four corner tie bars that, instead of being trimmed, are used for power and/or ground connections, and alternatively, to control mold flow during the encapsulation step of the assembly process.
    Type: Application
    Filed: July 11, 2013
    Publication date: January 15, 2015
    Inventors: Weng Hoong Chan, Ly Hoon Khoo, Boon Yew Low
  • Patent number: 8933547
    Abstract: A lead frame for a packaged semiconductor device has multiple, configurable power bars that can be selectively electrically connected, such as with bond wires, to each other and/or to other leads of the lead frame to customize the lead frame for different package designs. One or more of the configurable power bars may extend into one or more cut-out regions in a die paddle of the lead frame, which allows for short bond wires to be used to connect the power bars to die pads of a semiconductor die mounted on the die paddle.
    Type: Grant
    Filed: November 21, 2013
    Date of Patent: January 13, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jia Lin Yap, Yin Kheng Au, Ahmad Termizi Suhaimi, Seng Kiong Teng, Boon Yew Low, Navas Khan Oratti Kalandar
  • Publication number: 20140374890
    Abstract: In an SOP1 having a semiconductor chip and another semiconductor chip, in wire coupling between the chips, a withstand voltage can be secured by setting an inter-wire distance between a wire in a first wire group that is closest to a second wire group and a wire in the second wire group that is closest to the first wire group to be larger than an inter-wire distance between any wires in the first wire group and the second wire group, which makes it possible to attain improvement of reliability of the SOP1.
    Type: Application
    Filed: June 15, 2014
    Publication date: December 25, 2014
    Inventors: Takanori Yamashita, Toshinori Kiyohara
  • Publication number: 20140339691
    Abstract: A semiconductor device includes a base member and a first semiconductor chip mounted over the base member. The first semiconductor chip including a first circuit, a second circuit, and a third circuit arranged between the first circuit and the second circuit and a plurality of pads. The first, second and third circuits are arranged along a first side of the first semiconductor chip. In plan view, the pads are located outside of the circuits and include a plurality of first pads arranged at a first pitch, and a plurality of second pads arranged at the first pitch. A distance between a first pad group comprised of the first pads and a second pad group comprised of the second pads is larger than the first pitch. Further, in a plan view, a part of the third circuit is located between the first pad group and the second pad group.
    Type: Application
    Filed: August 1, 2014
    Publication date: November 20, 2014
    Inventor: Masato NUMAZAKI
  • Publication number: 20140332939
    Abstract: A semiconductor package and a method for making the same are provided. In the method, a clip is used to conduct a lead frame and at least one chip. The clip has at least one second connection segment, at least one third connection segment, and at least one intermediate connection segment. The second connection segment is electrically connected to a second conduction region of the chip and a second pin of the lead frame respectively, and the third connection segment is electrically connected to a third conduction region of the chip and a third pin of the lead frame respectively. The intermediate connection segment connects the at least one second connection segment and the at least one third connection segment, and is removed in a subsequent process. Thereby, the present invention does not need to use any gold wire, which effectively saves the material cost and the processing dine.
    Type: Application
    Filed: July 26, 2014
    Publication date: November 13, 2014
    Applicant: Siliconix Electronic Co., LTD.
    Inventors: Frank Kuo, Suresh Belani
  • Patent number: 8884414
    Abstract: An integrated circuit module including a generally flat die attachment pad (DAP) positioned substantially in a first plane; and a generally flat lead bar positioned substantially in a second plane above and parallel to said first plane and having at least one downwardly and outwardly extending lead bar lead projecting therefrom and terminating substantially in the first plane; a top leadframe having a plurality of generally flat contact pads positioned substantially in a third plane above and parallel to the second plane and a plurality of leads having proximal end portions connected to the pad portions and having downwardly and outwardly extending distal end portions terminating substantially in said first plane; an IC die connected to the top leadframe, and the DAP; and encapsulation material encapsulating at least portions of the DAP, the lead bar, the top lead frame, and the IC die.
    Type: Grant
    Filed: January 9, 2013
    Date of Patent: November 11, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Lee Han Meng@Eugene Lee, Anis Fauzi bin Abdul Aziz, Susan Goh Geok Ling, Ng Swee Tiang
  • Publication number: 20140327122
    Abstract: In one embodiment, a micro lead frame structure includes one or more stiffness reinforcing structures formed on leads and/or connecting structures. The stiffness reinforcing structures can be formed by leaving predetermined portions of the micro lead frame at full thickness including, for example, portions of an inner lead, portions of an outer lead, and portions of a connecting bar, combinations thereof, and other structures. The stiffness reinforcing structures are configured to reduce deformation defects and electrical short defects caused by assembly processes.
    Type: Application
    Filed: May 2, 2014
    Publication date: November 6, 2014
    Applicant: Amkor Technology, Inc.
    Inventors: Hyeong Il Jeon, Hyung Kook Chung, Hong Bae Kim, Byong Jin Kim
  • Publication number: 20140319663
    Abstract: A lead frame includes a die pad and a plurality of lead portions each including an internal terminal and an external terminal. The external terminals of the plurality of lead portions are arranged in an alternately staggered form such that the respective external terminals of a pair of lead portions adjacent to each other are alternatively located on an inside or an outside. A lead portion has an inside region located on the inside of a first external terminal, an outside region located on the outside of the first external terminal, and an external terminal region having the first external terminal. The inside region and the outside region are each formed thin by means of half etching. A maximum thickness of the outside region is larger than a maximum thickness of the inside region.
    Type: Application
    Filed: April 16, 2014
    Publication date: October 30, 2014
    Inventors: Satoshi SHIBASAKI, Koji TOMITA, Masaki YAZAKI, Kazuyuki MIYANO, Atsushi KURAHASHI, Kazuhito UCHIUMI, Masachika MASUDA