Abstract: Semiconductor packages including a die pad, at least one connecting bar, at least one supporting portion, a plurality of leads, a semiconductor chip, a heat sink and a molding compound. The connecting bar connects the die pad and the supporting portion. The leads are electrically isolated from each other and the die pad. The semiconductor chip is disposed on the die pad and electrically connected to the leads. The heat sink is supported by the supporting portion. The molding compound encapsulates the semiconductor chip and the heat sink. Heat from the semiconductor chip is efficiently dissipated from the die pad through the connecting bar, through the supporting portion, and through the heat sink.

Abstract: A lead frame including rails, section bars, and lead frame cells. The rails are respectively arranged at edges of the lead frame extending in a first direction. The section bars extend between the rails in a second direction and are orthogonal to the rails. The lead frame cells are aligned along the section bars. At least one of the section bars includes a rib extending in the second direction and formed through a half blanking process.

Abstract: A method of making a stacked semiconductor package having at least a leadframe, a first die mounted above and soldered to the lead frame and a first clip mounted above and soldered to the first die. The method includes positioning the leadframe, first die and first clip in a vertically stacked relationship and nonsolderingly locking the first clip in laterally nondisplaceble relationship with the leadframe. A stacked semiconductor package and an intermediate product produced in making a stacked semiconductor package are also disclosed.

Abstract: In one embodiment, a semiconductor package includes a clip frame with a first clip having a first support structure, a first lever, and a first contact portion, which is disposed on a front side of the semiconductor package. The first support structure is adjacent an opposite back side of the semiconductor package. The first lever joins the first contact portion and the first support structure. A first die is disposed over the first support structure of the first clip. The first die has a first contact pad on the front side of the semiconductor package. An encapsulant material surrounds the first die and the first clip.

Abstract: A lead frame has a flag, a peripheral frame, and main tie bars coupling the flag to the peripheral frame. At least one cross tie bar extends between two of the main tie bars and an inner row of external connector pads extending from an inner side of the cross tie bar and an outer row of external connector pads extending from an outer side of the cross tie bar. Both an inner non-electrically conductive support bar and an outer non-electrically conductive support bar are attached across the two of the main tie bars. The inner non-electrically conductive support bar is attached to upper surfaces of the two of the main tie bars and to upper surfaces of the inner row of the external connector pads.

Abstract: A semiconductor device includes a lead frame, a semiconductor element mounted on the lead frame, and a frame-like member formed on the lead frame, surrounding the semiconductor element, and covering a side surface of the lead frame and exposing a lower surface of the lead frame. The frame-like member has at least one concave portion in a side surface thereof. The concave portion has a ceiling portion located at the same height as or lower than an upper surface of the lead frame, and a bottom portion located higher than the lower surface of the lead frame.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a package paddle; forming a lead adjacent the package paddle, the lead having a hole in a lead body top side and a lead ridge protruding from a lead non-horizontal side; mounting an integrated circuit over the package paddle; connecting an electrical connector to the lead and the integrated circuit; and forming a fill layer within the hole.

Abstract: A substrate and a method of making thereof are disclosed. The substrate comprises an electrically conductive leadframe, the leadframe having a plurality of lands on a first side of the leadframe with a first recessed portion between the lands, and a plurality of routing leads on an opposing second side of the leadframe with a second recessed portion between the routing leads. The substrate also comprises a first bonding compound filling the first recessed portion. In one embodiment, the substrate also comprises a support material attached to the first bonding compound for holding the leadframe together. In another embodiment, the substrate comprises a second bonding compound filling the second recessed portion.

Abstract: An electronic device including a die-pad area, a die fixed to the die-pad area, a connection terminal, and a ribbon of conductive material. The ribbon is electrically connected to the die and to the connection terminal, and has a prevalent dimension along a first axis, a width, measured along a second axis, which is transverse to the first axis, and a thickness, which is negligible with respect to the width; the ribbon moreover has a cross section that defines a concave geometrical shape.

Abstract: A semiconductor device has a die pad, a heat dissipating plate in the form of a frame arranged between the die pad and leads so as to surround the die pad, members that connect the die pad and the inner edge of the heat dissipating plate, and a suspension lead linked to the outer extension of the heat dissipating plate. A semiconductor chip larger than the die pad is mounted over the die pad and the members. Top surfaces of the die pad and the members in opposition to the back surface of the chip are bonded to the back surface of the chip with silver paste. Heat is conducted from the back surface of the chip to the heat dissipating plate via the silver paste, the die pad, and the members, and dissipated to the outside of the semiconductor device via the leads.

Abstract: A semiconductor device includes a die pad, the die pad including a first surface and a second surface, a first chip arranged on the first surface, the first chip including a first side and a second side crossing to the first side, a second chip arranged on the first surface, a plurality of first recesses formed on the first surface, a plurality of second recesses formed on the first surface, the plurality of second recesses being different from the first plurality of recesses in at least one of size and geometry, a wire, a resin, and a lead, one end of the lead being connected to another end of the wire and a part the lead being encapsulated by the resin. The plurality of first recesses includes a third recess and a fourth recess, and the first chip is arranged in a first area.

Abstract: A package for a semiconductor die includes a die attach pad that provides an attachment surface area for the semiconductor die, and tie bars connected to the die attach pad. The die attach pad is disposed in a first general plane and the tie bars are disposed in a second general plane offset with respect to the first general plane. A molding compound encapsulates the semiconductor die in a form having first, second, third and fourth lateral sides, a top and a bottom. The tie bars are exposed substantially coincident with at least one of the lateral sides. The form includes a discontinuity that extends along the at least one of the lateral sides, the discontinuity increasing a creepage distance measured from the tie bars to the bottom of the package.

Abstract: A semiconductor composite wiring assembly includes a wiring assembly and a lead frame. A copper wiring layer of the wiring assembly includes first terminals, second terminals, and wiring sections connecting the terminals. The second terminals and the lead frame are electrically connected by connecting members. The lead frame includes a die pad for mounting the wiring assembly, and lead sections located at outer positions. The die pad includes a central area in which a semiconductor chip is mounted via the wiring assembly, and a peripheral area connected to the central area with spaces formed therebetween that serve as resin-seal inflow spaces. The wiring assembly is positioned over the central area and the peripheral area so as to cover the central area completely and the peripheral area partially, and at least the central area and the peripheral area of the die pad are glued to the wiring assembly by resin paste.

Abstract: A power module includes a first heat sink, first and second power chips, a thermo-conductive insulating layer, a lead frame and a molding compound. The first heat sink has a first area and a second area. The first power chip is disposed in the first area. The thermo-conductive insulating layer is disposed in the second area. The second power chip is disposed on the heat sink through the thermo-conductive insulating layer. The lead frame is electrically connected to at least one of the first and second power chips. The molding compound covers the first and second power chips, the thermo-conductive insulating layer and a portion of the lead frame. The first heat sink is electrically connected to at least one of the first and second power chips. Because the first power chip is not disposed on the first heat sink through the thermo-conductive insulating layer, the cost can be reduced.

Abstract: A bonded wire semiconductor device includes a sub-assembly including a semiconductor die having an active face with a set of internal electrical contact elements and an externally exposed set of electrical contact elements. A set of bond wires make respective electrical connections between the internal electrical contact elements and the externally exposed set of electrical contact elements. A molding compound encapsulates the semiconductor die with the active face embedded in the molding compound. The bond wires have the same length. The bond wires are bonded to the internal electrical contact elements and to the externally exposed electrical contact elements at first and second curved arrays and of bond positions respectively. The first and second curved arrays and of bond positions have corresponding concentric shapes.

Abstract: A device includes a package component, and a metal trace on a surface of the package component. A first and a second dielectric mask cover a top surface and sidewalls of the metal trace, wherein a landing portion of the metal trace is located between the first and the second dielectric masks. The landing portion includes a first portion having a first width, and a second portion connected to an end of the first portion. The second portion has a second width greater than the first width, wherein the first and the second widths are measured in a direction perpendicular to a lengthwise direction of the metal trace.

Abstract: In accordance with the present invention, there is provided a semiconductor package (e.g., a QFP package) including a uniquely configured leadframe sized and configured to maximize the available number of exposed leads in the semiconductor package. More particularly, the semiconductor package of the present invention includes a generally planar die pad or die paddle defining multiple peripheral edge segments. In addition, the semiconductor package includes a plurality of leads. Some of these leads include exposed bottom surface portions which are provided in at least two concentric rows or rings which at least partially circumvent the die pad, with other leads including portions which protrude from respective side surfaces of a package body of the semiconductor package. Connected to the top surface of the die pad is at least one semiconductor die which is electrically connected to at least some of the leads.

Abstract: A semiconductor device in which a semiconductor chip, a lead frame and metal wires for electrically connecting the lead frame are sealed with sealing resin. The lead frame has a plurality of lead terminal portions, a supporting portion for supporting the semiconductor chip, and hanging lead portions supporting the supporting portion. Each of the lead terminal portions adjacent to the hanging lead portion is a chamfered lead terminal portion having, at its head, a chamfered portion formed substantially in parallel with the hanging lead portion so as to avoid interference with the hanging lead portion.

Abstract: In a semiconductor laser device, a first lead has a mounting portion for mounting a semiconductor laser element on its top surface via a submount member, and a lead portion extending from the mounting portion. Given that a direction in which a primary beam is emitted from the laser element is defined as a forward direction, and that a direction vertical to the forward direction and parallel to the top surface of the mounting portion is defined as a lateral direction, the first lead has, in one region of a side face of the mounting portion, a lateral reference surface which is parallel to a side face of the semiconductor laser element and flat. In the one region of the side face of the mounting portion, a recess portion is formed adjacent to the lateral reference surface.

Abstract: An integrated circuit package system includes a leadframe with leads configured to provide electrical contact between an integrated circuit chip and an external electrical source. Configuring the leads to include outer leads, down set transitional leads, and down set inner leads. Connecting the integrated circuit chip electrically to the down set inner leads. Depositing an encapsulating material to prevent exposure of the down set inner leads.

Abstract: Disclosed is a memory card package with a small substrate by using a metal die pad having an opening to substitute the chip-carrying function of a conventional substrate so that substrate dimension can be reduced. A substrate is attached under the metal die pad. A first chip is disposed on the substrate located inside the opening. A second chip is disposed on the metal die pad without covering the opening. A card-like encapsulant encapsulates the metal die pad, the top surface of the substrate, the first chip, and the second chip. The dimension of the substrate is smaller than the dimension of the encapsulant. The substrate has a lumpy sidewall encapsulated by the encapsulant so that the bottom surface of the substrate is coplanar with a bottom side of the encapsulant to increase the adhesion between the substrate and the encapsulant.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a lead frame having a die attach paddle, an isolated pad, and a connector; attaching an integrated circuit die to the die attach paddle and the connector; forming an encapsulation over the integrated circuit die, the connector, the die attach paddle, and the isolated pad; and singulating the connector and the die attach paddle whereby the isolated pads are electrically isolated.

Abstract: A lead frame for a quad flat no-lead (QFN) type semiconductor device package includes a die pad, a plurality of leads that surround the die pad. The outer edge of leads includes a channel that extends from a lower surface to an upper surface of the leads. A semiconductor die is attached to the die pad. An inner edge of each lead is electrically connected to a corresponding bonding pad on the semiconductor die. The assembly is covered with an encapsulation material except that the outer edge of each lead and the corresponding channel are exposed. The channel allows solder to flow up the outer edge of a lead when the QFN device is soldered to a substrate, which improves the ability to perform visual inspection of the solder-lead connection.

Abstract: A semiconductor device of a multi-pin structure using a lead frame is provided. The semiconductor device comprises a tab having a chip supporting surface, the chip supporting surface whose dimension is smaller than a back surface of a semiconductor chip, a plurality of leads arranged around the tab, the semiconductor chip mounted over the chip supporting surface of the tab, a plurality of suspending leads for supporting the tab, four bar leads arranged outside the tab so as to surround the tab and coupled to the suspending leads, a plurality of wires for coupling between the semiconductor chip and the leads, and a sealing body for sealing the semiconductor chip and the wires with resin, with first slits being formed respectively in first coupling portions of the bar leads for coupling with the suspending leads.

Abstract: In accordance with the present invention, there is provided a quad flat no leads (QFN) semiconductor device or package including a leadframe wherein the leads of the leadframe are selectively formed so that portions one or more prescribed leads are exposed in a package body of the semiconductor package and electrically connected to an electromagnetic interference (EMI) shielding layer applied to the package body. In certain embodiments of the present invention, one or more tie bars of the leadframe may also be formed so as to be exposed in the package body of the semiconductor package and electrically connected to the shielding layer applied to the package body. Thus, in the present invention, the shielding layer may be electrically connected to one or more leads alone or in combination with one or more tie bars of the leadframe.

Abstract: A packaged semiconductor device has a metal plate (1200) with sawed sides (1200c), a flat first surface (1200a) and a parallel second surface (1200b); the plate is separated into a first section (1201) and a second section (1202) spaced apart by a gap (1230). The plate has on the second surface (1200b) at least one insular mesa (1205) of the same metal in each section, the mesas raised from the second plate surface. The device further has an insulating member (1231), which adheres to the first plate surface, bridges the gap, and thus couples the first and second sections together. The device further has a vertical stack (1270) of two power FET chips (1210) and (1220), each having a pair of terminals on the first chip surface (1211 and 1212; 1221 and 1222 respectively) and a single terminal on the second chip surface. The single terminals of chip (1210) and chip (1220) are attached to each other to form the common terminal (1240).

Abstract: Embodiments of the present disclosure provide window ball grid array semiconductor packages. A semiconductor package includes a substrate having (i) a first surface, (ii) a second surface that is opposite to the first surface, and (iii) an opening formed between the first surface of the substrate and the second surface of the substrate. The semiconductor package further includes a semiconductor die having (i) a first surface and (ii) a second surface that is opposite to the first surface, the first surface of the semiconductor die being electrically coupled to the second surface of the substrate by one or more interconnect bumps; one or more bonding wires that electrically couple the first surface of the semiconductor die to the first surface of the substrate through the opening of the substrate; and a first electrically insulative structure disposed to substantially fill an area between the first surface of the semiconductor die, the second surface of the substrate, and the one or more interconnect bumps.

Abstract: An orthogonal array is formed by performing electromagnetic field analysis only once and determining a range by using the mount position and type of a capacitor and the number of capacitors as parameters to perform circuit analysis a small number of times. An estimation equation is formed by using as an index a result of the absolute value of the calculated power source impedance, and a capacitor is disposed to reduce noises by using the estimation equation.

Abstract: Disclosed is a multi-chip package having leadframe-type contact fingers, primarily comprising a leadframe, a non-conductive tape, a first chip and a second chip disposed on the first chip. The leadframe includes a die paddle on which the first chip is disposed and a plurality of first contact fingers, moreover, at least a second contact finger is integrally extended from the die paddle and is located among the first contact fingers so that the first and second contact fingers are arranged in a row. The non-conductive tape is attached onto the first and second contact fingers conforming to the arranging row of the first contact fingers so that the second contact finger is mechanically fastened with the first contact fingers. An encapsulant encapsulates the first chip, the second chip and the non-conductive tape with a plated metal layer formed on the bottom surfaces of the first and second contact fingers and exposed from the encapsulant.

Abstract: The present invention relates generally to assembly techniques. According to the present invention, the alignment and probing techniques to improve the accuracy of component placement in assembly are described. More particularly, the invention includes methods and structures to detect and improve the component placement accuracy on a target platform by incorporating alignment marks on component and reference marks on target platform under various probing techniques. A set of sensors grouped in any array to form a multiple-sensor probe can detect the deviation of displaced components in assembly.

Abstract: A semiconductor package may include a package substrate having a first surface and a boundary that may be defined by edges of the package substrate. The package further includes a first semiconductor chip having a front surface and a back surface. The back surface of a first portion of the first semiconductor chip may be disposed on the first surface of the package substrate with the back surface of a second portion of the first semiconductor chip extending beyond of the defined boundary of the package substrate. The semiconductor package may also include a second semiconductor chip disposed on the back surface of the second portion of the first semiconductor chip that extends beyond the defined boundary of the package substrate.

Abstract: A leadframe strip comprises a plurality of units arranged in a line. Each unit provides two component positions, each having a chip support substrate. The chip support substrates of the two component positions are mechanically linked by at least one support bar. The two component positions of a unit are molded at essentially the same time to produce a plastic housing for a package in each component position. The central portion of the first support bars remains outside of the plastic housing of the two packages.

Abstract: A semiconductor light emitting device (A) includes a lead frame (1) having a constant thickness, a semiconductor light emitting element (2) supported by the lead frame (1), a case (4) covering part of the lead frame (1) and a light transmitting member (5) covering the semiconductor light emitting element (2). The lead frame (1) includes a die bonding pad (11a) and an elevated portion (11b). The die bonding pad (11a) includes an obverse surface on which the semiconductor light emitting element (2) is mounted, and a reverse surface exposed from the case (4). The elevated portion (11b) is shifted in position from the die bonding pad (11a) in the direction normal to the obverse surface of the die bonding pad (11a).

Abstract: A method for packaging one or more power semiconductor devices is provided. A lead frame comprising one or more base die paddles, multiple lead terminals, and a tie bar assembly is constructed. The lead terminals extend to a predetermined elevation from the base die paddles. The base die paddles are connected to the lead terminals by the tie bar assembly. The tie bar assembly mechanically couples the base die paddles to each other and to the lead terminals. The tie bar assembly is selectively configured to isolate the lead terminals from the base die paddles and to enable creation of multiple selective connections between one or more of the lead terminals and one or more power semiconductor devices mounted on the base die paddles, thereby enabling flexible packaging of one or more isolated and/or non-isolated power semiconductor devices and increasing their power handling capacity.

Abstract: A semiconductor device has a semiconductor die mounted to a substrate. A leadframe has a base plate and integrated tie bars and conductive bodies. The tie bars include a down step with an angled surface and horizontal surface between the conductive bodies. The leadframe is mounted to the semiconductor die and substrate with the base plate disposed on a back surface of the semiconductor die and the conductive bodies disposed around the semiconductor die and electrically connected to the substrate. An encapsulant is deposited over the substrate and semiconductor die and into the down step of the tie bars. A conductive layer is formed over the conductive bodies to inhibit oxidation. The leadframe is singulated through the encapsulant in the down step and through the horizontal portion of the tie bars to electrically isolate the conductive bodies. A semiconductor package can be mounted to the substrate and semiconductor die.

Abstract: A leadframe including a die pad, leads, an outer frame, connecting bars and grounding bars is provided. Each of the grounding bars is suspended between two connecting bars by being connected with branches of the two connecting bars, such that the grounding bars are spaced by the die pad. The leadframe and the chip package of the present invention can permit a great design variation.

Abstract: A semiconductor package which includes a generally planar die paddle defining multiple peripheral edge segments and a plurality of leads which are segregated into at least two concentric rows. Connected to the top surface of the die paddle is at least one semiconductor die which is electrically connected to at least some of the leads of each row. At least portions of the die paddle, the leads, and the semiconductor die are encapsulated by a package body, the bottom surfaces of the die paddle and the leads of at least one row thereof being exposed in a common exterior surface of the package body.

Abstract: This semiconductor device has a frame including a bed portion on which a semiconductor chip is mounted, lead groups arranged in an outer peripheral portion, first bus bars, second bus bars and a rectifying bus bar. The first bus bars and the second bus bars are arranged between the bed portion and the lead groups. The rectifying bus bar is arranged in a region where the second bus bar is not arranged. Wire bonding is not performed on the rectifying bus bar. The rectifying bus bar includes a third bus bar having at least one end joined to a lead or a hanging pin and/or a fourth bus bar formed by extending the first bus bar in an outer peripheral direction in which the leads are arranged. The semiconductor device is provided in which deformation and damage of bonding wires when molding a resin sealed body are prevented.

Abstract: An electronic package is provided. The electronic package comprises a die pad having a die attached thereon. A plurality of leads surrounds the die pad and spaced therefrom to define a ring gap therebetween. At least one first common electrode bar is in the ring gap and substantially coplanar to the die pad, in which at least one of the plurality of leads extends to the first common electrode bar. A molding compound partially encapsulates the die pad and the first common electrode bar, such that the bottom surfaces of the die pad and the first common electrode bar are exposed. A length of the first common electrode bar is substantially equal to a predetermined distance between two pads among a plurality of power or ground pads on a side of the die facing the first common electrode bar. An electronic device with the electronic package is also disclosed.

Abstract: A method of manufacturing a semiconductor package, where the package includes a surface for attachment of the package to a device by a joint formed of a connective material in a joint area of the surface. The method is characterized in that it comprises the step of patterning one or more channels on the surface which channels extend away from the joint area towards an edge of the surface. Also the method has the step of applying a compound to one or more channels which compound interacts with the connective material, such that when the semiconductor package is attached to the device the interaction defines one or more paths in the connective material. These correspond to the one or more channels on the surface and allow the passage of waste material away from the joint area to the outer edge of the surface.

Abstract: A heat spreader frame is provided including: heat spreaders having upper surfaces; a peripheral frame surrounding the heat spreaders; spreaders, the peripheral frame having stand-off legs; tie bars having upper surfaces and a pin identifier at an end portion of the tie bars, the heat spreaders connected to one another and to the peripheral frame by the tie bars, the width of the stand-off legs wider than widths of the tie bars; at least portions of the upper surfaces of the tie bars being thinned to reduce heights of the tie bars; the upper surfaces of the heat spreader in an elevated position supported by the peripheral frame; and the heat spreaders and the tie bars covered by an package molding compound exposing the upper surface of the heat spreaders and one surface of the pin identifier coplanar to the upper surfaces of the heat spreaders.

Abstract: The invention relates to leadframes and semiconductor chip package assemblies using leadframes, and to methods for their assembly. A disclosed embodiment of the invention includes a semiconductor package leadframe with a chip mounting surface for receiving a semiconductor chip and a plurality of leadfingers. The leadfingers have a proximal end for receiving one or more wirebond, and a distal end for providing an electrical path from the proximal end. One or more of the leadfingers also has an offset portion at its proximal end for increasing the clearance between the leadfinger and underlying heat spreader, increasing the stiffness of the leadfinger, and increasing leadfinger deflection-resistance and spring-back. The offset is in the direction opposite the plane of a heat spreader thermally coupled to the mounting surface.

Abstract: Embodiments of the present invention provide electrical bussing for multichip leadframes. In various embodiments, a leadframe may comprise a first die paddle for receiving a first microelectronic device, a second die paddle for receiving a second microelectronic device, and at least one electrical bus disposed between the first die paddle and the second die paddle.

Abstract: According to one exemplary embodiment, a lead frame package includes a number of leads and a number of contacts, where each of the contacts is situated over one of the leads. The lead frame package further includes a semiconductor die including a number of bond pads. Each of the contacts is directly attached and bonded to one of the bond pads on the semiconductor die. Each of the contacts is situated over a top portion of one of the leads, where the top portion has a shorter length than a middle portion of each of the leads. Each of the contacts is connected to one of the bond pads on the semiconductor die without a wire bond. The semiconductor die does not include a redistribution layer situated over an active surface of the semiconductor die.

Abstract: An integrated circuit package system is provided including forming a paddle having an integrated circuit die thereover, an outer lead, and an inner lead between the paddle and the outer lead. The integrated circuit package system is also provided including placing a lead support over the inner lead without traversing to an inner body bottom side of the inner lead, connecting the integrated circuit die and the inner lead, and encapsulating the inner lead having the lead support thereover and the inner lead exposed.

Abstract: A method of manufacturing a semiconductor package system includes: forming a leadframe having a passive device; encapsulating the passive device to form an encapsulant interposer; attaching a first die to the encapsulant interposer; forming a substrate interposer having a second die; and stacking the encapsulant interposer over the substrate interposer.

Abstract: A device is disclosed which includes a flexible material including at least one conductive wiring trace, a first die including at least an integrated circuit, the first die being positioned above a portion of the flexible material, and an encapsulant material that covers the first die and at least a portion of the flexible material. A method is disclosed which includes positioning a first die above a portion of a flexible material, the first die including an integrated circuit and the flexible material including at least one conductive wiring trace, and forming an encapsulant material that covers the first die and at least a portion of the flexible material, wherein at least a portion of the flexible material extends beyond the encapsulant material.

Abstract: An integrated circuit package system is provided including forming a lead frame including forming an inner lead having a planar surface, the inner lead extending inwardly from the lead frame and forming a stiffening structure integral with the lead frame for maintaining the planar surface; encapsulating the inner lead with an electrical connection to an integrated circuit die and with a first inner lead body of the inner lead exposed; and singulating the inner lead from the lead frame.

Abstract: An integrated circuit package system is provided including forming a lead frame includes forming a mold gate, providing a first surface, and providing a second surface opposite the first surface; and forming angled gate sides facing each other in the mold gate between the first surface and the second surface.

Abstract: A semiconductor chip package having multiple leadframes is disclosed. Packages can include a first leadframe having a first plurality of electrical leads and a die attach pad having a plurality of tie bars, a second leadframe generally parallel to the first leadframe and having a second plurality of electrical leads, and a mold or encapsulant. Tie bars can be located on three main sides of the die attach pad, but not the fourth main side. Gaps in the first and second plurality of electrical leads can be enlarged or aligned with each other to enable the elimination of mold flash outside the encapsulated region, which can be accomplished with mold cavity bar protrusions. Additional components can include a primary die, a secondary die, an inductor and/or a capacitor. The first and second leadframes can be substantially stacked atop one another, and one or both leadframes can be leadless leadframes.