Abstract: A leadframe strip comprises a plurality of units arranged in a line. Each unit provides two component positions, each having a chip support substrate. The chip support substrates of the two component positions are mechanically linked by at least one support bar. The two component positions of a unit are molded at essentially the same time to produce a plastic housing for a package in each component position. The central portion of the first support bars remains outside of the plastic housing of the two packages.

Abstract: The invention discloses a package structure for better heat-dissipation or EMI performance. A first conductive element and a second conductive element are both disposed between the top lead frame and the bottom lead frame. The first terminal of the first conductive element is electrically connected to the bottom lead frame, and the second terminal of the first conductive element is electrically connected to the top lead frame. The third terminal of the second conductive element is electrically connected to the bottom lead frame, and the fourth terminal of the second conductive element is electrically connected to the top lead frame. In one embodiment, a heat dissipation device is disposed on the top lead frame. In one embodiment, the molding compound is provided such that the outer leads of the top lead frame are exposed outside the molding compound.

Abstract: An integrated circuit package having a selectively etched leadframe strip defining a die attach pad and a plurality of contact pads, at least one side of the die attach pad having a plurality of spaced apart pad portions; a semiconductor die mounted to the die attach pad and wires bonding the semiconductor die to respective ones of the contact pads; a first surface of the leadframe strip, including the semiconductor die and wire bonds, encapsulated in a molding material such that at least one surface of the leadframe strip is exposed, and wherein solder paste is disposed on said contact pads and said at least one side of said die attach pad.

Abstract: A chip package including a lead frame, a heat sink, a chip and a molding compound is provided. The lead frame includes a chip pad and a plurality of leads, wherein the chip pad has a first surface and a second surface opposite thereto. The heat sink has a third surface and a fourth surface opposite thereto, wherein the lead frame is disposed on the third surface of the heat sink through the second surface of the chip pad, and the fourth surface of the heat sink is exposed. The chip is disposed on the first surface of the chip pad and electrically connected to each of the chip pad and the leads. The molding compound encapsulates the chip, the chip pad, the heat sink and a portion of each of the leads.

Abstract: One exemplary disclosed embodiment comprises a semiconductor package including an inside pad, a transistor, and a conductive clip coupled to the inside pad and a terminal of the transistor. A top surface of the conductive clip is substantially exposed at the top of the package, and a side surface of the conductive clip is exposed at a side of the package. By supporting the semiconductor package on an outside pad during the fabrication process and by removing the outside pad during singulation, the conductive clip may be kept substantially parallel and in alignment with the package substrate while optimizing the package form factor compared to conventional packages. The exposed top surface of the conductive clip may be further attached to a heat sink for enhanced thermal dissipation.

Abstract: Some exemplary embodiments of high voltage cascaded III-nitride semiconductor package with an etched leadframe have been disclosed. One exemplary embodiment comprises a III-nitride transistor having an anode of a diode stacked over a source of the III-nitride transistor, and a leadframe that is etched to form a first leadframe paddle portion coupled to a gate of the III-nitride transistor and the anode of the diode, and a second leadframe paddle portion coupled to a drain of the III-nitride transistor. The leadframe paddle portions enable the package to be surface mountable. In this manner, reduced package footprint, improved surge current capability, and higher performance may be achieved compared to conventional wire bonded packages. Furthermore, since multiple packages may be assembled at a time, high integration and cost savings may be achieved compared to conventional methods requiring individual package processing and externally sourced parts.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a peripheral lead having a peripheral lead bottom side, a peripheral lead top side, a peripheral lead non-horizontal side, a peripheral lead horizontal ridge, and a peripheral lead conductive plate, the peripheral lead horizontal ridge protruding from the peripheral lead non-horizontal side; forming a central lead adjacent to the peripheral lead; forming a first top distribution layer on the peripheral lead top side; connecting an integrated circuit to the first top distribution layer; applying an insulation layer directly on a bottom extent of the first top distribution layer and a peripheral lead ridge lower side of the peripheral lead horizontal ridge; and attaching a heatsink to the central lead under the integrated circuit.

Abstract: A redistributed lead frame for use in a molded plastic semiconductor package is formed from an electrically conductive substrate by a sequential metal removal process. The process includes patterning a first side of the substrate to form an array of lands separated by channels; disposing a first molding compound within those channels; patterning a second side of the substrate to form an array of chip attach sites and routing circuits electrically interconnecting the array of lands and the array of chip attach sites; directly electrically interconnecting input/output pads on a semiconductor device to the chip attach sites; and encapsulating the semiconductor device, the array of chip attach sites and the routing circuits with a second molding compound. This process is particularly suited for the manufacture of chip scale packages and very thin packages.

Abstract: A low profile heat removal system suitable for removing excess heat generated by a component operating in a compact computing environment is disclosed.

Abstract: A packaged semiconductor device includes a semiconductor die including a substrate having a topside including active circuitry and a bottomside with at least one backside metal layer directly attached. A package including a molding material having a die pad and a plurality of leads is encapsulated within the molding material, wherein the leads include an exposed portion that includes a bonding portion. The topside of the semiconductor die is attached to the die pad, and the package includes a gap that exposes the backside metal layer along a bottom surface of the package. Bond wires couple pads on the topside of the semiconductor die to the leads. The bonding portions, the molding material along the bottom surface of the package, and the backside metal layer are all substantially planar to one another.

Abstract: A semiconductor package structure is provided, including: a semiconductor chip having electrode pads disposed thereon and metal bumps disposed on the electrode pads; an encapsulant encapsulating the semiconductor chip; a dielectric layer formed on the encapsulant and having a plurality of patterned intaglios formed therein for exposing the metal bumps; a wiring layer formed in the patterned intaglios of the dielectric layer and electrically connected to the metal bumps; and a metal foil having a plurality of metal posts disposed on a surface thereof such that the metal foil is disposed on the encapsulant with the metal posts penetrating the encapsulant so as to extend to the inactive surface of the semiconductor chip. Compared with the prior art, the present invention reduces the overall thickness of the package structure, increases the electrical transmission efficiency and improves the heat dissipating effect.

Abstract: Provided is a high-power device having a thermocouple (thermoelectric couple) for measuring the temperature of a transistor constituting a high-power device. The high-power device includes a heating element, a thermocouple formed adjacent to the heating element, and a dielectric body formed between the heating element and the thermocouple.

Abstract: A semiconductor chip assembly includes a semiconductor device, a heat spreader, a conductive trace and first and second adhesives. The heat spreader includes a first post, a second post and a base. The conductive trace includes a pad and a terminal. The semiconductor device is electrically connected to the conductive trace and thermally connected to the heat spreader. The first post extends from the base in a first vertical direction into a first opening in the first adhesive, the second post extends from the base in a second vertical direction into a second opening in the second adhesive and the base is sandwiched between and extends laterally from the posts. The conductive trace provides signal routing between the pad and the terminal.

Abstract: Embodiments of a microelectronic package are generally described herein. A microelectronic package may include a die having a first side and a second side, opposite the first side, a flange coupled to the first side of the die, and a lead frame proximately positioned relative to the die and coupled to the second side of the die. Other embodiments may be described and claimed.

Abstract: An integrated circuit (IC) package is disclosed. The IC package includes a first die; and a second die bonded to the CPU die in a three dimensional packaging layout.

Abstract: A dual die semiconductor package has a grid array of electrical contacts on a bottom surface of a substrate. There is a first semiconductor die with a base surface mounted to an upper surface of the substrate and the first semiconductor die has first die upper surface external electrical connection pads on an upper surface that are electrically connected to respective electrical contacts of the grid array. There is also a second semiconductor die with a base surface mounted to an upper surface of a lead frame flag. There are second die upper surface external electrical connection pads on an upper surface of the second semiconductor die. The dual die semiconductor package includes leads and at least some of the leads are electrically connected to respective pads that provide the second die upper surface external electrical connection pads. A package body at encloses the first semiconductor die and the second semiconductor die.

Abstract: An electrical package with improved thermal management. The electrical package includes a die having an exposed back surface. The package further includes a plurality of fins extending outwardly from the back surface for dissipating heat from the package. The die can be arranged in a multi-die stacking configuration. In another embodiment, a method of forming a die for improved thermal management of an electrical package is provided.

Abstract: A semiconductor package includes a semiconductor device 30 and a molded upper heat sink 10. The heat sink has an interior surface 16 that faces the semiconductor device and an exterior surface 15 that is at least partially exposed to the ambient environment of the packaged device. An annular planar base 11 surrounds a raised or protruding central region 12. That region is supported above the plane of the base 11 by four sloped walls 13.1-13.4. The walls slope at an acute angle with respect to the planar annular base and incline toward the center of the upper heat sink 10. Around the outer perimeter of the annular base 11 are four support arms 18.1-18.4. The support arms are disposed at an obtuse angle with respect to the interior surface 16 of the planar annular base 11.

Abstract: A BGA type semiconductor device includes: a substrate having wirings and electrodes; a semiconductor element disposed on the substrate, having a rectangular plan shape, and a plurality of electrodes disposed along each side of the semiconductor element; a plurality of wires connecting the electrodes on the semiconductor element with the electrodes on the substrate; a heat dissipation member disposed on the substrate, covering the semiconductor element, and having openings formed in areas facing apex portions of the plurality of wires connected to the electrodes formed along each side of the semiconductor element; and a sealing resin member for covering and sealing the semiconductor element and heat dissipation member.

Abstract: A semiconductor device package includes a semiconductor chip including a conductive pad, a die pad on which the semiconductor chip is mounted and having a first thickness, a lead pattern including a first portion disposed adjacent to the edge of the die pad and having the first thickness and a second portion having a second thickness greater than the first thickness, a heat radiation member disposed on the die pad and the lead pattern and including a groove formed at its bottom surface, and a conductive line disposed to electrically connect the conductive pad to the lead pattern corresponding to the conductive pad and partially inserted into the groove.

Abstract: A multiple die package includes a folded leadframe for interconnecting at least two die attached to another leadframe. In a synchronous voltage regulator the folded leadframe, which is formed from a single piece of material, connects the high side switching device with the low side switching device to provide a low resistance, low inductance connection between the two devices.

Abstract: According to one embodiment, a power semiconductor device includes a first conductor, a second conductor, and a first semiconductor chip. The first conductor includes a first portion and a second portion. The first portion includes a first major surface and a second major surface opposite thereto. The second portion includes a third major surface intersecting at right angles with the first major surface and a fourth major surface opposite to the third major surface. The fourth major surface becomes farther from the third major surface to become continuous with the second major surface with proximity to the first major surface. The second conductor includes a third portion and a fourth portion. The third portion is similar to the first portion. The fourth portion is similar to the second portion. The first semiconductor chip is placed between the second portion and the forth portion.

Abstract: The invention relates to leadframes and semiconductor chip package assemblies using leadframes, and to methods for their assembly. A disclosed embodiment of the invention includes a semiconductor package leadframe with a chip mounting surface for receiving a semiconductor chip and a plurality of leadfingers. The leadfingers have a proximal end for receiving one or more wirebond, and a distal end for providing an electrical path from the proximal end. One or more of the leadfingers also has an offset portion at its proximal end for increasing the clearance between the leadfinger and underlying heat spreader, increasing the stiffness of the leadfinger, and increasing leadfinger deflection-resistance and spring-back. The offset is in the direction opposite the plane of a heat spreader thermally coupled to the mounting surface.

Abstract: Methods, systems, and apparatuses for integrated circuit packages, and for package stacking, are provided. An electrically conductive frame is attached to a first surface of a substrate. The electrically conductive frame includes a perimeter ring portion, a plurality of leads, and a plurality of interconnect members positioned within a periphery formed by the perimeter ring portion. Each interconnect member is coupled to the perimeter ring portion by a respective lead. A first end of each interconnect member is coupled to the first surface of the substrate. An encapsulating material is applied to the first surface of the substrate, without covering a second end of each interconnect member with the encapsulating material. The perimeter ring portion is removed from the electrically conductive frame to isolate the plurality of interconnect members. A first integrated circuit package is formed in this manner. A second integrated circuit package may be mounted to the first package.

Abstract: Apparatus may be provided including a high power light emitting diode (LED) unit, at least one printed circuit board, and an interfacing portion of a heat sink structure. The high power LED unit includes at least one LED die, at least one first lead and at least one second lead, and a heat sink interface. The at least one printed circuit board includes a conductive pattern configured to connect both the at least one first lead and the at least one second lead to a current source. The interfacing portion of the heat sink structure is that portion through which a majority of heat of the heat sink interface is transmitted. The interfacing portion is directly in touching contact with a majority of a heat transfer area of the heat sink interface.

Abstract: According to one embodiment, a light emitting device includes a first lead, a light emitting element, a second lead and a molded body. The first lead includes a die pad portion having a major surface and a recess provided in the major surface, a bent portion bent toward above the major surface, and a thermally conductive portion extending outward from the die pad portion. The first lead is provided with a slit at an end of a fold. The light emitting element is bonded to a bottom surface of the recess. The second lead with one end portion is opposed to one end portion of the first lead. The molded body covers the light emitting element, the bent portion, the die pad portion, the thermally conductive portion, and the one end portion of the second lead, penetrates through the slit, and is made of a resin.

Abstract: A heat-transfer mechanism which transfers heat of a heat-generating component mounted on a board to a housing includes a heat-transfer plate having a bottom face portion which has contact with the heat-generating component, a first heat-transfer portion which is screwed near one end portion of the housing and a second heat-transfer portion which is screwed near the other end portion of the housing.

Abstract: A chip package structure including a substrate, at least one chip, a plurality of leads, a heat dissipation device, a molding compound, and at least one insulating sheet is provided. The chip is disposed on the substrate. The leads are electrically connected to the substrate. The molding compound having a top surface encapsulates the chip, the substrate, and a portion of the leads. The heat dissipation device is disposed on the top surface of the molding compound. The insulating sheet disposed between the heat dissipation device and at least one of the leads has a bending line dividing the insulating sheet into a main body disposed on the molding compound and a bending portion extending from the main body.

Abstract: A system and method are provided for directly coupling a chassis and a heat sink. A circuit board is provided with at least one processor mounted thereon. Additionally, a heat sink is provided, the heat sink being mechanically coupled to at least one of the circuit board and the processor for providing thermal communication between the heat sink and the circuit board. Furthermore, a mount is provided, the mount being coupled to the heat sink for providing a direct mechanical coupling with a chassis.

Abstract: A light emitting chip includes a substrate, an epitaxial structure comprising a first semiconductor layer, a light emitting layer and a second semiconductor layer, a current conducting structure formed on a bottom side of the first semiconductor layer of the epitaxial structure, and heat conducting protrusions formed on a top side of the substrate. Each of the heat conducting protrusions includes a carbon nanotube layer vertically grown thereon. The heat conducting protrusions are embedded into the current conducting structure to thermally connect with the first semiconductor layer. A method for manufacturing the light emitting chip is also disclosed.

Abstract: Disclosed is a heat dissipating circuit board, which includes a metal core including an insulating layer formed on the surface thereof, a circuit layer formed on the insulating layer and including a seed layer and a first circuit pattern, and a heat dissipating frame layer bonded onto the circuit layer using solder and having a second circuit pattern, and in which the heat dissipating frame layer is bonded onto the circuit layer not by a plating process but by using solder, thus reducing the cost and time of the plating process and relieving stress applied to the heat dissipating circuit board due to the plating process. A method of manufacturing the heat dissipating circuit board is also provided.

Abstract: A semiconductor chip is mounted on a heat sink disposed inside a through-hole of a wiring board, electrodes of the semiconductor chip and connecting terminals of the wiring board are connected by bonding wires, a sealing resin is formed to cover the semiconductor chip and the bonding wires, and solder balls are formed on the lower surface of the wiring board, thereby constituting the semiconductor device. The heat sink is thicker than the wiring board. The heat sink has a protruded portion protruding to outside from the side surface of the heat sink, the protruded portion is located on the upper surface of the wiring board outside the through-hole, and the lower surface of the protruded portion contacts to the upper surface of the wiring board. When the semiconductor device is manufactured, the heat sink is inserted from the upper surface side of the wiring board.

Abstract: Embodiments of the present invention relate to the use of stamping to form features on a lead frame of a semiconductor device package. In one embodiment, portions of the lead frame such as pins are moved out of the horizontal plane of a diepad by stamping. In certain embodiments, indentations or a complex cross-sectional profile, such as chamfered, may be imparted to portions of the pins and/or diepad by stamping. The complexity offered by such a stamped cross-sectional profile serves to enhance mechanical interlocking of the lead frame within the plastic molding of the package body. Other techniques such as selective electroplating and/or formation of a brown oxide guard band to limit spreading of adhesive material during die attach, may be employed alone or in combination to facilitate fabrication of a package having such stamped features.

Abstract: Embodiments of the present invention relate to the use of stamping to form features on a lead frame of a semiconductor device package. In one embodiment, portions of the lead frame such as pins are moved out of the horizontal plane of a diepad by stamping. In certain embodiments, indentations or a complex cross-sectional profile, such as chamfered, may be imparted to portions of the pins and/or diepad by stamping. The complexity offered by such a stamped cross-sectional profile serves to enhance mechanical interlocking of the lead frame within the plastic molding of the package body. Other techniques such as selective electroplating and/or formation of a brown oxide guard band to limit spreading of adhesive material during die attach, may be employed alone or in combination to facilitate fabrication of a package having such stamped features.

Abstract: An electric power converter includes: a heat sink having a heat receiving surface; a semiconductor module including a metal plate having a heat radiation surface, a switching element on the metal plate opposite to the heat radiation surface, and a resin member covering a part of the metal plate and the switching element; a heat radiation member between the heat receiving surface and the semiconductor module for transmitting heat of the switching element to the heat receiving surface via the metal plate. The heat receiving surface includes a concavity, and the heat radiation surface includes a convexity. The heat radiation member has a predetermined area sandwiched between the concavity and the convexity.

Abstract: A semiconductor device includes a semiconductor chip including back side metal, a substrate, and an electrically conductive heat spreader directly contacting the back side metal. The semiconductor chip includes a sintered joint directly contacting the heat spreader and electrically coupling the heat spreader to the substrate.

Abstract: A semiconductor package and a method of manufacturing the same, and more particularly, to a package of a power module semiconductor and a method of manufacturing the same. The semiconductor package includes a substrate including a plurality of conductive patterns spaced apart from one another; a plurality of semiconductor chips disposed on the conductive patterns; a connecting member for electrically connecting the conductive patterns to each other, for electrically connecting the semiconductor chips to each other, or for electrically connecting the conductive pattern and the semiconductor chip; and a sealing member for covering the substrate, the semiconductor chips, and the connecting member, wherein a lower surface of the substrate and an upper surface of the connecting member are exposed to the outside by the sealing member.

Abstract: An integrated circuit package system comprising: providing a package substrate; attaching an integrated circuit die over the package substrate wherein the integrated circuit die has a mount height; attaching an attachment structure having a height substantially the same as the mount height and planar dimensions predetermined to fit adjacent the integrated circuit die and over the package substrate; and attaching a heat dissipation device over the integrated circuit die and the attachment structure.

Abstract: A semiconductor chip package comprises a lead frame having a chip carrier having a first surface and an opposite second surface. A first semiconductor chip is mounted on the first surface, having a plurality of bonding pads thereon, wherein the first semiconductor chip has an area larger that that of the chip carrier. A package substrate has a central region attached to the second surface of the chip carrier, having an area larger than that of the first semiconductor chip, wherein the package substrate comprises a plurality of fingers on a top surface thereof in a marginal region of the package substrate, which are arranged in an array with a row of inner fingers adjacent to the first semiconductor chip and a row of outer fingers adjacent to an edge of the package substrate, wherein the inner and outer fingers are electrically connected to the bonding pads of the first semiconductor chip and the lead frame respectively.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; attaching a base device over the base substrate; attaching a leadframe having a leadframe pillar adjacent the base device over the base substrate; applying a base encapsulant over the base device, the base substrate, and the leadframe; removing a portion of the base encapsulant and a portion of the leadframe providing the leadframe pillar partially exposed; and attaching a base substrate connector to the base substrate directly below the leadframe pillar.

Abstract: A driver IC which is operated by a power supply system insulated from a control IC is mounted in the vicinity of a switching element on a first conductor pattern. A second conductor pattern connected to a source terminal or an emitter terminal of the switching element is electrically connected to a third conductor pattern on which the driver IC is mounted. A ground terminal of the driver IC is electrically connected to the third conductor pattern, and a drive terminal of the driver IC is electrically connected to a gate terminal or a base terminal of the switching element.

Abstract: A semiconductor device according to the present disclosure includes: a plate (13) having a through hole (15); a metal column (16) fixed to the through hole with an insulating member (17) interposed therebetween, and having a projection projecting from the upper surface of the plate; a semiconductor element (12) fixed to the projection; a lead frame (11) electrically connected to the semiconductor element; and a package (14) covering the semiconductor element, and also covering at least part of each of the plate, the metal column, and the lead frame. The lower surface (13b) of the plate is exposed from the package.

Abstract: A semiconductor heat spreader from a unitary metallic plate is provided. The unitary metallic plate is formed into a panel, channel walls, at least two feet, and at least one external reversing bend. The channel walls depend from the panel to define a channel between the channel walls and the panel for receiving a semiconductor therein. The feet extend from respective channel walls for attachment to a substrate.

Abstract: A semiconductor device includes: a substrate; a semiconductor element installed on the substrate so that a surface formed with an electrode is directed to the substrate; a chip capacitor installed on the substrate; and a conductive material covering a rear surface opposite to the surface of the semiconductor element and joining to one terminal electrode of the chip capacitor.

Abstract: Provided are a power device package, which can be made compact by vertically stacking substrates on which semiconductor chips are mounted, and a method of fabricating the power device package.

Abstract: A semiconductor die package. The semiconductor die package includes a leadframe structure comprising a first lead structure comprising a die attach pad, a second lead structure, and a third lead structure. It also includes a semiconductor die comprising a first surface and a second surface. The semiconductor die is on the die attach pad of the leadframe structure. The first surface is proximate the die attach pad. The semiconductor die package further includes a clip structure comprising a first interconnect structure and a second interconnect structure, the first interconnect structure comprising a planar portion and a protruding portion, the protruding portion including an exterior surface and side surfaces defining the exterior surface. The protruding portion extends from the planar portion of the first interconnect structure.

Abstract: A modular package for a light emitting device includes a leadframe having a top surface and including a central region having a bottom surface and having a first thickness between the top surface of the leadframe and the bottom surface of the central region. The leadframe may further include an electrical lead extending away from the central region. The electrical lead has a bottom surface and has a second thickness from the top surface of the leadframe to the bottom surface of the electrical lead. The second thickness may be less than the first thickness. The package further includes a package body on the leadframe surrounding the central region and exposing the bottom surface of the central region. The package body may be at least partially provided beneath the bottom surface of the lead and adjacent the bottom surface of the central region. Methods of forming modular packages and leadframes are also disclosed.

Abstract: An integrated circuit package system having a body with a top surface, a bottom surface, and a plurality of side surfaces has a leadframe and encapsulating material that encapsulates at least a portion of the leadframe. The leadframe and encapsulating material are part of the body. The leadframe has a die paddle for supporting a die, and a plurality of leads spaced from the die paddle. The encapsulating material thus also separates the die paddle from the plurality of leads. At least a first portion of the die paddle is exposed to the top surface, while at least a second portion of the die paddle is exposed to the bottom surface.

Abstract: The invention provides a semiconductor high-power light-emitting module including a heat-dissipating member, a heat-conducting device, and a diode light-emitting device. The heat-dissipating member includes an isolator member coupled to a first side of the heat-dissipating member. The heat-dissipating member has a second side opposite to the first side. The isolator member has a third side opposite to the first side. The environment temperature at the third side is higher than that at the second side. The heat-conducting device has a flat end and a contact portion tightly mounted on the heat-dissipating member. The diode light-emitting device is disposed on the flat end of the heat-conducting device. The semiconductor light-emitting module of the invention, applied to a headlamp of an automobile, has properties of saving electricity and long life, and furthermore the capability of integrating the heat-dissipating member into a shell of the automobile is both artistic and practical.

Abstract: A high-speed I/O trace is part of an I/O package architecture for an integrated circuit package substrate. The integrated circuit package substrate includes an integrated heat spreader footprint on a die-side and the I/O trace to couple with an IC device to be disposed inside the IHS footprint. The I/O trace includes a pin-out terminal outside the IHS footprint to couple to an IC device to be disposed outside the IHS footprint. The high-speed I/O trace can sustain a data flow rate from a processor in a range from 5 gigabits per second (Gb/s) to 40 Gb/s.