Abstract: Disclosed are a leadframe having heat sink supporting parts, a light emitting diode package in which the leadframe is employed, and a fabricating method of a light emitting diode package using the leadframe. The leadframe includes an outer frame surrounding a predetermined region. The heat sink supporting parts extend inward to face each other from the outer frame. Each of the supporting parts has an end portion coupled to a heat sink. Further, lead terminals extend inward to face each other from the outer frame. The lead terminals are spaced apart from the supporting parts. Accordingly, a package main body can be formed by an insert molding technique after the heat sink is coupled to the end portions of the supporting parts, and the heat sink and the lead terminals can be easily aligned.

Abstract: A light-emitting diode includes a circuit board, a pair of electrodes provided on the circuit board, at least one light-emitting diode element electrically connected to the pair of electrodes, a central electrode for heat-dissipation, provided between the pair of electrodes on the circuit board, and a heat-dissipation plate disposed on the central electrode for heat-dissipation and including a reflection surface. The central electrode for heat-dissipation includes an upper central electrode disposed on the upper surface of the circuit board and a lower central electrode disposed on the lower surface of the circuit board and the upper central electrode thermally connected to the lower central electrode.

Abstract: A semiconductor package that includes a semiconductor die and a heat spreader thermally coupled to the semiconductor and disposed at least partially within the molded housing of the package.

Abstract: A method of forming an electronic assembly includes attaching a backside metal layer the bottomside of a semiconductor die. An area of the backside metal layer matches an area of the bottomside of the die. A die pad and leads are encapsulated within the molding material. The leads include an exposed portion that includes a bonding portion. A gap exposes the backside metal layer along a bottom surface of the package. Bond wires couple the pads on the topside of the die to the leads and the bonding portions. Packaged semiconductor device is soldered to a printed circuit board (PCB). The backside metal layer and the bonding portions of the leads are soldered substrate pads on said PCB.

Abstract: A thin flip chip package structure comprises a substrate, a chip and a heat dissipation paste, wherein the substrate comprises an insulating layer and a trace layer. The insulating layer comprises a first insulating portion and a second insulating portion, the first insulating portion comprises a first upward surface, a first downward surface, a first thickness and a recess formed on the first downward surface, wherein the recess comprises a bottom surface. The second insulating portion comprises a second upward surface, a second downward surface and a second thickness larger than the first thickness. The trace layer is at least formed on the second insulating portion, the chip disposed on top of the substrate is electrically connected with the trace layer and comprises a plurality of bumps, and the heat dissipation paste is disposed at the recess.

Abstract: Disclosed herein is a semiconductor package, including: a first heat dissipation substrate; a first lead frame that is formed on the first heat dissipation substrate by patterning; a first semiconductor device formed on the first lead frame; a second semiconductor device that is stacked on the first semiconductor device; a second lead frame that is patterned and bonded to the second semiconductor device; and a second heat dissipation substrate formed on the first lead frame.

Abstract: Disclosed herein is a semiconductor package. The semiconductor package includes: semiconductor elements, a first heat dissipation substrate formed under the semiconductor elements, a first lead frame electrically connecting the lower portions of the semiconductor elements to an upper portion of the first heat dissipation substrate, a second heat dissipation substrate formed over the semiconductor elements, and a second lead frame having a protrusion formed to be protruded from a lower surface thereof and electrically connecting the upper portions of the semiconductor elements to a lower portion of the second heat dissipation substrate.

Abstract: A packaged leadless semiconductor device (20) includes a heat sink flange (24) to which semiconductor dies (26) are coupled using a high temperature die attach process. The semiconductor device (20) further includes a frame structure (28) pre-formed with bent terminal pads (44). The frame structure (28) is combined with the flange (24) so that a lower surface (36) of the flange (24) and a lower section (54) of each terminal pad (44) are in coplanar alignment, and so that an upper section (52) of each terminal pad (44) overlies the flange (24). Interconnects (30) interconnect the die (26) with the upper section (52) of the terminal pad (44). An encapsulant (32) encases the frame structure (28), flange (24), die (26), and interconnects (30) with the lower section (54) of each terminal pad (44) and the lower surface (36) of the flange (24) remaining exposed from the encapsulant (32).

Abstract: The present disclosure provides systems and methods for forming a semiconductor device. The semiconductor device includes a substrate having a first side and a second side opposite the first side. A first heat producing element is formed on the first side of the substrate. A second heat producing element is formed on the first side of substrate co-planar with, but not touching the first heat producing element. A heat spreader is coupled to the second side of the substrate using a thermal interface material. The heat spreader includes a first and second vapor chambers. The first vapor chamber is embedded in the heat spreader substantially opposite the first heat producing element. The second vapor chamber is embedded in the heat spreader substantially opposite the second heat producing element. As an example, the first heat producing element may be a light-emitting diode (LED) and the second heat producing element may be a driver circuit for the LED.

Abstract: A packaged power semiconductor device is provided with voltage isolation between a metal backside and terminals of the device. The packaged power semiconductor device is arranged in an encapsulant defining a hole for receiving a structure for physically coupling the device to an object. A direct-bonded copper (“DBC”) substrate is used to provide electrical isolation and improved thermal transfer from the device to a heatsink. At least one power semiconductor die is mounted to a first metal layer of the DBC substrate. The first metal layer spreads heat generated by the semiconductor die. In one embodiment, the packaged power semiconductor device conforms to a TO-247 outline and is capable of receiving a screw for physically coupling the device to a heatsink.

Abstract: A structure includes a circuit substrate including a first substrate and a second substrate. The first substrate has a region where an electronic component is to be mounted. The second substrate has a side surface connected to a first side surface of the first substrate. The structure further includes a frame on the circuit substrate, enclosing the region in a plane view. The frame crosses the boundary between the first substrate and the second substrate.

Abstract: A double-side exposed semiconductor device includes an electric conductive first lead frame attached on top of a thermal conductive but electrical nonconductive second lead frame and a semiconductor chip flipped and attached on top of the first lead frame. The gate and source electrodes on top of the flipped chip form electrical connections with gate and source pins of the first lead frame respectively. The flipped chip and center portions of the first and second lead frames are then encapsulated with a molding compound, such that the heat sink formed at the center of the second lead frame and the drain electrode at bottom of the semiconductor chip are exposed on two opposite sides of the semiconductor device. Thus, heat dissipation performance of the semiconductor device is effectively improved without increasing the size of the semiconductor device.

Abstract: A leadframe, device package, and mode of construction configured to attain a thin profile and improved thermal performance. Leadframes of this invention include a raised die attachment pad arrange above distal ends of leadframe leads. A package will further include a die electrically coupled with an underside surface of the raised die attachment pad, in one example, using ball bonds, the whole sealed in an encapsulant that exposed a bottom portion of the die and a portion of a lead. Two leadframe stacks of such packages are also disclosed as are methods of manufacture.

Abstract: A package includes: a leadframe made of conductive material and on which the plurality of electronic components are to be mounted, the leadframe including a first surface and a second surface opposite to the first surface and including a plurality of elongate portions arranged in parallel to each other with a gap interposed between the adjacent elongate portions; a heat sink including a first surface and a second surface opposite to the first surface, wherein the leadframe is disposed above the heat sink such that the second surface of the leadframe faces the first surface of the heat sink; and a resin portion, wherein the leadframe and the heat sink are embedded in the resin portion such that the first surface of the leadframe and the second surface of the heat sink are exposed from the resin portion, respectively.

Abstract: Heat radiation surfaces 7b and 8b of electrode lead frames 7 and 8 make thermal contact with heat radiation members 301 via insulation sheets 10 to dissipate heat from a power semiconductor element 5 to the heat radiation members (thick portions 301). Each of exposed areas of the heat radiation surfaces 7b and 8b and a surface 13b of a mold material (sealing material 13) adjacent to the exposed area produce an uneven step from which either one of the exposed area and the surface 13b adjacent to the exposed area projects. The step side surface formed between the convex surface and the concave surface of the uneven step has an inclined surface 7a or 13a so configured that an obtuse angle can be formed by the inclined surface and the convex surface and by the inclined surface and the concave surface for each.

Abstract: Disclosed herein is a semiconductor package, including: a substrate having a first surface and a second surface; at least one semiconductor device formed on the first surface of the substrate; first lead frames respectively formed at both sides of the first surface of the substrate; and second lead frames respectively formed at both sides of the second surface of the substrate, wherein the first lead frame and the second lead frame are spaced apart from each other by an isolation distance base.

Abstract: A top-side cooled semiconductor package with stacked interconnection plate is disclosed. The semiconductor package includes a circuit substrate with terminal leads, a semiconductor die atop the circuit substrate, a low thermal resistance intimate interconnection plate for bonding and interconnecting a top contact area of the semiconductor die with the circuit substrate, a low thermal resistance stacked interconnection plate atop the intimate interconnection plate for top-side cooling, a molding encapsulant for encapsulating the package except for exposing a top surface of the stacked interconnection plate to maintain effective top-side cooling. The top portion of the stacked interconnection plate can include a peripheral overhang above the intimate interconnection plate. The peripheral overhang allows for a maximized exposed top surface area for heat dissipation independent of otherwise areal constraints applicable to the intimate interconnection plate.

Abstract: The semiconductor device has a unit stack body including a plurality of units stacked on one another. Each unit includes a power terminal constituted of a lead part and a connection part. The connection part is formed with a projection and a recess. When the units are stacked on one another, the projection of one unit is fitted to the recess of the adjacent unit, so that the power terminals of the respective unit are connected to one another.

Abstract: A semiconductor device includes a source region, a gate region and a drain region. A first leadframe subassembly is coupled to the drain region. on a second side of the die are attached to a second leadframe subassembly. A second leadframe subassembly has a first portion electrically coupled with the source region and a second portion electrically coupled with the gate region. The first leadframe subassembly is attached to a third leadframe subassembly. A die is interposed between the first leadframe subassembly and the second leadframe subassembly. The height of the third leadframe subassembly provides a standoff for a distance between the first leadframe subassembly and the second leadframe subassembly.

Abstract: Diode cell modules for use within photovoltaic systems, including lead frames including first leads extending from the first outlet terminal, second leads spaced from the first leads, second outlet terminals extending from the second leads, and diodes. In some examples, first leads define base portions connected to the first outlet terminal and diode portions extending from the base portions transverse to the first outlet terminal. In some examples, second leads may define a base portion and diode portions extending from the base portion substantially parallel to the diode portion of the first lead. In some examples, diodes may be in electrical contact with the diode portion of the first lead and with the diode portion of the second lead. In some examples, the first leads and second leads may be thermally conductive. In some examples, diodes may define die interfaces that are substantially fully engaged with diode portions of leads.

Abstract: A manufacturing method of a package carrier is provided. A substrate having an upper and lower surface is provided. A first opening communicating the upper and lower surface of the substrate is formed. A heat conducting element is disposed inside the first opening, wherein the heat conducting element is fixed in the first opening via an insulating material. At least a through hole passing through the substrate is formed. A metal layer is formed on the upper and lower surface of the substrate and inside the through hole. The metal layer covers the upper and lower surface of the substrate, the heat conducting element and the insulating material. A portion of the metal layer is removed. A solder mask is formed on the metal layer. A surface passivation layer is formed and covers the metal layer exposed by the solder mask and the metal layer located inside the through hole.

Abstract: An integrated circuit package system includes a leadframe with leads configured to provide electrical contact between an integrated circuit chip and an external electrical source. Configuring the leads to include outer leads, down set transitional leads, and down set inner leads. Connecting the integrated circuit chip electrically to the down set inner leads. Depositing an encapsulating material to prevent exposure of the down set inner leads.

Abstract: A package structure including a first leadframe, a second leadframe, a power pin, a ground pin, a first pin, several first wires, several second wires, and a package body is disclosed. The first leadframe is used for electrically coupling to the drains of a first power transistor and the second power transistor. The ground pin is electrically coupled to the first leadframe. The first pin is connected with the first leadframe through a conductive region used for increasing the amount of current which can be loaded by the first pin. The first wires are used for electrically coupling between the first leadframe and the source of the second power transistor, for reducing the internal resistance of the second power transistor. The second wires are used for electrically coupling between the ground pin and the source of the first power transistor, for reducing the internal resistance of the first power transistor.

Abstract: A stacked die package for an electromechanical resonator system includes an electromechanical resonator die bonded or fixed to a control IC die for the electromechanical resonator by, for example, a thermally and/or electrically conductive epoxy. In various embodiments, the electromechanical resonator can be a micro-electromechanical system (MEMS) resonator or a nano-electromechanical system (NEMS) resonator. Certain packaging configurations that may include the chip that contains the electromechanical resonator and the control chip include chip-on-lead (COL), chip-on-paddle (COP), and chip-on-tape (COT) packages. The stacked die package may provide small package footprint and/or low package thickness, and low thermal resistance and a robust conductive path between the dice.

Abstract: A semiconductor device includes a semiconductor element, a first heat sink, a second heat sink, and a resin member. The semiconductor element has first and second surfaces. The first heat sink has a first heat radiation surface and a first end surface. The first end surface is coupled with the first surface. The second heat sink has a second heat radiation surface, the second end surface being opposite the second heat radiation surface, and a depressed section depressed toward the second heat radiation surface. The second surface of the semiconductor element is coupled with a bottom surface of the depressed section. The resin member is disposed in the depressed section and seals the semiconductor element, the first heat sink, and the second heat sink in such a manner that the first heat radiation surface is exposed outside the resin member.

Abstract: A package structure including a circuit substrate, at least a chip, leads and an encapsulant is provided. The circuit substrate has a first surface, a second surface opposite to the first surface, and contacts disposed on the first surface. The chip is disposed on the second surface of the circuit substrate and electrically connected to the circuit substrate. The leads are disposed on the periphery of the second surface and surround the chip. Each lead has an inner lead portion and an outer lead portion and is electrically connected to the circuit substrate via the inner lead portion. The encapsulant encapsulates the circuit substrate, the chip and the inner lead portion and exposes the first surface of the circuit substrate and the outer lead portion, wherein the upper surface of the encapsulant and the first surface of the circuit substrate are coplanar with each other.

Abstract: Disclosed herein is a power module package, including: a first substrate having one surface and the other surface; first vias formed to penetrate from one surface of the first substrate to the other surface thereof; a metal layer formed on one surface of the first substrate; semiconductor devices formed on the metal layer; and a metal plate formed on the other surface of the first substrate.

Abstract: Disclosed herein are a power module package and a method for manufacturing the same. The power module package includes: a heat dissipation plate including a first heat dissipation plate and a second heat dissipation plate disposed to be spaced apart from each other; insulating layers formed on the heat dissipation plate; metal layers formed on the insulating layers, semiconductor devices mounted on the metal layers; and lead spacers formed to connect the metal layer of the first heat dissipation plate side or the metal layer of the second heat dissipation plate side with the semiconductor layers, wherein the semiconductor devices formed on the metal layers of the first heat dissipation plate side and the semiconductor devices formed on the metal layer of the second heat dissipation plate side are disposed in a multi-layered type.

Abstract: A semiconductor device includes a plurality of die pad sections, a plurality of semiconductor chips, each of which is arranged in each of the die pad sections, a resin encapsulation portion having a recess portion for exposing at least a portion of the die pad sections, the resin encapsulation portion configured to cover the die pad sections and the semiconductor chips, and a heat radiation layer arranged in the recess portion. The heat radiation layer includes an elastic layer exposed toward a direction in which the recess portion is opened. The heat radiation layer directly faces at least a portion of the die pad sections. The elastic layer overlaps with at least a portion of the die pad sections when seen in a thickness direction of the heat radiation layer.

Abstract: A semiconductor device includes: a cooling function component including an active region made of an impurity region and formed on a surface of a semiconductor layer, an N-type gate made of a semiconductor including an N-type impurity, a P-type gate made of a semiconductor including a P-type impurity, a first metal wiring connected to the N-type gate, the P-type gate and the active region, a second metal wiring connected to the P-type gate and the N-type gate, and a heat releasing portion connected to the second metal wiring for releasing heat to the outside.

Abstract: A method of forming a semiconductor device includes affixing a die to a heat sink to form a die and heat sink assembly and then placing the die and heat sink assembly on a support element. A semiconductor device includes a die and heat sink assembly disposed on a support element. The die and heat sink assembly is pre-assembled prior to being disposed on the support element.

Abstract: In a bump-on-leadframe semiconductor package a metal bump formed on a integrated circuit die is used to facilitate the transfer of heat generated in a semiconductor substrate to a metal heat slug and then to an external mounting surface.

Abstract: In one aspect of the invention, an integrated circuit package is described. The integrated circuit package includes a substrate formed from a dielectric material that includes multiple electrical contacts and conductive paths. An upper lead frame is attached with and underlies the substrate. The upper lead frame is electrically connected with at least one of the contacts on the substrate. The active surface of an integrated circuit die is electrically and physically coupled to the upper lead frame through multiple electrical connectors. A lower lead frame may be attached with the back surface of the integrated circuit die. A passive device is positioned on and electrically connected with one of the contacts on the substrate and/or the upper lead frame.

Abstract: A submount for a solid state lighting package includes a support member having upper and lower surfaces, a first side surface, and a second side surface opposite the first side surface, a first electrical bondpad on the upper surface of the support member and having a first bonding region proximate the first side surface of the support member and a second bonding region extending toward the second side surface of the support member, and a second electrical bondpad on the upper surface of the support member having a die mounting region proximate the first side surface of the support member and an extension region extending toward the second side surface of the support member. The die mounting region of the second electrical bondpad may be configured to receive an electronic device. The submount further includes a third electrical bondpad on the upper surface of the support member and positioned between the second side surface of the support member and the die mounting region of the second electrical bondpad.

Abstract: Provided is a circuit device having a configuration in which thermal interference between built-in elements is suppressed and being miniaturized in total size. A hybrid integrated circuit device of the present invention includes: a circuit substrate, a sealing resin and leads. The circuit substrate in its upper surface is incorporated with a hybrid integrated circuit formed of semiconductor elements and the like respectively fixed to heat spreaders. The sealing resin coats the circuit substrate and thus seals the hybrid integrated circuit. The leads each extend to the outside while being fixed to a pad formed of a conductive pattern. In this hybrid integrated circuit device, the semiconductor elements are mounted on the respective heat spreaders at positions offset from each other, and thereby are arranged to be spaced away from each other.

Abstract: A semiconductor package includes a metal plate, a power element, a lead frame having a die pad, a resin sheet having insulation properties, a control circuit that controls the power element, and a mold resin. The power element is mounted on the die pad, and the die pad is mounted on the metal plate via the resin sheet. The resin sheet is expanded including at least a lower surface of the die pad while the lower surface of the resin sheet is smaller than an surface of the metal plate, and the control circuit is arranged in a region on the metal plate, which region is other than the region where the power element is arranged.

Abstract: A side view light emitting diode (LED) package structure includes a package housing, a side view LED chip and a thermal conductive member. The side view LED chip is enclosed by the package housing and an emitting direction of the side view LED chip is perpendicular to a thickness direction of a substrate. The thermal conductive member connected with the side view LED chip is disposed inside the package housing and a portion of which extends out of a dissipation opening of the package housing to be exposed so that heat of the side view LED chip is dissipated.

Abstract: A molded, leadless packaged semiconductor multichip module includes 100 has four mosfets 10, 12, 14, 16 for a full bridge circuit. The mosfets may include two N-channel and two P-channel devices or four mosfets of the same type, but four N-channel are preferred. In module 100 there are two leadframes 30, 40 for assembling the mosfets. In particular, the two N-channel and two P-channel devices are disposed between two leadframes and encapsulated in an electrically insulating molding compound 84. The resulting package has four upper heat sinks 44.1-44.4 that are exposed in the molding compound 84 for transferring heat from the mosfets to the ambient environment. No wire bonds are required. This can significantly reduce the on resistance, RDSON. The top or source-drain lead frame 30 may be soldered to the sources and gates of the bridge mosfets.

Abstract: A double-side exposed semiconductor device includes an electric conductive first lead frame attached on top of a thermal conductive but electrical nonconductive second lead frame and a semiconductor chip flipped and attached on top of the first lead frame. The gate and source electrodes on top of the flipped chip form electrical connections with gate and source pins of the first lead frame respectively. The flipped chip and center portions of the first and second lead frames are then encapsulated with a molding compound, such that the heat sink formed at the center of the second lead frame and the drain electrode at bottom of the semiconductor chip are exposed on two opposite sides of the semiconductor device. Thus, heat dissipation performance of the semiconductor device is effectively improved without increasing the size of the semiconductor device.

Abstract: The present invention relates to a power device package module and a manufacturing method thereof. In one aspect of the present invention, a power device package module includes: a control unit a first lead frame, a control chip and a first coupling portion that are mounted on a first substrate, wherein the first lead frame and the first coupling portion are electrically connected to the control chip, and individually molded; and a power unit including a second lead frame, a power chip and a second coupling portion that are mounted on a second substrate, wherein the second lead frame and the second coupling portion are electrically connected to the power chip, and individually molded, wherein the individually molded control unit and power unit are coupled by the first coupling portion and the second coupling portion.

Abstract: Embodiments in accordance with the present invention relate to flip-chip packages for semiconductor devices, which feature a die sandwiched between metal layers. One metal layer comprises portions of the lead frame configured to be in electrical and thermal communication with various pads on a first surface of the die (e.g. IC pads or MOSFET gate or source pads) through a solder ball contact. The other metal layer is configured to be in at least thermal communication with the opposite side of the die. Embodiments of packages in accordance with the present invention exhibit superior heat dissipation qualities, while avoiding the expense of wire bonding. Embodiments of the present invention are particularly suited for packaging of power devices.

Abstract: A top-side cooled semiconductor package with stacked interconnection plate is disclosed. The semiconductor package includes a circuit substrate with terminal leads, a semiconductor die atop the circuit substrate, a low thermal resistance intimate interconnection plate for bonding and interconnecting a top contact area of the semiconductor die with the circuit substrate, a low thermal resistance stacked interconnection plate atop the intimate interconnection plate for top-side cooling, a molding encapsulant for encapsulating the package except for exposing a top surface of the stacked interconnection plate to maintain effective top-side cooling. The top portion of the stacked interconnection plate can include a peripheral overhang above the intimate interconnection plate. The peripheral overhang allows for a maximized exposed top surface area for heat dissipation independent of otherwise areal constraints applicable to the intimate interconnection plate.

Abstract: A parallel optical transceiver module is provided that has a heat dissipation system that dissipates large amounts of heat, while also protecting the laser diodes, ICs and other components of the module from particulates, such as dust, for example, and from mechanical handling forces. The heat dissipation system is configured to be secured to the optical subassembly (OSA) of the module such that when the OSA is secured to the upper surface of the leadframe of the module, the OSA and the heat dissipation system cooperate to encapsulate at least the laser diodes and laser diode driver IC in a way that protects these components from dust and other particulates and from external mechanical forces. The heat dissipation system of the module is disposed for coupling with an external heat dissipation system, e.g., with a heat dissipation system that is provided by the customer.

Abstract: A heat radiation structure of a light emitting element has leads, each lead having a plurality of leg sections, and a light emitting chip mounted on any one of the leads. The present invention can provide a high-efficiency light emitting element, in which a thermal load is reduced by widening a connecting section through which a lead and a chip seating section of the light emitting element are connected, and the heat generated from a heat source can be more rapidly radiated to the outside. Further, the present invention can also provide a high-efficiency light emitting element, in which heat radiation fins are formed between a stopper and a molding portion of a lead of the light emitting element so that natural convection can occur between the heat radiation fins, and an area in which heat radiation can occur is widened to maximize a heat radiation effect.

Abstract: A heat radiation structure of a light emitting element has leads, each lead having a plurality of leg sections, and a light emitting chip mounted on any one of the leads. The present invention can provide a high-efficiency light emitting element, in which a thermal load is reduced by widening a connecting section through which a lead and a chip seating section of the light emitting element are connected, and the heat generated from a heat source can be more rapidly radiated to the outside. Further, the present invention can also provide a high-efficiency light emitting element, in which heat radiation fins are formed between a stopper and a molding portion of a lead of the light emitting element so that natural convection can occur between the heat radiation fins, and an area in which heat radiation can occur is widened to maximize a heat radiation effect.

Abstract: A microelectronic unit can include a lead frame and a device chip. The lead frame can have a plurality of monolithic lead fingers extending in a plane of the lead frame. Each lead finger can have a fan-out portion and a chip connection portion extending in the lead frame plane. The fan-out portions can have first and second opposed surfaces and a first thickness in a first direction between the opposed surfaces. The chip connection portions can have a second thickness smaller than the first thickness. The chip connection portions can define a recess below the first surface. The device chip can have a plurality of at least one of passive devices or active devices. The device chip can have contacts thereon facing the chip connection portions and electrically coupled thereto. At least a portion of a thickness of the device chip can extend within the recess.

Abstract: Disclosed herein is a semiconductor package including: first power device; second power device formed in an upper portion of the first power device; a first lead frame formed in a lower portion of the first power device; a second lead frame formed in the upper portion of the first power device and a lower portion of the second power device; a third lead frame formed in an upper portion of the second power device; a fourth lead frame electrically connected to at least one of the power device and the second power device; and a sealing substance exposing a part of the first through fourth lead frames and sealing the other parts thereof.

Abstract: The present invention provides a power semiconductor package. The power semiconductor package comprises a dual lead frame assembly comprising a bottom lead frame having a first heat sink pad at its bottom surface and a top lead frame having a second heat sink pad at its bottom surface. The top lead frame is coupled to the bottom lead frame by an isolation layer, wherein the isolation layer is a thermal conductive, but electrical isolative, material. The power semiconductor package further comprises a power semiconductor device coupled to the top lead frame of the dual lead frame assembly and an encapsulation member encapsulating the dual lead frame assembly and the power semiconductor device, while exposing the first heat sink pad at the bottom surface of the bottom lead frame.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a lead array having an innermost space with an innermost lead having an inner lead profile different around an inner non-horizontal side of the innermost lead; forming a middle lead having a middle lead profile the same around a lead side of the middle lead; placing an integrated circuit in the innermost space adjacent to the innermost lead; and forming a package encapsulation over the integrated circuit, the innermost lead, and the middle lead.

Abstract: Provided is a semiconductor device including a flexible circuit board which includes a first external electrode provided on a first face and second and third external electrodes provided on a second face; a plurality of memory devices and passive components; a supporter which is provided with a groove on one face; and a computing processor device. The memory devices and the passive components are connected to the first external electrode, the one face of the supporter is bonded on the first face of the flexible circuit board so that the groove houses the memory devices and the passive components. The flexible circuit board is bent along a perimeter of the supporter to be wrapped around a side face and another face of the supporter. On the flexible circuit board, the second external electrode is provided on the second face which is opposite to the first external electrode, and the third external electrode is provided on the second face which is bent to the another face of the supporter.