Abstract: A method includes preparing a bonding surface of a heat dissipating member, applying flux to the bonding surface of the heat dissipating member, and removing excess flux from the bonding surface so that minimal flux is provided. The method also includes preparing a die surface of an electronic device package, applying flux to the die surface, and removing excess flux from the die surface so that minimal flux is provided. The method further includes positioning a preform solder component on the die surface, positioning the heat dissipating member over the die surface and the preform solder component such that the flux layer of the bonding surface is in contact with the preform solder component, and reflowing the solder component using a reflow oven. A heat spreader is also described for use in the process.

Abstract: Semiconductor packages including a die pad, at least one connecting bar, at least one supporting portion, a plurality of leads, a semiconductor chip, a heat sink and a molding compound. The connecting bar connects the die pad and the supporting portion. The leads are electrically isolated from each other and the die pad. The semiconductor chip is disposed on the die pad and electrically connected to the leads. The heat sink is supported by the supporting portion. The molding compound encapsulates the semiconductor chip and the heat sink. Heat from the semiconductor chip is efficiently dissipated from the die pad through the connecting bar, through the supporting portion, and through the heat sink.

Abstract: A semiconductor device (100) comprises a semiconductor chip (310) attached to the pad (302) of a planar leadframe and connected by bonding wires (411) to two leads (403) of the leadframe. The device further includes a plastic body (130) encapsulating chip and wires, the body shaped as a pentahedron with two sides (101, 102) touching at right angle, opposite body ends formed by parallel planes configured as right-angle triangles. The pad (302) and the two leads (303) are exposed from the plastic surface at one body end in order to be operable as solderable device pins positioned in the corners of the triangle.

Abstract: A double-side exposed semiconductor device includes an electric conductive first lead frame attached on top of a thermal conductive but electrical nonconductive second lead frame and a semiconductor chip flipped and attached on top of the first lead frame. The gate and source electrodes on top of the flipped chip form electrical connections with gate and source pins of the first lead frame respectively. The flipped chip and center portions of the first and second lead frames are then encapsulated with a molding compound, such that the heat sink formed at the center of the second lead frame and the drain electrode at bottom of the semiconductor chip are exposed on two opposite sides of the semiconductor device. Thus, heat dissipation performance of the semiconductor device is effectively improved without increasing the size of the semiconductor device.

Abstract: A lead frame includes a plurality of leads defined by an opening extending in a thickness direction. An insulating resin layer fills the opening to entirely cover side surfaces of each lead and to support the leads. A first surface of each lead is exposed from a first surface of the insulating resin layer.

Abstract: An integrated circuit (IC) package having an IC device; a heat source operably associated with said IC device; an electrical substrate operably electrically connected to the IC device; and a thermal isolation mat positioned between the IC device and the electrical substrate and having a base surface, a ceiling structure and a plurality of spaced apart elongate members positioned between the base surface and the ceiling structure. Other heat isolation structures are also disclosed.

Abstract: Provided are a semiconductor die and a semiconductor package. The semiconductor package includes: a monolithic die; a driving circuit, a low-side output power device, and a high-side output power device disposed in the monolithic die; and an upper electrode and a lower electrode disposed above and below the monolithic die.

Abstract: What is disclosed is a modular visualization display panel. The modular visualization display panel includes a first module having at least one surface and a connection to electrical ground. The modular visualization display panel also includes a second module having at least one surface with a plurality of raised contact nodes arranged on the one surface of the second module such that when in contact with the one surface of the first module electrostatic discharge energy is directed over at least one of the raised contact nodes to the one surface of the first module.

Abstract: A lead frame for a light-emitting diode (LED). The lead frame includes a first lead and a second lead. Each lead includes a top portion and an integrated wire-clasping portion. The first and second top portions each angle away from the center of the lead frame to form an increasingly larger gap between the two leads. The wire-clasping portions of each lead initially lie in a common plane and are adjacent one another. After securing the wire to the wire-clasping portions of the lead frame, the leads of the lead frame are rotated or twisted approximately 90 degrees such that the wire-clasping portions of the leads are opposite one another, rather than lying in the same plane. The wires and attached lead frame are inserted into a lampholder, the lampholder recesses receiving the top tabs of the lead frame and holding the wires and lead frame in place.

Abstract: A semiconductor device includes a die pad and a semiconductor die having a mounting surface attached to the die pad and an opposite, active surface with die external terminals. The device has package external connectors, each having a bond region selectively electrically coupled to the die external terminals with a bond wire. A heat spreader has a first region that encloses an inner recessed region. A thermally conductive sheet is sandwiched between the inner recessed region of the heat spreader and the active surface of the die. At least the die, die external terminals, and the bond region are covered with an encapsulant.

Abstract: A semiconductor device includes an IGBT as a vertical semiconductor element provided between first, and second lead frames, in pairs, the first, and second lead frames being opposed to each other, first and second sintered-metal bonding layers provided on first and second bonding surfaces of the IGBT, in pairs, respectively, a through-hole opened in the second lead frame, and a heat-release member having a surface on one side thereof, bonded to a second sintered-metal bonding layer of the second bonding surface while a side (lateral face) of a surface of the heat-release member, on the other side thereof, being fitted into the through-hole. A solder layer is formed in a gap between an outer-side wall of the side of the surface of the heat-release member, on the other side thereof, and an inner-side wall of the through-hole.

Abstract: The subject matter of the present application relates to a heat dissipation device that is embedded within a microelectronic die. The heat dissipation device may be fabricated by forming at least one trench extending into the microelectronic die from a microelectronic die back surface, which opposes an active surface thereof, and filling the trenches with at least one layer of thermally conductive material. In one embodiment, the heat dissipation device may be a thermoelectric cooling device.

Abstract: A packaged power semiconductor device is provided with voltage isolation between a metal backside and terminals of the device. The packaged power semiconductor device is arranged in an encapsulant defining a hole for receiving a structure for physically coupling the device to an object. A direct-bonded copper (“DBC”) substrate is used to provide electrical isolation and improved thermal transfer from the device to a heatsink. At least one power semiconductor die is mounted to a first metal layer of the DBC substrate. The first metal layer spreads heat generated by the semiconductor die. In one embodiment, the packaged power semiconductor device conforms to a TO-247 outline and is capable of receiving a screw for physically coupling the device to a heatsink.

Abstract: A low profile heat removal system suitable for removing excess heat generated by a component operating in a compact computing environment is disclosed.

Abstract: An electronic device including an insulating substrate, a chip and a patterned conductive layer is provided. The insulating substrate has an upper surface and a lower surface opposite to each other. The chip is disposed above the upper surface of the insulating substrate. The patterned conductive layer is disposed between the upper surface of the insulating substrate and the chip. The chip is electrically connected to an external circuit via the patterned conductive layer. Heat generated by the chip is transferred to external surroundings via the patterned conductive layer and the insulating substrate.

Abstract: A package for mounting a light emitting element includes a housing and a flat plate-shaped electrode. The electrode is exposed from a lower surface of the housing. An upper surface of the electrode includes a mounting area on which the light emitting element is mounted. An insulator is arranged on the upper surface of the electrode. An element connector is connected to the insulator. A tubular reflective portion extends from the element connector to a height corresponding to the upper surface of the housing. A terminal is arranged on the side surface of the housing and connected to the reflective portion. A recess accommodates the light emitting element. The recess is formed in an upper portion of the housing, and the recess is formed by the upper surface of the electrode, the element connector, and the reflective portion.

Abstract: A light-emitting diode includes a carrier with a mounting face and includes a metallic basic body and at least two light-emitting diode chips affixed to the carrier at least indirectly at the mounting face, wherein an outer face of the metallic basic body includes the mounting face, the at least two light-emitting diode chips connect in parallel with one another, the at least two light-emitting diode chips are embedded in a reflective coating, the reflective coating covering the mounting face and side faces of the light-emitting diode chips, and the light-emitting diode chips protrude with their radiation exit surfaces out of the reflective coating, and the radiation exit surfaces face away from the carrier.

Abstract: A packaged semiconductor device may include a termination surface having terminations configured as leadless interconnects to be surface mounted to a printed circuit board. A first flange has a first surface and a second surface. The first surface provides a first one of the terminations, and the second surface is opposite to the first surface. A second flange also has a first surface and a second surface, with the first surface providing a second one of the terminations, and the second surface is opposite to the first surface. A die is mounted to the second surface of the first flange with a material having a melting point in excess of 240° C. An electrical interconnect extends between the die and the second surface of the second flange opposite the termination surface, such that the electrical interconnect, first flange and second flange are substantially housed within a body.

Abstract: One implementation of present disclosure includes a semiconductor package stack. The semiconductor package stack includes an upper package coupled to a lower package by a plurality of solder balls. The semiconductor package stack also includes a lower active die situated in a lower package substrate in the lower package. The lower active die is thermally coupled to a heat spreader in the upper package by a thermal interface material. An upper active die is situated in an upper package substrate in the upper package, the upper package substrate being situated over the heat spreader. The thermal interface material can include an array of aligned carbon nanotubes within a filler material. The heat spreader can include at least one layer of metal or metal alloy. Furthermore, the heat spreader can be connected to ground or a DC voltage source. The plurality of solder balls can be situated under the heat spreader.

Abstract: A semiconductor device includes an electrically conducting carrier having a mounting surface. The semiconductor device further includes a metal block having a first surface facing the electrically conducting carrier and a second surface facing away from the electrically conducting carrier. A semiconductor power chip is disposed over the second surface of the metal block.

Abstract: A double-side exposed semiconductor device includes an electric conductive first lead frame attached on top of a thermal conductive but electrical nonconductive second lead frame and a semiconductor chip flipped and attached on top of the first lead frame. The gate and source electrodes on top of the flipped chip form electrical connections with gate and source pins of the first lead frame respectively. The flipped chip and center portions of the first and second lead frames are then encapsulated with a molding compound, such that the heat sink formed at the center of the second lead frame and the drain electrode at bottom of the semiconductor chip are exposed on two opposite sides of the semiconductor device. Thus, heat dissipation performance of the semiconductor device is effectively improved without increasing the size of the semiconductor device.

Abstract: A method of manufacturing is provided that includes providing a semiconductor chip with an insulating layer. The insulating layer includes a trench. A second semiconductor chip is stacked on the first semiconductor chip to leave a gap. A polymeric filler is placed in the gap wherein a portion of the polymeric filler is drawn into the trench.

Abstract: In a semiconductor package a lead having a bottom surface coplanar with the flat bottom surface of the plastic body extends outward at the bottom of the vertical side surface of the plastic body. The result is a package with a minimal footprint that is suitable for the technique known as “wave soldering” that is used in relatively low-cost printed circuit board assembly factories. Methods of fabricating the package are disclosed.

Abstract: A multi-LED package includes a heat sink including a primary slug and a secondary slug separated from each other, a primary LED chip mounted on the primary slug, one or more secondary LED chips mounted on the secondary slug, a lead frame structure electrically wired to the primary and secondary LED chips, and a phosphor covering at least a part of the primary LED chip. Another multi-LED package includes a heat sink having an upper surface and partitions protruding therefrom, a primary LED chip mounted inside the partitions, one or more secondary LED chips mounted outside the partitions, a lead frame structure electrically wired to the primary and secondary LED chips, and a phosphor covering at least a part of the primary LED chip.

Abstract: An electronic device includes at least one electronic component chip having a first conduction terminal and a control terminal on a first surface of the chip and a second conduction terminal on a second surface opposite the first surface of the chip. An insulating body embeds the chip. The insulating body includes a mounting surface and an electrically conductive heat-sink connected to the first conduction terminal on the first surface of the chip, but insulated from the control terminal. An opening in a first surface of the insulating body exposes a surface of the electrically conductive heat sink. The electrically conductive heat sink includes a perimeter cavity configured for alignment with an encircling configuration of the control terminal, wherein the perimeter cavity contains a material that insulates the control terminal from the heat sink.

Abstract: In one embodiment, a semiconductor module includes a leadframe having a first side and an opposite second side. A semiconductor chip is disposed over the first side of the leadframe. A switching element is disposed under the second side of the leadframe. In another embodiment, a method of forming a semiconductor module includes providing a semiconductor device having a leadframe. A semiconductor chip is disposed over a first side of the leadframe. A switching element is attached at an opposite second side of the leadframe.

Abstract: The reliability of a semiconductor device is improved. A semiconductor device has a first metal plate and a second metal plate electrically isolated from the first metal plate. Over the first metal plate, a first semiconductor chip including a transistor element formed thereover is mounted. Whereas, over the second metal plate, a second semiconductor chip including a diode element formed thereover is mounted. Further, the semiconductor device has a lead group including a plurality of leads electrically coupled with the first semiconductor chip or the second semiconductor chip. The first and second metal plates are arranged along the X direction in which the leads are arrayed. Herein, the area of the peripheral region of the first semiconductor chip in the first metal plate is set larger than the area of the peripheral region of the second semiconductor chip in the second metal plate.

Abstract: Embodiments provide provides a chip package. The chip package may include a leadframe having a die pad and a plurality of lead fingers; a first chip attached to the die pad, the first chip being bonded to one or more of the lead fingers via a first set of wire bonds; a second chip bonded to one or more of the lead fingers via flip chip; and a heat slug attached to the second chip.

Abstract: A semiconductor device module includes a dielectric layer, a semiconductor device having a first surface coupled to the dielectric layer, and a conducting shim having a first surface coupled to the dielectric layer. The semiconductor device also includes an electrically conductive heatspreader having a first surface coupled to a second surface of the semiconductor device and a second surface of the conducting shim. A metallization layer is coupled to the first surface of the semiconductor device and the first surface of the conducting shim. The metallization layer extends through the dielectric layer and is electrically connected to the second surface of the semiconductor device by way of the conducting shim and the heatspreader.

Abstract: A semiconductor package includes a lead frame, a semiconductor die, bond wires providing an electrical connection between the die and the lead frame, and a mold compound that encapsulates the lead frame, the die and the bond wires. The lead frame includes spaced apart first and second frame members each having an inner peripheral edge and an opposing outer peripheral edge, spaced apart lead pads disposed between the inner peripheral edges of the first and second frame members, and conductive leads disposed proximate to the outer peripheral edge of each of the first and second frame members. The die is mounted on the lead pads.

Abstract: Packaged chips comprising non-integer lead pitches, systems and methods for manufacturing packaged chips are disclosed. In one embodiment a packaged device includes a first chip, a package encapsulating the first chip and a plurality of leads protruding from the package, wherein the plurality of leads comprises differing non-integer multiple lead pitches.

Abstract: A semiconductor device of the present invention comprises: an outer package; a first lead frame including a first relay lead, a first die pad with a power element mounted thereon, and a first external connection lead which has an end protruding from the outer package; and a second lead frame including a second relay lead, a second die pad with a control element mounted thereon, and a second external connection lead which has an end protruding from the outer package, wherein the first die pad and the second die pad or the first external connection lead and the second relay lead are joined to each other at a joint portion, and an end of the second relay lead extending from a joint portion with the first relay lead is located inside the outer package.

Abstract: A power overlay (POL) structure includes a POL sub-module. The POL sub-module includes a dielectric layer and a semiconductor device having a top surface attached to the dielectric layer. The top surface of the semiconductor device has at least one contact pad formed thereon. The POL sub-module also includes a metal interconnect structure that extends through the dielectric layer and is electrically coupled to the at least one contact pad of the semiconductor device. A conducting shim is coupled to a bottom surface of the semiconductor device and a first side of a thermal interface is coupled to the conducting shim. A heat sink is coupled to a second side of the electrically insulating thermal interface.

Abstract: A plastic SON/QFN package (300) for high power has a pair of oblong metal pins (320, 321) exposed from a surface of the plastic (301), the pins straddling a corner (302) of the package; each pin has a long axis (320a, 321a), the long axes of the pair forming a non-orthogonal angle. Package (300) further includes a chip assembly pad (310), acting as a thermal spreader.

Abstract: A lead frame for assembling a semiconductor device has a die pad surrounded by lead fingers. Each of the lead fingers has a proximal end close to but spaced from an edge of the die pad and a distal end farther from the die pad. A semiconductor die is attached to a surface of the die pad. The die has die bonding pads on its upper surface that are electrically connected to the proximal ends of the lead fingers with bond wires. An encapsulation material covers the bond wires, semiconductor die and the proximal ends of the lead fingers. Prior to assembly, hot spots of the die are determined and the lead fingers closest to the hot spots are selected to project closer to the die than the other lead fingers. These longer lead fingers assist in dissipating the heat at the die hot spot.

Abstract: Various stress relief structures are provided for effectively reducing thermal stress on a semiconductor chip in a chip package. Trenches on a metal substrate are created in groups in two-dimension, where each trench is opened from top or bottom surface of the metal substrate and in various shapes. The metal substrate is partitioned into many smaller substrates depending on the number of trench groups and partitions, and is attached to a semiconductor chip for stress relief. In an alternative embodiment, a plurality of cylindrical metal structures are used together with a metal substrate in a chip package for the purpose of heat removal and thermal stress relief on a semiconductor chip. In another alternative embodiment, a metal foam is used together with a semiconductor chip to create a chip package. In another alternative embodiment, a semiconductor chip is sandwiched between a heat sink and a circuit board by solder bumps directly with underfill on the circuit board.

Abstract: An electric device and a method of making an electric device are disclosed. In one embodiment the electric device comprises a component comprising a component contact area and a carrier comprising a carrier contact area. The electric device further comprises a first conductive connection layer connecting the component contact area with the carrier contact area, wherein the first conductive connection layer overlies a first region of the component contact area and a second connection layer connecting the component contact area with the carrier contact area, wherein the second connection layer overlies a second region of the component contact area, and wherein the second connection layer comprises a polymer layer.

Abstract: Provided is a power semiconductor device including: a power semiconductor element; a metal block as a first metal block that is connected to the power semiconductor element through an upper surface electrode pattern as a first upper surface electrode pattern selectively formed on an upper surface of the power semiconductor element; and a mold resin filled so as to cover the power semiconductor element and the metal block, wherein an upper surface of the metal block is exposed from a surface of the mold resin.

Abstract: Disclosed herein is a semiconductor light emitting device module comprising: a heat transfer member having a cavity; first conductive layer and second conductive layer contacting the heat transfer member via an insulating layer, the first conductive layer and the second conductive layer being electrically separated from each other in accordance with exposure of the insulating layer or exposure of the heat transfer member; and at least one semiconductor light emitting device electrically connected to the first conductive layer and the second conductive layer, the at least one semiconductor light emitting device is thermally contacted an exposed portion of the heat transfer member, wherein the insulating layer has an exposed portion disposed outside the cavity.

Abstract: Disclosed herein is a semiconductor package. The semiconductor package includes: semiconductor elements, a first heat dissipation substrate formed under the semiconductor elements, a first lead frame electrically connecting the lower portions of the semiconductor elements to an upper portion of the first heat dissipation substrate, a second heat dissipation substrate formed over the semiconductor elements, and a second lead frame having a protrusion formed to be protruded from a lower surface thereof and electrically connecting the upper portions of the semiconductor elements to a lower portion of the second heat dissipation substrate.

Abstract: Provided are a multilayer board and a light-emitting module having the same. The light-emitting module comprises a light-emitting diode chip and a multilayer board. The multilayer board is electrically connected to the light-emitting diode chip and comprises a nonconductive heat sink via and a thin copper layer.

Abstract: A resin package includes: a die pad having a main surface on which a semiconductor substrate and a matching circuit substrate is mounted; at least one lead terminal electrically connected to the semiconductor substrate and the matching circuit substrate; a thin plate fixed to at least one of the main surface of the die pad and a main surface of the at least one lead terminal; and molding resin which covers the semiconductor substrate, the matching circuit substrate, and the thin plate.

Abstract: The invention relates to a method for producing a solder joint between at least one base part (2) and at least one first component (3), comprising the following steps: providing the base part (2); partially blasting a surface of the base part (2) using a SACO blasting agent, the blasting material (50) of which has a silicate coating (52), in such a way that a SACO-blasted region (20) and a non-blasted positioning region (40) are present; and soldering the at least first component (3) onto the non-blasted positioning region (40), wherein the SACO-blasted region (20) acts as a solder resist.

Abstract: There is provided a semiconductor package including: a lead frame having an electronic component mounted on one surface thereof; a heat dissipation substrate disposed downwardly of the lead frame; an insulating member disposed upwardly of the electronic component such that the electronic components are electrically connected to one another; a conductive member disposed between the insulating member and the lead frame and electrically connecting the electronic component to the lead frame; and a molded portion hermetically sealing the insulating member and the heat dissipation substrate.

Abstract: According to an exemplary embodiment, a power semiconductor package includes a power module having a plurality of power devices. Each of the plurality of power devices can be a power switch. The power semiconductor package also includes a double-sided heat sink with a top side in contact with a plurality of power device top surfaces and a bottom side in contact with a bottom surface of the power module. The power semiconductor package can include at least one fastening clamp pressing the top side and the bottom side of the double-sided heat sink into the power module. The double-sided heat sink can also include a water-cooling element.

Abstract: A method for producing a semiconductor device includes laser welding to bond an upper terminal and a lower terminal as internal wiring members of the semiconductor device. When the upper terminal is fixed to the lower terminal by the laser welding, a gap between an upper surface of the lower terminal and a lower surface of the upper terminal is equal to or more than 20 ?m and equal to or less than 400 ?m.

Abstract: In one aspect of the invention, an integrated circuit package is described. The integrated circuit package includes a substrate formed from a dielectric material that includes multiple electrical contacts and conductive paths. An upper lead frame is attached with and underlies the substrate. The upper lead frame is electrically connected with at least one of the contacts on the substrate. The active surface of an integrated circuit die is electrically and physically coupled to the upper lead frame through multiple electrical connectors. A lower lead frame may be attached with the back surface of the integrated circuit die. A passive device is positioned on and electrically connected with one of the contacts on the substrate and/or the upper lead frame.

Abstract: A three dimensional (3D) stacked chip structure with chips having on-chip heat spreader and method of forming are described. A 3D stacked chip structure comprises a first die having a first substrate with a dielectric layer formed on a front surface. One or more bonding pads and a heat spreader may be simultaneously formed in the dielectric layer. The first die is bonded with corresponding bond pads on a surface of a second die to form a stacked chip structure. Heat generated in the stacked chip structure may be diffused to the edges of the stacked chip structure through the heat spreader.

Abstract: Provided is a stacked semiconductor device (50) in which a semiconductor package (5) is stacked via connection terminals (8) on a semiconductor package (1), including a heat dissipating member (10) which is disposed between the semiconductor packages (1, 5), is brought into thermal contact with both of the packages (1, 5), and hangs over whole outer peripheral portions of the package (5). Such a structure causes heat generated from the package (5) to be released by heat dissipation into air above the package (5), heat dissipation into the air below the semiconductor package (5), heat transfer via the heat dissipating member (10) and a semiconductor element (3) to a first wiring substrate (2), heat transfer via the connection terminals (8) to the first wiring substrate (2), and heat dissipation via the heat dissipating member (10) into the air, thereby enhancing a temperature reduction effect of the semiconductor element.

Abstract: An electronic device includes a heat sink, a substrate mounted on the heat sink, a coating layer formed on the substrate, a lead frame fixed to the heat sink, and a mold resin sealing the substrate and the lead frame. The coating layer is made of one of a polyimide-based resin and a polyamideimide-based resin. The lead frame has a fixing terminal fixed to the heat sink through an adhesive layer. The adhesive layer is made of the same material as the coating layer.