Smart (e.g., Credit) Card Package Patents (Class 257/679)
  • Patent number: 10388329
    Abstract: A SSD storage module comprising a printed circuit board (1), an encapsulating colloid (2), and an electronic circuit (3) welded on an inner surface of the printed circuit board (1) and having a data storage function; the encapsulating colloid (2) is formed on the inner surface of the printed circuit board (1) and is configured for seamlessly encapsulating the electronic circuit (3), an outer surface of the printed circuit board (1) is provided with a plurality of metal contact pieces (11), the plurality of metal contact pieces (11) are electrically connected with the electronic circuit (3), and the plurality of metal contact pieces (11) comprise a plurality of SATA interface contact pieces (110).
    Type: Grant
    Filed: July 18, 2016
    Date of Patent: August 20, 2019
    Assignee: SHENZHEN LONGSYS ELECTRONICS CO., LTD.
    Inventors: Zhixiong Li, Weiwen Pang, Xiaoqiang Li, Honghui Hu, Jinmou Qin
  • Patent number: 10381067
    Abstract: Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: August 13, 2019
    Assignee: Rambus Inc.
    Inventors: Ian Shaeffer, Ely Tsern, Craig Hampel
  • Patent number: 10366321
    Abstract: An RFIC device including a resin block having a first surface, a second surface that faces the first surface, and a through-hole that extends through the first surface and the second surface. Moreover, the RFIC device includes an RFIC element that is embedded in the resin block and a coil antenna disposed in the resin block that is connected with the RFIC element and that has a central axis that extends from the first surface to the second surface. In addition, the through-hole extends inside the coil antenna.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: July 30, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Kunihiro Komaki, Shunji Mandai, Kengo Matsumoto
  • Patent number: 10362699
    Abstract: An electronic device includes a display screen, one or more internal components, and a foam outer housing coupled to the display screen and enclosing the one or more internal components. The electronic device may also include a foam midframe enclosed by the foam outer housing. The foam outer housing may be resilient so as to provide impact absorption and water resistance, while the foam midframe may be rigid to provide stiffness to the electronic device. The electronic device may have a density less than 1 gram/centimeter3 such that the electronic device is buoyant in liquid water.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: July 23, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: ChengChien Lu, David Eric Peters
  • Patent number: 10347576
    Abstract: A semiconductor package includes a package substrate, the package substrate including a conductive plate, an insulating plate on the conductive plate, the insulating plate including a mounting region and a peripheral region surrounding the mounting region, and at least one capillary channel in the peripheral region, a semiconductor chip on the mounting region of the insulating plate, and a molding member on the insulating plate to cover the semiconductor chip, a portion of the molding member being in the at least one capillary channel.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: July 9, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kwang-Won Choi, Sang-Woo Pae, Seong-Won Jeong, Min-Jae Kwon, Da-Hye Min, Jin-Chul Park, Jae-Won Chang
  • Patent number: 10314216
    Abstract: The invention relates to a method for fabricating electronic cards by A) forming a plurality of card bodies in the form of a thick sheet with a plurality of electronic units or modules embedded in the sheet; B) printing a plurality of first patterns on a first face of the thick sheet in a printing station where ink is applied on the first face; C) applying a first at least partially transparent coating on each printed first pattern, that adheres to the card body. The method can also include printing a plurality of second patterns on the inner surface of a film forming the first coating. Preferably, the printing of the first patterns is carried out in an offset type station for printing high definition patterns, essentially of the security type. The second patterns define personal data. The printed thick sheet defines an intermediate product according to the invention.
    Type: Grant
    Filed: July 6, 2015
    Date of Patent: June 4, 2019
    Assignee: Nagravision S.A.
    Inventor: François Droz
  • Patent number: 10282655
    Abstract: A chip card module is provided. The chip card module may include a carrier having a first side and an opposite second side, a chip arranged over the carrier, the chip having a first chip contact, a first and a second antenna contact formed over the first side, a metal-free area formed over the first side between the first antenna contact and the second antenna contact, wherein the metal-free area extends between a first edge portion and a second edge portion of the carrier, and a first chip connection electrically connecting the first chip contact to the first antenna contact, wherein the first chip connection is at least partially arranged over the second side in a region opposite the metal-free area.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: May 7, 2019
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Frank Pueschner, Siegfried Hoffner, Jens Pohl
  • Patent number: 10236187
    Abstract: The invention provides a semiconductor package and a method for fabricating a base for a semiconductor package. The semiconductor package includes a base. The base has a device-attach surface. A radio-frequency (RF) device is embedded in the base. The RF device is close to the device-attach surface.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: March 19, 2019
    Assignee: MediaTek Inc.
    Inventors: Wen-Sung Hsu, Ta-Jen Yu
  • Patent number: 10204733
    Abstract: Provided is a module substrate including an inductor that can be made thinner and smaller. A module substrate according to an aspect of the present invention includes a substrate member having a mounting surface on which electronic components are mounted, a magnetic core disposed within the substrate member, and a conductor coil provided in the substrate member and wound around the magnetic core. The module substrate has a configuration in which an inductor is built into the substrate member, which makes it possible to make the overall module substrate smaller and thinner.
    Type: Grant
    Filed: July 6, 2016
    Date of Patent: February 12, 2019
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Yuichi Sugiyama, Masashi Miyazaki, Yutaka Hata
  • Patent number: 10199312
    Abstract: A packaged electronic device includes a substrate having a lead. The lead includes an outward facing side surface having a first height, and an inward facing side surface having a second height that is less than the first height. An electronic device is electrically connected to the lead. A package body encapsulates the electronic device and portions of the lead. The outward facing side surface is exposed through a side surface of the package body, and the inward facing side surface is encapsulated by the package body. A conductive layer is disposed on the outward facing side surface to provide the packaged electronic device with an enhanced wettable flank. In one embodiment, the electronic device is electrically connected to a thick terminal portion having the outward facing side surface. In another embodiment, the electronic device is electrically connected to a thin terminal portion having the inward facing side surface.
    Type: Grant
    Filed: September 9, 2017
    Date of Patent: February 5, 2019
    Assignee: AMKOR TECHNOLOGY, INC.
    Inventor: Pedro Joel Rivera-Marty
  • Patent number: 10187993
    Abstract: A device includes a circuit board, a plastic case accommodating the circuit board therein, the plastic case protecting the circuit board, and a plurality of conductive support members supporting the circuit board such that the circuit board is fixed to the plastic case. In the device, the conductive support members are fixed to the circuit board inside the plastic case, and extend to the outside of the plastic case to be fixed to the plastic case.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: January 22, 2019
    Assignee: SAMSUNG SDI CO., LTD.
    Inventor: Jun Young Lee
  • Patent number: 10163780
    Abstract: A package includes a device die, and an encapsulating material encapsulating the device die therein. The encapsulating material has a top surface coplanar with a top surface of the device die. A coil extends from the top surface to a bottom surface of the encapsulating material, and the device die is in the region encircled by the coil. At least one dielectric layer is formed over the encapsulating material and the coil. A plurality of redistribution lines is in the at least one dielectric layer. The coil is electrically coupled to the device die through the plurality of redistribution lines.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chiang-Jui Chu, Chung-Shi Liu, Hao-Yi Tsai, Ming Hung Tseng, Hung-Yi Kuo
  • Patent number: 10157848
    Abstract: A chip card module arrangement may include a first surface and a second surface, which are opposite from one another, and a chip receptacle for one or more semiconductor chips on the surfaces. The chip card module arrangement may further include a connecting material receiving area on one of the two surfaces, the connecting material receiving area only taking up a portion of the surface.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: December 18, 2018
    Assignee: Infineon Technologies AG
    Inventors: Frank Pueschner, Jens Pohl, Thomas Spoettl, Peter Stampka
  • Patent number: 10153424
    Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor element, a plurality of terminals, and a sealing resin. The semiconductor element has a front surface and a back surface. The front surface and the back surface face in opposite directions to each other in a thickness direction of the semiconductor element. The plurality of terminals are disposed at a distance from the semiconductor element and are electrically connected to the front surface. The sealing resin has a first surface facing in a same direction as the direction in which the front surface faces. Each of the plurality of terminals has a main surface exposed from the first surface.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: December 11, 2018
    Assignee: ROHM CO., LTD.
    Inventors: Shinsei Mizuta, Satohiro Kigoshi, Takaaki Masaki
  • Patent number: 10108898
    Abstract: A method of tracking a package. The method includes applying a package label to a package in which the package label comprises an antenna circuit, an activation tab configured to activate the antenna circuit, and a deactivation tab configured to deactivate the antenna circuit. The method also includes activating the antenna circuit by removing the activation tab and periodically transmitting a signal by the antenna circuit upon activation. The signal comprises information that identifies the package. The method also includes receiving the signal and using the information in the signal to track a location of the package.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: October 23, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Robert Scott Ballam, Robert Ganton
  • Patent number: 10102466
    Abstract: Magnetic keys having a plurality of magnetic layers having holes are disclosed. The location and orientation of the holes are controlled to generate magnetic fields that are of sufficient strength to be reliably read and sufficient complexity to be difficult to counterfeit. The magnetic keys are located on imaging-device supply items along with non-volatile memory devices containing measurements of the magnetic fields that are digitally signed. These supply items are difficult to counterfeit. Other devices are disclosed.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: October 16, 2018
    Assignee: Lexmark International, Inc.
    Inventors: Roger Steven Cannon, Gary Allen Denton, Graydon Randall Dodson, Keith Bryan Hardin
  • Patent number: 10083911
    Abstract: A semiconductor device package includes a flexible substrate, an electronic component, at least one flexible member, and a package body. The electronic component is disposed on the flexible substrate. The at least one flexible member is disposed on the flexible substrate. The package body encapsulates the electronic component and has a first part and a second part separated from the first part by the at least one flexible member.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: September 25, 2018
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hao-Chih Hsieh, Tun-Ching Pi
  • Patent number: 10068513
    Abstract: An electronic paper apparatus including a communication module and a control module is provided. The communication module receives an electrical signal and generates a power voltage according to the electric signal. The communication module wakes up a controller during a first period of a work period by using the power voltage. The control module is electrically connected to the communication module, and includes the controller and an electronic paper display. The control module establishes a communication connection with the communication module during a second period of the work period. The power circuit module generates a driving voltage according to the power voltage to drive the electronic paper display to display image information according to the driving voltage during a display period. The first period and the second period are two continuous time intervals forming the work period. Furthermore, a driving method of the electronic paper apparatus is also provided.
    Type: Grant
    Filed: July 26, 2015
    Date of Patent: September 4, 2018
    Assignee: E Ink Holdings Inc.
    Inventors: Chuen-Jen Liu, Li-Wei Chou, Jia-Hong Xu, Yu-Ming Lee, Chi-Mao Hung
  • Patent number: 10043766
    Abstract: The integrated circuit includes a functional block performing a logic and/or analog function. A control circuit is configured to transmit at least a first signal to the receiver and receive a second signal from receiver. The electrically conducting lines' first and second series connect the control circuit and receiver to perform the first and second signals' transit. A plurality of monitoring stations is simultaneously connected to first and second series of electrically conducting lines to define a first elementary electric pattern in the electrically conducting lines' first series and a distinct second elementary electric pattern equivalent to first elementary electric pattern in the electrically conducting lines' second series. A shield at least partially covers the functional block. The control circuit is configured to detect modification of first elementary electric pattern with respect to the second elementary electric pattern by absence of receipt of the second signal after a predefined time-out.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: August 7, 2018
    Assignee: TIEMPO
    Inventors: Marc Renaudin, Bertrand Folco, Boubkar Boulahia
  • Patent number: 10021791
    Abstract: In one embodiment of the present invention, a multilayer wiring substrate includes: a first wiring substrate having a first core member made of metal with cavities therein; a second wiring substrate having a second core member made of metal; and a bonding layer between the first wiring substrate and the second wiring substrate to bond a top surface of the first wiring substrate to a bottom surface of the second wiring substrate, the bonding layer having a patterned conductive layer.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: July 10, 2018
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Yuichi Sugiyama, Masashi Miyazaki
  • Patent number: 9984984
    Abstract: A semiconductor element mounting board includes: a circuit conductor disposed on the insulating board, a plurality of semiconductor element connection pads connected to the circuit conductor, a semiconductor element mounted on a surface of the insulating board, a first capacitor and a second capacitor disposed on a surface or an inside of the insulating board, and a first conductor path configured to connect the first capacitor between the semiconductor element connection pads, and a second conductor path configured to connect the second capacitor between the semiconductor element connection pads; and an inductance of the first conductor path is smaller than an inductance of the second conductor path, and capacitance of the first capacitor is smaller than capacitance of the second capacitor, and an internal inductance of the first capacitor is smaller than an internal inductance of the second capacitor.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: May 29, 2018
    Assignee: KYOCERA CORPORATION
    Inventors: Makoto Shiroshita, Hisayoshi Wada
  • Patent number: 9922844
    Abstract: The invention provides a semiconductor package and a method for fabricating a base for a semiconductor package. The semiconductor package includes a base. The base has a device-attach surface. A radio-frequency (RF) device is embedded in the base. The RF device is close to the device-attach surface.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: March 20, 2018
    Assignee: MediaTek Inc.
    Inventors: Wen-Sung Hsu, Ta-Jen Yu
  • Patent number: 9898694
    Abstract: A transaction card having three layers, wherein the first layer is metal, the second layer is a polymer, and the third layer is a carbon-containing layer.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: February 20, 2018
    Assignee: Black Card LLC
    Inventor: Scott Alan Blum
  • Patent number: 9848493
    Abstract: A printed circuit board assembly comprises a printed circuit board (PCB) defining a mounting end and an opposite contacting end, a row of first pads on the mounting end, a row of second pads on the contacting end, and an edge connector on the contacting end electrically contacted with the second pads, and a high speed line module mounted on a top side of the PCB and including a group of conductive lines, the conductive lines extending parallel to each other over the plane of the PCB, each conductive line having two ends electrically connected to corresponding first and second pads, respectively.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: December 19, 2017
    Assignee: FOXCONN INTERCONNECT TECHNOLOGY LIMITED
    Inventors: Andrew Engel, Paul Yu, Klaus Giessler, Omid Momtahan, Michael John Brosnan, David Meadowcroft
  • Patent number: 9806060
    Abstract: A flexible package may be provided. The flexible package may include a flexible molding member including a top surface. The flexible package may include a first chip within the flexible molding member, and including a first top surface. The flexible package may include a second chip within the flexible molding member, and including a second top surface. The first top surface may face away from the top surface of the flexible molding member and the second top surface may face towards the top surface of the flexible molding member.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: October 31, 2017
    Assignee: Sk hynix Inc.
    Inventor: Chan Woo Jeong
  • Patent number: 9795036
    Abstract: A mounting structure includes a bonding material (106) that bonds second electrodes (104) of a circuit board (105) and bumps (103) of a semiconductor package (101), the bonding material (106) being surrounded by a first reinforcing resin (107). Moreover, a portion between the outer periphery of the semiconductor package (101) and the circuit board (105) is covered with a second reinforcing resin (108). Even if the bonding material (106) is a solder material having a lower melting point than a conventional bonding material, high drop resistance is obtained.
    Type: Grant
    Filed: April 5, 2013
    Date of Patent: October 17, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Arata Kishi, Hironori Munakata, Koji Motomura, Hiroki Maruo
  • Patent number: 9768037
    Abstract: A method of manufacturing an electronic device package includes structuring a metal layer to generate a structured metal layer having a plurality of openings. Semiconductor chips are placed into at least some of the openings. An encapsulating material is applied over the structured metal layer and the semiconductor chips to form an encapsulation body. The encapsulation body is separated into a plurality of electronic device packages.
    Type: Grant
    Filed: May 16, 2014
    Date of Patent: September 19, 2017
    Assignee: Infineon Technologies AG
    Inventors: Petteri Palm, Edward Fuergut, Irmgard Escher-Poeppel
  • Patent number: 9760754
    Abstract: A Printed Circuit Board Assembly (PCBA) forming an enhanced fingerprint module is disclosed. The PCBA includes a Printed Circuit Board (PCB), an image sensing chip, at least one electrode and a protection layer. An opening in a first insulation layer and a second insulation layer of the PCB together form a sensor portion so that the image sensing chip can be packaged in the opening. Thus, the thickness of the enhanced fingerprint module can be thinner than other fingerprint modules provided by the conventional package methods.
    Type: Grant
    Filed: July 6, 2015
    Date of Patent: September 12, 2017
    Assignee: SunASIC Technologies Inc.
    Inventors: Chi-Chou Lin, Zheng-Ping He
  • Patent number: 9733428
    Abstract: Three-dimensional flexible photonic integrated circuits on silicon are fabricated in semiconductor wafer form and then transferred to Silicon-on-Polymer (SOP) substrates. SOP provides flexibility for conformal mounting with devices capable of maintaining performance when dynamically deformed to allow routing of light in x, y and z directions. Bonding a wafer or individual die of III-V semiconductor, such as Gallium Arsenide or similar photonic material, to the flexible silicon creates an active region for lasers, amplifiers, modulators, and other photonic devices using standard processing. Mounting additional photonic devices to the opposite side of a flexible photonic waveguide produces a stack for three-dimensional devices. Multiple flexible photonic waveguides may be stacked to increase functionality by transferring light between stacked waveguides.
    Type: Grant
    Filed: February 4, 2014
    Date of Patent: August 15, 2017
    Assignee: American Semiconductor, Inc.
    Inventors: Douglas R. Hackler, Sr., Dale G. Wilson
  • Patent number: 9721200
    Abstract: In a smart card having an antenna structure and a metal layer, an insulator layer is formed between the antenna structure and the metal layer to compensate for the attenuation due to the metal layer. The thickness of the insulator layer affects the capacitive coupling between the antenna structure and the metal layer and is selected to have a value which optimizes the transmission/reception of signals between the card and a card reader.
    Type: Grant
    Filed: November 17, 2014
    Date of Patent: August 1, 2017
    Assignee: COMPOSECURE, L.L.C.
    Inventors: John Herslow, Michele Logan, David Finn
  • Patent number: 9667410
    Abstract: In data processing including high-speed cipher calculation for which it is not appropriate to employ a leveling technique, tamper resistance is improved against an attack to a specific position performed by knowing a layout of functional blocks in a semiconductor chip. Examples of the attack include micro-probing, fault injection, and electromagnetic wave analysis. A semiconductor device, in which a plurality of IC chips that perform the same cipher calculation in parallel are laminated or stacked, performs data processing including the cipher calculation. A chip that compares and verifies results of the cipher calculations performed by the plurality of chips is laminated in an intermediate layer whose element surface is covered by another chip. For example, when three chips are laminated, a chip in the intermediate layer sandwiched by the upper layer and the lower layer has a comparative verification function.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: May 30, 2017
    Assignee: Renesas Electronics Corporation
    Inventor: Daisuke Oshida
  • Patent number: 9666833
    Abstract: An array substrate and a manufacturing method thereof, a flexible display panel and a display device are provided. The array substrate includes a flexible substrate divided into a display region and a periphery region, the periphery region surrounding the display region. The array substrate further includes: an array layer and a first film layer sequentially formed in the display region on the flexible substrate; a plurality of integrate circuits and a flexible printed circuit board interface formed in the periphery region on the flexible substrate; a flexible protective film layer formed on a junction of the periphery region and the first film layer and in a region of the periphery region other than the integrate circuits and the flexible printed circuit board interface on the flexible substrate.
    Type: Grant
    Filed: February 9, 2015
    Date of Patent: May 30, 2017
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Tao Gao, Weifeng Zhou
  • Patent number: 9627338
    Abstract: A semiconductor device has a plurality of semiconductor die. A first prefabricated insulating film is disposed over the semiconductor die. A conductive layer is formed over the first prefabricated insulating film. An interconnect structure is formed over the semiconductor die and first prefabricated insulating film. The first prefabricated insulating film is laminated over the semiconductor die. The first prefabricated insulating film includes glass cloth, glass fiber, or glass fillers. The semiconductor die is embedded within the first prefabricated insulating film with the first prefabricated insulating film covering first and side surfaces of the semiconductor die. The interconnect structure is formed over a second surface of the semiconductor die opposite the first surface. A portion of the first prefabricated insulating film is removed after disposing the first prefabricated insulating film over the semiconductor die.
    Type: Grant
    Filed: February 21, 2014
    Date of Patent: April 18, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: See Chian Lim, Teck Tiong Tan, Yung Kuan Hsiao, Ching Meng Fang, Yoke Hor Phua, Bartholomew Liao
  • Patent number: 9627916
    Abstract: An electronic card including an antenna, a chip, a charging circuit and a battery is provided. The antenna receives an external electric signal, and the chip is coupled to the antenna, so as to receive the external electric signal and provide a demodulated electric signal. The charging circuit is coupled to the chip, receives the demodulated electric signal and converts the demodulated electric signal to generate a charging power. The battery is coupled to the charging circuit, wherein, the charging circuit provides the charging power to the battery according to a residual electricity of the battery, so as to charge the battery.
    Type: Grant
    Filed: June 13, 2013
    Date of Patent: April 18, 2017
    Assignee: E Ink Holdings Inc.
    Inventors: Yao-Jen Hsieh, Ming-Jong Jou, Chi-Mao Hung, Wei-Min Sun
  • Patent number: 9603295
    Abstract: In a case where a first mounted substrate to which a semiconductor element is bounded by solder is mounted on a second substrate, connection strength becomes low, when the first mounted substrate is bonded to the second substrate by using a solder having a low melting point. A mounted structure, in which a first mounted substrate on which a semiconductor element is bonded by using a first solder having a melting point of 217° C. or more, is mounted on a second substrate, includes plural bonding parts bonding the first mounted substrate to the second substrate; and a reinforcing member formed around the bonding part. Each of the bonding parts contains a second solder having a melting point, that is lower than the melting point of the first solder, and a space exists, in which the reinforcing members do not exist, between the bonding parts neighboring each other.
    Type: Grant
    Filed: April 2, 2012
    Date of Patent: March 21, 2017
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Atsushi Yamaguchi, Hisahiko Yoshida, Arata Kishi, Naomichi Ohashi
  • Patent number: 9601442
    Abstract: A mold package being a half-mold type includes: a substrate includes a first face and a second face; an electronic component that is mounted on the first face; and a mold resin that is provided on the first face and seals the first face with the electronic component. The second face is exposed from the mold resin. The mold resin is disposed on the first face so as to seal a sealed portion and to expose a remaining part of the first face as an exposure portion. One side face is provided by an end side face. One side face is provided by a boundary side face. At least a site on a lower end of the boundary side face is provided by an inclined face. In the boundary side face, a site on an upper end side is provided by an other inclined face having a second inclination angle.
    Type: Grant
    Filed: January 9, 2015
    Date of Patent: March 21, 2017
    Assignee: DENSO CORPORATION
    Inventors: Kengo Oka, Tetsuto Yamagishi
  • Patent number: 9578763
    Abstract: Disclosed is a technique for tamper detection in an electronic device by use of an internal power supply signal. The technique includes electrically coupling a conductive trace, in series via a resistor, to an internal power supply that supplies power to a security module within a processor of the device. The technique further includes electrically coupling the power supply to a detector for use in tamper detection on the trace. Upon occurrence of a short-circuit condition on the conductive trace, substantially all voltage of the local power supply is dropped across the resistor. As a result, the detector detects a drop in voltage below a predetermined threshold, and perceives such drop as a “collapse” of the internal power supply. The collapse of the power supply is indicative of a tampering event to the detector, which in response, outputs a signal to disable an operation of the security module.
    Type: Grant
    Filed: May 22, 2014
    Date of Patent: February 21, 2017
    Assignee: Square, Inc.
    Inventor: Jeremy Wade
  • Patent number: 9570380
    Abstract: An electronic device comprising: a semiconductor die integrating an electronic component; a leadframe housing the semiconductor die; a protection body, which surrounds laterally and at the top the semiconductor die and, at least in part, the leadframe structure, defining a top surface, a bottom surface, and a thickness of the electronic device; and a conductive lead electrically coupled to the semiconductor die. The conductive lead is modelled in such a way as to extend throughout the thickness of the protection body for forming a front electrical contact accessible from the top surface of the electronic device, and a rear electrical contact accessible from the bottom surface of the electronic device.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: February 14, 2017
    Assignee: STMicroelectronics S.r.l.
    Inventors: Fabio Vito Coppone, Agatino Minotti, Francesco Salamone
  • Patent number: 9564686
    Abstract: A near field communication antenna device of a mobile terminal is provided. The near field communication antenna device includes a window including a display region for transmitting an image displayed by a display and a black mark region formed around the display region, a multi-layer Flexible Printed Circuit Board (FPCB) on which a plurality of layers are laminated on the lower side of the black mark region of the window, and a spiral loop-shaped antenna pattern in which conductive lines are formed on respective layers of the multi-layer FPCB and are connected to each other. Accordingly, a near field communication antenna is not disposed in a separated installation space, an antenna pattern width can be reduced, and performance of the near field communication antenna may be prevented from being degraded when a battery cover is made of metal or has a curved shape.
    Type: Grant
    Filed: February 9, 2015
    Date of Patent: February 7, 2017
    Assignees: Samsung Electronics Co., Ltd., EXAX Inc.
    Inventors: Kyu Sik Cho, In Sook Kim
  • Patent number: 9548263
    Abstract: Electronic device packages and related fabrication methods are provided. An exemplary electronic device includes a semiconductor die having debug circuitry fabricated thereon, a framing structure including an interior portion having the semiconductor die mounted thereto, and a conductive element providing an electrical connection between the interior portion and a contact pad on the semiconductor die that corresponds or is otherwise coupled to an interface of the debug circuitry.
    Type: Grant
    Filed: June 16, 2015
    Date of Patent: January 17, 2017
    Assignee: NXP USA, Inc.
    Inventors: Damon Peter Broderick, Dirk Heisswolf, Andreas R. Pachl
  • Patent number: 9530715
    Abstract: A multi-chip semiconductor device comprises a thermally enhanced structure, a first semiconductor chip, a second semiconductor chip, an encapsulation layer formed on top of the first semiconductor chip and the second semiconductor chip. The multi-chip semiconductor device further comprises a plurality of thermal vias formed in the encapsulation layer. The thermally enhanced structure comprises a heat sink block attached to a first semiconductor die. The heat sink block may further comprise a variety of thermal vias and thermal openings. By employing the thermal enhanced structure, the thermal performance of the multi-chip semiconductor device can be improved.
    Type: Grant
    Filed: September 11, 2015
    Date of Patent: December 27, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chih-Hang Tung, Tung-Liang Shao
  • Patent number: 9509306
    Abstract: According to an aspect of the invention an integrated circuit is conceived which comprises a physical unclonable function which is at least partially implemented in a passivation layer of said integrated circuit. According to a further aspect of the invention, a corresponding method for manufacturing an integrated circuit is conceived. According to a further aspect of the invention, an electronic device is conceived which comprises an integrated circuit of the kind set forth.
    Type: Grant
    Filed: April 19, 2013
    Date of Patent: November 29, 2016
    Assignee: NXP B.V.
    Inventors: Soenke Ostertun, Michael Ziesmann
  • Patent number: 9454724
    Abstract: A membrane is formed from a release liner upon which a plurality of labels and a margin sheet are attached. Each label is a flexible planar body, including a display surface on a top side and an electronic circuit on a bottom side. A first adhesive coating is applied to the bottom of the flexible planar body, allowing the label to be temporarily adhered to the release liner. An antenna is joined to the electronic circuit and connected to the flexible planar body. The electronic circuit itself enables item identification, such as through Radio-Frequency Identification or Electronic Article Surveillance. In order to provide visual information, a primary printed graphic can be applied to each of the labels, while a supplementary printed graphic can be applied to the margin sheet. The plurality of labels can be arranged in different arrays, such as a plurality of rows or a tessellated pattern.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: September 27, 2016
    Inventor: Bong J. Im
  • Patent number: 9437777
    Abstract: When a conductive layer occupying a large area is provided in a coiled antenna portion, it has been difficult to supply power stably. A memory circuit portion and a coiled antenna portion are disposed by being stacked together; therefore, it is possible to prevent a current from flowing through a conductive layer occupying a large area included in the memory circuit portion, and thus, power saving can be achieved. In addition, the memory circuit portion and the coiled antenna portion are disposed by being stacked together, and thus, it is possible to use a space efficiently. Therefore, downsizing can be realized.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: September 6, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tamae Takano, Nobuharu Ohsawa, Kiyoshi Kato
  • Patent number: 9361489
    Abstract: An electromagnetic transponder including a resonant circuit; a rectifying bridge having input terminals connected across the resonant circuit and having rectified output terminals providing an electronic circuit power supply voltage; and a device for limiting the voltage across the resonant circuit, connected between the input terminals of the rectifying bridge.
    Type: Grant
    Filed: June 15, 2015
    Date of Patent: June 7, 2016
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Marc Battista, Gilles Bas, Francois Tailliet
  • Patent number: 9355347
    Abstract: A card is provided comprising an information setting unit configured to output a first signal including unique information of the card, and a bending sensor configured to output a second signal corresponding to a curvature of the card. An information processing apparatus is also provided comprising a card reading unit configured to acquire information from a card a processor, and a memory device. The memory device stores instructions which when executed by the processor, causes the processor to acquire unique information from the card, and acquire curvature information from the card corresponding to a curvature of the card.
    Type: Grant
    Filed: October 21, 2013
    Date of Patent: May 31, 2016
    Assignee: Sony Corporation
    Inventors: Takehisa Ishida, Nobuyuki Nagai, Yusaku Kato, Hideo Kawabe, Osamu Ito
  • Patent number: 9323941
    Abstract: The component comprises a first memory (MM) comprising a first portion (P1) having a content modified with a first modification entity (K1) and a second portion (P2) having a content modified with a second entity (K2), a storage means (MS) configured to store the first entity (K1) secretly, a non-volatile memory (NVM) storing an item of entity information representative of the second entity (K2) in a location (END) designated by a first indication (INDK2) contained in the said first portion of the first memory.
    Type: Grant
    Filed: November 9, 2010
    Date of Patent: April 26, 2016
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Fabrice Marinet, Mathieu Lisart
  • Patent number: 9286951
    Abstract: According to one embodiment, there are provided a memory which is provided on a circuit board, a controller which is provided on the circuit board and controls the memory, and a signal line which is formed on the circuit board and configured to perform data transmission between the controller and the memory, in which a width of the signal line in the place where the signal line is led out from the memory is large compared with a place disposed under the memory.
    Type: Grant
    Filed: January 12, 2015
    Date of Patent: March 15, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Okada, Atsuko Seki
  • Patent number: 9275983
    Abstract: A method of making an integrated circuit (IC) package including electrically and physically attaching a die to an interposer, attaching the interposer to a bottom leadframe, attaching a discrete circuit component to the interposer and attaching a top leadframe to the bottom leadframe.
    Type: Grant
    Filed: May 7, 2015
    Date of Patent: March 1, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Lee Han Meng@ Eugene Lee, Anis Fauzi bin Abdul Aziz, Yien Sien Khoo
  • Patent number: 9245828
    Abstract: A package and integrated circuit assembly is configured to perform signal conditioning on a signal. The assembly includes a line card having line card contacts that correspond to conductors in the line card connector. Two or more integrated circuits are configured to perform signal conditioning on the signal and the two or more integrated circuits are configured within a package into at least a first row and a second row on the package. The package includes a grid array of bonding pads to electrically connect to the two or more integrated circuits through bond wires or down bonds such that the structure of the grid array corresponds in physical arrangement or bond pad pitch to the line card contacts. This assembly also includes an electrical connection from the two or more integrated circuits to the line card through the package.
    Type: Grant
    Filed: July 11, 2013
    Date of Patent: January 26, 2016
    Assignee: Mindspeed Technologies, Inc.
    Inventors: Atul K. Gupta, Ryan S. Latchman, Marek S. Tlalka