Smart (e.g., Credit) Card Package Patents (Class 257/679)
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Patent number: 8772917Abstract: When a conductive layer occupying a large area is provided in a coiled antenna portion, it has been difficult to supply power stably. A memory circuit portion and a coiled antenna portion are disposed by being stacked together; therefore, it is possible to prevent a current from flowing through a conductive layer occupying a large area included in the memory circuit portion, and thus, power saving can be achieved. In addition, the memory circuit portion and the coiled antenna portion are disposed by being stacked together, and thus, it is possible to use a space efficiently. Therefore, downsizing can be realized.Type: GrantFiled: February 5, 2007Date of Patent: July 8, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Tamae Takano, Nobuharu Ohsawa, Kiyoshi Kato
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Patent number: 8736048Abstract: A multi-chip module (MCM) structure comprises more than one semiconductor chip lying in a horizontal plane, the MCM having individual chip contact patches on the chips and a flexible heat sink having lateral compliance and extending in a plane in the MCM and secured in a heat exchange relation to the chips through the contact patches. The MCM has a mismatch between the coefficient of thermal expansion of the heat sink and the MCM and also has chip tilt and chip height mismatches. The flexible heat sink with lateral compliance minimizes or eliminates shear stress and shear strain developed in the horizontal direction at the interface between the heat sink and the chip contact patches by allowing for horizontal expansion and contraction of the heat sink relative to the MCM without moving the individual chip contact patches in a horizontal direction.Type: GrantFiled: February 16, 2012Date of Patent: May 27, 2014Assignee: International Business Machines CorporationInventor: Mark D. Schultz
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Patent number: 8723744Abstract: The invention relates to a method for manufacturing contactless portable objects having an integrated circuit, and to contactless portable objects having an integrated circuit. The method of the invention is characterized in that it comprises the following steps: providing a dielectric antenna substrate (6) which carries an antenna circuit (7) having at least one turn (7-1, 7-2, 7-3, 7-4) and two contact terminals (8-1, 8-2); providing a bridge (5) having a dielectric bridge substrate (1) and a chip (3) having an integrated circuit; and placing said bridge (5) with said chip (3) onto said dielectric antenna substrate (6) so that the bridge (5) straddles said at least one turn (7-1, 7-2, 7-3, 7-4) and forms an electric connection between said chip (3) and said antenna circuit (7). The invention is particularly useful for HF RFID objects.Type: GrantFiled: November 24, 2009Date of Patent: May 13, 2014Assignee: RFIDEALInventor: Yannick Grasset
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Patent number: 8710639Abstract: A wiring substrate in which a semiconductor element is built includes a semiconductor element; a peripheral insulating layer covering at least an outer circumferential side surface of this semiconductor element; and an upper surface-side wiring line provided on the upper surface side of the wiring substrate. The semiconductor element includes an internal terminal electrically connected to the upper surface-side wiring line on the upper surface side of the semiconductor element. This internal terminal includes a first conductive part exposed out of an insulating surface layer of the semiconductor element; an adhesion layer on this first conductive part; and a second conductive part on this adhesion layer.Type: GrantFiled: February 22, 2011Date of Patent: April 29, 2014Assignee: NEC CorporationInventors: Katsumi Kikuchi, Shintaro Yamamichi, Hideya Murai, Kentaro Mori, Yoshiki Nakashima
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Patent number: 8708222Abstract: A method for producing a finishing layer containing a window (104) for a portable data storage medium, in particular a chip card, and the use of the method for producing a data storage medium. A transparent plastic-based support layer (28) is used and an opaque color layer (30) is applied on the support layer in a screen printing process, wherein the color layer (30) has a recess (32) having the dimensions of the window (104). A first layer (40) of a transparent primer is then screen printed onto the color layer and a design color layer (50) is then applied in an offset printing process onto the first layer. A second layer (60) of a transparent primer is applied in an offset printing process on top of the design color layer (50) and a transparent finish (70) is finally applied onto the second layer (60).Type: GrantFiled: February 12, 2010Date of Patent: April 29, 2014Assignee: Giesecke & Devirent GmbHInventors: Peter Huber, Klaus Kohl, Fabik Roman, Christina Schellenberger, Manuela Schropf
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Patent number: 8704334Abstract: A semiconductor device includes an internal circuit provided on a substrate, a plurality of external terminals connected to the internal circuit, a plurality of wires connecting the internal circuit and the external terminals, and a plurality of inductors communicating with an external device. Each of the inductors is connected to each of the wires. The external terminals are formed in a region not to interrupt communication between the inductors and the external device.Type: GrantFiled: July 19, 2011Date of Patent: April 22, 2014Assignee: Renesas Electronics CorporationInventor: Yasutaka Nakashiba
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Publication number: 20140091450Abstract: A semiconductor housing includes a front side with a semiconductor chip and a first metallization on a substrate, and a rear side with a second metallization. The rear side is situated opposite the front side of the semiconductor housing. The semiconductor housing further includes a first compensation layer applied on the front side of the semiconductor housing.Type: ApplicationFiled: September 24, 2013Publication date: April 3, 2014Inventors: Frank Pueschner, Juergen Hoegerl, Peter Scherl, Thomas Spoettl
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Patent number: 8680663Abstract: Methods and apparatus for package on package structures. A structure includes a first integrated circuit package including at least one integrated circuit device mounted on a first substrate, a plurality of package on package connectors extending from a bottom surface and arranged in a pattern of one or more rows proximal to an outer periphery of the first substrate; and a second integrated circuit package including at least another integrated circuit device mounted on a second substrate and a plurality of lands on an upper surface coupled to the plurality of package on package connectors, and a plurality of external connectors extending from a bottom surface of the second substrate; wherein the pattern of the external connectors is staggered from the pattern of the package on package connectors so that the package on package connectors are not in vertical alignment with the external connectors. Methods for forming structures are disclosed.Type: GrantFiled: January 3, 2012Date of Patent: March 25, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Feng Chen, Han-Ping Pu
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Patent number: 8674493Abstract: It is an object of the present invention to provide a highly sophisticated functional IC card that can ensure security by preventing forgery such as changing a picture of a face, and display other images as well as the picture of a face. An IC card comprising a display device and a plurality of thin film integrated circuits; wherein driving of the display device is controlled by the plurality of thin film integrated circuits; a semiconductor element used for the plurality of thin film integrated circuits and the display device is formed by using a polycrystalline semiconductor film; the plurality of thin film integrated circuits are laminated; the display device and the plurality of thin film integrated circuits are equipped for the same printed wiring board; and the IC card has a thickness of from 0.05 mm to 1 mm.Type: GrantFiled: September 14, 2012Date of Patent: March 18, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Toru Takayama, Junya Maruyama, Yuugo Goto, Yumiko Ohno, Mai Akiba
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Patent number: 8648439Abstract: The present invention provides a thin and bendable semiconductor device utilizing an advantage of a flexible substrate used in the semiconductor device, and a method of manufacturing the semiconductor device. The semiconductor device has at least one surface covered by an insulating layer which serves as a substrate for protection. In the semiconductor device, the insulating layer is formed over a conductive layer serving as an antenna such that the value in the thickness ratio of the insulating layer in a portion not covering the conductive layer to the conductive layer is at least 1.2, and the value in the thickness ratio of the insulating layer formed over the conductive layer to the conductive layer is at least 0.2. Further, not the conductive layer but the insulating layer is exposed in the side face of the semiconductor device, and the insulating layer covers a TFT and the conductive layer.Type: GrantFiled: April 18, 2013Date of Patent: February 11, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yoshitaka Dozen, Tomoyuki Aoki, Hidekazu Takahashi, Daiki Yamada, Eiji Sugiyama, Kaori Ogita, Naoto Kusumoto
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Patent number: 8640962Abstract: The radio-frequency identification device includes embedded in an envelope a substrate on one face of which an antenna is produced and a chip connected to the antenna is positioned, a potting locally covering the substrate face level with the chip, an intermediate layer made of a magnetic superconductor material placed against the substrate on the antenna side, the intermediate layer having dimensions greater than those of the antenna so as to be able to cover the antenna and having a cavity arranged so that the potting and the chip can be approximately completely housed therein.Type: GrantFiled: November 6, 2007Date of Patent: February 4, 2014Assignee: ID3S—Identification Solutions Systems & ServicesInventor: Philippe Charrin
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Patent number: 8637978Abstract: A system-in-a-package based flash memory card including an integrated circuit package occupying a small overall area within the card and cut to conform to the shape of a lid for the card. An integrated circuit may be cut from a panel into a shape that fits within and conforms to the shape of lids for a finished memory card, such as for example an SD Card. The integrated circuit package may be a system-in-a-package, a multi-chip module, or other arrangement where a complete electronic system is formed in a single package.Type: GrantFiled: September 19, 2011Date of Patent: January 28, 2014Assignee: SanDisk Technologies Inc.Inventors: Hem Takiar, Robert C. Miller, Warren Middlekauff, Michael W. Patterson, Shrikar Bhagath
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Patent number: 8633056Abstract: A method of manufacture of an integrated circuit package system includes forming a substrate with a device thereover, forming an encapsulation having a planar top surface to cover the device and the substrate spanning to an extraction side of the encapsulation, and forming a recess in the encapsulation from the planar top surface.Type: GrantFiled: March 12, 2010Date of Patent: January 21, 2014Assignee: Stats Chippac Ltd.Inventors: Hyung Jun Jeon, Tae Keun Lee, Sung Soo Kim
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Patent number: 8633576Abstract: A module can include a module card and first and second microelectronic elements having front surfaces facing a first surface of the module card. The module card can also have a second surface and a plurality of parallel exposed edge contacts adjacent an edge of at least one of the first and second surfaces for mating with corresponding contacts of a socket when the module is inserted in the socket. Each microelectronic element can be electrically connected to the module card. The front surface of the second microelectronic element can partially overlie a rear surface of the first microelectronic element and can be attached thereto.Type: GrantFiled: November 29, 2011Date of Patent: January 21, 2014Assignee: Tessera, Inc.Inventors: Wael Zohni, Belgacem Haba
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Patent number: 8610256Abstract: An integrated circuit including an intrusion attack detection device. The device includes a single-piece formed of a conductive material and surrounded with an insulating material and includes at least one stretched or compressed elongated conductive track, connected to a mobile element, at least one conductive portion distant from said piece and a circuit for detecting an electric connection between the piece and the conductive portion. A variation in the length of said track in an attack by removal of the insulating material, causes a displacement of the mobile element until it contacts the conductive portion.Type: GrantFiled: August 7, 2009Date of Patent: December 17, 2013Assignee: STMicroelectronics (Rousset) SASInventors: Pascal Fornara, Christian Rivero
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Patent number: 8602315Abstract: The invention relates to a chip card comprising, a molded card body made by means of injection molding and, an integrated circuit chip, as well as to a method for manufacturing such a card. The invention is characterized in that the card body includes polyacrylic acid. The invention applies to SIM cards in particular.Type: GrantFiled: January 11, 2011Date of Patent: December 10, 2013Assignee: Gemalto SAInventors: Alexis Froger, Jeremy Renouard, Laurent Oddou
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Patent number: 8596545Abstract: A component of a wireless IC device includes a wireless IC chip and a feeding circuit substrate including a plurality of laminated resin layers. The wireless IC chip is included inside the feeding circuit substrate, and an annular electrode is arranged inside the feeding circuit substrate. The component of a wireless IC device and the radiation plate define the wireless IC device.Type: GrantFiled: November 11, 2010Date of Patent: December 3, 2013Assignee: Murata Manufacturing Co., Ltd.Inventors: Noboru Kato, Jun Sasaki
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Patent number: 8599571Abstract: Memory card (1) includes at least semiconductor chip (3), circuit board (2) with semiconductor chip (3) mounted on main surface (21), having at least rigidity reducing portion (23) formed in main surface (21) or in a linear region of surface (22) opposite to the main surface, and cover portion (71) for covering semiconductor chip (3) on main surface (21) of circuit board (2), wherein circuit board (2) has a plurality of convex regions (201) which flex in a convex shape toward main surface (21) due to rigidity reducing portion (23).Type: GrantFiled: April 18, 2007Date of Patent: December 3, 2013Assignee: Panasonic CorporationInventors: Hidenobu Nishikawa, Daido Komyoji, Atsunobu Iwamoto, Hiroyuki Yamada, Shuichi Takeda, Shigeru Kondou
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Patent number: 8588686Abstract: A Method and system for remote power distribution and networking for passive devices is provided. In this regard, a sensor comprising a leaky wave antenna may be powered utilizing energy from a radio frequency signal received via the leaky wave antenna. The sensor may be operable to recover a baseband signal from the received radio frequency signal. The sensor may be operable to generate one or more sensor readings in response to the received baseband signal. The sensor may be operable to communicate the sensor reading to a source of the received radio frequency signal via a backscattered signal. The backscattered signal may be generated by controlling spacing between surfaces of the leaky wave antenna. The backscattered signal may be generated by switching a load in and out of a receive path of the sensor and/or by switching between a plurality of feed points of the leaky wave antenna.Type: GrantFiled: June 9, 2010Date of Patent: November 19, 2013Assignee: Broadcom CorporationInventors: Ahmadreza Rofougaran, Maryam Rofougaran
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Patent number: 8583311Abstract: A storage battery control device detects an overhead wire supply current value showing a sum of a current value output from a storage battery and a current value output from a transformer substation, and charging or discharging of the storage battery is controlled so that a charging rate of the storage battery becomes a charging rate target value when the detected overhead wire supply current value is less than a first threshold. In addition, charging or discharging of the storage battery is controlled so that the output voltage of the storage battery control device is maintained at a constant voltage control mode when the detected overhead wire supply current value is greater than or equal to the first threshold.Type: GrantFiled: July 29, 2011Date of Patent: November 12, 2013Assignee: Mitsubishi Heavy Industries, Ltd.Inventors: Kenji Takao, Katsuaki Morita
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Patent number: 8575739Abstract: A semiconductor package is disclosed including a leadframe, memory die and controller die, one or more of which are customized to facilitate electrical connection of the memory and controller die bond pads to the contact pads of the host device via the leadframe. By customizing one or more of the leadframe, memory die and controller die, an interposer layer normally required to connect the die in the semiconductor package with a host device may be omitted.Type: GrantFiled: May 6, 2011Date of Patent: November 5, 2013Assignee: SanDisk Technologies Inc.Inventors: Suresh Upadhyayula, Ming Hsun Lee, Hem Takiar
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Patent number: 8575740Abstract: An object of the present invention is providing a semiconductor device that is capable of improving the reliability of a semiconductor element and enhancing the mechanical strength without suppressing the scale of a circuit. The semiconductor device includes an integrated circuit sandwiched between first and second sealing films, an antenna electrically connected to the integrated circuit, the first sealing film sandwiched between a substrate and the integrated circuit, which includes a plurality of first insulating films and at least one second insulating film sandwiched therebetween, the second sealing film including a plurality of third insulating films and at least one fourth insulating film sandwiched therebetween. The second insulating film has lower stress than the first insulting film and the fourth insulating film has lower stress than the third insulating film. The first and third insulating films are inorganic insulating films.Type: GrantFiled: September 14, 2012Date of Patent: November 5, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yasuyuki Arai, Yuko Tachimura, Yohei Kanno, Mai Akiba
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Patent number: 8577031Abstract: An integrated circuit (1) is provided with function modules (2) which comprise a central processing unit (4) for treating data and executing a program and a cache memory (5). Until now, it was complicated and costly to ensure the manipulation security of the modules. The function modules (2) comprise an encoding unit (6) for data encoding and decoding.Type: GrantFiled: March 10, 2005Date of Patent: November 5, 2013Assignee: Continental Automotive GmbHInventors: Karl Asperger, Jochen Kiemes, Roland Lange, Andreas Lindinger, Gerhard Rombach
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Patent number: 8561291Abstract: A method for producing a number of chip cards includes a step for preparing a supporting film comprising a number of locations each of which constituting a card support and being provided with a cavity capable of receiving an integrated circuit, a step for processing this supporting film carried out, in part, by a multi-head tool, one of the heads of this tool being provided for carrying out an operation on a location of the film essentially at the same time as another head of this tool carries out the same operation on another location of this film, and a step for separating the locations after the processing step.Type: GrantFiled: October 25, 2006Date of Patent: October 22, 2013Assignee: Oberthur TechnologiesInventors: Francois Launay, Guy Enouf
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Patent number: 8552418Abstract: The present invention provides a semiconductor device which is not easily damaged by external local pressure. The present invention further provides a method for manufacturing a highly-reliable semiconductor device, which is not destructed by external local pressure, with a high yield. A structure body, in which high-strength fiber of an organic compound or an inorganic compound is impregnated with an organic resin, is provided over an element layer having a semiconductor element formed using a non-single crystal semiconductor layer, and heating and pressure bonding are performed, whereby a semiconductor device is manufactured, to which the element layer and the structure body in which the high-strength fiber of an organic compound or an inorganic compound is impregnated with the organic resin are firmly fixed together.Type: GrantFiled: June 10, 2011Date of Patent: October 8, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Eiji Sugiyama, Yoshitaka Dozen, Hisashi Ohtani, Takuya Tsurume
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Patent number: 8552544Abstract: A package structure includes first and second substrates, a sealant and a filler. The first substrate has a surface including an active region and a bonding region. The first substrate has a component in the active region and a pad in bonding region. The pad is electrically connected to the component. The sealant is disposed on the surface surrounding the active region. The sealant has a breach at a side of the active region. The second substrate is bonded to the first substrate via the sealant. The second substrate has a first opening corresponding to the pad, and a second opening corresponding to the breach. The filler fills the second opening, covers the breach such that the first substrate, the second substrate, the sealant and the filler together form a sealed space for accommodating the component.Type: GrantFiled: August 2, 2010Date of Patent: October 8, 2013Assignee: Advanced Semiconductor Engineering, Inc.Inventor: Ching-Hong Chuang
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Patent number: 8546927Abstract: An RFIC module includes an RFIC chip that is mounted on a mounting substrate and that is encapsulated with an encapsulation resin layer. The mounting substrate includes a flexible base and electrodes provided on the flexible base. External terminals are disposed near four corners of a mounting surface of the RFIC chip. One of a plurality of mounting lands located on the surface of the flexible base is a shared mounting land and defines an integrated mounting land that is shared by an RF terminal and an NC terminal of the RFIC chip. The shared mounting land is arranged to cover one side of the RFIC chip when viewed from above.Type: GrantFiled: September 1, 2011Date of Patent: October 1, 2013Assignee: Murata Manufacturing Co., Ltd.Inventors: Koji Shiroki, Makoto Osamura, Takeshi Kurihara, Masami Mizuyama
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Patent number: 8547703Abstract: Disclosed herein is a card-type peripheral apparatus including: a case body configured to accommodate an electronic package including a circuit board between a first surface and a second surface that are opposite to each other; a first electronic package including a memory mounted on the circuit board; a second electronic package including an electronic part for controlling the memory mounted on the circuit board; a first thermal conductive material arranged inside the case body, the first thermal conductive material in contact with a surface of at least one of the first electronic package and the second electronic package; and a second thermal conductive material formed with the first surface and the second surface of the case body, wherein the first thermal conductive material and the second thermal conductive material are in contact with each other inside the case body.Type: GrantFiled: October 22, 2010Date of Patent: October 1, 2013Assignee: Sony CorporationInventors: Yoshitaka Aoki, Hitoshi Kimura
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Patent number: 8517264Abstract: A smart card includes: a host integrated circuit (IC) and one or more secure authentication ICs disposed on a board. The host IC contacts a user's terminal. The host IC is configured to receive signals and execute services in accordance with the received signals. The one or more secure authentication ICs are also configured to receive signals from the host IC and accommodate an application independent of or relevant to the host IC to execute a function of the application. Accordingly, independence and security of the secure authentication ICs is improved.Type: GrantFiled: March 24, 2010Date of Patent: August 27, 2013Assignee: Samsung Electronics Co., Ltd.Inventor: Zanghee Cho
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Patent number: 8508027Abstract: The semiconductor device of the invention includes a transistor, an insulating layer provided over the transistor, a first conductive layer (corresponding to a source wire or a drain wire) electrically connected to a source region or a drain region of the transistor through an opening portion provided in the insulating layer, a first resin layer provided over the insulating layer and the first conductive layer, a layer containing conductive particles which is electrically connected to the first conductive layer through an opening portion provided in the first resin layer, and a substrate provided with a second resin layer and a second conductive layer serving as an antenna. In the semiconductor device having the above-described structure, the second conductive layer is electrically connected to the first conductive layer with the layer containing conductive particles interposed therebetween. In addition, the second resin layer is provided over the first resin layer.Type: GrantFiled: September 9, 2009Date of Patent: August 13, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hidekazu Takahashi, Daiki Yamada, Kyosuke Ito, Eiji Sugiyama, Yoshitaka Dozen
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Patent number: 8502396Abstract: Systems and methods for embedded tamper mesh protection are provided. The embedded tamper mesh includes a series of protection bond wires surrounding bond wires carrying sensitive signals. The protection bond wires are positioned to be vertically higher than the signal bond wires. The protection wires may be bonded to outer contacts on the substrate while the signal bond wires are bonded to inner contacts, thereby creating a bond wire cage around the signal wires. Methods and systems for providing package level protection are also provided. An exemplary secure package includes a substrate having multiple contacts surrounding a die disposed on an upper surface of the substrate. A mesh die including a series of mesh die pads is coupled to the upper surface of the die. Bond wires are coupled from the mesh die pads to contacts on the substrate thereby creating a bond wire cage surrounding the die.Type: GrantFiled: December 8, 2008Date of Patent: August 6, 2013Assignee: Broadcom CorporationInventors: Mark Buer, Matthew Kaufmann
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Patent number: 8486759Abstract: A semiconductor chip module having high degree of freedom in assignment of a circuit to each semiconductor chip and in position of a connection terminal of each semiconductor chip is provided. The present invention relates to a semiconductor chip module in which a plurality of semiconductor chips, each provided on the side face thereof with a part of a connection terminal coupled with a circuit pattern formed on the front face, have been stacked and bonded. Connection terminal portions on the side faces of the respective semiconductor chips are interconnected by a wiring pattern. The connection terminal on the semiconductor chip is led from the front face to the side face and formed by applying spraying of a conductive material in a mist state.Type: GrantFiled: September 23, 2011Date of Patent: July 16, 2013Assignee: Kabushiki Kaisha Nihon MicronicsInventor: Masato Ikeda
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Patent number: 8472199Abstract: A solid state drive is disclosed. The solid state drive includes a circuit board having opposing first and second surfaces. A plurality of semiconductor chips are attached to the first surface of the circuit board of the solid state drive, and the plurality of semiconductor chips of the solid state drive include at least one memory chip that is at least substantially encapsulated in a resin. An in-line memory module-type form factor circuit board is also disclosed. The in-line memory module-type form factor circuit board has opposing first and second surfaces. A plurality of semiconductor chips are attached to the first surface of the in-line memory module-type form factor circuit board, and these semiconductor chips include at least one memory chip that is at least substantially encapsulated in a resin.Type: GrantFiled: February 6, 2009Date of Patent: June 25, 2013Assignee: MOSAID Technologies IncorporatedInventor: Jin-Ki Kim
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Patent number: 8467192Abstract: A method for producing a rollable web with successive antennas, where an electronic chip is attached to an antenna in a predetermined position. The position of an electronic chip changes with respect to the antenna when compared to at least some of the chips within individual and successive antennas. A rollable web includes successive antennas, where electronic chips are attached to antennas in a predetermined position. In the rollable web, the position of a chip changes with respect to the antenna compared to at least some of the chips within individual and successive antennas.Type: GrantFiled: April 20, 2009Date of Patent: June 18, 2013Assignee: Smartrac IP B.V.Inventor: Samuli Strömberg
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Patent number: 8455990Abstract: A barrier layer can be attached in a semiconductor package to one or more sensitive devices. The barrier layer can be used to obstruct tampering by a malicious agent attempting to access sensitive information on the sensitive device. The barrier layer can cause the sensitive device to become inoperable if physically tampered. Additional other aspects of the protective packaging provide protection against x-ray and thermal probing as well as chemical and electrical tampering attempts.Type: GrantFiled: February 25, 2010Date of Patent: June 4, 2013Assignee: Conexant Systems, Inc.Inventors: Robert W Warren, Hyun Jung Lee, Nic Rossi
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Patent number: 8441099Abstract: An ID tag capable of communicating data wirelessly, the size of which is reduced, and where the size of an IC chip is reduced, a limited area of the chip is effectively used, current consumption is reduced, and communication distance is prevented from decreasing. The ID tag of the invention includes an IC chip having an integrated circuit, a resonance capacitor portion and a storage capacitor portion, and an antenna formed over the IC chip so as to overlap at least partially with an insulating film interposed therebetween. The antenna, the insulating film and wirings or semiconductor films forming the integrated circuit are stacked, and one or both of capacitors in the resonance capacitor portion and the storage capacitor portion are formed by this stacked structure.Type: GrantFiled: September 29, 2010Date of Patent: May 14, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Yutaka Shionoiri
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Patent number: 8432018Abstract: The present invention provides a thin and bendable semiconductor device utilizing an advantage of a flexible substrate used in the semiconductor device, and a method of manufacturing the semiconductor device. The semiconductor device has at least one surface covered by an insulating layer which serves as a substrate for protection. In the semiconductor device, the insulating layer is formed over a conductive layer serving as an antenna such that the value in the thickness ratio of the insulating layer in a portion not covering the conductive layer to the conductive layer is at least 1.2, and the value in the thickness ratio of the insulating layer formed over the conductive layer to the conductive layer is at least 0.2. Further, not the conductive layer but the insulating layer is exposed in the side face of the semiconductor device, and the insulating layer covers a TFT and the conductive layer.Type: GrantFiled: October 12, 2011Date of Patent: April 30, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yoshitaka Dozen, Tomoyuki Aoki, Hidekazu Takahashi, Daiki Yamada, Eiji Sugiyama, Kaori Ogita, Naoto Kusumoto
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Patent number: 8432284Abstract: Methods and systems of attaching a radio transceiver to an antenna. At least some of the illustrative embodiments are systems comprising an antenna and an integrated circuit configured to operate as a radio transceiver. The antenna comprises a ground plane having a first edge surface, and an active element having a second edge surface. The ground plane and the active element are retained together such that the first and second edge surfaces are substantially coplanar and form an antenna edge. The integrated circuit is configured to operate as a radio transceiver, and the integrated circuit is mechanically coupled to the edge of the antenna and electrically coupled to the active element.Type: GrantFiled: July 2, 2009Date of Patent: April 30, 2013Assignee: Round Rock Research, LLCInventor: John R. Tuttle
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Patent number: 8426234Abstract: An integrated circuit including an intrusion attack detection device. The device includes a single-piece formed of a conductive material and surrounded with an insulating material and includes at least one stretched or compressed elongated conductive track, connected to a mobile element, at least one conductive portion distant from said piece and a circuit for detecting an electric connection between the piece and the conductive portion. A variation in the length of said track in an attack by removal of the insulating material, causes a displacement of the mobile element until it contacts the conductive portion.Type: GrantFiled: September 21, 2011Date of Patent: April 23, 2013Assignee: STMicroelectronics (Rousset) SASInventors: Pascal Fornara, Christian Rivero
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Patent number: 8421224Abstract: Provided is a semiconductor chip having a double bump structure. The semiconductor chip may include a semiconductor substrate, a circuit region on a surface of the semiconductor substrate, a pad on the semiconductor substrate and connected to the circuit region, a first bump on the pad, and a second bump on the first bump. The second bump may be arranged at one side of an upper surface of the first bump and the upper surface of the first bump may include a test area configured to interface with a probe tip, wherein the test area is an area of the upper surface of the first bump exposed by the second bump.Type: GrantFiled: January 7, 2011Date of Patent: April 16, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Seung-hyun Shin, Dong-yoon Sun
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Patent number: 8415782Abstract: The present invention relates to a chip card and a method for the production of a chip card having a chip (21) which is arranged in a card body, and having a plurality of components (18, 19, 22) being electrically conductively connected to the chip by means of a conductor arrangement (20), wherein the card body is composed of a plurality of substrate layers (11, 12, 13) which are arranged in a layer structure, wherein the components and the conductor arrangement are arranged in different substrate layers, specifically a component layer arrangement and a connecting layer arrangement, and have contact surfaces (23, 24, 25, 26, 31, 32, 33, 34), which are disposed so as to overlap one another, for producing an electrically conductive contacting.Type: GrantFiled: May 14, 2009Date of Patent: April 9, 2013Assignee: Smartrac IP B.V.Inventors: Manfred Rietzler, Raymond Freeman
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Patent number: 8399964Abstract: A magnetic shield is presented. The shield may be used to protect a microelectronic device from stray magnetic fields. The shield includes at least two layers. A first layer includes a magnetic material that may be used to block DC magnetic fields. A second layer includes a conductive material that may be used to block AC magnetic fields. Depending on the type of material that the first and second layers include, a third layer may be inserted in between the first and second layers. The third layer may include a non-conductive material that may be used to ensure that separate eddy current regions form in the first and second layers.Type: GrantFiled: August 23, 2010Date of Patent: March 19, 2013Assignee: Honeywell International Inc.Inventor: Romney R. Katti
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Patent number: 8396136Abstract: A system includes a first device having a first transceiver and a first device electrode pair connected to the first transceiver, and a second device having a second transceiver and a second device electrode pair connected to the second transceiver. The second device electrode pair is located relative to the first device electrode pair such that the first device electrode pair and the second device electrode pair form a capacitive network. The first transceiver and second transceiver are each configured to receive a plurality of bits, encode each bit of the plurality of bits, and DC balance and transmit each of the plurality of encoded bits over the capacitive network. Methods for use with the system are provided for encoding and transmitting data, as well as receiving and decoding the encoded data.Type: GrantFiled: July 22, 2009Date of Patent: March 12, 2013Assignee: The United States of America as Represented by the Secretary of the NavyInventor: Narek Pezeshkian
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Patent number: 8390132Abstract: A chip card in the form of an ID-1 card, a plug-in SIM or a USB token has a layered compound (12) with two (4, 5) or three (4, 5, 9) layers extending over the complete chip card (1). An exterior foil layer (4) has on its outward facing front side (4a) a communication contact layout (2) and on its back side (4b) a flip chip (7), as well as a flip chip contact layout (6) which is electroconductively connected with the communication contact layout (2) on the front side.Type: GrantFiled: January 18, 2012Date of Patent: March 5, 2013Assignee: Giesecke & Devrient GmbHInventor: Thomas Tarantino
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Patent number: 8378473Abstract: In inlets used for ID tags and the like, a defective connection between an integrated circuit part and an antenna is suppressed by improvement of tolerance for a bending or a pressing pressure. The integrated circuit part includes a semiconductor chip and a multilayer substrate having a concave portion. The semiconductor chip is mounted on the bottom of the concave portion. The multilayer substrate includes a connection electrode at the top surface and a connection electrode connected to the semiconductor chip on the bottom of the concave portion. The connection electrode on the bottom of the concave portion is connected to the connection electrode at the top surface by a penetration electrode inside a multilayer substrate. By such a configuration, the semiconductor chip is connected to the antenna.Type: GrantFiled: November 23, 2010Date of Patent: February 19, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Yasuyuki Arai
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Patent number: 8330261Abstract: In general, the invention relates to manufacturing a wafer. The method includes manufacturing a wafer that includes a front side and a back side, thinning the wafer down to a thickness suitable for an intended operation of the wafer, polarizing the substrate wafer from the back side, and cutting the wafer. The wafer is polarized such that an attempt to thin the wafer from the backside results in at least one selected from a group consisting of destruction of the wafer and damage to the wafer.Type: GrantFiled: February 7, 2006Date of Patent: December 11, 2012Assignee: Gemalto SAInventor: Michel Thill
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Publication number: 20120280380Abstract: A glass-based, high-performance 60 GHz/mm-wave antenna includes cavities disposed in a phased-array antenna (PAA) substrate. The cavities are disposed below planar antenna elements. Emitter traces are disposed on the PAA substrate opposite the planar antenna elements and the emitter traces, the cavities, and the planar antenna elements are vertically aligned.Type: ApplicationFiled: May 5, 2011Publication date: November 8, 2012Inventor: Telesphor Kamgaing
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Patent number: 8297517Abstract: Provided are an antenna circuit constituent body for an IC card/tag, which enhances a Q value by reducing a permittivity of a resin film of which a base material is made; and an IC card. The antenna circuit constituent body includes the base material made of resin film; and circuit pattern layers formed on each of both sides of the base material and made of aluminum foil. The circuit pattern layer includes a coiled pattern layer. Parts of the circuit pattern layers, which mutually face each other; and a part of the base material, which is interposed between the parts of the circuit pattern layers, constitute a capacitor. The circuit pattern layers are electrically connected by crimping parts. The base material includes a plurality of void-state-air layers. A relative density of the base material with respect to a density of a resin is less than or equal to 0.9.Type: GrantFiled: April 28, 2009Date of Patent: October 30, 2012Assignee: Toyo Aluminium Kabushiki KaishaInventors: Akira Shingu, Kiyoji Egashira
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Patent number: 8283664Abstract: A method of forming a semiconductor package is disclosed including disguising the test pads. Test pads are defined in the conductive pattern of the semiconductor package for allowing electrical test of the completed package. The test pads are formed in shapes such as letters or objects so that they are less recognizable as test pads.Type: GrantFiled: March 7, 2011Date of Patent: October 9, 2012Assignee: SanDisk Technologies Inc.Inventor: Arie Frenklakh
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Patent number: 8258613Abstract: A semiconductor package for a semiconductor chip, e.g., a memory chip, is disclosed. The semiconductor package includes a substrate having a generally rectangular perimeter with four sidewalls and a chamfer between adjacent first and second ones of the sidewalls. The memory chip is electrically coupled contacts provided on an opposite surface of the substrate. The contacts are in a row along only the one sidewall of the substrate. A body of a plastic encapsulant covers the first surface of the substrate, the memory chip, and at least two of the sidewalls of the package. The entire perimeter of the substrate, including all four sidewalls and the chamfer, are covered by the plastic encapsulant. Alternatively, only two or three of the sidewalls are covered by the plastic encapsulant, with the other sidewall(s) being exposed and vertically coplanar with a respective sidewall of the plastic encapsulant.Type: GrantFiled: August 4, 2003Date of Patent: September 4, 2012Assignee: Amkor Technology, Inc.Inventors: Vincent DiCaprio, Kenneth Kaskoun