Smart (e.g., Credit) Card Package Patents (Class 257/679)
-
Patent number: 10083911Abstract: A semiconductor device package includes a flexible substrate, an electronic component, at least one flexible member, and a package body. The electronic component is disposed on the flexible substrate. The at least one flexible member is disposed on the flexible substrate. The package body encapsulates the electronic component and has a first part and a second part separated from the first part by the at least one flexible member.Type: GrantFiled: February 8, 2017Date of Patent: September 25, 2018Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Hao-Chih Hsieh, Tun-Ching Pi
-
Patent number: 10068513Abstract: An electronic paper apparatus including a communication module and a control module is provided. The communication module receives an electrical signal and generates a power voltage according to the electric signal. The communication module wakes up a controller during a first period of a work period by using the power voltage. The control module is electrically connected to the communication module, and includes the controller and an electronic paper display. The control module establishes a communication connection with the communication module during a second period of the work period. The power circuit module generates a driving voltage according to the power voltage to drive the electronic paper display to display image information according to the driving voltage during a display period. The first period and the second period are two continuous time intervals forming the work period. Furthermore, a driving method of the electronic paper apparatus is also provided.Type: GrantFiled: July 26, 2015Date of Patent: September 4, 2018Assignee: E Ink Holdings Inc.Inventors: Chuen-Jen Liu, Li-Wei Chou, Jia-Hong Xu, Yu-Ming Lee, Chi-Mao Hung
-
Patent number: 10043766Abstract: The integrated circuit includes a functional block performing a logic and/or analog function. A control circuit is configured to transmit at least a first signal to the receiver and receive a second signal from receiver. The electrically conducting lines' first and second series connect the control circuit and receiver to perform the first and second signals' transit. A plurality of monitoring stations is simultaneously connected to first and second series of electrically conducting lines to define a first elementary electric pattern in the electrically conducting lines' first series and a distinct second elementary electric pattern equivalent to first elementary electric pattern in the electrically conducting lines' second series. A shield at least partially covers the functional block. The control circuit is configured to detect modification of first elementary electric pattern with respect to the second elementary electric pattern by absence of receipt of the second signal after a predefined time-out.Type: GrantFiled: July 25, 2017Date of Patent: August 7, 2018Assignee: TIEMPOInventors: Marc Renaudin, Bertrand Folco, Boubkar Boulahia
-
Patent number: 10021791Abstract: In one embodiment of the present invention, a multilayer wiring substrate includes: a first wiring substrate having a first core member made of metal with cavities therein; a second wiring substrate having a second core member made of metal; and a bonding layer between the first wiring substrate and the second wiring substrate to bond a top surface of the first wiring substrate to a bottom surface of the second wiring substrate, the bonding layer having a patterned conductive layer.Type: GrantFiled: August 31, 2015Date of Patent: July 10, 2018Assignee: TAIYO YUDEN CO., LTD.Inventors: Yuichi Sugiyama, Masashi Miyazaki
-
Patent number: 9984984Abstract: A semiconductor element mounting board includes: a circuit conductor disposed on the insulating board, a plurality of semiconductor element connection pads connected to the circuit conductor, a semiconductor element mounted on a surface of the insulating board, a first capacitor and a second capacitor disposed on a surface or an inside of the insulating board, and a first conductor path configured to connect the first capacitor between the semiconductor element connection pads, and a second conductor path configured to connect the second capacitor between the semiconductor element connection pads; and an inductance of the first conductor path is smaller than an inductance of the second conductor path, and capacitance of the first capacitor is smaller than capacitance of the second capacitor, and an internal inductance of the first capacitor is smaller than an internal inductance of the second capacitor.Type: GrantFiled: November 29, 2016Date of Patent: May 29, 2018Assignee: KYOCERA CORPORATIONInventors: Makoto Shiroshita, Hisayoshi Wada
-
Patent number: 9922844Abstract: The invention provides a semiconductor package and a method for fabricating a base for a semiconductor package. The semiconductor package includes a base. The base has a device-attach surface. A radio-frequency (RF) device is embedded in the base. The RF device is close to the device-attach surface.Type: GrantFiled: March 12, 2014Date of Patent: March 20, 2018Assignee: MediaTek Inc.Inventors: Wen-Sung Hsu, Ta-Jen Yu
-
Patent number: 9898694Abstract: A transaction card having three layers, wherein the first layer is metal, the second layer is a polymer, and the third layer is a carbon-containing layer.Type: GrantFiled: February 24, 2016Date of Patent: February 20, 2018Assignee: Black Card LLCInventor: Scott Alan Blum
-
Patent number: 9848493Abstract: A printed circuit board assembly comprises a printed circuit board (PCB) defining a mounting end and an opposite contacting end, a row of first pads on the mounting end, a row of second pads on the contacting end, and an edge connector on the contacting end electrically contacted with the second pads, and a high speed line module mounted on a top side of the PCB and including a group of conductive lines, the conductive lines extending parallel to each other over the plane of the PCB, each conductive line having two ends electrically connected to corresponding first and second pads, respectively.Type: GrantFiled: December 9, 2016Date of Patent: December 19, 2017Assignee: FOXCONN INTERCONNECT TECHNOLOGY LIMITEDInventors: Andrew Engel, Paul Yu, Klaus Giessler, Omid Momtahan, Michael John Brosnan, David Meadowcroft
-
Patent number: 9806060Abstract: A flexible package may be provided. The flexible package may include a flexible molding member including a top surface. The flexible package may include a first chip within the flexible molding member, and including a first top surface. The flexible package may include a second chip within the flexible molding member, and including a second top surface. The first top surface may face away from the top surface of the flexible molding member and the second top surface may face towards the top surface of the flexible molding member.Type: GrantFiled: February 13, 2017Date of Patent: October 31, 2017Assignee: Sk hynix Inc.Inventor: Chan Woo Jeong
-
Patent number: 9795036Abstract: A mounting structure includes a bonding material (106) that bonds second electrodes (104) of a circuit board (105) and bumps (103) of a semiconductor package (101), the bonding material (106) being surrounded by a first reinforcing resin (107). Moreover, a portion between the outer periphery of the semiconductor package (101) and the circuit board (105) is covered with a second reinforcing resin (108). Even if the bonding material (106) is a solder material having a lower melting point than a conventional bonding material, high drop resistance is obtained.Type: GrantFiled: April 5, 2013Date of Patent: October 17, 2017Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Arata Kishi, Hironori Munakata, Koji Motomura, Hiroki Maruo
-
Patent number: 9768037Abstract: A method of manufacturing an electronic device package includes structuring a metal layer to generate a structured metal layer having a plurality of openings. Semiconductor chips are placed into at least some of the openings. An encapsulating material is applied over the structured metal layer and the semiconductor chips to form an encapsulation body. The encapsulation body is separated into a plurality of electronic device packages.Type: GrantFiled: May 16, 2014Date of Patent: September 19, 2017Assignee: Infineon Technologies AGInventors: Petteri Palm, Edward Fuergut, Irmgard Escher-Poeppel
-
Patent number: 9760754Abstract: A Printed Circuit Board Assembly (PCBA) forming an enhanced fingerprint module is disclosed. The PCBA includes a Printed Circuit Board (PCB), an image sensing chip, at least one electrode and a protection layer. An opening in a first insulation layer and a second insulation layer of the PCB together form a sensor portion so that the image sensing chip can be packaged in the opening. Thus, the thickness of the enhanced fingerprint module can be thinner than other fingerprint modules provided by the conventional package methods.Type: GrantFiled: July 6, 2015Date of Patent: September 12, 2017Assignee: SunASIC Technologies Inc.Inventors: Chi-Chou Lin, Zheng-Ping He
-
Patent number: 9733428Abstract: Three-dimensional flexible photonic integrated circuits on silicon are fabricated in semiconductor wafer form and then transferred to Silicon-on-Polymer (SOP) substrates. SOP provides flexibility for conformal mounting with devices capable of maintaining performance when dynamically deformed to allow routing of light in x, y and z directions. Bonding a wafer or individual die of III-V semiconductor, such as Gallium Arsenide or similar photonic material, to the flexible silicon creates an active region for lasers, amplifiers, modulators, and other photonic devices using standard processing. Mounting additional photonic devices to the opposite side of a flexible photonic waveguide produces a stack for three-dimensional devices. Multiple flexible photonic waveguides may be stacked to increase functionality by transferring light between stacked waveguides.Type: GrantFiled: February 4, 2014Date of Patent: August 15, 2017Assignee: American Semiconductor, Inc.Inventors: Douglas R. Hackler, Sr., Dale G. Wilson
-
Patent number: 9721200Abstract: In a smart card having an antenna structure and a metal layer, an insulator layer is formed between the antenna structure and the metal layer to compensate for the attenuation due to the metal layer. The thickness of the insulator layer affects the capacitive coupling between the antenna structure and the metal layer and is selected to have a value which optimizes the transmission/reception of signals between the card and a card reader.Type: GrantFiled: November 17, 2014Date of Patent: August 1, 2017Assignee: COMPOSECURE, L.L.C.Inventors: John Herslow, Michele Logan, David Finn
-
Patent number: 9666833Abstract: An array substrate and a manufacturing method thereof, a flexible display panel and a display device are provided. The array substrate includes a flexible substrate divided into a display region and a periphery region, the periphery region surrounding the display region. The array substrate further includes: an array layer and a first film layer sequentially formed in the display region on the flexible substrate; a plurality of integrate circuits and a flexible printed circuit board interface formed in the periphery region on the flexible substrate; a flexible protective film layer formed on a junction of the periphery region and the first film layer and in a region of the periphery region other than the integrate circuits and the flexible printed circuit board interface on the flexible substrate.Type: GrantFiled: February 9, 2015Date of Patent: May 30, 2017Assignee: BOE Technology Group Co., Ltd.Inventors: Tao Gao, Weifeng Zhou
-
Patent number: 9667410Abstract: In data processing including high-speed cipher calculation for which it is not appropriate to employ a leveling technique, tamper resistance is improved against an attack to a specific position performed by knowing a layout of functional blocks in a semiconductor chip. Examples of the attack include micro-probing, fault injection, and electromagnetic wave analysis. A semiconductor device, in which a plurality of IC chips that perform the same cipher calculation in parallel are laminated or stacked, performs data processing including the cipher calculation. A chip that compares and verifies results of the cipher calculations performed by the plurality of chips is laminated in an intermediate layer whose element surface is covered by another chip. For example, when three chips are laminated, a chip in the intermediate layer sandwiched by the upper layer and the lower layer has a comparative verification function.Type: GrantFiled: September 3, 2015Date of Patent: May 30, 2017Assignee: Renesas Electronics CorporationInventor: Daisuke Oshida
-
Patent number: 9627916Abstract: An electronic card including an antenna, a chip, a charging circuit and a battery is provided. The antenna receives an external electric signal, and the chip is coupled to the antenna, so as to receive the external electric signal and provide a demodulated electric signal. The charging circuit is coupled to the chip, receives the demodulated electric signal and converts the demodulated electric signal to generate a charging power. The battery is coupled to the charging circuit, wherein, the charging circuit provides the charging power to the battery according to a residual electricity of the battery, so as to charge the battery.Type: GrantFiled: June 13, 2013Date of Patent: April 18, 2017Assignee: E Ink Holdings Inc.Inventors: Yao-Jen Hsieh, Ming-Jong Jou, Chi-Mao Hung, Wei-Min Sun
-
Patent number: 9627338Abstract: A semiconductor device has a plurality of semiconductor die. A first prefabricated insulating film is disposed over the semiconductor die. A conductive layer is formed over the first prefabricated insulating film. An interconnect structure is formed over the semiconductor die and first prefabricated insulating film. The first prefabricated insulating film is laminated over the semiconductor die. The first prefabricated insulating film includes glass cloth, glass fiber, or glass fillers. The semiconductor die is embedded within the first prefabricated insulating film with the first prefabricated insulating film covering first and side surfaces of the semiconductor die. The interconnect structure is formed over a second surface of the semiconductor die opposite the first surface. A portion of the first prefabricated insulating film is removed after disposing the first prefabricated insulating film over the semiconductor die.Type: GrantFiled: February 21, 2014Date of Patent: April 18, 2017Assignee: STATS ChipPAC Pte. Ltd.Inventors: See Chian Lim, Teck Tiong Tan, Yung Kuan Hsiao, Ching Meng Fang, Yoke Hor Phua, Bartholomew Liao
-
Patent number: 9601442Abstract: A mold package being a half-mold type includes: a substrate includes a first face and a second face; an electronic component that is mounted on the first face; and a mold resin that is provided on the first face and seals the first face with the electronic component. The second face is exposed from the mold resin. The mold resin is disposed on the first face so as to seal a sealed portion and to expose a remaining part of the first face as an exposure portion. One side face is provided by an end side face. One side face is provided by a boundary side face. At least a site on a lower end of the boundary side face is provided by an inclined face. In the boundary side face, a site on an upper end side is provided by an other inclined face having a second inclination angle.Type: GrantFiled: January 9, 2015Date of Patent: March 21, 2017Assignee: DENSO CORPORATIONInventors: Kengo Oka, Tetsuto Yamagishi
-
Patent number: 9603295Abstract: In a case where a first mounted substrate to which a semiconductor element is bounded by solder is mounted on a second substrate, connection strength becomes low, when the first mounted substrate is bonded to the second substrate by using a solder having a low melting point. A mounted structure, in which a first mounted substrate on which a semiconductor element is bonded by using a first solder having a melting point of 217° C. or more, is mounted on a second substrate, includes plural bonding parts bonding the first mounted substrate to the second substrate; and a reinforcing member formed around the bonding part. Each of the bonding parts contains a second solder having a melting point, that is lower than the melting point of the first solder, and a space exists, in which the reinforcing members do not exist, between the bonding parts neighboring each other.Type: GrantFiled: April 2, 2012Date of Patent: March 21, 2017Assignee: Panasonic Intellectual Property Management Co., Ltd.Inventors: Atsushi Yamaguchi, Hisahiko Yoshida, Arata Kishi, Naomichi Ohashi
-
Patent number: 9578763Abstract: Disclosed is a technique for tamper detection in an electronic device by use of an internal power supply signal. The technique includes electrically coupling a conductive trace, in series via a resistor, to an internal power supply that supplies power to a security module within a processor of the device. The technique further includes electrically coupling the power supply to a detector for use in tamper detection on the trace. Upon occurrence of a short-circuit condition on the conductive trace, substantially all voltage of the local power supply is dropped across the resistor. As a result, the detector detects a drop in voltage below a predetermined threshold, and perceives such drop as a “collapse” of the internal power supply. The collapse of the power supply is indicative of a tampering event to the detector, which in response, outputs a signal to disable an operation of the security module.Type: GrantFiled: May 22, 2014Date of Patent: February 21, 2017Assignee: Square, Inc.Inventor: Jeremy Wade
-
Patent number: 9570380Abstract: An electronic device comprising: a semiconductor die integrating an electronic component; a leadframe housing the semiconductor die; a protection body, which surrounds laterally and at the top the semiconductor die and, at least in part, the leadframe structure, defining a top surface, a bottom surface, and a thickness of the electronic device; and a conductive lead electrically coupled to the semiconductor die. The conductive lead is modelled in such a way as to extend throughout the thickness of the protection body for forming a front electrical contact accessible from the top surface of the electronic device, and a rear electrical contact accessible from the bottom surface of the electronic device.Type: GrantFiled: September 30, 2015Date of Patent: February 14, 2017Assignee: STMicroelectronics S.r.l.Inventors: Fabio Vito Coppone, Agatino Minotti, Francesco Salamone
-
Patent number: 9564686Abstract: A near field communication antenna device of a mobile terminal is provided. The near field communication antenna device includes a window including a display region for transmitting an image displayed by a display and a black mark region formed around the display region, a multi-layer Flexible Printed Circuit Board (FPCB) on which a plurality of layers are laminated on the lower side of the black mark region of the window, and a spiral loop-shaped antenna pattern in which conductive lines are formed on respective layers of the multi-layer FPCB and are connected to each other. Accordingly, a near field communication antenna is not disposed in a separated installation space, an antenna pattern width can be reduced, and performance of the near field communication antenna may be prevented from being degraded when a battery cover is made of metal or has a curved shape.Type: GrantFiled: February 9, 2015Date of Patent: February 7, 2017Assignees: Samsung Electronics Co., Ltd., EXAX Inc.Inventors: Kyu Sik Cho, In Sook Kim
-
Patent number: 9548263Abstract: Electronic device packages and related fabrication methods are provided. An exemplary electronic device includes a semiconductor die having debug circuitry fabricated thereon, a framing structure including an interior portion having the semiconductor die mounted thereto, and a conductive element providing an electrical connection between the interior portion and a contact pad on the semiconductor die that corresponds or is otherwise coupled to an interface of the debug circuitry.Type: GrantFiled: June 16, 2015Date of Patent: January 17, 2017Assignee: NXP USA, Inc.Inventors: Damon Peter Broderick, Dirk Heisswolf, Andreas R. Pachl
-
Patent number: 9530715Abstract: A multi-chip semiconductor device comprises a thermally enhanced structure, a first semiconductor chip, a second semiconductor chip, an encapsulation layer formed on top of the first semiconductor chip and the second semiconductor chip. The multi-chip semiconductor device further comprises a plurality of thermal vias formed in the encapsulation layer. The thermally enhanced structure comprises a heat sink block attached to a first semiconductor die. The heat sink block may further comprise a variety of thermal vias and thermal openings. By employing the thermal enhanced structure, the thermal performance of the multi-chip semiconductor device can be improved.Type: GrantFiled: September 11, 2015Date of Patent: December 27, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Chih-Hang Tung, Tung-Liang Shao
-
Patent number: 9509306Abstract: According to an aspect of the invention an integrated circuit is conceived which comprises a physical unclonable function which is at least partially implemented in a passivation layer of said integrated circuit. According to a further aspect of the invention, a corresponding method for manufacturing an integrated circuit is conceived. According to a further aspect of the invention, an electronic device is conceived which comprises an integrated circuit of the kind set forth.Type: GrantFiled: April 19, 2013Date of Patent: November 29, 2016Assignee: NXP B.V.Inventors: Soenke Ostertun, Michael Ziesmann
-
Patent number: 9454724Abstract: A membrane is formed from a release liner upon which a plurality of labels and a margin sheet are attached. Each label is a flexible planar body, including a display surface on a top side and an electronic circuit on a bottom side. A first adhesive coating is applied to the bottom of the flexible planar body, allowing the label to be temporarily adhered to the release liner. An antenna is joined to the electronic circuit and connected to the flexible planar body. The electronic circuit itself enables item identification, such as through Radio-Frequency Identification or Electronic Article Surveillance. In order to provide visual information, a primary printed graphic can be applied to each of the labels, while a supplementary printed graphic can be applied to the margin sheet. The plurality of labels can be arranged in different arrays, such as a plurality of rows or a tessellated pattern.Type: GrantFiled: November 9, 2015Date of Patent: September 27, 2016Inventor: Bong J. Im
-
Patent number: 9437777Abstract: When a conductive layer occupying a large area is provided in a coiled antenna portion, it has been difficult to supply power stably. A memory circuit portion and a coiled antenna portion are disposed by being stacked together; therefore, it is possible to prevent a current from flowing through a conductive layer occupying a large area included in the memory circuit portion, and thus, power saving can be achieved. In addition, the memory circuit portion and the coiled antenna portion are disposed by being stacked together, and thus, it is possible to use a space efficiently. Therefore, downsizing can be realized.Type: GrantFiled: June 17, 2014Date of Patent: September 6, 2016Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Tamae Takano, Nobuharu Ohsawa, Kiyoshi Kato
-
Patent number: 9361489Abstract: An electromagnetic transponder including a resonant circuit; a rectifying bridge having input terminals connected across the resonant circuit and having rectified output terminals providing an electronic circuit power supply voltage; and a device for limiting the voltage across the resonant circuit, connected between the input terminals of the rectifying bridge.Type: GrantFiled: June 15, 2015Date of Patent: June 7, 2016Assignee: STMicroelectronics (Rousset) SASInventors: Marc Battista, Gilles Bas, Francois Tailliet
-
Patent number: 9355347Abstract: A card is provided comprising an information setting unit configured to output a first signal including unique information of the card, and a bending sensor configured to output a second signal corresponding to a curvature of the card. An information processing apparatus is also provided comprising a card reading unit configured to acquire information from a card a processor, and a memory device. The memory device stores instructions which when executed by the processor, causes the processor to acquire unique information from the card, and acquire curvature information from the card corresponding to a curvature of the card.Type: GrantFiled: October 21, 2013Date of Patent: May 31, 2016Assignee: Sony CorporationInventors: Takehisa Ishida, Nobuyuki Nagai, Yusaku Kato, Hideo Kawabe, Osamu Ito
-
Patent number: 9323941Abstract: The component comprises a first memory (MM) comprising a first portion (P1) having a content modified with a first modification entity (K1) and a second portion (P2) having a content modified with a second entity (K2), a storage means (MS) configured to store the first entity (K1) secretly, a non-volatile memory (NVM) storing an item of entity information representative of the second entity (K2) in a location (END) designated by a first indication (INDK2) contained in the said first portion of the first memory.Type: GrantFiled: November 9, 2010Date of Patent: April 26, 2016Assignee: STMicroelectronics (Rousset) SASInventors: Fabrice Marinet, Mathieu Lisart
-
Patent number: 9286951Abstract: According to one embodiment, there are provided a memory which is provided on a circuit board, a controller which is provided on the circuit board and controls the memory, and a signal line which is formed on the circuit board and configured to perform data transmission between the controller and the memory, in which a width of the signal line in the place where the signal line is led out from the memory is large compared with a place disposed under the memory.Type: GrantFiled: January 12, 2015Date of Patent: March 15, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Okada, Atsuko Seki
-
Patent number: 9275983Abstract: A method of making an integrated circuit (IC) package including electrically and physically attaching a die to an interposer, attaching the interposer to a bottom leadframe, attaching a discrete circuit component to the interposer and attaching a top leadframe to the bottom leadframe.Type: GrantFiled: May 7, 2015Date of Patent: March 1, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Lee Han Meng@ Eugene Lee, Anis Fauzi bin Abdul Aziz, Yien Sien Khoo
-
Patent number: 9245828Abstract: A package and integrated circuit assembly is configured to perform signal conditioning on a signal. The assembly includes a line card having line card contacts that correspond to conductors in the line card connector. Two or more integrated circuits are configured to perform signal conditioning on the signal and the two or more integrated circuits are configured within a package into at least a first row and a second row on the package. The package includes a grid array of bonding pads to electrically connect to the two or more integrated circuits through bond wires or down bonds such that the structure of the grid array corresponds in physical arrangement or bond pad pitch to the line card contacts. This assembly also includes an electrical connection from the two or more integrated circuits to the line card through the package.Type: GrantFiled: July 11, 2013Date of Patent: January 26, 2016Assignee: Mindspeed Technologies, Inc.Inventors: Atul K. Gupta, Ryan S. Latchman, Marek S. Tlalka
-
Patent number: 9232639Abstract: Some embodiments described herein include apparatuses and methods of forming such apparatuses. One such embodiment may include a routing arrangement having pads to be coupled to a semiconductor die, with a first trace coupled to a first pad among the pads, and a second trace coupled to a second pad among the pads. The first and second traces may have different thicknesses. Other embodiments including additional apparatuses and methods are described.Type: GrantFiled: December 6, 2012Date of Patent: January 5, 2016Assignee: Intel CorporationInventors: Zhichao Zhang, Tao Wu, Zhiguo Qian, Kemal Aygun
-
Patent number: 9218562Abstract: The invention relates to a method for manufacturing a contactless microcircuit antenna coil, including steps of: depositing a first electrically conducting layer on a first face of a wafer, and forming in the first layer an antenna coil in a spiral having several turns, including an internal turn coupled to an internal contact pad and an external turn coupled to an external contact pad, the external turn following the entire contour of antenna coil except for a zone through which a conducting path coupling the external contact pad to the external turn can pass, the external and internal contact pads of the antenna coil being formed in a central zone of the external turn, the antenna coil having a bypass zone in which each turn bypasses the external contact pad.Type: GrantFiled: May 3, 2013Date of Patent: December 22, 2015Assignee: INSIDE SECUREInventors: Ghislain Boiron, Pierre Pic
-
Patent number: 9210813Abstract: A high-density Subscriber Identity Module (SIM) card package and a production method thereof are provided. The SIM card package includes a substrate, an Integrated Circuit (IC) chip, a bonding wire, and a mold cap. The substrate is a two-layer, a four-layer, a six-layer or an eight-layer high-density interlinked and packaged organic laminated substrate that is manufactured through an etching-back process, and a passive device and a crystal oscillator are provided on the organic laminated substrate. Two IC chips are provided side by side, or one of the IC chips is stacked with a third IC chip, the third IC chip being respectively connected to the organic laminated substrate and the IC chip under the third IC chip by the bonding wire. The IC chip, the passive device, and the crystal oscillator are adhered to the organic laminated substrate.Type: GrantFiled: December 30, 2010Date of Patent: December 8, 2015Assignee: TIANSHUI HUATIAN TECHNOLOGY CO., LTD.Inventors: Jianyou Xie, Xiaowei Guo, Wenhai He, Wei Mu, Xin Chen
-
Patent number: 9172143Abstract: An electronic device module as described herein includes an electronic device package having device contacts. The electronic device package is fixed within encapsulating material, along with an electrically conductive ground layer. The ground layer has a device opening in which the electronic device package resides, and the ground layer also has an antenna opening spaced apart from the device opening. The device contacts and one side of the ground layer correspond to a first surface, and a patch antenna element overlies the first surface. The antenna element is coupled to the electronic device package, and a projection of the patch antenna element onto the first surface resides within the antenna opening. Also provided are methods for manufacturing such an electronic device module.Type: GrantFiled: January 28, 2013Date of Patent: October 27, 2015Assignee: FREESCALE SEMICONDUCTOR INC.Inventor: Jinbang Tang
-
Patent number: 9152912Abstract: A smart card capable of independently displaying information is wirelessly connectable to an external interface. The smart card includes a main body, an antenna module, an electronic paper, a drive member and a radio frequency identification chip isolated from the drive member. The antenna module includes a first antenna for receiving first electromagnetic wave and a second antenna for receiving/transmitting second electromagnetic wave. The first and second antennas are respectively connected to the drive member and the radio frequency identification chip. The information can be independently displayed on the smart card to ensure confidence of the data. Moreover, the smart card can be more conveniently used.Type: GrantFiled: October 13, 2011Date of Patent: October 6, 2015Assignee: Asia Vital Components Co., Ltd.Inventor: Dasheng Lee
-
Patent number: 9147147Abstract: A portable data carrier with a card body in which an integrated circuit is embedded may include a token, a token holder, and one or more fixing portions. The token may comprise the integrated circuit. The token holder may include a first end and a second end, the first end configured to flexibly extend from the card body, and the second end configured to be releasably attached to the token, and a separation line along a length of the token holder between the token holder and the token, the separation line configured to allow the token to be detached from the token holder. The one or more fixing portions may be configured to releasably hold the token and the token holder to corresponding portions of the card body surrounding the token and the token holder.Type: GrantFiled: February 26, 2014Date of Patent: September 29, 2015Assignee: Giesecke & Devrient America, Inc.Inventors: Scott Marquardt, Michael Tagscherer
-
Patent number: 9136143Abstract: A multi-chip semiconductor device comprises a thermally enhanced structure, a first semiconductor chip, a second semiconductor chip, an encapsulation layer formed on top of the first semiconductor chip and the second semiconductor chip. The multi-chip semiconductor device further comprises a plurality of thermal vias formed in the encapsulation layer. The thermally enhanced structure comprises a heat sink block attached to a first semiconductor die. The heat sink block may further comprise a variety of thermal vias and thermal openings. By employing the thermal enhanced structure, the thermal performance of the multi-chip semiconductor device can be improved.Type: GrantFiled: June 17, 2013Date of Patent: September 15, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Chih-Hang Tung, Tung-Liang Shao
-
Patent number: 9136239Abstract: Methods and designs for increasing interconnect areas for interconnect bumps are disclosed. An interconnect bump may be formed on a substrate such that the interconnect bump extends beyond a contact pad onto a substrate. An interconnect bump may be formed on a larger contact pad, the bump having a large diameter.Type: GrantFiled: February 3, 2014Date of Patent: September 15, 2015Assignee: Micron Technology, Inc.Inventors: Terry Lee Sterrett, Richard J. Harries
-
Patent number: 9098761Abstract: A protection device is provided, which includes a detection circuit for detecting a short-circuit between at least two output branches of a magnetic reading head. Each of the output branches is able to convey a signal read by the reading head on a track of a magnetic card and the detection circuit is able to detect a short-circuit during the reading of at least one track of a magnetic card.Type: GrantFiled: August 30, 2011Date of Patent: August 4, 2015Assignee: INGENICO GROUPInventor: Jean-Jacques Delorme
-
Patent number: 9087230Abstract: The invention relates to a method of switching communication channels enabling a card reader to communicate with several card circuits, each circuit having a communication channel. The reader applies a power supply voltage to the card by electrical contacts arranged on a connection button. The reader transmits a control signal for controlling the switching of the communication channel to an electrical contact located in the inserted part of the card but not on the button. Finally, the reader sets up activation signals for at least one circuit to enable said circuit to communicate via the connection button. The invention also relates to a removable device and a receiver for reading said device.Type: GrantFiled: December 22, 2005Date of Patent: July 21, 2015Assignee: THOMSON LICENSINGInventors: Patrick Will, Olivier Horr, Philippe Launay
-
Patent number: 9075578Abstract: A transmission port module for expanding transmission capacity of a host module is disclosed. The host module includes a host casing and a host circuit board installed inside the host casing. The transmission port module includes a base casing, a transmission circuit board, at least one transmission port and an integrated connector. The base casing is installed onto the host casing in a detachable manner. The transmission circuit board is installed inside the base casing. The at least one transmission port is electrically connected to the transmission circuit board, and the integrated connector is electrically connected to the transmission circuit board. The integrated connector is electrically connected to the host circuit board when the base casing is installed onto the host casing, so as to establish connection between the host circuit board and the at least one transmission port.Type: GrantFiled: July 22, 2013Date of Patent: July 7, 2015Assignee: Aopen Inc.Inventor: Jo-Chiao Wang
-
Patent number: 9053406Abstract: Provided are an antenna circuit constituent body for an IC card/tag capable of reducing environmental load in a manufacturing process for joining both end portions of an antenna circuit pattern layer and capable of enhancing reliability of joined portions of the both end portions of the antenna circuit pattern layer: and a method for manufacturing the antenna circuit constituent body for an IC card/tag. In the antenna circuit constituent body for an IC card/tag, an insulating layer (107) is formed so as to extend from an upper part of a first circuit pattern layer part (103), via an upper part of a third circuit pattern layer part (101), and to an upper part of a second circuit pattern layer part (104). A conductive layer (108) is formed on the insulating layer (107) so as to bring the first circuit pattern layer part (103) and the second circuit pattern layer part (104) into conduction.Type: GrantFiled: June 6, 2011Date of Patent: June 9, 2015Assignee: TOYO ALUMINIUM KABUSHIKI KAISHAInventor: Hiroki Higashiyama
-
Patent number: 9053375Abstract: A contactless bi-directional device including first and second generally mutually electromagnetically decoupled contactless loop antennas which are arranged in at least partially mutually overlapping orientation, first and second contactless communication chips, each of the first and second communications chips being connected to a corresponding one of the generally mutually electromagnetically decoupled contactless loop antennas, thereby providing bi-directional communication.Type: GrantFiled: January 15, 2013Date of Patent: June 9, 2015Assignee: On Track Innovations Ltd.Inventors: Hemy Itay, Oded Bashan, Yaacov Haroosh
-
Patent number: 9006584Abstract: An electronic isolation device is formed on a monolithic substrate and includes a plurality of passive isolation components. The isolation components are formed in three metal levels. The first metal level is separated from the monolithic substrate by an inorganic PMD layer. The second metal level is separated from the first metal level by a layer of silicon dioxide. The third metal level is separated from the second metal level by at least 20 microns of polyimide or PBO. The isolation components include bondpads on the third metal level for connections to other devices. A dielectric layer is formed over the third metal level, exposing the bondpads. The isolation device contains no transistors.Type: GrantFiled: August 6, 2013Date of Patent: April 14, 2015Assignee: Texas Instruments IncorporatedInventors: Thomas Dyer Bonifield, Byron Williams, Shrinivasan Jaganathan, David Larkin, Dhaval Atul Saraiya
-
Patent number: 8994086Abstract: The invention provides a semiconductor device which is non-volatile, easily manufactured, and can be additionally written. A semiconductor device of the invention includes a plurality of transistors, a conductive layer which functions as a source wiring or a drain wiring of the transistors, and a memory element which overlaps one of the plurality of transistors, and a conductive layer which functions as an antenna. The memory element includes a first conductive layer, an organic compound layer and a phase change layer, and a second conductive layer stacked in this order. The conductive layer which functions as an antenna and a conductive layer which functions as a source wiring or a drain wiring of the plurality of transistors are provided on the same layer.Type: GrantFiled: October 14, 2010Date of Patent: March 31, 2015Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hiroko Abe, Yukie Nemoto, Ryoji Nomura, Mikio Yukawa
-
Patent number: 8969730Abstract: Printed circuits may be electrically and mechanically connected to each other using connections such as solder connections. A first printed circuit such as a rigid printed circuit board may have solder pads and other metal traces. A second printed circuit such as a flexible printed circuit may have openings. Solder connections may be formed in the openings to attach metal traces in the flexible printed circuit to the solder pads on the rigid printed circuit board. A ring of adhesive may surround the solder connections. The flexible printed circuit may be attached to the rigid printed circuit board using the ring of adhesive. An insulating tape may cover the solder connections. A conductive shielding layer with a conductive layer and a layer of conductive adhesive may overlap the solder joints. The conductive adhesive may connect the shielding layer to the metal traces on the rigid printed circuit board.Type: GrantFiled: August 16, 2012Date of Patent: March 3, 2015Assignee: Apple Inc.Inventors: Anthony S. Montevirgen, Emery A. Sanford, Stephen Brian Lynch