Abstract: A common carrier for forming multiple printheads thereon and method of forming thereof is described. The common carrier includes a carrier substrate for adhering a plurality of unprocessed, integrateable semiconductor chips. Once adhered, the carrier substrate is lithographically processed to form a plurality of integrated circuit (IC) printhead chips such that alignment of the IC chips on the carrier substrate has the precision of lithographic alignment tolerances which is well within printhead alignment requirements.

Abstract: The invention concerns an optical semiconductor housing comprising an optical semiconductor component (8) whereof one front surface includes an optical sensor (10) and encapsulating means delimiting a cavity wherein is arranged said optical component and comprising means for external electrical connection (11) of said optical semiconductor component, said encapsulating means comprising a glass allowing light through to said optical sensor. Said encapsulating means (2, 5) comprise electromagnetic shielding means (23, 24, 28) made of an electrically conductive material, capable of being externally connected, said shielding means being electrically insulated from the electrical connecting means of said optical component.

Abstract: A semiconductor device includes an electrically insulating board; conductive interconnections formed on a first face of the board and on a second face opposite to the first face; a semiconductor chip fixed to the board through at least the interconnections on the first face, said semiconductor chip having a semiconductor element electrically connected to the interconnections; a conductive bump formed on the second face of the board and electrically connected to the interconnections on the second face; and a first through-hole passing through the board to ventilate at least a part of the region between the board and the semiconductor chip.

Abstract: A microelectronic package with an integral window mounted in a recessed lip for housing a microelectronic device. The device can be a semiconductor chip, a CCD chip, a CMOS chip, a VCSEL chip, a laser diode, a MEMS device, or a IMEMS device. The package can be formed of a low temperature co-fired ceramic (LTCC) or high temperature cofired ceramic (HTCC) multilayered material, with the integral window being simultaneously joined (e.g. co-fired) to the package body during LTCC or HTCC processing. The microelectronic device can be flip-chip bonded and oriented so that a light-sensitive side is optically accessible through the window. The result is a compact, low profile package, having an integral window mounted in a recessed lip, that can be hermetically sealed.

Abstract: A COF tape carrier includes a resist formed on the COF tape carrier. The resist has portions that define a resist opening within the resist so that a semiconductor element is mounted on the COF tape carrier in alignment with the resist opening. The COF tape carrier also includes ridges and valleys formed within the resist opening, the ridges and valleys extending in directions oblique to a perimeter of the resist opening. Inner leads are provided in the resist opening and have portions that extend in a direction oblique to the perimeter. The semiconductor element may include a surface, and ridges and valleys. The surface has perimeters that define the surface. The ridges and valleys are formed on said surface, each of the ridges and valleys extending in directions oblique to the perimeters.

Abstract: An optoelectronic package includes a supporting structure with a surface, an opposed surface, and at least one side, at least one conductive interconnect extending through the supporting structure from the surface to the opposed surface of the supporting structure, wherein the at least one conductive interconnect is substantially flush with the opposed surface of the supporting structure.

Abstract: An optoelectronic semiconductor package device includes a semiconductor chip, an insulative housing and a conductive trace, wherein the chip includes an upper surface and a lower surface, the upper surface includes a light sensitive cell and a conductive pad, the insulative housing includes a first single-piece non-transparent insulative housing portion that contacts the lower surface and is spaced from the light sensitive cell and a second transparent insulative housing portion that contacts the first housing portion and the light sensitive cell, and the conductive trace extends outside the insulative housing and is electrically connected to the pad inside the insulative housing.

Abstract: A 2-metal layer TAB and a both-sided CSP.BGA tape having an insulating substrate and a wiring layer provided on at least both sides of the substrate, the substrate having evenly spaced sprocket holes on both width direction edges in the longitudinal direction thereof and also having through-holes formed with a punching press, and the through-holes being filled with a conductor by means of a punching press such that the conductor and the wiring layers are electrically connected, which is characterized by having round pilot holes between the sprocket holes formed in the longitudinal direction thereof; and a process of producing the same.

Abstract: A die carrier for holding a die, such as a microdisplay die, may be electrically connected to a substrate by pressing the substrate against flexible, resilient leads of the die carrier. The package includes a housing and a shroud mounted to the housing. The substrate is inserted through a slot in the shroud and, within the shroud, engages against the flexible, resilient leads, thereby establishing an electrical contact.

Abstract: A sensor chip comprises a layer-shaped base body, which has a plurality of fine holes formed in one surface, and fine metal particles, each of which is loaded in one of the fine holes of the base body. At least a part of each of the fine metal particles is exposed to a side of the layer-shaped base body, which side is more outward than the one surface of the layer-shaped base body. The layer-shaped base body may be constituted of anodic oxidation alumina. The sensor chip constitutes a sensor utilizing localized plasmon resonance, with which a state of binding of a sensing medium with a specific substance is capable of being detected quickly and with a high sensitivity.

Abstract: A manufacturing method of semiconductor devices, micromachines such as semiconductor device, narrow pitch connectors, electrostatic actuators or piezoelectric actuators, and ink jet heads, ink jet printers, liquid crystal panels, and electronic appliances, including them characterized in that short circuit due to dusts floating in the air will not take place. In a method where a silicon wafer (30) undergoes dicing to manufacture semiconductor devices (20), a groove (30a) covered by an insulating layer and spanning a dicing line is formed in the above described silicon wafer, and the silicon wafer undergoes dicing along the dicing line.

Abstract: In a process for producing a ceramic housing (1), first of all a ceramic base body (4) comprising a ceramic base (2) and side parts (3) is produced. Then, a metal frame (7) is placed onto the ceramic base body (4) and a window (11) is soldered onto a side opening (6). After a photoactive semiconductor chip has been introduced into the ceramic base body (4), the ceramic housing (1) is closed off using a metal cover (12).

Abstract: A unit cell is disclosed that facilitates the creation of a layout of at least a portion of a microelectromechanical system. The unit cell includes a plurality of electrical traces. Some of these electrical traces pass through the unit cell. Other electrical traces extend only part way through the unit cell. At least certain boundary conditions exist for the unit cell that allow the same to be tiled in a row and in a manner that results in adjacently disposed unit cells in the row being electrically interconnected in the desired manner.

Abstract: A semiconductor device, in which the air within a gel resin can be efficiently and well purged, comprising a casing, a semiconductor device electrically connected by bonding wires and a gel resin filled in the casing and serves for insulation covering of the semiconductor device and the bonding wire. The device further comprises a board-shaped vibration damper in contact with the gel resin and is provided with a plurality of perforations each having an air inlet and an air outlet for the purpose of air extraction during the filling of the gel resin. The sectional area of the perforations is tapered and larger at the inlet than at the outlet, thus causing the perforations to have the form of a substantially conical trapezoid as a whole.

Abstract: A chip package for semiconductor chips is provided by the method of forming a chip package includes the steps of forming a printed circuit board with a window therethrough; forming semiconductor chip connections of one or more primary chips which overlie the window to the printed circuit board by solder connections, locating a suspended semiconductor chip within the window, and connecting the suspended semiconductor chip to one or more primary chips overlying the window in a chip-on-chip connection. A bypass capacitor is formed on the printed circuit board.

Abstract: Semiconductor dies are bonded to contact pads formed in a substrate's cavity. Vias through the substrate open into the cavity. Conductive lines passing through the vias connect the contact pads in the cavity to contact pads on another side of the substrate. A passage in the substrate opens into the cavity and provides an escape or pressure relief path for material filling the cavity. The passage can also be used to introduce material into the cavity.

Abstract: An optical package structure (2) includes a cover (21) with a lens part (22), and a base member (23) which combines with the cover to define a closed space in which to package optical components. The base member has a bottom panel (232) and a substrate (234). A plurality of solder pads (231, 237) is provided on a top and bottom surfaces (2321, 2342) of the bottom panel and of the substrate. The solder pads on the top surface electrically connect with the optical components. A plurality of inner conductive traces (236, 238) is provided through the bottom panel and the substrate which electrically connect the solder pads on the top surface of the bottom panel with corresponding solder pads on the bottom surface of the substrate via printed circuits (235) on the substrate. Thus, an external electrical connection of the optical components is attained without wires and electrical pins.

Abstract: An electronic device is described which comprises a functional element chip having a photofunctional element formed thereon, a wiring member electrically connected to a terminal of the functional element chip, and an encapsulant for fixing the functional element chip and the wiring member, wherein a light blocking member with an opening portion is provided on a front face side of the wiring member, and wherein an end of the opening portion is located more inside than an inner end of the wiring member.

Abstract: In a semiconductor memory device, a printed circuit board connects a memory chip to an external circuit. The printed circuit board includes a multiplicity of pads arranged in a column. These pads connect the board to the memory chip. The board also includes a multiplicity of data terminals arranged in at least two columns and connected to the pads by data connections. The data connections are configured such that each data connection has essentially the same electrical properties as any other data connection.

Abstract: The package for mounting a solid state image sensor is a box-type resin package having in its bottom surface an opening for allowing light to pass so that a solid state image sensor may be mounted face down there. In the package, a three-dimensional circuit is formed which has a lead comprising a conductive metal plate making electrical conductance possible. The top surface of the inner lead of the lead is exposed on the inside bottom surface in the vicinity of the opening, and the top surface of the outer lead and the edge of the lead, following a bent section of the lead, are exposed on the side wall top surface of and the top edges of the side wall side surface of the aforesaid box-type resin package, respectively, with all the parts of the lead other than the exposed parts of both ends being embedded in the resin. Because of this, a small, thin package for mounting a solid state image sensor can be manufactured at low cost by using a simple process.

Abstract: A semiconductor memory card is disclosed which achieves augmentation in design property, promotion of understanding and augmentation in identification facility of the type thereof. A memory card housing is entirely or partially transparent or translucent so that a circuit board, a memory chip and so forth in the inside thereof can be visually observed from the outside therethrough. Or, the card housing is partially opaque or is colored at the transparent or translucent portion thereof. Or else, the card housings of different types of memory cards are formed as different ones of transparent, translucent and opaque housings from each other.

Abstract: A wiring substrate includes (1) an insulating substrate having an opening, or a core substrate and a build-up layer wherein at least one of the core substrate and the build-up layer has an opening, (2) at least one electronic part disposed in the opening, and (3) an embedding resin comprising a thermoplastic resin, an acid anhydride curing agent, a curing accelerator, and a filler, wherein the embedding resin shows a viscosity of not higher than 85 Pa·s in a shear rate of 8.4 s−1 after allowing to stand for 24 hours at 25° C.±1° C.

Abstract: An image sensor of a quad flat non-leaded package (QFN). The image sensor of a quad flat non-leaded package includes a lead frame having a plurality of leads and a die pad, and the leads are located around a periphery of the die pad. A molding structure is formed around an outer boundary of the leads and located on a first surface of the lead frame. A plurality of bonding pads is formed on the active surface of a chip. A plurality of wires is utilized to electrically connect the bonding pads respectively to bonding portions of the leads on a first surface of the lead frame. A liquid compound is filled in between the chip and the molding structure and covering portions of the leads. A transmittance lid is allocated over the active surface, sealing the space between the molding structure and the lead frame.

Abstract: A method and apparatus of hermetically passivating a semiconductor device includes sealing a lid directly onto a semiconductor substrate. An active device is formed on the surface of the substrate and is surrounded by a substantially planar lid sealing region, which in turn is surrounded by bonding pads. A first layer of solderable material is formed on the lid sealing region. A lid is provided which has a second layer of solderable material in a configuration corresponding to the first layer. A solder is provided between the first layer and second layer of solderable materials. In the preferred embodiment, the solder is formed over the second layer. Heat is provided to hermetically join the lid to the semiconductor device without requiring a conventional package. Preferably the first and second layers are sandwiches of conventionally known solderable materials which can be processed using conventional semiconductor techniques.

Abstract: A semiconductor element provided in a semiconductor device includes a built-in contact-type sensor having a sensor area formed on a circuit formation surface. Connection terminals are provided in an area other than the sensor area. A wiring board is connected to the connection terminals of the semiconductor element so that an end surface of the wiring board is positioned on the circuit formation surface. A protective resin part covers a part extending from the end surface of the wiring board to the circuit formation surface so as to protect a connection portion between the semiconductor element and the wiring board.

Abstract: A method and structures for vertically interconnecting a plurality of chips to provide increased volume circuit density for a given surface chip footprint. One aspect is a stack of two chips with a preformed interconnecting support connecting the two chips and with space for mounting a third chip to at least one of the other two chips in an interstitial space between the two chips and inside the support. Another aspect is a chip stack where two smaller chips are interconnected a larger third chip on both sides thereof and further with interconnecting structures extending beyond the extent of either of the two chips as attached to the third chip. Yet another aspect is a chip stack of at least two chips interconnected to each other with a smaller third chip positioned therebetween and interconnected with at least one of the larger two chips.

Abstract: Signal communication structures and methods for making the same are provided. One embodiment of the present invention comprises a signal communication structure. The structure comprises a signal communication element having a signal communication surface, an integrated circuit chip, and a substrate. A surface of the signal communication element other than the signal communication surface is physically coupled to a surface of the integrated circuit chip. In addition, another surface of the integrated circuit chip is communicatively coupled to the substrate. Furthermore, the size of the signal communication surface is greater than the size of the surface of the integrated circuit chip to which the signal communication element is physically coupled.

Abstract: A multilayered substrate for a semiconductor device, which has a multilayered substrate body formed of a plurality sets of a conductor layer and an insulation layer, and having a face for mounting a semiconductor element thereon and another face for external connection terminals, the face for mounting a semiconductor device being provided with pads through which the substrate is connected to a semiconductor element to be mounted thereon, and the face for external connection terminals being provided with pads through which the substrate is connected to an external electrical circuit, wherein a reinforcing sheet is respectively joined to the face for mounting a semiconductor element thereon and the face for external connection terminals of the multilayered substrate body.

Abstract: A method for manufacturing a cover assembly including a transparent window portion and a frame of gas-impervious material that can be hermetically attached to a micro-device package base to form a hermetically sealed micro-device package. First, a frame of gas-impervious material is provided, the frame having a continuous sidewall defining a frame aperture there through. The sidewall includes a frame seal-ring area circumscribing the frame aperture. A sheet of a transparent material is also provided, the sheet having a window portion defined thereupon. The window portion has finished top and bottom surfaces. A sheet seal-ring area is prepared on the sheet, the sheet seal-ring area circumscribing the window portion. The frame is positioned against the sheet such that at least a portion of the frame seal-ring area and at least a portion of the sheet seal-ring area contact one another along a continuous junction region that circumscribes the window portion.

Abstract: Light emitting die package is disclosed. The die package includes a leadframe, a bottom heatsink, a top heatsink, a reflector and a lens. The top and bottom heatsinks are thermally coupled but electrically insulated from the leadframe. The leadframe includes a plurality of leads and defines a mounting pad for mounting LEDS. The top heatsink defines an opening over the mounting pad. The reflector is coupled to the top heatsink at the opening. The lens is placed over the opening defining an enclosed cavity over the mounting pad. At least one light emitting device (LED) is mounted on the mounting pad within the cavity. Encapsulant optically couples the LED to its surrounding surfaces to maximize its optical performance. When energized, the LED generates light and heat. The light is reflected by the reflector and operated on by the lens. The heat is dissipated by the top and the bottom heatsinks.

Abstract: A semiconductor chip module and forming method is provided. The module includes a support member having at least one well being open to receive a semiconductor chip. Each well depth is substantially equal to the thickness of a chip. The support member has a planar region surrounding each well. A chip is in each well. A dielectric sheet of material is laminated over each chip and extends onto the planar area surrounding the wells and has a face oriented away from the chip. Electrical circuitry including capture pads is formed on the face of the dielectric sheet and extends onto the sheet that overlies the planar region. Conducting vias are formed in the dielectric sheet connecting the electrical circuitry on the dielectric sheet with the contact pads on the chip. A multilayer, circuitized laminate having a fan-out pattern is laminated to the dielectric sheet.

Abstract: In an integrated circuit assembly, know good die (KGD) are assembled on a substrate. Interconnect elements electrically connect pads on a die attached to the substrate to traces or other electrical conductors on the substrate or to pads on another die attached to the substrate. The substrate may have one or more openings, exposing pads of the die. The assembly may comprise one or more dice.

Abstract: A focal plane plate for a high-resolution camera with light-sensitive semiconductor sensors, includes an electrically nonconductive material for accommodating housed light-sensitive semiconductor sensors. Adjustment elements are arranged on the focal plane plate at arrangement locations of the housings of the light-sensitive semiconductor sensors, or the focal plane plate is designed with the adjustment elements. The adjustment elements are capable of being adapted in a complementary fashion to the form of the housings in the top sides of the light-sensitive semiconductor sensors lying in a common plane.

Abstract: A leadframe includes at least one peripheral lead secured to a paddle. A paddle solder bump pad and a peripheral solder bump pad are respectively situated on the at least one peripheral lead and the paddle. A first recess is adjacent to the paddle solder bump pad and a second recess is adjacent to the peripheral solder bump pad. A semiconductor die having at least first and second solder bumps is situated on the leadframe such that the first solder bump is soldered to the paddle solder bump pad while the second solder bump is soldered to the peripheral solder bump pad. The first and second recesses adjacent to respectively the paddle solder bump pad and the peripheral solder bump pad prevent solder from flowing out of the solder bump pad areas during solder reflow process. In this manner, the potential shorting of adjacent solder bump pads is prevented.

Abstract: A semiconductor device package interposer including a receptacle extending substantially therethrough. Methods for assembling the interposer with one or more semiconductor devices are also disclosed. A film may be secured to a bottom surface of the interposer so as to at least partially cover a bottom end of the receptacle. One or more semiconductor devices are positioned within the receptacle, on the film. Each semiconductor device within the receptacle may then be electrically connected to the interposer. An encapsulant material, which is introduced into the receptacle, extends at least between portions of the outer periphery of each semiconductor device within the receptacle and a peripheral edge of the receptacle. Upon curing, setting, or hardening, the encapsulant material retains each semiconductor device within the receptacle and maintains a lateral position of each semiconductor device with respect to the interposer. Semiconductor device packages and multi-chip modules are also disclosed.

Abstract: A semiconductor element, such as a pressure sensor, having an upper surface, so that a part of the upper surface is exposed to the outside, while this element is in use. The element is sealed with a sealing resin. The sealing resin has a second, upper surface and a recess, so that said part of the first, upper surface of the semiconductor element is exposed outside at the bottom of said recess which is opened at the second, upper second surface. A releasable protective member has a shape corresponding to the recess and is placed in the recess, so that, when said protective member is in the recess, a bottom surface thereof is in contact with the part of the first, upper face of the protective member and the upper face of the resin coincides with the second surface of the sealing resin.

Abstract: An optical device package having improved conductor efficiency, optical coupling and thermal transfer, as well as various methods for packaging a semiconductor die provide reduced connection length, and improved optical and thermal characteristics. In one package, a conductive circuit pattern disposed on a transparent or translucent cover connects bond pads on the light receiving surface of the semiconductor die to external electrical contacts. The construction of the package reduces connection length and eliminates the air gap between the glass and the die. In another package, a substrate having a protruding wall supports the glass and the substrate provides an electrical connection to terminals for connection to an external device. In another package, the glass is supported by a die mounting board that supports the semiconductor die and includes leads for connection to an external device.

Abstract: A micromechanical switch includes a substrate, at least one pair of support members fixed to the substrate, and at least one pair of beam members placed in proximity and parallel to each other above the substrate, and connected to one of the support members, respectively, each of the beam members having a moving portion which is movable with a gap with respect to the substrate. A contact portion is provided on the moving portion, and a driving electrode is placed on the substrate between the pair of beam members to attract the moving portions of the beam members in a direction in a plane substantially parallel to the substrate with an electrostatic force so that the contact portions of the bean members which are opposed to each other are short-circuited.

Abstract: A microelectronic substrate including at least one microelectronic die disposed within an opening in a microelectronic substrate core, wherein an encapsulation material is disposed within portions of the opening not occupied by the microelectronic dice, or a plurality microelectronic dice encapsulated without the microelectronic substrate core. Interconnection layers of dielectric materials and conductive traces are then fabricated on the microelectronic die, the encapsulation material, and the microelectronic substrate core (if present) to form the microelectronic substrate.

Abstract: A method and system for universal packaging in conjunction with an automated in-line back-end IC manufacturing process. In one method embodiment, the present invention processes a die-strip through a number of integrated in-line processes that function independently of the die size of the die-strip. A control computer maintains a die-strip map database recording the die size of the die-strip. In-line molding and solder ball attachment processes are then performed and function independently of the die size of the die-strip. Processes that are independent of die size provide a universal packaging manufacturing solution. The present invention then accesses the database to determine the die size for cutting the die-strip based on specifications maintained by the electronic die-strip map database. Sorting, testing and finish assembly processes are then performed.

Abstract: An optical chip having an optical section and an electrode is formed above a substrate. The optical chip is surrounded by a body. The optical section is sealed by a first seal section. An electrical connection portion between the electrode of the optical chip and an interconnecting line of the substrate is sealed by a second seal section.

Abstract: The invention relates to a packaging for a semiconductor chip. A frame that directly surrounds the slot is provide on the carrier board on the side of the nubbins. Said frame is provided with the same height as the nubbins and the slot and the frame surrounding said slot are at least partially filled with a casting compound which is preferably adapted to the thermal expansion coefficients of the semiconductor chip.

Abstract: A semiconductor device includes two semiconductor chips that are interposed between a pair of radiation members, and thermally and electrically connected to the radiation members. One of the radiation members has two protruding portions and front ends of the protruding portions are connected to principal electrodes of the semiconductor chips. The radiation members are made of a metallic material containing Cu or Al as a main component. The semiconductor chips and the radiation members are sealed with resin with externally exposed radiation surfaces.

Abstract: A strengthened window-type semiconductor package is provided. A substrate having an opening is mounted with at least a chip in a manner that, an active surface of the chip covers and partly exposed to the opening, and electrically connected to the substrate by bonding wires formed through the opening. An elastic non-conductive material is applied over the chip exclusive of the active surface. An upper encapsulant is formed to encapsulate the chip and the non-conductive material, and a lower encapsulant is formed to encapsulate the bonding wires and seal the opening. With provision of the non-conductive material for encapsulating the chip before forming the upper encapsulant, the chip can be prevented from cracking particularly at corner and edge positions that encounter relatively greater thermal stress during subsequent fabrication processes such as curing of the upper encapsulant and thermal cycles.

Abstract: An electronic package, such as a ball grid array (“BGA”) package, includes a high speed signal trace formed at a conductive layer and a corresponding reference plane formed at another conductive layer. The reference plane includes a cutout region formed therein; the cutout region is positioned over the signal solder ball to which the high speed signal trace is coupled. The lateral center point of the cutout region is offset relative to the lateral center point of the signal solder ball. The offset configuration reduces the capacitance between the signal solder ball and the reference plane and improves the high frequency transmission characteristics of the electronic package.

Abstract: A package for a printed circuit and a method for packaging a circuit including exposed components placed on a printed circuit, the circuit including microwave components. At least part of the circuit that contains microwave components is covered with a layer of syntactic foam including a matrix of epoxy resin or cyanate ester, filled with microballoons of glass or a ceramic material. Subsequently, the entire circuit is covered with a moisture-proof top layer.

Abstract: A stacked chip package has a substrate with a through hole. A first chip is received in the through hole. A second chip is disposed on the first chip. Two chips are electrically connected to an upper surface of the substrate. An adhesive layer and a planar member, which are thermally and electrically conductive, are disposed on a lower surface of the substrate to support the chips and dissipate the heat generated by the chips. An encapsulant covers the upper surface of the substrate. The package has superior heat-dissipating ability, high yield in assembly and small size.

Abstract: A semiconductor package and fabricating method are described, in which solder balls can be easily arrayed in a fan-out type arrangement and the package fabricating process is simplified. The semiconductor package includes a unit semiconductor chip and a first stress buffer layer contacting the unit semiconductor chip on two sides of the unit semiconductor chip. Bonding pads are separately arrayed on an upper part the unit semiconductor chip, and a second stress buffer layer formed on the first stress buffer layer and on the unit semiconductor chip, but not on an upper surface of each bonding pad. A plurality of conducting lines are formed on the second stress buffer layer, each conducting line contacting the upper surface of a respective bonding pad. A solder mask layer, which having a plurality of holes therein to expose at least one region of each conducting line, is formed over the conducting lines and the second stress buffer layer.

Abstract: A flip-chip-bonded optical module package using flip chip bonding is provided. The flip-chip-bonded optical module package includes an optical device chip which has an input/output pad formed on a substrate, an under bump metal layer fanned on the input/output pad, and a solder bump formed on the under bump metal layer to transmit an electric signal to the outside. The flip-chip-bonded optical module package includes a silicon wafer through which a through hole is formed, on which an under ball metal layer is formed, and to which the optical device chip is flip-chip-banded. The flip-chip-banded optical module package includes a solder ball which is fanned on the under ball metal layer and transmits an electrical signal from the solder bump to the outside, and an optical fiber which is inserted into the through hole and is optically coupled with the optical device chip.

Abstract: A multi-chip module (MCM) and method of manufacturing is disclosed that provides for attachment of semiconductor dice to both sides of the MCM printed circuit board (PCB). Semiconductor dice attached to the top surface of the PCB may be attached by conventional wire bonding, TAB or flip chip methods whereas those semiconductor dice attached to the bottom surface of the PCB are wire bonded or TAB connected to the top surface through openings in the PCB. The openings provide a lead-over-chip (LOC) arrangement for those semiconductor dice attached to the bottom surface resulting in shortened wire bonds. The bottom surface of the PCB may be provided with die recesses into which the openings extend, to receive the dice and bring their active surfaces even closer to the top surface of the PCB for wire bonding.