With Window Means Patents (Class 257/680)
  • Publication number: 20080135999
    Abstract: The present invention relates to a package device including a first substrate, a plurality of first chips positioned on the first substrate, a second substrate positioned on the first substrate, a second chip positioned on the second substrate, an adhesive layer positioned on the second chip, and a heat spreader positioned above the first substrate, the first chips, the second substrate, and the adhesive layer, wherein the heat spreader has a plurality of openings for cold air to flow into the package device and generate convection with hot air inside the package device in order to cool down the package device.
    Type: Application
    Filed: May 17, 2007
    Publication date: June 12, 2008
    Inventor: Wu-Der Yang
  • Publication number: 20080122056
    Abstract: Provided is a semiconductor device package comprising a printed circuit board, the printed circuit board including a window at a central portion and a connection part, a semiconductor chip including center-type bonding pads, wherein the semiconductor chip is mounted on an upper surface of the printed circuit board such that the center-type bonding pads are exposed by the window, bonding wires electrically connecting the center-type bonding pads with the printed circuit board through the window, a lower molding material at a lower surface of the printed circuit board, the lower molding material encapsulating the center-type bonding pads and the bonding wires, and an upper molding material encapsulating the semiconductor chip and the upper surface of the printed circuit board, wherein the lower molding material and the upper molding material are connected to each other through the connection part of the printed circuit board.
    Type: Application
    Filed: November 9, 2007
    Publication date: May 29, 2008
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Shle-Ge Lee, Dong-Kil Shin, Min-Young Son
  • Publication number: 20080122055
    Abstract: A method for fabricating semiconductor components with lens structures and lens support structures includes the steps of providing semiconductor substrates on a substrate, attaching a carrier to the substrate configured to support the substrate during various processes, thinning the carrier to form lens support structures having desired geometrical characteristics, singulating the substrate and the carrier such that each semiconductor substrate includes a lens support structure, and then attaching the lens structures to the support structures. Each semiconductor component includes a thinned semiconductor substrate, a support structure attached to the semiconductor substrate, and a lens structure attached to the support structure. A system for fabricating the semiconductor components includes the substrate containing the semiconductor substrates, and the carrier configured to support the wafer, to protect the semiconductor substrates and to provide the lens support structures.
    Type: Application
    Filed: November 28, 2006
    Publication date: May 29, 2008
    Applicant: MICRON TECHNOLOGY INC.
    Inventor: Andrew E. Perkins
  • Patent number: 7378748
    Abstract: A solid-state imaging device comprises a housing in which a base and ribs forming a rectangular frame are formed in one piece by a resin; a plurality of metal lead pieces embedded in the housing, each of which has an internal terminal portion facing an internal space of the housing and an external terminal portion exposed at an outer portion of the housing; an imaging element arranged on the base in the internal space of the housing; connecting members connecting electrodes of the imaging element to the internal terminal portions of the metal lead pieces; and a transparent plate fastened to an upper face of the ribs. The upper face of the ribs is provided with a lower step portion that is lowered along an external periphery, and the transparent plate is fastened to the upper face of the ribs by an adhesive filled at least into the lower step portion.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: May 27, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Katsutoshi Shimizu, Masanori Minamio, Kouichi Yamauchi
  • Publication number: 20080116554
    Abstract: A method for applying anti-stiction material to a micro device includes encapsulating a micro device in a chamber, vaporizing anti-stiction material in a container to form vaporized anti-stiction material, transferring the vaporized anti-stiction material from the container to the chamber, and depositing the vaporized anti-stiction material on a surface of the micro device.
    Type: Application
    Filed: November 21, 2006
    Publication date: May 22, 2008
    Applicant: SPATIAL PHOTONICS, INC.
    Inventor: Shaoher X. Pan
  • Patent number: 7372122
    Abstract: The present invention relates to an image sensor chip package and a method for fabricating the same. In one embodiment of an image sensor chip package, chip pads on a first surface of an image sensor chip are attached to electrode pads of a glass substrate with conductive material. In addition, electrode pads are connected to solder balls via a metal wiring pattern arranged on a second surface of the image sensor chip. As a result, the present invention can provide further miniaturized and thinned image sensor chip packages, reduce fabricating processes, and improve device performance and reliability.
    Type: Grant
    Filed: September 30, 2005
    Date of Patent: May 13, 2008
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Byoung Young Kang
  • Patent number: 7367120
    Abstract: A method of manufacturing a solid-state imaging device. An end portion on the aperture side of each of the plurality of wirings forms an internal terminal portion and an end portion on the outer peripheral side of each of the plurality of wirings forms an external terminal portion, the internal terminal portion of the wiring being connected electrically with an electrode of the imaging element. The wirings are made of thin metal plate leads, the base is made up of a resin molded member in which the thin metal plate leads are embedded, and at least a part of a side edge face of the thin metal plate leads is embedded in the base. The rigidity of the base is enhanced by the thin metal plate leads, thus reducing a curl and a warp of the base.
    Type: Grant
    Filed: November 14, 2006
    Date of Patent: May 6, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masanori Minamio, Mutsuo Tsuji, Kouichi Yamauchi
  • Patent number: 7368695
    Abstract: An image sensor package is disclosed that reduces the overall size of known image sensor packages. The image sensor package includes an image sensor and image sensor controller that are arranged on a substrate so that the surfaces of the image sensor and image sensor controller are directly adjacent one another. A package in accordance with the present invention reduces the amount of space in the package by allowing at least one surface of the image sensor controller and at least one surface of the image sensor to be directly attached or connected to one another. Electrical conductive material in the nature of anisotropic conductive materials is also preferably applied to the substrate in the form of an adhesive layer to allow for the image sensor controller and the image sensor to be in electrical communication with one another.
    Type: Grant
    Filed: May 3, 2005
    Date of Patent: May 6, 2008
    Assignee: Tessera, Inc.
    Inventors: Teck-Gyu Kang, Michael Estrella, Jae M. Park, Kenneth Robert Thompson, Craig S. Mitchell, Belgacem Haba
  • Patent number: 7368795
    Abstract: An image sensor module includes a flexible printed circuit board having an upper surface, which is formed with electric circuits and a lower surface. A passive component is arranged on the upper surface of the circuit board. A substrate has a first surface, a second surface and a penetrated hole. The second surface of the substrate is mounted on the upper surface of the circuit board so that the passive component is located within the penetrated hole. A chip is mounted on the first surface of the substrate, and is located onto the penetrated hole. Wires are electrically connected to the chip and the substrate. A lens holder is mounted on the first surface of the substrate and formed with an internal thread. A lens barrel is formed with an external thread screwed on the internal thread and is formed with an opening, an aspheric lens and an infrared filter.
    Type: Grant
    Filed: December 22, 2005
    Date of Patent: May 6, 2008
    Assignee: Kingpak Technology Inc.
    Inventor: Chung Hsien Hsin
  • Patent number: 7368758
    Abstract: A method is provided for producing a housing body for optoelectronic components that are reliable and inexpensive. The method creates a hermetic joint between a metal sleeve and a glass pane by joining together a housing element and a preferably metallic housing arrangement. The housing element and the housing arrangement are brought into contact with a glass solder, before the housing element and housing arrangement are joined. The glass solder is applied as a shapeable material, in particular as a paste. The glass solder is pre-vitrified and has its shape fixed by energy being introduced at least once, in particular as a result of organic constituents being burnt off. After the housing element has been inserted into the housing arrangement, a joint that is hermetic at least in regions, is produced between the glass pane and housing arrangement.
    Type: Grant
    Filed: April 9, 2003
    Date of Patent: May 6, 2008
    Assignee: Schott AG
    Inventors: Dietrich Mund, Bernd Hammer, Robert Hettler, Klaus Schachtelbauer, Edeltraud Sausenthaler, Markus Maier
  • Publication number: 20080093721
    Abstract: A chip package for an image sensor includes a first semiconductor chip having a first surface where a photographing device and a first circuit pattern are formed and a second surface that is opposite to the first surface where a second circuit pattern is formed. The first and second circuit patterns are electrically connected. The chip package further includes a second semiconductor chip attached to a second circuit pattern on the second surface of the first semiconductor chip. A printed circuit board faces the second surface of the first semiconductor chip and transfers an electric signal between the first and second semiconductor chips and externally. A housing accommodates the first and second semiconductor chips. The housing allows light to pass through to the photographing device.
    Type: Application
    Filed: October 2, 2007
    Publication date: April 24, 2008
    Applicant: Samsung Techwin Co., Ltd.
    Inventors: Byoung-young Kang, San-deok Hwang
  • Patent number: 7358602
    Abstract: A semiconductor chip includes: a semiconductor substrate; a penetrating electrode which is formed through the semiconductor substrate from a first surface to a second surface of the semiconductor substrate and has a projection which projects from the second surface; an insulating layer formed over an entire surface of the second surface. The insulating layer includes a first insulating section formed in a region around the projection and a second insulating section other than the first insulating section. The second insulating section is formed to be thinner than a thickest area of the first insulating section.
    Type: Grant
    Filed: January 14, 2004
    Date of Patent: April 15, 2008
    Assignee: Seiko Epson Corporation
    Inventor: Kazumi Hara
  • Publication number: 20080083974
    Abstract: A light-emitting device comprises: a coupling base, at least one light-emitting chip, a layer of glue, and a lens, wherein the coupling base is designed for coupling with at least one light-emitting chip. The light-emitting chip is electrically connected with a plurality of frames mounted inside the coupling base. The lens has a convex bottom. The glue is filled into the coupling base, and the lens is located on the glue, which is not yet dry. As a result, no bubble is formed on the contact junction between the lens and the glue after the glue is dry. Accordingly, the problems including poor refraction and poor transparency caused by the bubbles can be improved effectively.
    Type: Application
    Filed: October 6, 2006
    Publication date: April 10, 2008
    Inventor: Yuan-Cheng Chin
  • Publication number: 20080079130
    Abstract: An integrated circuit package system that includes: providing an electrical interconnect system including a first lead-finger system and a second lead-finger system; connecting a first device to the first lead-finger system with a wire bond; stacking a second device over the first device; and connecting the second device to the second lead-finger system with a bump bond.
    Type: Application
    Filed: September 28, 2006
    Publication date: April 3, 2008
    Applicant: STATS CHIPPAC LTD.
    Inventors: Jong-Woo Ha, BumJoon Hong
  • Patent number: 7348604
    Abstract: The light-emitting module according to the present invention comprises a heat dissipation element, a substrate for example a metal core printed circuit board (MCPCB), or FR4 board which is coupled to one or more light-emitting elements and provides a means for operative connection of the light-emitting elements to a source of power. The substrate is positioned such that it is thermally coupled to the heat dissipation element. The light-emitting module further comprises a housing element which matingly connects with the heat dissipation element, wherein the housing element may further comprise an optical element integrated therein for manipulation of the light generated by the one or more light-emitting elements.
    Type: Grant
    Filed: May 19, 2006
    Date of Patent: March 25, 2008
    Assignee: TIR Technology LP
    Inventor: George E. Matheson
  • Patent number: 7348241
    Abstract: Provided are a cell structure of an EPROM device and a method for fabricating the same. The cell structure includes a gate stack, which includes a first floating gate, an insulating pattern including a nitride layer, and a control gate that are sequentially stacked on a semiconductor substrate, and includes a window for exposing the top surface or both sidewalls of the first floating gate on both sides of the control gate, so that charges of the first floating gate can be erased by ultraviolet rays. The cell structure further includes a floating gate transistor, which includes a gate insulating layer formed on the semiconductor substrate, a second floating gate that is formed on the gate insulating layer and is connected to the first floating gate in the gate stack, and a source/drain that is formed in the semiconductor substrate so as to be aligned to the second floating gate. In the cell structure, the window is formed on the top surface or both sidewalls of the first floating gate of the gate stack.
    Type: Grant
    Filed: March 20, 2006
    Date of Patent: March 25, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joon-hyung Lee, Byung-sun Kim, Tae-jung Lee
  • Publication number: 20080067653
    Abstract: It is an object to reduce a thickness of a semiconductor component (chip) on a substrate to a predetermined thickness regardless of a variation in thickness of a substrate in a semiconductor product. In a semiconductor product mounted on a base plate, a surface of a semiconductor component on a substrate is set to be located at a predetermined height h from a surface of a base plate. Thereafter, through machining the surface of the semiconductor component which is adjusted to be located at the predetermined height, it is possible to make the thickness of the semiconductor component on the substrate equal to a predetermined thickness.
    Type: Application
    Filed: September 18, 2007
    Publication date: March 20, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Toshihiko Nishio, Yasumitsu Orii, Yukifumi Oyama
  • Publication number: 20080067654
    Abstract: An electronic component package includes, a die pad on which an electronic component is mounted, a radiation plate disposed to be connected to part of the die pad and bent downward, a plurality of leads disposed side by side on a periphery of the die pad, each lead composed of an inner lead disposed on the die pad side and an outer lead connected to the inner lead and bent downward, and a resin portion composed of a lower resin portion formed under the die pad and the inner lead, and a frame-like resin portion formed in a ring shape to stand up on the lower resin portion so that a connection part of the inner lead and an upper surface of the die pad can be exposed, wherein the die pad, the radiation plate and the leads are supported by the resin portion and integrated with each other.
    Type: Application
    Filed: September 11, 2007
    Publication date: March 20, 2008
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Kenichi Sakaguchi
  • Patent number: 7342263
    Abstract: A circuit device is provided which can be manufactured at reduced costs and which is highly reliable. The circuit device includes a Sensor area formed on part of a semiconductor substrate, a circuit area formed around the sensor area on the semiconductor substrate to process electric signals produced at the sensor area, and a sealring disposed between the sensor area and the circuit area. The sealring is disposed between the outer periphery of the sensor area and the inner periphery of the circuit area to surround the sensor area. In the circuit device, the sealring prevents water or moisture from infiltrating from the sensor area into the circuit area.
    Type: Grant
    Filed: March 14, 2005
    Date of Patent: March 11, 2008
    Assignee: Sanyo Electric Co., Ltd.
    Inventor: Naoteru Matubara
  • Patent number: 7323720
    Abstract: A light-emitting device includes a substrate having a plurality of light-emitting elements and a light emission region arranged on one surface thereof, light being emitted from one surface of the light emission region; and an integrated circuit chip that generates signals for controlling the plurality of light-emitting elements. The integrated circuit chip is connected to the substrate so as to overlap a portion of or the entire light emission region, as viewed from the other surface of the substrate.
    Type: Grant
    Filed: February 6, 2006
    Date of Patent: January 29, 2008
    Assignee: Seiko Epson Corporation
    Inventors: Takehiko Kubota, Shinsuke Fujikawa
  • Patent number: 7323777
    Abstract: A semiconductor substrate has an integrated circuit, an interconnect electrically connected to the inside of the semiconductor substrate, and an electrode formed on the interconnect. A plurality of resin layers are separately formed on the semiconductor substrate so that part of the semiconductor substrate is exposed. A redistribution interconnect is electrically connected to the electrode. An external terminal is formed on the redistribution interconnect and supported by the resin layers.
    Type: Grant
    Filed: April 26, 2005
    Date of Patent: January 29, 2008
    Assignee: Seiko Epson Corporation
    Inventor: Koji Yamaguchi
  • Publication number: 20080017964
    Abstract: A method and apparatus with a first substrate made of an inorganic material having at least one signal trace and a second substrate made of an organic material having at least one signal trace, at least one interconnect and at least one reception cavity. The first and second substrates are mechanically joined and the at least one signal trace of the first substrate is electrically connected to the at least one signal trace of the second substrate. The first substrate overlays the reception cavity.
    Type: Application
    Filed: July 20, 2006
    Publication date: January 24, 2008
    Inventors: Donald E. Schott, Peter J. Martinez
  • Publication number: 20080012109
    Abstract: The invention relates to a method for producing package parts for optical or optoelectronic components. To this end a metal package element is bonded to a transparent package element by means of a glass solder ring, the glass solder being brought in contact with the metal package element and the transparent package element, and the metal package element being inductively heated by an alternating electromagnetic field generated by an induction coil, so that the glass solder is heated and fused in contact with the metal package element and a hermetic, preferably ring-shaped bond between the metal package element and the transparent package element being produced by fusing and subsequently solidifying the glass solder.
    Type: Application
    Filed: July 2, 2007
    Publication date: January 17, 2008
    Applicant: SCHOTT AG
    Inventors: Joern Besinger, Sabine Pichler-Wilhem, Dieter Goedeke, Luise Sedlmeier
  • Patent number: 7307773
    Abstract: A micro-optoelectromechanical system (MOEMS) package for a light modulator includes a sealed modulator package containing a light modulator sealed under a first transparent lid; a secondary, larger package containing the sealed modulator package, the secondary package comprising a seal and a second transparent lid; and an optical material disposed between the first transparent lid and the second transparent lid, where the optical material is a solid, gel or liquid. An alternatively micro-optoelectromechanical system (MOEMS) package for a light modulator includes a sealed modulator package containing a light modulator sealed under a first transparent lid; a secondary, larger package containing the sealed modulator package; and a desiccant or getter material disposed inside the secondary package with the modulator package.
    Type: Grant
    Filed: January 4, 2005
    Date of Patent: December 11, 2007
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Chien-Hua Chen, David M. Craig, Charles C. Haluzak
  • Patent number: 7301227
    Abstract: A package for an integrated circuit (IC) die comprises a substrate and a lid. The substrate has an upper surface facing an interior of the package and a lower surface facing an exterior of the package. The upper surface of the substrate carries an IC die and provides electrical connections from the IC die to the lower surface of the substrate. The lid includes an outer lid and an inner lid. The inner lid is positioned over the IC die and is in thermal communication with the IC die. The inner lid is formed of a material suitable for conducting heat away from the IC die. The outer lid is attached to the upper surface of the substrate. A gap extends between the outer lid and inner lid.
    Type: Grant
    Filed: August 19, 2005
    Date of Patent: November 27, 2007
    Assignee: Sun Microsystems, Inc.
    Inventors: Vadim Gektin, Deviprasad Malladi
  • Patent number: 7298030
    Abstract: A method of making a plurality of sealed assemblies is provided which includes a) assembling a first element to a second element so that a bottom surface of the first element faces downwardly toward a front surface of the second element and a top surface of the first element faces upwardly away from the second element; and (b) forming ring seals surrounding regions of the front surface of the second element by introducing flowable material between the first element and the second element from the top surface of the first element through openings in the first element. A chip is provided which includes: (a) a body defining a front surface and one or more circuit elements on or within the body; (b) one or more bond pads exposed at the front surface in a bond pad region; and (c) a metallic ring exposed at the front surface, the ring substantially surrounding the bond pad region. Sealed chip assemblies are formed by sealing an array of the chips, e.g., in wafer form, to a cap element.
    Type: Grant
    Filed: September 24, 2004
    Date of Patent: November 20, 2007
    Assignee: Tessera, Inc.
    Inventors: Bruce M. McWilliams, Giles Humpston, Belgacem Haba, David B. Tuckerman
  • Patent number: 7294925
    Abstract: An optical scanner package having a heating dam is provided. The optical scanner package having a heating dam includes: an optical scanner on which a mirror surface is formed; a ceramic package in which the optical scanner is installed at the bottom of a cavity thereof; a glass lid covering a sidewall of the ceramic package; a heating dam formed on the sidewall of the ceramic package; and solder on the heating dam sealing between the glass lid and the sidewall of the ceramic package. The heating dam locally heats the solder to form hermetic sealing.
    Type: Grant
    Filed: December 23, 2005
    Date of Patent: November 13, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-kyoung Choi, Young-chul Ko
  • Patent number: 7291902
    Abstract: A chip component (1) includes a semiconductor body (2), in which at least one switchable element (6, 62) is arranged in a partial region (24) of the semiconductor body (2). The partial region (24) can be reached by light of at least one wavelength. Furthermore, a circuit (9) integrated into the semiconductor body (2) is provided, which integrated circuit can assume one configuration from at least two possible configurations, one of these configurations being prescribed by a state of the at least one switchable element (6, 62). Furthermore, a housing (3) is provided, which encloses the semiconductor body (2) and is arranged with a partial region (35, 32) at least partly above the partial region (24) of the semiconductor body (2). The partial region (35, 32) of the housing (3) is formed in such a way that light can be fed to the partial region (24) of the semiconductor body (2).
    Type: Grant
    Filed: December 15, 2005
    Date of Patent: November 6, 2007
    Assignee: Infineon Technologies AG
    Inventors: Youssef Gannoune, Christian Stocken
  • Patent number: 7285850
    Abstract: A support structure for a semiconductor device with peripherally disposed contacts includes a support substrate and at least one conductive column protruding from the support substrate. The at least one conductive column is configured to contact an outer connector on a peripheral edge of a semiconductor device that may be carried by the support structure. Optionally, the at least one conductive column may engage a feature of (e.g., a recess in) the peripherally disposed outer connector. The at least one conductive column may facilitate alignment of one or more semiconductor devices with the support substrate alignment of semiconductor devices relative to one another, or electrical connection between multiple semiconductor devices of other components.
    Type: Grant
    Filed: May 8, 2006
    Date of Patent: October 23, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Chia Yong Poo, Boon Suan Jeung, Low Siu Waf, Chan Min Yu, Neo Yong Loo, Chua Swee Kwang
  • Patent number: 7285445
    Abstract: A thermal management system is provided for semiconductor devices such as an LED array, wherein coolant directly cools the LED array. Preferably, the coolant may be selected, among other bases, based on its index of refraction relative to the index associated with the semiconductor device.
    Type: Grant
    Filed: June 13, 2006
    Date of Patent: October 23, 2007
    Assignee: Phoseon Technology, Inc.
    Inventors: Mark D. Owen, Francois Vlach, Duwayne R. Anderson
  • Patent number: 7282788
    Abstract: In an image sensing chip package structure, plated through vias penetrate a substrate to electrically connect metallization traces disposed on the upper and lower surfaces of the substrate. The plated through vias can be opened from the center of the substrate instead of being located at the periphery of the substrate. Contamination can thus be avoided during the glue dispensing process, and protection layers can also be used to seal gaps generated by the plated through vias, hence enhancing the producing yield. Moreover, protection layers having stickiness can further be used to secure components so as to reduce the production cost and enhance the product quality.
    Type: Grant
    Filed: September 14, 2005
    Date of Patent: October 16, 2007
    Assignee: Sigurd Microelectronics Corp.
    Inventor: Po-Hung Chen
  • Patent number: 7279782
    Abstract: A structure of package comprises a die placed on printed circuit board. A glass substrate is adhered on an adhesive film pattern to form an air gap area between the glass substrate and the chip. Micro lens are disposed on the chip. A lens holder is fixed on printed circuit board. The glass substrate can prevent the micro lens from particle contamination.
    Type: Grant
    Filed: January 5, 2005
    Date of Patent: October 9, 2007
    Assignee: Advanced Chip Engineering Technology Inc.
    Inventors: Wen-Kun Yang, Chin-Chen Yang, Wen-Bin Sun, Jui-Hsien Chang, Chun Hui Yu, His-Ying Yuan
  • Patent number: 7276787
    Abstract: A carrier structure and method for fabricating a carrier structure with through-vias each having a conductive structure with an effective coefficient of thermal expansion which is less than or closely matched to that of the substrate, and having an effective elastic modulus value which is less than or closely matches that of the substrate. The conductive structure may include concentric via fill areas having differing materials disposed concentrically therein, a core of the substrate material surrounded by an annular ring of conductive material, a core of CTE-matched non-conductive material surrounded by an annular ring of conductive material, a conductive via having an inner void with low CTE, or a full fill of a conductive composite material such as a metal-ceramic paste which has been sintered or fused.
    Type: Grant
    Filed: December 5, 2003
    Date of Patent: October 2, 2007
    Assignee: International Business Machines Corporation
    Inventors: Daniel Charles Edelstein, Paul Stephen Andry, Leena Paivikki Buchwalter, Jon Alfred Casey, Sherif A. Goma, Raymond R. Horton, Gareth Geoffrey Hougham, Michael Wayne Lane, Xiao Hu Liu, Chirag Suryakant Patel, Edmund Juris Sprogis, Michelle Leigh Steen, Brian Richard Sundlof, Cornelia K. Tsang, George Frederick Walker
  • Patent number: 7274101
    Abstract: A semiconductor package includes: a first substrate including: a semiconductor base material having a first side and a second side; a functional element that is provided at the first side of the semiconductor base material; a first wiring; a pad that is electrically connected to the functional element via the first wiring; a through-hole interconnection that is electrically connected to the pad and is provided in a hole that is defined penetrating the semiconductor base material from the first side thereof to the second side thereof, the through-hole interconnection including a first insulating film and a first conductive material formed on the first insulating film; and a sealing material provided surrounding the functional element; a second substrate that is bonded to a first side of the first substrate via the sealing material.
    Type: Grant
    Filed: June 27, 2005
    Date of Patent: September 25, 2007
    Assignee: Fujikura Ltd.
    Inventors: Michikazu Tomita, Tatsuo Suemasu, Sayaka Hirafune
  • Patent number: 7274095
    Abstract: A semiconductor device package interposer including a receptacle extending substantially therethrough. Methods for assembling the interposer with one or more semiconductor devices are also disclosed. A film may be secured to a bottom surface of the interposer so as to at least partially cover a bottom end of the receptacle. One or more semiconductor devices are positioned within the receptacle, on the film. Each semiconductor device within the receptacle may then be electrically connected to the interposer. An encapsulant material, which is introduced into the receptacle, extends at least between portions of the outer periphery of each semiconductor device within the receptacle and a peripheral edge of the receptacle. Upon curing, setting, or hardening, the encapsulant material retains each semiconductor device within the receptacle and maintains a lateral position of each semiconductor device with respect to the interposer. Semiconductor device packages and multi-chip modules are also disclosed.
    Type: Grant
    Filed: June 8, 2004
    Date of Patent: September 25, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Setho Sing Fee, Lim Thiam Chye, Steven W. Heppler, Leng Nam Yin, Keith Tan, Patrick Guay, Edmund Lua Koon Tian, Yap Kah Eng, Eric Tan Swee Seng
  • Patent number: 7274096
    Abstract: A light transmissive cover for a device comprising: a cover member of light transmissive material; and a junction member joined to the cover member, the junction member being a member used to be joined to the body of the device and having a light interrupting film on the inner surface thereof. A device provided with a light transmissive cover, the device being provided with a cover member of light transmissive material joined to the body of device via a junction member so as to cover at least a part of the device, and having a light interrupting film on the inner surface of the junction member is also disclosed. In addition, methods for manufacturing them disclosed.
    Type: Grant
    Filed: October 21, 2004
    Date of Patent: September 25, 2007
    Assignee: Shinko Electric Industries, Co., Ltd.
    Inventor: Akinori Shiraishi
  • Patent number: 7274094
    Abstract: A leadless image sensor package and methods for its assembly. In a first embodiment, an image sensor chip is mounted within a bottom-side cavity of a package shell in a flip-chip manner such that sensing circuitry on the image sensor chip is exposed through an aperture in the top side of the package shell. A transparent encapsulant material is deposited within the aperture to encase interconnect bonds between the package shell and the image sensor chip. A transparent lid is held in place over the aperture by the encapsulant material. The back surface of the image sensor chip is left exposed. In a second embodiment particularly suitable for high-end image sensors, an encapsulant material is not required. Instead, a backing cap is hermetically sealed to a ledge surface in the package shell to cover the bottom-side cavity. A compression member formed on the backing cap contacts the image sensor chip and maintains interconnect bond integrity.
    Type: Grant
    Filed: August 28, 2002
    Date of Patent: September 25, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Suan Jeung Boon, Yong Poo Chia, Yong Loo Neo, Swee Kwang Chua, Siu Waf Low
  • Publication number: 20070210399
    Abstract: A method of manufacturing a micro-element package which can reduce a manufacturing cost and improve productivity by simplifying its structure and manufacturing process, and also can make contributions to miniaturization and thinness, and the micro-element package are provided. The method of the micro-element package including: providing a substrate having a micro-element on its top surface and a transparent cover having a groove on its bottom surface; attaching the transparent cover on the substrate, wherein the bottom surface of the transparent cover where the groove is formed faces the micro-element; exposing the groove by selectively eliminating the transparent cover; and dicing the substrate along the exposed groove.
    Type: Application
    Filed: October 23, 2006
    Publication date: September 13, 2007
    Inventors: Seung Wan Lee, Woon Bae Kim, Kyu Dong Jung, Min Seog Choi
  • Patent number: 7268436
    Abstract: An electronic device can include a top side with circuit structures. The circuit structures form the bottom region of a cavity. Each cavity can be surrounded by a cavity frame made of plastic and can have a cavity cover made of semiconductor material.
    Type: Grant
    Filed: March 9, 2004
    Date of Patent: September 11, 2007
    Assignee: Infineon Technologies AG
    Inventors: Robert Aigner, Albert Auburger, Frank Daeche, Guenter Ehrler, Andreas Meckes, Horst Theuss, Michael Weber
  • Patent number: 7263768
    Abstract: The present invention features a novel design for a fiducial and pin one indicator that utilizes a single solder resist opening in a die mounting substrate to perform the combined functions of prior art fiducials and pin one indicators. Methods of fabricating a carrier substrate and fabricating a semiconductor device package using the combination pin one indicator and alignment fiducial of the present invention are also provided.
    Type: Grant
    Filed: August 25, 2004
    Date of Patent: September 4, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Brad D. Rumsey, Matt E. Schwab
  • Patent number: 7262500
    Abstract: In a metal film production apparatus, a copper plate member is etched with a Cl2 gas plasma within a chamber to form a precursor comprising a Cu component and a Cl2 gas; and the temperatures of the copper plate member and a substrate and a difference between their temperatures are controlled as predetermined, to deposit the Cu component of the precursor on the substrate, thereby forming a film of Cu. In this apparatus, Cl* is formed in an excitation chamber of a passage communicating with the interior of the chamber to flow a Cl2 gas, and the Cl* is supplied into the chamber to withdraw a Cl2 gas from the precursor adsorbed onto the substrate, thereby promoting a Cu film formation reaction. The apparatus has a high film formation speed, can use an inexpensive starting material, and can minimize impurities remaining in the film.
    Type: Grant
    Filed: May 19, 2005
    Date of Patent: August 28, 2007
    Assignee: Phyzchemix Corporation
    Inventors: Hitoshi Sakamoto, Naoki Yahata, Toshihiko Nishimori, Yoshiyuki Ooba, Hiroshi Tonegawa, Ikumasa Koshiro, Yuzuru Ogura
  • Publication number: 20070164386
    Abstract: A semiconductor device and the fabrication method thereof are provided.
    Type: Application
    Filed: December 28, 2006
    Publication date: July 19, 2007
    Applicant: Siliconware Precision Industries Co., Ltd.
    Inventors: Cheng-Yi Chang, Chien-Ping Huang, Yu-Po Wang, Chih-Ming Huang, Cheng-Hsu Hsiao
  • Publication number: 20070164416
    Abstract: A system and method for combining a leaded package IC and a semiconductor die using a flex circuitry. The leaded packaged IC is disposed along an obverse side of a flex circuit. In a preferred embodiment, the lower surface of the body of the leaded packaged IC contacts the surface of the flex circuitry. The semiconductor die is disposed beneath the leaded package IC and, in preferred embodiments, disposed in a window that passes through at least a part of the flex circuitry and is attached to a conductive layer of the flex circuitry. In other embodiments, the semiconductor die is attached to the body of the leaded packaged IC. The flex circuitry preferably employs at least two conductive layers and, in preferred embodiments, the leaded packaged IC is connected to the flex circuitry at one layer while the semiconductor die is connected to the flex circuitry at the other conductive layer.
    Type: Application
    Filed: June 7, 2006
    Publication date: July 19, 2007
    Inventors: James Douglas Wehrly, Leland Szewerenko, David L. Roper
  • Patent number: 7245007
    Abstract: An interposer for use in an external lead or land pattern semiconductor package. The interposer includes an interposer body which is molded from a dielectric material. The interposer body defines opposed top and bottom surfaces, an outer peripheral edge, and an inner peripheral edge. Embedded within the interposer body is a die pad which itself defines opposed top and bottom surfaces and a peripheral edge. The bottom surface of the die pad is exposed in and substantially flush with the bottom surface of the interposer body, with the inner peripheral edge of the interposer body and the top surface of the die pad collectively defining a cavity of the interposer. A plurality of electrically conductive interposer leads are embedded within the top surface of the interposer body and at least partially exposed therein. The interposer body forms a nonconductive barrier between each of the interposer leads and between the interposer leads and the die pad.
    Type: Grant
    Filed: September 18, 2003
    Date of Patent: July 17, 2007
    Assignee: Amkor Technology, Inc.
    Inventor: Donald Craig Foster
  • Patent number: 7242068
    Abstract: A photosensitive semiconductor package, a method for fabricating the same, and a lead frame thereof are proposed. The lead frame has a die pad and a plurality of leads, wherein at least one recessed portion is formed at an end of each lead close to the die pad, and at least one recessed region is formed on the die pad. An encapsulant fills the recessed portions, the recessed region, and between the leads and the die pad, and is formed on the lead frame to define a chip receiving cavity. A photosensitive chip is mounted in the chip receiving cavity, wherein at least partially a non-active surface of the chip is attached to the encapsulant filling the recessed region and is not in contact with the recessed region. A light-penetrable unit is attached to the encapsulant formed on the lead frame to seal the chip receiving cavity.
    Type: Grant
    Filed: September 28, 2004
    Date of Patent: July 10, 2007
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventor: Chien-Ping Huang
  • Patent number: 7242538
    Abstract: An optical device includes a base of ring shape, and a light emitting/receiving element and a transparent plate both attached to the base. A side face of the opening of the base is formed to have a taper serving as a draft for a molding resin. A side surface of the transparent plate is formed to have a taper widened upwardly and corresponding to the draft. These side face and surface engage each other with an adhesive layer interposed therebetween. A hologram may be mounted instead of the transparent plate.
    Type: Grant
    Filed: October 13, 2004
    Date of Patent: July 10, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masanori Minamio, Hikaru Sano, Kenji Furumoto
  • Patent number: 7238897
    Abstract: A contact sensor includes a base, a wall device securely attached to the top face of the base and having a hole defined in the wall device to correspond to the top contacts so as to allow the top contacts of the base to be exposed and a chip receiving space defined to communicate with the hole, a sensing chip received in the chip receiving space and having a sensing area formed on top of the sensing chip and contacts formed thereon to electrically connect to the top contacts of the base and a cover received in the hole to enclose the contacts of the sensing chip and the top contacts of the base yet still allowing the sensing area exposed for application.
    Type: Grant
    Filed: December 7, 2005
    Date of Patent: July 3, 2007
    Assignee: Taiwan IC Packaging Corporation
    Inventors: Ching-Chung Tseng, Chung-Chi Yang, Hsiu-Chung Lin, Chun-I Kao, Hsiang-Hsin Kuo
  • Patent number: 7235878
    Abstract: A thermal management system is provided for semiconductor devices such as an LED array, wherein coolant directly cools the LED array. Preferably, the coolant may be selected, among other bases, based on its index of refraction relative to the index associated with the semiconductor device.
    Type: Grant
    Filed: March 18, 2005
    Date of Patent: June 26, 2007
    Assignee: Phoseon Technology, Inc.
    Inventors: Mark D. Owen, Francois Vlach, Duwayne R. Anderson
  • Patent number: 7224047
    Abstract: A semiconductor device package comprises a container including a base and sidewalls. The base is configured to support a semiconductor device chip, and a lead frame extends through at least one of the sidewalls. A portion of the lead frame within the sidewall has at least one aperture penetrating into the lead frame. The sidewall material extends into the aperture, thereby forming a strong interfacial bond that provides a low leakage, sidewall-lead-frame interface. The base has a reentrant feature that is positioned within the thickness of at least one of the sidewalls and engages the at least one sidewall, thereby forming a low leakage base-sidewalls interface. The top surface of the base has a groove that is positioned within the thickness of at least one of the sidewalls and engages the at least one sidewall, thereby enhancing the low leakage base-sidewall interface.
    Type: Grant
    Filed: December 18, 2004
    Date of Patent: May 29, 2007
    Assignee: LSI Corporation
    Inventors: Patrick Joseph Carberry, Jeffery John Gilbert, George John Libricz, Jr., Ralph Salvatore Moyer, John William Osenbach, Hugo Fernando Safar, Thomas Herbert Shilling
  • Patent number: 7224046
    Abstract: A multilayer wiring board (X1) comprises a core portion (100) and out-core wiring portion (30). The core portion (100) comprises a carbon fiber reinforced portion (10) composed of a carbon fiber material (11) and resin composition (12), and an in-core wiring portion (20) which has a laminated structure of at least one insulating layer (21) containing a glass fiber material (21a) and a wiring pattern (22) composed of a conductor having an elastic modulus of 10 to 40 GPa and which is bonded to the carbon fiber reinforced portion (10). The out-core wiring portion (30) has a laminated structure of at least one insulating layer (31) and a wiring pattern (32) and is bonded to the core portion (100) at the in-core wiring portion (20).
    Type: Grant
    Filed: June 1, 2005
    Date of Patent: May 29, 2007
    Assignee: Fujitsu Limited
    Inventors: Tomoyuki Abe, Nobuyuki Hayashi, Motoaki Tani