With Semiconductor Element Forming Part (e.g., Base, Of Housing) Patents (Class 257/684)
  • Patent number: 11309621
    Abstract: The present disclosure relates to a communication method and system for converging a 5th-Generation (5G) communication system for supporting higher data rates beyond a 4th-Generation (4G) system with a technology for Internet of Things (IoT). The present disclosure may be applied to intelligent services based on the 5G communication technology and the IoT-related technology, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. An antenna module includes a first printed circuit board (PCB) stacked at least one layer, and a second PCB disposed on an upper surface of the first PCB and stacked at least one layer.
    Type: Grant
    Filed: April 9, 2020
    Date of Patent: April 19, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwanghyun Baek, Dohyuk Ha, Youngju Lee, Jungyub Lee, Juneseok Lee, Jinsu Heo
  • Patent number: 11291919
    Abstract: Technologies for executing a virtual character development application using machine learning are described herein. In typical simulation applications, a user may be enabled to create a virtual character and navigate a virtual world. A typical simulation application may accept inputs from the user, determine actions initiated by the user based on the inputs, determine subsequent outcomes of the user-initiated actions, and mold the simulation according to the outcomes. However, most outcomes may be predetermined and predictable by design. In contrast, some embodiments may include a server configured to execute a virtual character development application in conjunction with one or more client devices. A user may utilize a client device to create and develop a virtual character within the application. The user may be enabled to provide inputs to the virtual character development application, and the artificial component may process the input and extract information associated with the virtual character.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: April 5, 2022
    Assignee: Interlake Research, LLC
    Inventors: Yanjun Ma, Christine K. Ma, Kevin L. Ma
  • Patent number: 11287486
    Abstract: A micro-electro-mechanical system (MEMS) magnetometer is provided for measuring magnetic field components along three orthogonal axes. The MEMS magnetometer includes a top cap wafer, a bottom cap wafer and a MEMS wafer having opposed top and bottom sides bonded respectively to the top and bottom cap wafers. The MEMS wafer includes a frame structure and current-carrying first, second and third magnetic field transducers. The top cap, bottom cap and MEMS wafer are electrically conductive and stacked along the third axis. The top cap wafer, bottom cap wafer and frame structure together form one or more cavities enclosing the magnetic field transducers. The MEMS magnetometer further includes first, second and third electrode assemblies, the first and second electrode assemblies being formed in the top and/or bottom cap wafers. Each electrode assembly is configured to sense an output of a respective magnetic field transducer induced by a respective magnetic field component.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: March 29, 2022
    Assignee: Motion Engine, Inc.
    Inventor: Robert Mark Boysel
  • Patent number: 11239140
    Abstract: Disclosed a chip packaging structure and a manufacturing method thereof. The chip packaging structure comprises: a metal heat dissipation layer; a chip structure comprising a plurality of first electrical contacts on an upper surface of the chip structure; a pin layer comprising a plurality of second electrical contacts and a plurality of separate metal bumps; an encapsulant encapsulating at least one portion of the chip structure, the metal heat dissipation layer and the pin layer, wherein at least one portion of the pin layer is exposed to an upper surface of the encapsulant, and an lower surface of the metal heat dissipation layer is exposed outside the encapsulant. The metal heat dissipation layer includes a flange on the side surface for tightly combining the metal heat dissipation layer and the encapsulant.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: February 1, 2022
    Assignee: HEFEI SMAT TECHNOLOGY CO., LTD.
    Inventor: Xiaochun Tan
  • Patent number: 11216376
    Abstract: A memory circuit includes a first memory circuit formed of a first die or a set of stacked dies. The memory circuit further includes a second memory circuit formed of a second die, the second memory circuit comprising one or more sets of memory cells of a second type and each set of the memory cells of the second type comprising multiple cache sections. The first die or the set of stacked dies are stacked over the second die, wherein the second die further includes a first plurality of I/O terminals and a second plurality of I/O terminals, the first plurality of I/O terminals being electrically coupled to the first memory circuit, and the second plurality of I/O terminals being electrically isolated from the first memory circuit.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: January 4, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsien-Hsin Sean Lee, William Wu Shen, Yun-Han Lee
  • Patent number: 11217505
    Abstract: An electronics heat exchanger including a fluid flow body having a first panel, a second panel, and at least one fluid flow guide connecting the first panel and the second panel, a plurality of pedestals extending from the second panel, the plurality of pedestals including at least a first pedestal having a first height and a second pedestal having a second height, distinct from the first height, and wherein each of the pedestals is integral with the second panel.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: January 4, 2022
    Assignee: Aptiv Technologies Limited
    Inventors: Scott D. Brandenburg, Mark W. Hudson
  • Patent number: 11152363
    Abstract: The present disclosure relates to a bulk complementary-metal-oxide-semiconductor (CMOS) device including a device substrate, a thinned device die with a device region over the device substrate, a first mold compound, and a second mold compound. The device region includes a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion. The first mold compound resides over the device substrate, surrounds the thinned device die, and extends vertically beyond the thinned device die to define an opening over the thinned device die and within the first mold compound. The second mold compound fills the opening and directly connects the thinned device die. Herein, a silicon material with a resistivity between 5 Ohm-cm and 30000 Ohm-cm does not exist between the second mold compound and the thinned device die.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: October 19, 2021
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Michael Carroll, Dirk Robert Walter Leipold, George Maxim, Baker Scott
  • Patent number: 11145581
    Abstract: A leadless package with wettable flanks is formed by providing a substrate and plating a metal layer onto the substrate to form a contact on the substrate extending across a saw street. An encapsulant is deposited over the contact. The substrate is removed to expose the contact and encapsulant. The encapsulant and contact are singulated. In some embodiments, the substrate includes a ridge, and the contact is formed over the ridge.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: October 12, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Darrell D. Truhitte, James P. Letterman, Jr.
  • Patent number: 11112574
    Abstract: Optoelectronic systems with an adapter and methods of manufacturing or assembling the same are provided. An example of an optoelectronic system according to the present disclosure includes a substrate, an interposer, an electronic component disposed on the interposer, and an optical component. The optoelectronic system includes a ferrule and an optical fiber coupled to the ferrule. The optoelectronic system also includes an optical socket configured to receive the ferrule therein. The optoelectronic system further includes an adapter positioned between the interposer and the optical socket. The adapter has a wedge-shaped configuration such that the ferrule is disposed at a non-zero angle relative to the interposer when the ferrule is received in the optical socket and the optical socket is coupled to the adapter.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: September 7, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Sagi Varghese Mathai, Paul Kessler Rosenberg, Georgios Panotopoulos
  • Patent number: 11088079
    Abstract: A package structure includes a first through via structure formed in a substrate and a semiconductor die formed below the first through via structure. The package structure further includes a conductive structure formed in a passivation layer over the substrate. The conductive structure includes a first via portion and a second via portion, the first via portion is directly over the first through via structure, and there is no conductive material directly below and in direct contact with the second via portion.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: August 10, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Kai Cheng, Tsung-Shu Lin, Tsung-Yu Chen, Hsien-Pin Hu, Wen-Hsin Wei
  • Patent number: 11081438
    Abstract: An object of the present invention is to improve manufacturing efficiency of a semiconductor device. The method of manufacturing a semiconductor device includes a sealing step of sealing a semiconductor chip mounted on the wiring substrate. The sealing step includes a step of arranging the wiring substrate between an upper mold and a lower mold, suctioning a lower surface of the wiring substrate with the plurality of suction holes, thereby holding the wiring substrate the upper mold, and a step of sealing the semiconductor chip, an upper surface of the wiring substrate, and the plurality of side surfaces of the wiring substrate such that each of the semiconductor chip, the upper surface of the wiring substrate, and the plurality of side surfaces of the wiring substrate is covered with the resin in the lower mold.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: August 3, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoshiaki Sato, Yoshinori Miyaki, Junichi Arita
  • Patent number: 11049859
    Abstract: The present disclosure relates to a bulk complementary-metal-oxide-semiconductor (CMOS) device including a device substrate, a thinned device die with a device region over the device substrate, a first mold compound, and a second mold compound. The device region includes a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion. The first mold compound resides over the device substrate, surrounds the thinned device die, and extends vertically beyond the thinned device die to define an opening over the thinned device die and within the first mold compound. The second mold compound fills the opening and directly connects the thinned device die. Herein, a silicon material with a resistivity between 5 Ohm-cm and 30000 Ohm-cm does not exist between the second mold compound and the thinned device die.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: June 29, 2021
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Michael Carroll, Dirk Robert Walter Leipold, George Maxim, Baker Scott
  • Patent number: 11018107
    Abstract: A semiconductor device includes a low-density substrate, a high-density patch positioned inside a cavity in the low-density substrate, a first semiconductor die, and a second semiconductor die. The first semiconductor dies includes high-density bumps and low-density bumps. The second semiconductor die includes high-density bumps and low-density bumps. The high-density bumps of the first semiconductor die and the high-density bumps of the second semiconductor die are electrically connected to the high-density patch. The low-density bumps of the first semiconductor die and the low-density bumps of the second semiconductor die are electrically connected to the low-density substrate.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: May 25, 2021
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Jae Hun Bae, Won Chul Do, Min Yoo, Young Rae Kim, Min Hwa Chang, Dong Hyun Kim, Ah Ra Jo, Seok Geun Ahn
  • Patent number: 11018098
    Abstract: A system may include a first semiconductor substrate having a first side and a second side opposite the first side. The system may further include multiple device layers positioned on the first side of the substrate. The system may also include a first portion of an antenna structure positioned within at least one of the multiple device layers. The system may include a second portion of the antenna structure positioned over the second side of the substrate. The system may further include a via passing through the substrate and electrically coupling the first portion of the antenna structure to the second portion of the antenna structure.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: May 25, 2021
    Assignee: Micron Technology, Inc.
    Inventors: John F. Kaeding, Owen R. Fay
  • Patent number: 11004853
    Abstract: The present disclosure relates to a bulk complementary-metal-oxide-semiconductor (CMOS) device including a device substrate, a thinned device die with a device region over the device substrate, a first mold compound, and a second mold compound. The device region includes a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion. The first mold compound resides over the device substrate, surrounds the thinned device die, and extends vertically beyond the thinned device die to define an opening over the thinned device die and within the first mold compound. The second mold compound fills the opening and directly connects the thinned device die. Herein, a silicon material with a resistivity between 5 Ohm-cm and 30000 Ohm-cm does not exist between the second mold compound and the thinned device die.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: May 11, 2021
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Michael Carroll, Dirk Robert Walter Leipold, George Maxim, Baker Scott
  • Patent number: 10978409
    Abstract: A semiconductor package includes a first substrate having a first surface and a second surface opposite to the first surface, a first semiconductor chip on the first surface of the first substrate, a second semiconductor chip on the first surface of the first, a stiffener on the first semiconductor chip and the second semiconductor chip, and an encapsulant on the first surface of the first substrate. The first substrate includes a plurality of first pads on the first surface thereof and a plurality of second pads on the second surface thereof. The first semiconductor chip is connected to a first group of first pads of the plurality of first pads. The second semiconductor chip is connected to a second group of first pads of the plurality of first pads. The stiffener covers a space between the first semiconductor chip and the second semiconductor chip. The encapsulant covers at least a sidewall of each of the first and second semiconductor chips and the stiffener.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: April 13, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Kyong Soon Cho
  • Patent number: 10978378
    Abstract: A leadless package includes an at least partially electrically conductive carrier having a mounting section and a lead section, an electronic chip mounted on the mounting section, and an encapsulant at least partially encapsulating the electronic chip and partially encapsulating the carrier so that at least part of an interior sidewall of the lead section not forming part of an exterior sidewall of the package is exposed.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: April 13, 2021
    Assignee: Infineon Technologies AG
    Inventors: Thomas Bemmerl, Kuok Wai Chan, Christoph Liebl, Bun Kian Tay, Wee Boon Tay, Wae Chet Yong
  • Patent number: 10950567
    Abstract: A ring-like sealing frame (3) and a bump (4) are simultaneously formed on a main surface of a first substrate (1) by patterning a metal paste. A ring-like protrusion (8) having a smaller width than a width of the sealing frame (3) is formed on a main surface of a second substrate (5). The main surface of the first substrate (1) and the main surface of the second substrate (5) are aligned to face each other. The sealing frame (3) is bonded to the protrusion (8), and the bump (4) is electrically bonded to the second substrate (5). A height of the protrusion (8) is 0.4 to 0.7 times a distance between the first substrate (1) and the second substrate (2) after bonding.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: March 16, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventor: Koichiro Nishizawa
  • Patent number: 10943905
    Abstract: The present disclosure relates to a bulk complementary-metal-oxide-semiconductor (CMOS) device including a device substrate, a thinned device die with a device region over the device substrate, a first mold compound, and a second mold compound. The device region includes a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion. The first mold compound resides over the device substrate, surrounds the thinned device die, and extends vertically beyond the thinned device die to define an opening over the thinned device die and within the first mold compound. The second mold compound fills the opening and directly connects the thinned device die. Herein, a silicon material with a resistivity between 5 Ohm-cm and 30000 Ohm-cm does not exist between the second mold compound and the thinned device die.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: March 9, 2021
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Michael Carroll, Dirk Robert Walter Leipold, George Maxim, Baker Scott
  • Patent number: 10910290
    Abstract: A semiconductor structure is disclosed. In one example, the semiconductor structure includes: a device region having at least one semiconductor device; a dummy region in contact with the device region; and at least one thermal conductor embedded in the dummy region.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: February 2, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: S. L. Chen, Chen-Hsuan Yen, Han-Tang Lo
  • Patent number: 10896908
    Abstract: The present disclosure relates to a bulk complementary-metal-oxide-semiconductor (CMOS) device including a device substrate, a thinned device die with a device region over the device substrate, a first mold compound, and a second mold compound. The device region includes a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion. The first mold compound resides over the device substrate, surrounds the thinned device die, and extends vertically beyond the thinned device die to define an opening over the thinned device die and within the first mold compound. The second mold compound fills the opening and directly connects the thinned device die. Herein, a silicon material with a resistivity between 5 Ohm-cm and 30000 Ohm-cm does not exist between the second mold compound and the thinned device die.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: January 19, 2021
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Michael Carroll, Dirk Robert Walter Leipold, George Maxim, Baker Scott
  • Patent number: 10833052
    Abstract: A semiconductor package includes a resin molded package substrate comprising a resin molded core, a plurality of metal vias in the resin molded core, a front-side RDL structure, and a back-side RDL structure. A bridge TSV interconnect component is embedded in the resin molded core. The bridge TSV interconnect component has a silicon substrate portion, an RDL structure integrally constructed on the silicon substrate portion, and TSVs in the silicon substrate portion. A first semiconductor die and a second semiconductor die are mounted on the front-side RDL structure. The first semiconductor die and the second semiconductor die are coplanar.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: November 10, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Shing-Yih Shih
  • Patent number: 10796215
    Abstract: Embodiments are directed to assembling an RFID tag through wire bonding techniques. In some examples, the RFID tag may be assembled by wire bonding of an RFID integrated circuit (IC) to an antenna through a hole in a substrate. In other examples, methods for assembling RFID tags from a singulated IC or diced ICs still on a dicing frame may be disclosed. The disclosed methods may use a single metal layer for producing RFID tags with multi-turn loop antenna.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: October 6, 2020
    Assignee: Interlake Research, LLC
    Inventor: Yanjun Ma
  • Patent number: 10790332
    Abstract: Techniques to fabricate an RF filter using 3 dimensional island integration are described. A donor wafer assembly may have a substrate with a first and second side. A first side of a resonator layer, which may include a plurality of resonator circuits, may be coupled to the first side of the substrate. A weak adhesive layer may be coupled to the second side of the resonator layer, followed by a low-temperature oxide layer and a carrier wafer. A cavity in the first side of the resonator layer may expose an electrode of the first resonator circuit. An RF assembly may have an RF wafer having a first and a second side, where the first side may have an oxide mesa coupled to an oxide layer. A first resonator circuit may be then coupled to the oxide mesa of the first side of the RF wafer.
    Type: Grant
    Filed: December 24, 2015
    Date of Patent: September 29, 2020
    Assignee: Intel Corporation
    Inventors: Bruce A. Block, Paul B. Fischer, Nebil Tanzi, Gregory Chance, Han Wui Then, Sansaptak Dasgupta, Marko Radosavljevic
  • Patent number: 10756006
    Abstract: A leadframe includes a frame, a die pad, a contact including a flank adjacent to the frame, a first tie bar between the frame and die pad, and a second tie bar between the die pad and contact. The leadframe is disposed over a carrier. A semiconductor die is disposed over the die pad. An encapsulant is deposited over the leadframe and semiconductor die including between the carrier and half-etched portions of the leadframe. A first trench is formed in the encapsulant to remove a portion of the frame and expose the flank of the contact. A conductive layer is formed over the flank by electroplating. A second trench is formed in the encapsulant through the second tie bar after forming the conductive layer.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: August 25, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Darrell D. Truhitte, Soon Wei Wang, Chee Hiong Chew
  • Patent number: 10707157
    Abstract: A semiconductor device package includes a first conductive base, a first insulation layer and a second insulation layer. The first conductive base has a first surface, a second surface opposite to the first surface and a lateral surface extended between the first surface and the second surface. The lateral surface includes a first portion adjacent to the first surface and a second portion adjacent to the second surface. The first insulation layer comprises a first insulation material. The first insulation layer has a first surface and a second surface opposite to the first surface. The first insulation layer covers the first portion of the lateral surface of the first conductive base. The second insulation layer comprises a second insulation material and covers the second portion of the lateral surface of the first conductive base. The first insulation material is different from the second insulation material.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: July 7, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hui Hua Lee, Chun Hao Chiu, Hui-Ying Hsieh, Kuo-Hua Chen, Chi-Tsung Chiu
  • Patent number: 10692824
    Abstract: A semiconductor radar module includes an integrated circuit (IC) radar device embedded within a wafer level package compound layer, the wafer level package compound layer extending at least partially lateral to the IC radar device. An interface layer abutting the wafer level package compound layer comprises a redistribution layer coupled to the IC radar device for connecting the IC radar device externally. An underfill material extends between the interface layer and an external substrate and abuts the interface layer and the external substrate. The interface layer is disposed between the wafer level package compound layer and the underfill material.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: June 23, 2020
    Assignee: Infineon Technologies AG
    Inventors: Rudolf Lachner, Linus Maurer, Maciej Wojnowski
  • Patent number: 10685922
    Abstract: A package structure includes a redistribution structure, a chip, one or more structural reinforcing elements, and a protective layer. The redistribution structure includes a first circuit layer and a second circuit layer disposed over the first circuit layer. The first circuit layer is electrically connected to the second circuit layer. The chip is disposed over the redistribution structure and electrically connected to the second circuit layer. The one or more structural reinforcing elements are disposed over the redistribution structure. The structural reinforcing element has a Young's modulus in a range of of 30 to 200 GPa. The protective layer overlays the chip and a sidewall of the structural reinforcing element.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: June 16, 2020
    Assignee: UNIMICRON TECHNOLOGY CORP.
    Inventors: Pu-Ju Lin, Cheng-Ta Ko, Yu-Hua Chen, Tzyy-Jang Tseng, Ra-Min Tain
  • Patent number: 10679919
    Abstract: An integrated circuit package having an interposer with increased thermal conductivity and techniques for fabricating such an integrated circuit package are provided. One example integrated circuit package generally includes a package substrate, at least one semiconductor die disposed above the package substrate, and an interposer disposed above the at least one semiconductor die. The interposer includes a dielectric layer, and a metallic plate disposed adjacent to a first portion of the dielectric layer. The height of the metallic plate is greater than a height of the dielectric layer.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: June 9, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Kuiwon Kang, Zhijie Wang, Bohan Yan
  • Patent number: 10672740
    Abstract: Methods and systems for a semiconductor package with high routing density routing patch are disclosed and may include a semiconductor die bonded to a substrate and a high routing density patch bonded to the substrate and to the semiconductor die, wherein the high routing density patch comprises a denser trace line density than the substrate. The high routing density patch can be a silicon-less-integrated module (SLIM) patch, comprising a BEOL portion, and can be TSV-less. Metal contacts may be formed on a second surface of the substrate. A second semiconductor die may be bonded to the substrate and to the high routing density patch. The high routing density patch may provide electrical interconnection between the semiconductor die. The substrate may be bonded to a silicon interposer. The high routing density patch may have a thickness of 10 microns or less. The substrate may have a thickness of 10 microns or less.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: June 2, 2020
    Assignee: Amkor Technology, Inc.
    Inventors: Michael Kelly, Ronald Patrick Huemoeller, David Jon Hiner
  • Patent number: 10535913
    Abstract: In accordance with some embodiments, a package structure includes an RFIC chip. an insulating encapsulation, a redistribution circuit structure, an antenna and a microwave director. The insulating encapsulation encapsulates the RFIC chip. The redistribution circuit structure is disposed on the insulating encapsulation and electrically connected to the RFIC chip. The antenna is disposed on the insulating encapsulation and electrically connected to the RFIC chip through the redistribution circuit structure. The antenna is located between the microwave director and the RFIC chip. The microwave director has a microwave directivity enhancement surface located at a propagating path of a microwave received or generated by the antenna.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: January 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Min-Chien Hsiao, Chen-Hua Yu, Chung-Shi Liu, Chao-Wen Shih, Shou-Zen Chang
  • Patent number: 10504847
    Abstract: A chip package structure includes a plurality of first chips, a plurality of first conductive pillars, a second chip, a plurality of second conductive pillars, an encapsulated material and a redistribution structure. Each first chip has a first active surface. Each of the first conductive pillars is disposed on the first active surface of the corresponding first chip. A second active surface of the second chip is electrically connected to the first active surfaces of the first chips through the second conductive pillars. The encapsulated material partially covers the first chips, the first conductive pillars, the second chip and the second conductive pillars. The redistribution structure is disposed on the encapsulated material and connects the first conductive pillars. A chip package structure array is also provided.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: December 10, 2019
    Assignee: Shanghai Zhaoxin Semiconductor Co., Ltd.
    Inventors: Wen-Yuan Chang, Yeh-Chi Hsu, Hsueh-Chung Shelton Lu, Wei-Cheng Chen
  • Patent number: 10504841
    Abstract: An embodiment method includes providing a fan-out package structure having cavities to confine semiconductor dies by applying adhesive material which has similar coefficient of thermal expansion (CTE) with semiconductor dies in the gap between the edges of dies and the edges of cavities. The method further includes forming a molding compound over a fan-out package structure with semiconductor dies, building fan-out redistribution layers over a fan-out package structure with semiconductor dies and electrically connected to the semiconductor dies.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: December 10, 2019
    Inventor: Shun-Ping Huang
  • Patent number: 10461019
    Abstract: A semiconductor package formed utilizing a removable backside protective layer includes a leadframe, a die pad, leads and a molding compound around them. The first surface of the die pad and leads are exposed to an external environment by the plurality of recesses. The recesses are formed by coupling a removable backside protective layer to the leadframe before applying the molding compound. After the molding compound is applied and cured, the backside protective layer is removed to expose the first surface of the die pad and the first surfaces of the leads so the semiconductor package may be mounted within an electronic device. The removable backside protective layer protects the die pad and the leads from mold flashing and residue when forming the semiconductor package during the fabrication process.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: October 29, 2019
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Aaron Cadag, Ian Harvey Arellano, Ela Mia Cadag
  • Patent number: 10444557
    Abstract: The present disclosure relates to a display module and a display device. The display module includes a display panel, at least one chip-on-film, a printed circuit board and a cover plate, wherein: the printed circuit board is located on a back side of the display panel; one end of the chip-on-film is connected with the display panel, the other end of the chip-on-film is bent towards the back side of the display panel and is connected with a printed circuit board, with a chip being packaged in a portion of the chip-on-film which is bent towards the back side of the display panel; the cover plate is located on the back side of the printed circuit board and covers the same; the cover plate is provided with thermal conductive blocks which are in thermal contact with the chip at each location of the cover plate corresponding to one of the chip-on-film respectively.
    Type: Grant
    Filed: April 5, 2017
    Date of Patent: October 15, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Zifeng Wang, Yan Ren, Nannan Hu, Lei Cao, She Lin
  • Patent number: 10430334
    Abstract: A method of operating a memory circuit is disclosed. The memory circuit comprises a primary memory and a cache memory. The primary memory has P access channels of Q bits of channel bandwidth, and the cache memory has P subsets of Q*N memory cells, wherein P and Q are integers greater than 1, and N is a positive integer. The method includes determining, in response to a command for reading first and second data accessible through first and second access channels respectively, if a valid duplication of the first and second data is stored in the cache memory. If yes, the method further includes storing a duplication of Q*n bits of consecutively addressed data from each of the first and second access channels to the cache memory, n being an integer from 1 to N. Otherwise, the method further includes outputting the first and second data from the cache memory.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: October 1, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsien-Hsin Sean Lee, William Wu Shen, Yun-Han Lee
  • Patent number: 10324107
    Abstract: Provided is a highly reliable acceleration sensor having little 0-point drift. For example, an acceleration sensor having a support substrate having a first direction and a second direction orthogonal thereto in a single surface, a device layer disposed on the support substrate with a space interposed therebetween and having a weight that deforms according to the application of acceleration, and a cap layer disposed on the device layer with a space interposed therebetween, wherein a fixed part fixed to the support substrate is provided in the center of the weight, a beam is provided that extends from the fixed part and makes the weight mobile by being connected thereto, a plurality of posts for coupling the support substrate and the cap layer are disposed on the fixed part, and electric signals are applied to and received from the weight via the posts.
    Type: Grant
    Filed: April 8, 2015
    Date of Patent: June 18, 2019
    Assignee: HITACHI AUTOMOTIVE SYSTEMS, LTD.
    Inventors: Heewon Jeong, Masahide Hayashi, Kiyoko Yamanaka, Daisuke Maeda
  • Patent number: 10325841
    Abstract: According to an embodiment of the present invention, there is provided a semiconductor device having a first semiconductor component and a second semiconductor component which are mounted on a wiring substrate. The first semiconductor component has a first terminal for transmitting a first signal between the first semiconductor component and the outside and a second terminal for transmitting a second signal between the first semiconductor component and the second semiconductor component. In addition, the second semiconductor component has a third terminal for transmitting the second signal between the second semiconductor component and the first semiconductor component. Further, the first signal is transmitted at a higher frequency than the second signal. Furthermore, the second terminal of the first semiconductor component and the third terminal of the second semiconductor component are electrically connected to each other via the first wiring member.
    Type: Grant
    Filed: February 10, 2016
    Date of Patent: June 18, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kazuyuki Nakagawa, Katsushi Terajima, Keita Tsuchiya, Yoshiaki Sato, Hiroyuki Uchida, Yuji Kayashima, Shuuichi Kariyazaki, Shinji Baba
  • Patent number: 10282654
    Abstract: Embodiments are directed to assembling an RFID tag through wire bonding techniques. In some examples, the RFID tag may be assembled by wire bonding of an RFID integrated circuit (IC) to an antenna through a hole in a substrate. In other examples, methods for assembling RFID tags from a singulated IC or diced ICs still on a dicing frame may be disclosed. The disclosed methods may use a single metal layer for producing RFID tags with multi-turn loop antenna.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: May 7, 2019
    Assignee: Interlake Research, LLC
    Inventor: Yanjun Ma
  • Patent number: 10257610
    Abstract: A microphone module has a substrate with an aperture to allow sound waves to pass through the substrate, a lid mounted to the substrate to define a first interior volume, a microphone mounted to the substrate within the first interior volume, and a housing coupled to the substrate and covering the aperture. The housing forms a second interior volume and includes an acoustic port configured to allow sound to enter the second interior volume. The module further includes a pipe extending from the acoustic port in the housing, and at least one exterior interface pad outside of the second interior volume. The pipe has an open end to receive sound waves and direct them toward the acoustic port in the housing. Moreover, the at least one exterior interface pad electrically couples to the microphone.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: April 9, 2019
    Assignee: INVENSENSE, INC.
    Inventors: Kieran P. Harney, Dipak Sengupta, Brian Moss, Alain V. Guery
  • Patent number: 10236227
    Abstract: An electronic package is provided, including a circuit portion, an electronic element disposed on the circuit portion and a lid member disposed on the circuit portion to cover the electronic element. A separation portion is formed between the lid member and the electronic element. The lid member facilitates to prevent warping of the overall package structure. The invention further provides a method for fabricating the electronic package.
    Type: Grant
    Filed: December 24, 2015
    Date of Patent: March 19, 2019
    Assignee: Siliconware Prescision Industries Co., Ltd.
    Inventors: Lung-Shan Chuang, Ching-Wen Chiang, Tzung-Yen Wu, Chun-Hung Lu
  • Patent number: 10228577
    Abstract: There is disclosed a mobile terminal comprising a panel assembly comprising a display panel and a support plate provided in a rear surface of the display panel; a film portion which covers a lateral end of the panel assembly to locate one end connected with a front surface of the display panel and the other end behind the support plate; a drive chip provided in one surface of the film portion which faces a rear surface of the support plate; and a supporting portion provided in a first area near the drive chip and configured to form a spaced gap between the rear surface of the support plate and the drive chip.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: March 12, 2019
    Assignee: LG ELECTRONICS INC.
    Inventor: Wooyong Kwon
  • Patent number: 10224288
    Abstract: A fan-out semiconductor package includes a frame having a through hole, a semiconductor chip disposed in the through hole and including connection pads, an encapsulant encapsulating at least a portion of the frame and the semiconductor chip, and a redistribution layer disposed on the frame and the semiconductor chip and including a first region and a second region. In the first region, a first via and a second via, electrically connected to one of the connection pads, disposed in different layers, and connected by a wiring pattern, are disposed. In the second region, a third via and a fourth via, electrically connected to another of the connection pads, disposed in different layers, and connected by the wiring pattern, are disposed. A distance between axes of the first via and the second via is shorter than a distance between axes of the third via and the fourth via.
    Type: Grant
    Filed: October 9, 2017
    Date of Patent: March 5, 2019
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Kyung Seob Oh, Kyoung Moo Harr, Doo Hwan Lee, Seung Chul Oh, Hyoung Joon Kim, Yoon Suk Cho
  • Patent number: 10212818
    Abstract: A structure for a core layer of a substrate and a method for fabricating a core layer of a substrate are disclosed. The core layer comprises a molding compound encapsulating a die or a plurality of dies, a dielectric layer on the surfaces of the molding compound, and a conductive layer on top of the dielectric layer. A through hole is formed through the dielectric layer and the molding compound, which may be filled with a metal plate. A laser via is formed similarly. Build-up layers may be assembled next to the core layer to form the substrate, which can be used to package dies.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: February 19, 2019
    Assignee: FUTUREWEI TECHNOLOGIES, INC.
    Inventors: Fei Yu, Anwar A. Mohammed, Rui Niu
  • Patent number: 10211137
    Abstract: A method for manufacturing a semiconductor device package includes providing a substrate having a first surface and a second surface opposite to the first surface; disposing a passive component layer on the first surface of the substrate; after disposing the passive component layer, forming at least one via in the substrate, wherein the via penetrates the substrate and the passive component layer; and disposing a conductive layer on the passive component layer and filling the via with the conductive layer.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: February 19, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chien-Hua Chen, Sheng-Chi Hsieh, Cheng-Yuan Kung
  • Patent number: 10183860
    Abstract: A method for fabricating a multiple MEMS device includes providing a semiconductor substrate having a first and second MEMS device, and an encapsulation wafer with a first cavity and a second cavity, which includes at least one channel. The first MEMS is encapsulated within the first cavity and the second MEMS device is encapsulated within the second cavity. These devices is encapsulated within a first encapsulation environment at a first air pressure, and encapsulating the first MEMS device within the first cavity at the first air pressure. The second MEMS device within the second cavity is then subjected to a second encapsulating environment at a second air pressure via the channel of the second cavity.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: January 22, 2019
    Assignee: mCube Inc.
    Inventors: Wenhua Zhang, Shingo Yoneoka
  • Patent number: 10186779
    Abstract: Various embodiments of the present disclosure relate to a semiconductor device package including a carrier, an electrical component, an antenna, a conductive pad and a conductive line. The carrier includes a top surface. The electrical component is disposed over the top surface of the carrier. The antenna is disposed over the top surface of the carrier and spaced away from the electrical component. The conductive pad is disposed over the top surface of the carrier and beneath the antenna, wherein the conductive pad includes a resonant structure. The conductive line is electrically connected to the electrical component and extends within the carrier. A part of the conductive line is beneath the antenna and the resonant structure of the conductive pad.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: January 22, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Cheng-Yu Ho, Chen-Chao Wang, Chun-Yen Ting, Ming-Fong Jhong, Po-Chih Pan
  • Patent number: 10172186
    Abstract: A heater includes a ceramic body having a pillar or cylindrical shape; a heat generating resistor disposed in an interior of the ceramic body; a metallic layer which is disposed on an outer peripheral surface of the ceramic body and extends along a circumferential direction thereof; a flange bonded to the metallic layer via a bonding material, the bonding material including a meniscus part extending from the metallic layer to the flange; and a metallic wire which is disposed in an interior of the meniscus part on the outer peripheral surface of the ceramic body and extends along the circumferential direction.
    Type: Grant
    Filed: April 11, 2016
    Date of Patent: January 1, 2019
    Assignee: Kyocera Corporation
    Inventor: Hideaki Yoshidome
  • Patent number: 10167190
    Abstract: An apparatus and method for wafer-level hermetic packaging of MicroElectroMechanical Systems (MEMS) devices of different shapes and form factors is presented in this disclosure. The method is based on bonding a glass cap wafer with fabricated micro-glassblown “bubble-shaped” structures to the substrate glass/Si wafer. Metal traces fabricated on the substrate wafer serve to transfer signals from the sealed cavity of the bubble to the outside world. Furthermore, the method provides for chip-level packaging of MEMS three dimensional structures. The packaging method utilizes a micro glass-blowing process to create “bubbleshaped” glass lids. This new type of lids is used for vacuum packaging of three dimensional MEMS devices, using a standard commercially available type of package.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: January 1, 2019
    Assignee: The Regents of the University of California
    Inventors: Andrei A. Shkel, Alexandra Efimovskaya, Doruk Senkal
  • Patent number: 10163833
    Abstract: In a multi-chip module (MCM), a “super” chip (110N) is attached to multiple “plain” chips (110F? “super” and “plain” chips can be any chips). The super chip is positioned above the wiring board (WB) but below at least some of plain chips (110F). The plain chips overlap the super chip. Further, the plain chips' low speed IOs can be connected to the WB by long direct connections such as bond wires (e.g. BVAs) or solder stacks; such connections can be placed side by side with the super chip. Such connections can be long, so the super chip is not required to be thin. Also, if through-substrate vias (TSVs) are omitted, the manufacturing yield is high and the manufacturing cost is low. Other structures are provided that combine the short and long direct connections to obtain desired physical and electrical properties.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: December 25, 2018
    Assignee: Invensas Corporation
    Inventors: Liang Wang, Rajesh Katkar, Hong Shen