Abstract: A method for fabricating a multiple MEMS device includes providing a semiconductor substrate having a first and second MEMS device, and an encapsulation wafer with a first cavity and a second cavity, which includes at least one channel. The first MEMS is encapsulated within the first cavity and the second MEMS device is encapsulated within the second cavity. These devices is encapsulated within a first encapsulation environment at a first air pressure, and encapsulating the first MEMS device within the first cavity at the first air pressure. The second MEMS device within the second cavity is then subjected to a second encapsulating environment at a second air pressure via the channel of the second cavity.

Abstract: Various embodiments of the present disclosure relate to a semiconductor device package including a carrier, an electrical component, an antenna, a conductive pad and a conductive line. The carrier includes a top surface. The electrical component is disposed over the top surface of the carrier. The antenna is disposed over the top surface of the carrier and spaced away from the electrical component. The conductive pad is disposed over the top surface of the carrier and beneath the antenna, wherein the conductive pad includes a resonant structure. The conductive line is electrically connected to the electrical component and extends within the carrier. A part of the conductive line is beneath the antenna and the resonant structure of the conductive pad.

Abstract: An apparatus and method for wafer-level hermetic packaging of MicroElectroMechanical Systems (MEMS) devices of different shapes and form factors is presented in this disclosure. The method is based on bonding a glass cap wafer with fabricated micro-glassblown “bubble-shaped” structures to the substrate glass/Si wafer. Metal traces fabricated on the substrate wafer serve to transfer signals from the sealed cavity of the bubble to the outside world. Furthermore, the method provides for chip-level packaging of MEMS three dimensional structures. The packaging method utilizes a micro glass-blowing process to create “bubbleshaped” glass lids. This new type of lids is used for vacuum packaging of three dimensional MEMS devices, using a standard commercially available type of package.

Abstract: A heater includes a ceramic body having a pillar or cylindrical shape; a heat generating resistor disposed in an interior of the ceramic body; a metallic layer which is disposed on an outer peripheral surface of the ceramic body and extends along a circumferential direction thereof; a flange bonded to the metallic layer via a bonding material, the bonding material including a meniscus part extending from the metallic layer to the flange; and a metallic wire which is disposed in an interior of the meniscus part on the outer peripheral surface of the ceramic body and extends along the circumferential direction.

Abstract: In a multi-chip module (MCM), a “super” chip (110N) is attached to multiple “plain” chips (110F? “super” and “plain” chips can be any chips). The super chip is positioned above the wiring board (WB) but below at least some of plain chips (110F). The plain chips overlap the super chip. Further, the plain chips' low speed IOs can be connected to the WB by long direct connections such as bond wires (e.g. BVAs) or solder stacks; such connections can be placed side by side with the super chip. Such connections can be long, so the super chip is not required to be thin. Also, if through-substrate vias (TSVs) are omitted, the manufacturing yield is high and the manufacturing cost is low. Other structures are provided that combine the short and long direct connections to obtain desired physical and electrical properties.

Abstract: The heat conduction member comprises a laminate formed by laminating a resin layer and a metal layer. The resin layer is formed from a thermally conductive resin material. The thickness of the laminate is smaller at the peripheral edge of the laminate than in the center portion of the laminate, and the thickness of the laminate is greater in the intermediate portion of the laminate than in the center portion of the laminate. An inclined surface is formed on the laminate so as to form a falling gradient from the intermediate portion toward the peripheral edge.

Abstract: A package structure includes a lead frame, an insulator, a plurality of conductive vias, a patterned metal layer, and a chip. The lead frame includes a plurality of contacts. The insulator covers the lead frame. The conductive vias are disposed on the insulator and connected to the contacts. The patterned metal layer covers an outer surface of the insulator and includes a groove and a circuit portion. The circuit portion is connected to and covers the conductive vias and contacts. The groove surrounds the circuit portion such that the circuit portion is electrically insulated from the rest of the patterned metal layer. A surface of the insulator exposed by the groove is lower than the outer surface. The chip is disposed on the insulator and electrically connected to the circuit portion.

Abstract: A light-emitting device includes first and second lead frames spaced apart from each other, the first and second lead frames each including a top surface, an opposing bottom surface, and sidewalls arranged between the top surface and the bottom surface thereof, in which at least one of the first and second lead frames include three inset sidewalls that at least partially define a fixing space, the fixing space undercutting at least one of the first lead frame and second lead frame, a light-emitting diode chip disposed on the top surface of the first or second lead frame, and the top surfaces of the first and second lead frames are substantially flat.

Abstract: A chip package is provided, the chip package including: a chip carrier; a chip disposed over and electrically connected to a chip carrier top side; an electrically insulating material disposed over and at least partially surrounding the chip; one or more electrically conductive contact regions formed over the electrically insulating material and in electrical connection with the chip; a further electrically insulating material disposed over a chip carrier bottom side; wherein an electrically conductive contact region on the chip carrier bottom side is released from the further electrically insulating material.

Abstract: A semiconductor structure includes a substrate including a plurality of vias passing through the substrate and filled with a conductive or semiconductive material, and an oxide layer surrounding the conductive or semiconductive material, the substrate defining a cavity therein; a membrane disposed over the substrate and the cavity; a heater disposed within the membrane and electrically connected with the substrate; and a sensing electrode disposed over the membrane and the heater.

Abstract: A liquid discharge head includes an element substrate to which an electric signal is supplied, an electrical wiring board that is connected to the element substrate and that is capable of supplying the electric signal to the element substrate, and a printed circuit board that includes a wiring line and an insulating layer covering the wiring line and that is capable of supplying the electric signal to the element substrate via the wiring line. A protruding structure that has a thickness approximately equal to a thickness of the wiring line and that is covered with the insulating layer is disposed along the wiring line on the printed circuit board, and a portion of the electrical wiring board is bonded to a portion of the insulating layer located on the wiring line disposed on the printed circuit board.

Abstract: Packaged semiconductor devices and methods of packaging semiconductor devices are disclosed. In some embodiments, a packaged semiconductor device includes an integrated circuit die, a molding compound disposed around the integrated circuit die, and an interconnect structure disposed over the integrated circuit die and the molding compound. The molding compound is thicker than the integrated circuit die.

Abstract: A method is provided for attaching components to pads on a PCB, where total accumulated tolerances are reduced by separating accumulated tolerances into multiple processes. The method includes performing first and second processes having first and second accumulated tolerances, respectively. The first process includes placing a first stencil over the PCB, the first stencil defining first apertures corresponding to the pads; printing solder paste onto the pads using the first stencil; and reflowing the printed solder paste to form corresponding solder bumps on the pads. The second process includes placing a second stencil over the PCB, the second stencil defining second apertures corresponding to the pads; printing flux onto the solder bumps using the second stencil; placing at least one component on the printed flux; and reflowing the printed flux and the solder bumps to form corresponding solder joints between the at least one component and the first pads, respectively.

Abstract: There is provided a flexible display having a plurality of innovations configured to allow bending of a portion or portions to reduce apparent border size and/or utilize the side surface of an assembled flexible display.

Abstract: Provided is a semiconductor device including: a first external electrode which includes a circular outer peripheral portion; a MOSFET chip; a control circuit chip which receives voltages of a drain electrode and a source electrode of the MOSFET and supplies a signal to a gate electrode to control the MOSFET on the basis of the voltage; a second external electrode which is disposed on an opposite side of the first external electrode with respect to the MOSFET chip and includes an external terminal on a center axis of the circular outer peripheral portion of the first external electrode; and an isolation substrate which isolates the control circuit chip from the external electrode. The first external electrode, the drain electrode and the source electrode of the MOSFET chip, and the second external electrode are disposed to be overlapped in a direction of the center axis. The drain electrode of the MOSFET chip and the first external electrode are connected.

Abstract: A circuit board structure includes a multi-layer board and a ceramic resistor embedded in the multi-layer board. The ceramic resistor includes a ceramic sheet, a plurality of connecting pads spacedly arranged on the ceramic sheet, and a plurality of resistance layers arranged on the ceramic sheet. At least one of the resistance layers is arranged between and electrically connected to any two of the connecting pads for providing a resistance value. The number of the resistance values provided by the ceramic resistor is more than the number of the resistance layers. The multi-layer board has a plurality of contacts arranged apart from each other, and the contacts are respectively and electrically connected to the connecting pads.

Abstract: A printed circuit board includes chip regions on which semiconductor chips are mounted, and a scribe region surrounding each of the chip regions. The scribe region includes first vent holes that are configured to receive a flow of molding resin and are arranged along a first direction corresponding to a flow direction of the molding resin.

Abstract: A package structure includes a substrate, a sensor, a base, a lead frame, conductive vias and patterned circuit layer. The substrate includes a component-disposing region and electrode contacts. The sensor is disposed at the component-disposing region and electrically connected to the electrode contacts. The base covers the substrate with its bonding surface and includes a receiving cavity, a slanted surface extended between a bottom surface of the receiving cavity and the bonding surface, and electrodes disposed on the bonding surface and electrically connected to the electrode contacts respectively. The sensor is located in the receiving cavity. The lead frame is disposed at the base. The conductive vias penetrates the base and electrically connected to the lead frame. The patterned circuit layer is disposed on the slanted surface and electrically connected to the conductive vias and the electrodes.

Abstract: Disclosed are apparatus and methods related to ground paths implemented with surface mount devices to facilitate shielding of radio-frequency (RF) modules. In some embodiments, a module can include a packaging substrate configured to receive a plurality of components. The module can further include an RF component mounted on the packaging substrate and configured to facilitate processing of an RF signal. The module can further include an RF shield disposed relative to the RF component, with the RF shield being configured to provide shielding for the RF component. The RF shield can include at least one shielding-component configured to provide one or more electrical paths between a conductive layer on an upper surface of the module and a ground plane of the packaging substrate. The shielding-component can include a surface-mount device such as an RF filter implemented as a chip size surface acoustic wave (SAW) device (CSSD).

Abstract: Provided is a bonding wire for a semiconductor package and a semiconductor package including the same. The bonding wire for the semiconductor package may include a core portion including silver (Ag), and a shell layer surrounding the core portion, having a thickness of 2 nm to 23 nm, and including gold (Au). The semiconductor package may include a package body having a first electrode structure and a second electrode structure, a semiconductor light emitting device comprising a first electrode portion and a second electrode portion electrically connected to the first electrode structure and the second electrode structure, and a bonding wire connecting at least one of the first electrode structure and the second electrode structure to the semiconductor light emitting device.

Abstract: Light emitting devices and methods for their manufacture are provided. According to one aspect, a light emitting device is provided that comprises a substrate having a recess, and an interlayer dielectric layer located on the substrate. The interlayer dielectric layer may have a first hole and a second hole, the first hole opening over the recess of the substrate. The light emitting device may further include first and second micro LEDs, the first micro LED having a thickness greater than the second micro LED. The first micro LED and the second micro LED may be placed in the first hole and the second hole, respectively.

Abstract: A flexible display apparatus including: a first film including a first surface and a second surface that are opposite each other, and a first groove formed in the first surface, the first film having a first rigidity; a third film on the second surface of the first film; a fourth film facing the third film; an emission display unit between and encapsulated by the third film and the fourth film; and a second film on the fourth film and facing the first film, the second film having a second rigidity that is less than the first rigidity.

Abstract: A semiconductor package structure and a method for making a semiconductor package. As non-limiting examples, various aspects of this disclosure provide various semiconductor package structures, and methods for making thereof, that comprise a connect die that routes electrical signals between a plurality of other semiconductor die.

Abstract: A package structure includes a substrate, at least one electronic component, a housing and at least one strut. The at least one electronic component is disposed on a first surface of the substrate. The housing covers the first surface of the substrate. The housing has an accommodation space. The at least one electronic component is accommodated within the accommodation space. The at least one strut is protruded from an inner surface of the housing and extended toward the accommodation space. The at least one elastomer is arranged between the corresponding strut and the substrate.

Abstract: An embodiment is a semiconductor device comprising a first bond pad on a first substrate, the first bond pad having a first center line through a center of the first bond pad and orthogonal to a top surface of the first substrate, and a first conductive connector on a second substrate, the first conductive connector having a second center line through a center of the first conductive connector and orthogonal to a top surface of the second substrate, the second substrate over the first substrate with the top surface of the first substrate facing the top surface of the second substrate. The semiconductor device further comprises a first alignment component adjacent the first bond pad on the first substrate, the first alignment component configured to align the first center line with the second center line.

Abstract: MEMS device for low resistance applications are disclosed. In a first aspect, the MEMS device comprises a MEMS wafer including a handle wafer with one or more cavities containing a first surface and a second surface and an insulating layer deposited on the second surface of the handle wafer. The MEMS device also includes a device layer having a third and fourth surface, the third surface bonded to the insulating layer of the second surface of handle wafer; and a metal conductive layer on the fourth surface. The MEMS device also includes CMOS wafer bonded to the MEMS wafer. The CMOS wafer includes at least one metal electrode, such that an electrical connection is formed between the at least one metal electrode and at least a portion of the metal conductive layer.

Abstract: A semiconductor device has a first substrate. A conductive layer is formed over the first substrate. A first cavity is formed through the first substrate and extending to the conductive layer. A first semiconductor die including a plurality of first interconnect structures is disposed in the first cavity. A second substrate is disposed over the first substrate. A second cavity is formed through second substrate. A second semiconductor die including a plurality of second interconnect structures is disposed in the second cavity. A discrete device or third semiconductor die is disposed over the second semiconductor die. A plurality of third interconnect structures is formed between the second substrate and discrete device or third semiconductor die. The first, second, and third interconnect structures are reflowed simultaneously. An encapsulant is deposited over and around the first semiconductor die, the second semiconductor die, and the discrete device or third semiconductor die.

Abstract: A package includes a device die, which includes a metal pillar at a top surface of the device die, and a solder region on a sidewall of the metal pillar. A molding material encircles the device die, wherein a top surface of the molding material is substantially level with a top surface of the device die. A dielectric layer overlaps the molding material and the device die, with a bottom surface of the dielectric layer contacting a top surface of the device die and a top surface of the molding material. A redistribution line (RDL) extends into the dielectric layer to electrically couple to the metal pillar.

Abstract: Embodiments of the present disclosure include interconnect structures and methods of forming interconnect structures. An embodiment is a method of forming an interconnect structure, the method including forming a first post-passivation interconnect (PPI) over a first substrate, forming a second PPI over the first substrate, and forming a first conductive connector on the first PPI. The method further includes forming a second conductive connector on the second PPI, and forming a molding compound on top surfaces of the first and second PPIs and surrounding portions of the first and second connectors, a first section of molding compound being laterally between the first and second connectors, the first section of molding compound having a curved top surface.

Abstract: Methods for an embedded die panel are disclosed and may include fabricating a first layered structure by: forming first redistribution layers on a first carrier, forming a first dielectric layer on the first redistribution layers and carrier, forming a mask pattern on the first dielectric layer exposing a portion of the first dielectric layer, forming a second dielectric layer on the exposed portion of the first dielectric layer, forming vias in the first and second dielectric layers, and forming second redistribution layers on the second dielectric layer. The mask pattern may be removed forming a die cavity defined by the second dielectric layer. A second layered structure coupled to the first layered structure may be formed comprising a second carrier, a third dielectric layer, third and fourth redistribution layers on opposite surfaces of the third dielectric layer, and a semiconductor die.

Abstract: A semiconductor structure includes a first device and a second device. The first device includes a first substrate, a plurality of vias passing through the first substrate and filled with a conductive or semiconductive material and a first oxide layer surrounding the conductive or semiconductive material, a cavity surrounded by the first substrate, a metallic material disposed over the first surface, a second oxide layer disposed over the second surface, a membrane disposed over the second oxide layer and the cavity, a heater disposed within the membrane, a sensing electrode disposed over the membrane and the heater, and a sensing material disposed over the cavity and contacting with the sensing electrode. The second device includes a second substrate, and a bonding structure disposed over the second substrate. The metallic material is bonded with the bonding structure to integrate the first device with the second device.

Abstract: First electrode pads formed on one semiconductor package surface include a first reinforcing electrode pad having a surface area larger than that of other first electrode pads. Second electrode pads formed on a printed wiring board on which the semiconductor package is mounted include at least one second reinforcing electrode pad. The second reinforcing electrode pad opposes the first reinforcing electrode pad, and has a surface area greater than that of the other second electrode pads. The first and second electrode pads are connected by solder connection parts. A cylindrical enclosing member encloses an outer perimeter of a solder connection part connecting the first and second reinforcing electrode pads. Increases in the amount of warping of semiconductor devices such as the package substrate and the printed wiring board are suppressed, and the development of solder bridges with respect to adjacent solder connecting parts or adjacent components is reduced.

Abstract: A semiconductor device comprises a substrate, a source region over the substrate, and a guard ring over the substrate. The guard ring is separated from the source region by a first spacing. The semiconductor device also comprises a first heat conductive layer formed over couples the source region and the guard ring. The semiconductor device further comprises a first via over a first portion of the first heat conductive layer. The semiconductor device additionally comprises a second via separate from the first via over a second portion of the first conductive layer. The semiconductor device also comprises a second heat conductive layer over and coupling the first via and the second via. In use, the semiconductor device generates heat, and the heat dissipates, at least partially, from the source region through the first heat conductive layer to the guard ring and the substrate.

Abstract: A method of manufacturing a cover structure is provided. A first insulating layer is provided. The first insulating layer has a first surface and a second surface opposite to each other. A second insulating layer is provided. The second insulating layer has a third surface and a fourth surface opposite to each other and an opening passing through the third surface and the fourth surface. A thickness of the second insulating layer is greater than a thickness of the first insulating layer. The first insulating layer and the second insulating layer are laminated to each other, so that the third surface of the second insulating layer connects to the second surface of the first insulating layer. A cavity is defined by the opening of the second insulating layer and the first insulating layer. A metal layer is formed on the cavity.

Abstract: Methods for the fabrication of a Microelectromechanical Systems (“MEMS”) devices are provided, as are MEMS devices. In one embodiment, the MEMS device fabrication method includes forming at least one via opening extending into a substrate wafer, depositing a body of electrically-conductive material over the substrate wafer and into the via opening to produce a via, bonding the substrate wafer to a transducer wafer having an electrically-conductive transducer layer, and forming an electrical connection between the via and the electrically-conductive transducer layer. The substrate wafer is thinned to reveal the via through a bottom surface of the substrate wafer, and a backside conductor is produced over a bottom surface of the substrate wafer electrically coupled to the via.

Abstract: A cache memory die includes a substrate, a predetermined number of sets of memory cells on the substrate, a first set of input/output terminals on a first surface of the cache memory die, and a second set of input/output terminals on a second surface of the cache memory die. The first set of input/output terminals are connected to a primary memory circuit outside the cache memory die. A portion of the second set of input/output terminals are compatible with the first set of input/output terminals.

Abstract: Techniques for packaging an integrated circuit include attaching a die to a conductive layer before forming dielectric layers on an opposing surface of the conductive layer. The conductive layer may first be formed on a carrier substrate before the die is disposed on the conductive layer. The die may be electrically coupled to the conductive layer via wires or solder bumps. The carrier substrate is removed before the dielectric layers are formed. The dielectric layers may collectively form a coreless package substrate for the integrated circuit package.

Abstract: A chip-on-film package includes a base film including a bending area, an integrated circuit chip at an upper surface of the base film, a first line at the upper surface of the base film and overlapping the bending area, a second line at a lower surface of the base film and overlapping the bending area, a via pattern penetrating the base film to electrically couple the first line and the second line, and a common line coupled to the first line and to the integrated circuit chip, wherein at least a portion of the first line does not overlap at least a portion of the second line in a plan view.

Abstract: An electronic component includes a base substance, a cooling channel formed in the base substance and flows a cooling medium in a second direction from a first direction, a radiator formed in a surface of the cooling channel using a material of which thermal conductivity is higher than a thermal conductivity of the base substance or formed so that the radiator may project to the cooling channel, and that contacts the cooling medium.

Abstract: A method of fabricating a device includes forming a moveable plate over a substrate. The method further includes forming an energy harvesting coil in the moveable plate. The method further includes forming at least one connector connecting the movable plate with the substrate, wherein a portion of the energy harvesting coil extends along the at least one connector. The method further includes enclosing the movable plate using a capping wafer.

Abstract: A method of making a semiconductor package with package-on-package stacking capability is characterized by the step of attaching a chip-on-interposer subassembly on a base carrier with the chip inserted into a through opening of the base carrier and the interposer laterally extending beyond the through opening. The interposer provides primary fan-out routing for the chip whereas dual buildup circuitries formed on both opposite sides of the base carrier provides further fan-out routing and are electrically connected to each other by plated through holes to provide the package with stacking capacity.

Abstract: Methods for fabricating stacked microelectronic packages are provided, as are embodiments of a stacked microelectronic package. In one embodiment, the method includes arranging a plurality of microelectronic device panels in a panel stack. Each microelectronic device panel contains plurality of microelectronic devices and a plurality of package edge conductors extending therefrom. Trenches are created in the panel stack exposing the plurality of package edge conductors, and a plurality of sidewall conductors is formed interconnecting different ones of the package edge conductors exposed through the trenches. The panel stack is then separated into a plurality of stacked microelectronic packages each including at least two microelectronic devices electrically interconnected by at least one of the plurality of sidewall conductors included within the stacked microelectronic package.

Abstract: Methods for fabricating stacked microelectronic packages are provided, as are embodiments of a stacked microelectronic package. In one embodiment, the method includes arranging a plurality of microelectronic device panels in a panel stack. Each microelectronic device panel contains plurality of microelectronic devices and a plurality of package edge conductors extending therefrom. Trenches are created in the panel stack exposing the plurality of package edge conductors, and a plurality of sidewall conductors is formed interconnecting different ones of the package edge conductors exposed through the trenches. The panel stack is then separated into a plurality of stacked microelectronic packages each including at least two microelectronic devices electrically interconnected by at least one of the plurality of sidewall conductors included within the stacked microelectronic package.

Abstract: An integrated chip package structure and method of manufacturing the same is by adhering dies on a silicon substrate and forming a thin-film circuit layer on top of the dies and the silicon substrate. Wherein the thin-film circuit layer has an external circuitry, which is electrically connected to the metal pads of the dies, that extends to a region outside the active surface of the dies for fanning out the metal pads of the dies. Furthermore, a plurality of active devices and an internal circuitry is located on the active surface of the dies. Signal for the active devices are transmitted through the internal circuitry to the external circuitry and from the external circuitry through the internal circuitry back to other active devices. Moreover, the chip package structure allows multiple dies with different functions to be packaged into an integrated package and electrically connecting the dies by the external circuitry.

Abstract: An integrated passives package includes an encapsulation compound and a plurality of electrically conductive pads embedded in the encapsulation compound. Each of the pads has opposing first and second sides. The first side of the pads is uncovered by the encapsulation compound and forms array of external electrical connections at a first side of the package. The integrated passives package further includes a plurality of passive components embedded in the encapsulation compound. Each of the passive components has a first terminal attached to one of the pads and a second terminal attached to a different one the pads at the second side of the pads. Corresponding semiconductor modules and methods of manufacturing are also provided.

Abstract: Embodiments of a method for fabricating stacked microelectronic packages are provided, as are embodiments of a stacked microelectronic package. In one embodiment, the method includes arranging microelectronic device panels in a panel stack. Each microelectronic device panel includes a plurality of microelectronic devices and a plurality of package edge conductors extending therefrom. Trenches are formed in the panel stack exposing the plurality of package edge conductors. An electrically-conductive material is deposited into the trenches and contacts the plurality of package edge conductors exposed therethrough. The panel stack is then separated into partially-completed stacked microelectronic packages. For at least one of the partially-completed stacked microelectronic packages, selected portions of the electrically-conductive material are removed to define a plurality of patterned sidewall conductors interconnecting the microelectronic devices included within the stacked microelectronic package.

Abstract: In one embodiment, there is provided a heat radiating component. The heat radiating component includes: a base material made mainly of copper; an electroplated aluminum layer that covers at least a part of a surface of the base material; and an alumite layer formed on the electroplated aluminum layer and formed by anodic-oxidizing the electroplated aluminum layer.

Abstract: A power semiconductor device may comprise: a lower structure; a solder layer on the lower structure; a semiconductor structure on the solder layer; a contact layer on the semiconductor structure; a pad layer on the contact layer; and/or a wire between the pad layer and the lower structure. The solder layer may be electrically connected to a first electrode of the semiconductor structure.

Abstract: Light-emitting semiconductor packages and related methods. The light-emitting semiconductor package includes a central barrier, a plurality of leads, a light-emitting device, a first encapsulant, a package body, and a second encapsulant. The light-emitting device is disposed in the interior space defined by the central barrier and is electrically connected to the leads surrounding the central barrier. The light-emitting device includes upper and lower light-emitting surfaces. The first encapsulant and the second encapsulant cover the upper and lower light-emitting surfaces, respectively. The package body encapsulates portions of the central barrier, portions of each of the leads, and the first encapsulant. The light-emitting semiconductor package can emit light from both the upper and lower sides thereof.

Abstract: According to an exemplary embodiment, a monolithic power converter package includes a monolithic die over a substrate, the monolithic die integrating a driver integrated circuit (IC) with a control power transistor and a sync power transistor connected in a half-bridge. A high side power input, a low side power input, and a power output of the half-bridge are each disposed on a top surface of the monolithic die. The high side power input is electrically and mechanically coupled to the substrate by a high side power strip. Also, the low side power input is electrically and mechanically coupled to the substrate by a low side power strip. Furthermore, the power output is electrically and mechanically coupled to the substrate by a power output strip.