Abstract: A method of forming an actuator and a relay using a micro-electromechanical (MEMS)-based process is disclosed. The method first forms the lower sections of a square copper coil, and then forms an actuation member that includes a core section and a horizontally adjacent floating cantilever section. The core section, which lies directly over the lower coil sections, is electrically isolated from the lower coil sections. The method next forms the side and upper sections of the coil, along with first and second electrodes that are separated by a switch gap. The first electrode lies directly over an end of the core section, while the second electrode lies directly over an end of the floating cantilever section.

Abstract: An integrally packaged integrated circuit device including an integrated circuit die including a crystalline substrate having first and second generally planar surfaces and edge surfaces and an active surface formed on the first generally planar surface, at least one chip scale packaging layer formed over the active surface and at least one electrical contact formed over the at least one chip scale packaging layer, the at least one electrical contact being connected to circuitry on the active surface by at least one pad formed on the first generally planar surface.

Abstract: This invention is directed to offer a semiconductor device in which a cavity space is easily provided in a specific region when a supporting member is bonded to a semiconductor substrate through an adhesive layer, and its manufacturing method. A resist layer is applied to an entire top surface of the semiconductor substrate 2, and exposure to transfer a pattern is performed. By subsequent development and selective removal of the resist layer, the resist layer is formed into a shape of a plurality of columnar structures 4. Then, an adhesive material made of an epoxy resin or the like is applied to the entire top surface of the semiconductor substrate 2. The adhesive material is gathered around the columnar structures 4 by itself to form an adhesive layer 5. Therefore, in contrast, the adhesive layer 5 does not deposit in a region where the cavity is to be formed. Then, the supporting member 6 is bonded through the columnar structures 4 and the adhesive layer 5.

Abstract: The present invention provides a semiconductor device, including: a semiconductor substrate having a circuit formed thereon; a mounting substrate cemented to a rear face of the semiconductor substrate; a plurality of pads arranged in a linearly juxtaposed relationship with each other in a direction perpendicular to a peripheral edge side of the semiconductor substrate which is nearest to the pads on a main face of the semiconductor substrate and electrically connected to the circuit in a corresponding relationship to a signal, a power supply voltage and a reference signal; a plurality of wires individually cemented at one end thereof to the pads; and a plurality of wire cemented elements formed on the mounting substrate and cemented to the other end of the wires.

Abstract: A semiconductor package is disclosed. In one embodiment, the semiconductor package includes a leadframe including a chip position and a plurality of leadfingers. Each leadfinger includes a cutout in an inner edge providing a chip recess. The semiconductor package further includes a semiconductor chip located in the chip recess. The semiconductor chip has an active surface with a plurality of chip contact pads on each of which an electrically conductive bump is disposed. The inner portions of the leadfingers protrude into the chip position and are electrically connected to the chip contact pads by electrically conductive bumps.

Abstract: A shielded package includes a shield assembly having a shield fence, a shield lid, and a shield lid adhesive electrically coupling the shield lid to the shield fence. The shield fence includes a porous sidewall through which molding compound passes during molding of the shielded package. Further, the shield fence includes a central aperture through which an electronic component is die attached and wire bonded.

Abstract: An optical device package comprises: a metal frame including a substrate and a rectangular die pad portion integrally connected to the substrate, wherein the substrate is a metal plate, and the die pad portion is bent from the substrate such that the die pad portion extends from the substrate at an angle of 90 degrees; signal lead pins extend in the opposite direction from the die pad portion relative to the substrate such that the first lead pins intersect the principal surfaces of the substrate at a right angle and are spaced apart from the metal frame; and a molded resin member including a plate-like resin base extending across and in close contact with one of the principal surfaces of the substrate, wherein the signal lead pins protrude from a surface of the resin base; surfaces of the signal lead pins are covered with the molded resin member; and the metal frame and the signal lead pins are secured in place by the molded resin member.

Abstract: This describes a procedure for replicative fabrication and packaging of at least one microstructured molded part as one magazine/molded part composite as well as a magazine with at least one microstructured molded part as one magazine/molded part composite. The first step covers fabrication of at least one microstructured molded part using an initially closed tool which consists of at least one first and one second tool half. In the second step, both tool halves are opened, whereby the molded part remains in the first tool half. In the third step, at least the second tool half is replaced with at least one additional tool half. In the fourth step, the replicative fabrication of the magazine is carried out using the first tool half containing the molded part and the additional tool half. Finally in the fifth step, magazine and molded part are demolded simultaneously as one magazine/molded part composite.

Abstract: In one embodiment, an edge seal region of a semiconductor die is formed by forming a first dielectric layer on a surface of a semiconductor substrate near an edge of the semiconductor die and extending across into a scribe grid region of the semiconductor substrate. Another dielectric layer is formed overlying the first dielectric layer. An opening is formed through the first and second dielectric layers. The second dielectric layer is used as a mask for forming a doped region on the semiconductor substrate through the opening. A metal is formed that electrically contacts the doped region and an exterior edge of the first dielectric layer within the opening.

Abstract: A miniaturized semiconductor device has a package substrate, a semiconductor chip mounted on the main surface of the package substrate and having plural LNAs each for amplifying a signal, an RF VCO for converting the frequency of the signal supplied from each LNA, and an IF VCO for converting the frequency of a signal supplied from a baseband. A plurality of ball electrodes are provided on the back surface of the package substrate. The package substrate is provided with a first common GND wire for supplying a GND potential to each of the LNAs, with a second common GND wire for supplying the GND potential to the RF VCO, and with a third common GND wire for supplying the GND potential to the IF VCO. The first, second, and third common GND wires are separated from each other.

Abstract: A semiconductor device is provided which comprises a heat-radiative support plate 5; and first and second semiconductor elements 1 and 2 mounted and layered on support plate 5 for alternate switching of first and second semiconductor elements 1 and 2. The arrangement of piling and securing first and second semiconductor elements 1 and 2 on support plate 5 improves integration degree of semiconductor elements 1 and 2, and reduces the occupation area on support plate 5. Alternate switching of first and second semiconductor elements 1 and 2 controls heat produced from first and second semiconductor elements 1 and 2 because one of first and second semiconductor elements 1 and 2 is turned on, while the other is turned off.

Abstract: A first semiconductor element and a second semiconductor element each have an electrode forming surface with an electrode pad thereon. The first semiconductor element and the second semiconductor element are stacked to expose each electrode pad and bonded while facing the electrode forming surfaces each other. The electrode pads of the first and second semiconductor elements are connected to the first and second connection terminals via bonding wires. A metal circuit board including the first and second connection terminals, and the first and second semiconductor elements are sealed by a sealing material such that parts of the respective connection terminals expose.

Abstract: An elongated light source (50) comprises a subassembly (51) including a base (54), a light engine (10) positioned in mounting means (56) formed with the base; a light guide (58) positioned in spaced apart supports (57), and a cover (62) fixed to the base (54). The light engine (10) comprises a thermally conductive substrate (12) having a dielectric (14) on one side thereof; upper and lower lens guards, (16, 18), respectively, positioned near one end (20) of the substrate (12); at least one LED (22) mounted on the substrate between the lens guards (16, 18); and electrical conductors (24, 26) mounted upon the substrate at another end (28) thereof for supplying power to the LED (22).

Abstract: A cap wafer with cavities is etched through areas not covered by a patterned photoresist to form a plurality of openings. The cap wafer is bonded to a transparent wafer at the surface having the cavities and is segmented around the cavities to form a plurality of cap structures. The cap structures are hermetically sealed to a device wafer to form hermetic windows over devices and pads located on the device wafer.

Abstract: The semiconductor chip 1 has a semiconductor substrate 10. In the present embodiment, the semiconductor substrate 10, which is an SOI substrate, is constituted by comprising a support substrate 12, an insulating layer 14 formed on the support substrate 12 with a layered structure, and a silicon layer 16 formed on the insulating layer 14 with the layered structure. The semiconductor substrate 10 has a circuit forming region A1 provided in the silicon layer 16. An insulating region 18 is provided on the semiconductor substrate 10. The insulating region 18 is provided so as to surround the entire side face of the circuit forming region A1.

Abstract: A chip package includes a coreless package substrate and a chip. The coreless package substrate includes an interconnection structure and a ceramic stiffener. The interconnection structure has a first inner circuit, a carrying surface and a corresponding contact surface. The first inner circuit has multiple contact pads disposed on the contact surface. The ceramic stiffener is disposed on the carrying surface and has a first opening. In addition, the chip is disposed on the carrying surface and within the first opening and electrically connected to at least one of the contact pads.

Abstract: A semiconductor device and method has trenches for raising reliability. An electrode pad, with a protective film and an interlayer film which form an opening on top, are on a substrate. A rewiring pattern in contact with the electrode pad at this opening is on top of the interlayer film. A trench is etched outside the rewiring pattern. A bump is formed on top of the rewiring pattern. The rewiring pattern and the trench are covered by a sealing film that that exposes the upper end of the bump. An external terminal is formed on top of the bump. The trenches increase contact area and adhesion between the covering film and the sealing film. The rougher the surface of the trench the better the adhesion, which makes the sealing film stick better and the semiconductor device more reliable.

Abstract: A hermetic interconnect is fabricated on a substrate by forming a stud of conductive material over a metallization layer, and then overcoating the stud of conductive material and the metallization layer with a layer of compliant dielectric material. In one embodiment, the layer of compliant dielectric material is low Young's modulus silicon dioxide, formed by sputter-deposition at low temperature, in a low pressure argon atmosphere. The interconnect may provide electrical access to a micromechanical device, which is enclosed with a capping wafer hermetically sealed to the substrate with an AuInx alloy bond.

Abstract: A package system for integrated circuit (IC) chips and a method for making such a package system. The method uses a solder-ball flip-chip method for connecting the IC chips onto a lead frame that has pre-formed gull-wing leads only on the source/gate side of the chip. A boschman molding technique is used for the encapsulation process, leaving exposed land and die bottoms for a direct connection to a circuit board. The resulting packaged IC chip has the source of the chip directly connected to the lead frame by solder balls. As well, the drain and gate of the chip are directly mounted to the circuit board without the need for leads from the drain side of the chip.

Abstract: A semiconductor die includes a plurality of interconnection pads for connecting with a memory die. The two dies are packaged together in a stacked manner. The plurality of pads are disposed so that the circuit layout of the semiconductor die is invariable with respect to the size of the memory die within a given range of sizes.

Abstract: Methods for reducing stress in microelectronic devices and microelectronic devices formed using such methods are disclosed herein. One such device can include a first support member, a second support member, and a microelectronic die positioned between the first support member and the second support member such that the second support member at least approximately completely covers a surface of the die. The die is in intimate contact with both the first support member and the second support member and electrically coupled to at least one of the first support member and the second support member. The device further includes a fill material between the first and second support members and at least partially encapsulating the die. The second support member has structural material characteristics that are closer to those of the first support member than to the structural material characteristics of the fill material.

Abstract: An electronic component includes a vertical semiconductor power transistor and a further semiconductor device arranged on the transistor to form a stack. The first vertical semiconductor power transistor has a semiconductor body having a first side and a second side and device structures, at least one first electrode positioned on the first side and at least one second electrode positioned on the second side. The semiconductor body further has at least one electrically conductive via. The via extends from the first side to the second side of the semiconductor body and is galvanically isolated from the device structures of the semiconductor body and from the first electrode and the second electrode.

Abstract: A method of (and heat spreader for) dissipating heat from a heat source, includes providing a plurality of heat flux paths from the heat source, to remove the heat from the heat source.

Abstract: A multi-leadframe semiconductor package and method of manufacture includes a first leadframe having a die pad and a plurality of contact leads around the periphery of the die pad. A die is attached to the die pad and electrically connected to the plurality of contact leads. A heat spreader leadframe having a heat spreader and a plurality of terminal leads around the periphery of the heat spreader is provided. The die pad is attached to the heat spreader, and the plurality of contact leads is attached to the plurality of terminal leads.

Abstract: Example embodiments may provide a camera module including a high-resolution lens member and/or an image sensor chip that may be integrally formed, and a method of fabricating a camera module. Example embodiment camera modules may include a semiconductor package including an image sensor chip. A transparent substrate may include an upper plate portion and/or a supporting portion defined by a cavity under the upper plate portion, and the supporting portion may be attached on the semiconductor package. The upper plate portion may be spaced from the semiconductor package by the supporting portion. A lens member may be attached to the upper plate portion of the transparent substrate. A stop member may be formed on a top side of the transparent substrate and may expose a portion of the lens member.

Abstract: [Problems] To provide a package for light emitting element accommodation that realizes enhanced reflectance without application of a metal plating onto a ceramic. [Means for Solving Problems] There is provided a package for light emitting element accommodation comprising ceramic substrate (2) having conductor mounting region (8) for mounting of light emitting element (1) on its upper surface; frame (4) of a light reflecting material containing 74.6 mass % or more of alumina whose average particle diameter after sintering is 2.5 ?m or less, the frame (4) disposed on an upper surface of the substrate (2) in such a fashion that internal circumferential surface (7) of through-hole (3) expands outward; and light emitting element (1) mounted on the conductor mounting region (8) of the substrate (2). Thus, the reflectance of the frame (4) is enhanced without application of a metal plating thereonto.

Abstract: Methods and structures for monolithically integrating monocrystalline silicon and monocrystalline non-silicon materials and devices are provided. In one structure, a monolithically integrated semiconductor device structure comprises a silicon substrate and a first monocrystalline semiconductor layer disposed over the silicon substrate, wherein the first monocrystalline semiconductor layer has a lattice constant different from a lattice constant of relaxed silicon. The structure further includes an insulating layer disposed over the first monocrystalline semiconductor layer in a first region and a monocrystalline silicon layer disposed over the insulating layer in the first region. The structure includes at least one silicon-based electronic device including an element including at least a portion of the monocrystalline silicon layer.

Abstract: A semiconductor package having improved adhesiveness between the chip paddle and the package body and having improved ground-bonding of the chip paddle. A plurality of through-holes are formed in the chip paddle for increasing the bonding strength of encapsulation material in the package body. A plurality of tabs are formed in the chip paddle may also be used alone or in conjunction with the through-holes to further increase the bonding strength of the encapsulation material in the package body. The tabs provide additional area for the bonding site to ground wires from the semiconductor chip by increasing the length of the chip paddle.

Abstract: By disposing a rear surface of a first island 12 and a top surface of a second island 13 so as to at least partially overlap each other, a first semiconductor chip on the first island and a second semiconductor chip on a rear surface of the second island are configured so as to overlap each other. Accordingly, a planar occupied area can be set smaller than planar areas of both of the chips. Moreover, thin metal wires to be connected to the second semiconductor chip 20 are extended to a back side. Consequently, a thickness of a semiconductor device can also be reduced.

Abstract: An integrated circuit package system comprising: providing a substrate having a cavity; sealing a package over the cavity of the substrate; and forming an encapsulant over the package and a portion of the substrate substantially preventing the encapsulant from forming in the cavity.

Abstract: The present invention relates to an IC substrate provided with over voltage protection functions and thus, a plurality of over voltage protection devices are provided on a single substrate to protect an IC chip directly. According to the present invention, there is no need to install protection devices at respective I/O ports on a printed circuit board to prevent the IC devices from damage by surge pulses. Therefore, the costs to design circuits are reduced, the limited space is efficiently utilized, and unit costs to install respective protection devices are lowered down.

Abstract: A chip package mechanism. A substrate is disposed in a receiving chamber of a base. A chip is disposed on a target surface of the substrate. A plurality of supporting elements is disposed on the target surface and surrounds the chip. A gap for receiving the chip is created in the receiving chamber and between the target surface and the base by means of the supporting elements. A barricade is disposed in the gap to separate glue filled in the receiving chamber from contacting the chip. Outside water and particles cannot enter the chip package mechanism. The chip thus has a prolonged lifespan after packaged in the chip package mechanism.

Abstract: Semiconductor equipment includes: a first lead frame having a first semiconductor device; a second lead frame having a second semiconductor device; a thermal resistor for preventing heat transfer from the first lead frame to the second lead frame; and a temperature sensitive device for detecting operational temperature of the first semiconductor device. The first lead frame is separated from the second lead frame by a predetermined distance. The thermal resistor is disposed in a clearance between the first lead frame and the second lead frame. The second semiconductor device controls to restrict operation of the first semiconductor device when the operational temperature of the first semiconductor device is higher than a predetermined temperature.

Abstract: An exemplary embodiment of an optical device may include a lead frame with a plurality of leads and a reflector housing formed around the lead frame. The reflector housing includes a first end face and a second end face and a peripheral sidewall extending between the first end face and the second end face. The reflector housing includes a first pocket with a pocket opening in the first end face and a second pocket with a pocket opening in the second end face. At least one LED die is mounted in the first pocket of the reflector housing, and a light transmitting encapsulant is disposed in the first pocket and encapsulating the at least one LED die.

Abstract: A semiconductor package including a base body having a recessed portion for installing an electronic component on one surface, the recessed portion including an inner bottom surface, inclined surface and a shoulder part and a wiring pattern having one end positioned in the inner bottom surface of the recessed portion and the other end extending to an outside region of the recessed portion beyond the shoulder part of the recessed portion. The shoulder part of the recessed portion is a smoothly curved surface.

Abstract: A semiconductor integrated circuit (IC) chip includes an IC chip body and a nano-structure-surface passivation film. The IC chip body has at least one surface. The nano-structure-surface passivation film is formed on the at least one surface. The nano-structure-surface passivation film including nano-particles and a carrier resin protects the IC chip body from encountering any external interference. The IC chip body further has a plurality of fingerprint sensing members for sensing a whole fingerprint or a partial fingerprint.

Abstract: A surface mount electronic chip (10) is mounted on a holder (70) and electrically connected to holder terminals (74,76, 80) by the use of a carrier device (30). The carrier device has clips (36) mounted on walls of the carrier frame. The chip is merely pressed into a cavity (48) between inner tabs (44) of the chips. The carrier with the chip in place is merely pressed into a cradle (78) formed in the holder by the holder terminals, so outer tabs (46) of the clips press against the holder terminals.

Abstract: A surface mountable chip comprises a semiconductor substrate having IC devices formed thereon and also vertically exposed electrical contacts formed as part of the IC fabrication substrate. Metallization lines electrically connect the IC devices with the contacts. The inventor also contemplates wafers having electrical connection vias in place on the wafers in preparation as a product for further fabrication. A method embodiment of the invention describes methods of fabricating such surface mountable chips.

Abstract: An electronic component device of the present invention includes: a silicon package unit having a structure in which a through electrode provided to a silicon substrate while an electrode post connected to the through electrode is provided upright on an upper side of the silicon substrate; an electronic component mounted on the electrode post and having a connection terminal connected to the top end of the electrode post; and a cap package unit joined onto a periphery of the silicon package unit, and constructing a housing portion in which the electronic component is housed to be hermetically sealed.

Abstract: A semiconductor device includes: a substrate; a semiconductor element mounted on the substrate; a sealing structure for sealing the semiconductor element, the sealing structure being mounted on the substrate; and an adhesive for bonding the sealing structure and the substrate, wherein the sealing structure has a groove for storing the adhesive.

Abstract: An SIP for performing a plurality of hard and soft functions comprises standard IC die and custom platforms mounted to a substrate. Die are identified for each standard hard function, such as memory, processing, I/O and other standard functions and one or more user-configurable base platforms are selected that, when configured, execute the custom soft functions. Optionally, the substrate is laminated to the die and the platforms are attached to the substrate. Testing is performed by defining the configured base platforms coupled to logic representing the die and their connections and performing placement and timing closure on the combination.

Abstract: An semiconductor device package (10) includes a semiconductor device (die) (12) and passive devices (14) electrically connected to a common lead frame (17). The lead frame (17) is formed from a stamped and/or etched metallic structure and includes a plurality of conductive leads (16) and a plurality of interposers (20). The passive devices (14) are electrically connected to the interposers (20), and I/O pads (22) on the die (12) are electrically connected to the leads (16). The die (12), passive devices (14), and lead frame (17) are encapsulated in a molding compound (28), which forms a package body (30). Bottom surfaces (38) of the leads (16) are exposed at a bottom face (34) of the package (10).

Abstract: A semiconductor device. The device includes a substrate and an integrated circuit chip. The device also includes an electrically or thermally reactive layer located between a top surface of the substrate and a bottom surface of the integrated circuit chip, wherein the reactive layer is positioned such that detection of tampering causes the reactive layer to be electrically or thermally energized such that the semiconductor device is at least partially destroyed.

Abstract: A method for activating a getter at low temperature for encapsulation in a device cavity containing a microdevice comprises etching a passivation layer off the getter material while the device wafer and lid wafer are enclosed in a bonding chamber. A plasma etching process may be used, wherein by applying a large negative voltage to the lid wafer, a plasma is formed in the low pressure environment within the bonding chamber. The plasma then etches the passivation layer from the getter material, which is directly thereafter sealed within the device cavity of the microdevice, all within the etching/bonding chamber.

Abstract: The semiconductor device uses an insulating resin that contains at least a resin anti-repellent for adjusting wettability of the insulating resin. The insulating resin is applied on a circuit board, and a semiconductor element is placed thereon and pressed against it. The applied pressure pushes out a portion of the insulating resin under the semiconductor element. This portion of the insulating resin combines with a portion of the insulating resin around the semiconductor element to form a resin fillet on the side surfaces of the semiconductor element.

Abstract: A method of forming an actuator and a relay using a micro-electromechanical (MEMS)-based process is disclosed. The method first forms the lower sections of a square copper coil, and then forms a magnetic core member. The magnetic core member, which lies directly over the lower coil sections, is electrically isolated from the lower coil sections. The method next forms the side and upper sections of the coil, followed by the formation of an overlying cantilevered magnetic flexible member. Switch electrodes, which are separated by a switch gap, can be formed on the magnetic core member and the magnetic flexible member, and closed and opened in response to the electromagnetic field that arises in response to a current in the coil.

Abstract: The semi-conducting support comprises a graphite substrate having a front surface and a rear surface and at least a first stack arranged on the front surface of the substrate. The first stack successively comprises a single-crystal diamond layer, an electrically insulating oxide layer and a semi-conducting layer. The support can comprise a second stack arranged on the rear surface of the substrate and comprising the same succession of layers as the first stack or comprising a polymer material layer. A thermal connection passing through the first and/or second stacks and connecting the graphite substrate to an external surface of the support enables heat to be removed. The method can comprise production of the semi-conducting layer by molecular bonding of rectangular silicon strips onto the oxide layer.

Abstract: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.

Abstract: A plasma display device includes a plasma display panel, a chassis base coupled to the plasma display panel, a drive circuit coupled to the chassis base, a flexible printed circuit (FPC) couples the drive circuit to electrodes of the plasma display panel. An integrated circuit (IC) is mounted on a film structured in the form of a tape carrier package (TCP), and coupled to the FPC. An epoxy resin deposited in a connecting region where the driver IC is connected to wiring of the FPC is formed with an uneven area that includes indentations and protrusions formed substantially uniformly.

Abstract: A semiconductor device includes: a first substrate made of semiconductor and having first regions, which are insulated from each other and disposed in the first substrate; and a second substrate having electric conductivity and having second regions and insulation trenches. Each insulation trench penetrates the second substrate so that the second regions are insulated from each other. The first substrate provides a base substrate, and the second substrate provides a cap substrate. The second substrate is bonded to the first substrate so that a sealed space is provided between a predetermined surface region of the first substrate and the second substrate. The second regions include an extraction conductive region, which is coupled with a corresponding first region.