Abstract: A high voltage durability III-nitride semiconductor device comprises a support substrate including a first silicon body, an insulator body over the first silicon body, and a second silicon body over the insulator body. The high voltage durability III-nitride semiconductor device further comprises a III-nitride semiconductor body characterized by a majority charge carrier conductivity type, formed over the second silicon body. The second silicon body has a conductivity type opposite the majority charge carrier conductivity type. In one embodiment, the high voltage durability III-nitride semiconductor device is a high electron mobility transistor (HEMT) comprising a support substrate including a <100> silicon layer, an insulator layer over the <100> silicon layer, and a P type conductivity <111> silicon layer over the insulator layer.

Abstract: A solid-state imaging device 1 is arranged so that a hollow section 9 is formed between a solid-state imaging element 2 and a covering section 4 and an air path 7 is formed in an adhesive section 5 so as to extend from the hollow section 9 to the outside, wherein the adhesive section 5 is formed so as not to be positioned on a signal processing section 8 for processing a signal of the solid-state imaging element 2. This makes it possible to reduce noises occurring in the signal processing section of the semiconductor element while preventing occurrence of condensation in the covering section for covering the semiconductor element.

Abstract: The invention provides a chip package and a fabrication method thereof. In one embodiment, the chip package includes: a substrate having a semiconductor device and a conductive pad thereon; an insulator ring filling a trench formed in the substrate, wherein the insulator ring surrounds an intermediate layer below the conductive pad; and a conductive layer disposed below a backside of the substrate and electrically connected to the conductive pad.

Abstract: A sensor module has a carrier substrate having a bottom side and a top side, a sensor chip arranged on the top side of the carrier substrate and having a pressure-sensitive active area, a signal-processing chip arranged on the top side of the carrier substrate next to the sensor chip and being connected to the sensor chip in an electrically conducting manner, a continuous casting material covering the top side of the carrier substrate and the signal-processing chip and being in mechanical contact with both, the casting material having a recess which is arranged such that the casting material does not cover at least a part of the active area of the sensor chip.

Abstract: A multi-layer electronic package having polymeric tape layers, where at least one of the polymeric tape layers has a via, through hole, or aperture therein to pass wiring between the layers. This enables a balance of package size, adhesive thickness, chip access, inventory management, package width, JEDEC ball out, and die exposure. The polymeric tape layers have surface circuits (e.g., leads, pads, and wiring) located on the surface.

Abstract: A method, in which the semiconductor components forming part of an electronic circuit, or at least some of them, are embedded in a base, such as a circuit board, during the manufacture of the base, when part of the base structure is, as it were, manufactured around the semiconductor components. Through-holes for the semiconductor components are made in the base, in such a way that the holes extend between the first and second surface of the base. After the making of the holes, a polymer film is spread over the second surface of the base structure, in such a way that the polymer film also covers the through-holes made for the semiconductor components from the side of the second surface of the base structure. Before the hardening, or after the partial hardening of the polymer film, the semiconductor components are placed in the holes made in the base, from the direction of the first surface of the base.

Abstract: A microelectronic assembly and a method for forming a microelectronic assembly are provided. A semiconductor substrate (22) is provided. The semiconductor substrate (22) has first and second opposing sides (24, 26) and first and second portions (28, 30). A tuning depression (32) is formed on the second opposing side and the second portion of the semiconductor substrate. A radio frequency conductor (34) is formed on the first opposing side (24) of the first semiconductor substrate. The radio frequency conductor (34) has a first end (46) on the first portion (28) of the first semiconductor substrate (22) and a second end (48) on the second portion (30) of the first semiconductor substrate (22). A microelectronic die (78) having an integrated circuit formed therein is attached to the first opposing side (24) and the first portion (28) of the semiconductor substrate (22) such that the integrated circuit is electrically connected to the first end (46) of the radio frequency conductor (34).

Abstract: A semiconductor package including a package body which is uniquely configured to partially expose the semiconductor die of the package. The partial exposure of the semiconductor die enhances heat dissipation from the die. Additionally, the reduced amount of encapsulant material used in the fabrication of the semiconductor package attributable to only the partial encapsulation of the semiconductor die facilitates a reduction in the overall manufacturing cost related to the semiconductor package, and further allows one or more additional semiconductor packages to be stacked upon the package while still maintaining an overall profile of reduced thickness in the resultant stack.

Abstract: The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations.

Abstract: A miniaturized semiconductor device has a package substrate, a semiconductor chip mounted on the main surface of the package substrate and having plural LNAs each for amplifying a signal, an RF VCO for converting the frequency of the signal supplied from each LNA, and an IF VCO for converting the frequency of a signal supplied from a baseband. A plurality of ball electrodes are provided on the back surface of the package substrate. The package substrate is provided with a first common GND wire for supplying a GND potential to each of the LNAs, with a second common GND wire for supplying the GND potential to the RF VCO, and with a third common GND wire for supplying the GND potential to the IF VCO. The first, second, and third common GND wires are separated from each other.

Abstract: An embedded chip package includes a substrate, a semiconductor structure, an encapsulating material layer and a plurality of conductive vias. Herein the substrate includes at least a dielectric layer and at least a patterned circuit layer disposed on the dielectric layer. The semiconductor structure is disposed on the substrate and has a plurality of electrical bonding pads, and the electrical bonding pads contact the dielectric layer. The encapsulating material layer is disposed on the substrate and around the semiconductor structure. In addition, a plurality of conductive vias is disposed in the substrate to electrically connect the patterned circuit layer to the electrical bonding pads.

Abstract: In a semiconductor device bonded to a motherboard with a bonding material having a melting point of 200° C. to 230° C., a bonding material 15 which is a die bonding material for bonding a semiconductor element 13 to a semiconductor substrate 11 is a Bi alloy containing 0.8 wt % to 10 wt % of Cu and 0.02 wt % to 0.2 wt % of Ge, so that the bonding material 15 for bonding the semiconductor element 13 to the semiconductor substrate 11 is not melted when the semiconductor device is bonded to the motherboard by reflowing. It is therefore possible to suppress poor connection on the semiconductor element 13, thereby securing the mountability and electrical reliability of the semiconductor device.

Abstract: An embedded chip package structure is proposed. The embedded chip package structure includes a supporting board with a protruding section, a semiconductor chip formed on the protruding section of the supporting board, a dielectric layer formed on the supporting board and the semiconductor chip, and a circuit layer formed on the dielectric layer. The circuit layer is electrically connected to electrode pads of the semiconductor chip via a plurality of conducting structures formed inside the dielectric layer such that the semiconductor chip can be electrically connected to an external element through the circuit layer. By varying the thicknesses of the protruding section, the dielectric layer and the supporting board, warpage of the package structure resulted from temperature change during the fabrication process can be prevented.

Abstract: An integrated circuit package system includes: providing a substrate with an integrated circuit mounted thereover; mounting a structure, having ground pads, over the integrated circuit; encapsulating the integrated circuit with an encapsulation while leaving the structure partially exposed; and attaching a conformal shielding to the encapsulation and electrically connected to the grounding pads.

Abstract: A semiconductor device that includes a metal substrate including a top surface, a bottom surface and four side surfaces, a conductive pattern insulated from the metal substrate, and a semiconductor element mounted on and electrically connected to the conductive pattern. The top surface is insulated. Each of the side surfaces of the metal substrate includes a first inclining side surface and a second inclining side surface so as to form a convex shape protruding outwardly between the top surface and the bottom surface of the metal substrate, and the first inclining side surfaces of a pair of two opposing side surfaces are smaller than corresponding first inclining side surfaces of another pair of two opposing side surfaces.

Abstract: An RF power amplifier including a single piece heat sink and an RF power transistor die mounted directly onto the heat sink.

Abstract: A semiconductor package in which an electronic device chip is provided in a cavity of a silicon substrate stacked product constituted by stacking a plurality of silicon substrates.

Abstract: An integrated circuit device and method of making the integrated circuit device are disclosed. An exemplary apparatus includes: a semiconductor layer; and a dielectric layer on the semiconductor layer, the dielectric layer having conductive vias and dummy vias formed therein, wherein the conductive vias and dummy vias extend varying distances into the dielectric layer, the conductive vias extending through the dielectric layer to the semiconductor layer, and the dummy vias extending through the dielectric layer to a distance above the semiconductor layer.

Abstract: A stacked structure includes a first substrate bonded to a second substrate such that a first pad structure of the first substrate contacts a second pad structure of the second substrate. A transistor gate is formed over the second substrate, and a first conductive structure extends through the second substrate and has a top surface that is substantially planar with a top surface of the second substrate. An interlayer dielectric (ILD) layer is disposed over the transistor gate, and a passivation layer is disposed over the ILD layer and includes a second pad structure that makes electrical contact with the second conductive structure. The ILD layer includes at least one contact structure that extends through the ILD layer and makes electrical contact with the transistor gate. A second conductive structure is disposed in the ILD layer and is at least partially disposed over a surface of the first conductive structure.

Abstract: A semiconductor device having a multilayer wiring structure and a manufacturing method thereof are provided. A semiconductor device and a manufacturing method thereof are provided in which the reliability and the manufacturing yield are high and the design constraint is small. Wirings are formed on a substrate. Low dielectric constant films are formed around the wirings. Reinforcement insulating films are formed in a dielectric material of a larger elastic modulus than that of a formation material of the low dielectric constant films and are arranged to overlap with the wirings when viewed perpendicularly to a substrate surface. Reinforcement insulating films are arranged to intersect with the wirings.

Abstract: A semiconductor package includes a bare chip which has a plurality of external electrodes, a land grid array substrate having an edge, a first surface and a second surface. The first surface includes a first portion apart from the edge and a second portion adjacent to the edge. The first portion of the first surface mounts the bare chip and is covered with a resin to seal the bare chip with the resin. The first portion of the first surface and the second surface includes a non-sealed region which is not covered with the resin. A plurality of first electrodes are arranged on the non-sealed region and connected to the external electrodes and a plurality of second electrodes are arranged on the second surface and connected to the external electrodes.

Abstract: A wiring substrate includes a first insulation layer, a connection terminal, a second insulation layer, a via, and a wiring pattern. The connection terminal is disposed in the first insulation layer so as to be exposed from a first main surface of the first insulation layer, and is electrically connected with a semiconductor chip. The second insulation layer is disposed on a second main surface of the first insulation layer situated on the opposite side from the first main surface. The via is disposed in the second insulation layer, and is electrically connected with the connection terminal. The via is separated from the connection terminal. The wiring pattern is disposed on the second main surface of the first insulation layer and electrically connects the connection terminal and the via.

Abstract: There is provided a semiconductor device whose cost is low and whose case is restrained from breaking. In the semiconductor device having a semiconductor sensor chip, a signal processing circuit for processing signals output from the semiconductor sensor chip and a hollow case for mounting the semiconductor sensor chip and the signal processing circuit therein, the case is constructed by bonding a concave bottom member whose one end is opened with a plate-like lid member that covers the opening of the bottom member. Then, the bottom and lid members are both made of a semiconductor material and are bonded by means of anode bonding or metal bonding for example.

Abstract: In one embodiment, the present invention includes a semiconductor package having a substrate with a first surface to support a semiconductor die. A second surface of the substrate includes compliant conductive pads to provide electrical connections to the semiconductor die. In this way, improved connection between the semiconductor package and a socket is provided. Other embodiments are described and claimed.

Abstract: A semiconductor device includes: a semiconductor element; a die pad with the semiconductor element mounted thereon; a plurality of electrode terminals each having a connecting portion electrically connected with the semiconductor element; and a sealing resin for sealing the semiconductor element, the die pad and the electrode terminals so that a surface of each electrode terminal on an opposite side from a surface having the connecting portion is exposed as an external terminal surface. A recess having a planar shape of a circle is formed on the surface of each electrode terminal with the connecting portion, and the recess is arranged between an end portion of the electrode terminal exposed from an outer edge side face of the sealing resin and the connecting portion. While a function of the configuration for suppressing the peeling between the electrode terminal and the sealing resin can be maintained by mitigating an external force applied to the electrode terminal, the semiconductor device can be downsized.

Abstract: An apparatus and a method for producing three-dimensional integrated circuit packages. In one embodiment, an electronics package with at least two dice are stacked one atop another is disclosed. A top die is of smaller size compared with a bottom die such that after a die attach operation, wire-bond pads of the bottom die will be exposed for a subsequent wire bonding operation. The bottom die contains contact pads on the front side that couple with one or more passive components fabricated on the back side of the top die to complete the circuit. In another exemplary embodiment, a method to form one or more three-dimensional passive components in a stacked-die package is disclosed wherein partial inductor elements are fabricated on the front side of the bottom die and the back side of the top die. The top and bottom elements are coupled together completing the passive component.

Abstract: A semiconductor device capable of wireless communication, which has high reliability in terms of resistance to external force, in particular, pressing force and can prevent electrostatic discharge in an integrated circuit without preventing reception of an electric wave. The semiconductor device includes an on-chip antenna connected to the integrated circuit and a booster antenna which transmits a signal or power included in a received electric wave to the on-chip antenna without contact. In the semiconductor device, the integrated circuit and the on-chip antenna are interposed between a pair of structure bodies formed by impregnating a fiber body with a resin. One of the structure bodies is provided between the on-chip antenna and the booster antenna. A conductive film having a surface resistance value of approximately 106 to 1014 ?/cm2 is formed on at least one surface of each structure body.

Abstract: A heat spreader attached to a heat source that includes a semiconductor chip includes a silicon structure that provides a plurality of heat flux paths, including a lateral, in-plane heat flux path. The heat spreader is mounted in-plane with the heat source.

Abstract: An exemplary imaging module package includes a substrate, an imaging sensor chip set on the substrate, a housing positioned on the substrate, and a lens module. The housing includes a first chamber enclosing the imaging sensor chip therein, a second chamber coaxially extending from the first chamber for receiving the lens module therein, and a shoulder between the first and second chambers. The shoulder abuts against a top surface of the imaging sensor chip.

Abstract: A laminated substrate and the semiconductor package utilizing the substrate are revealed. The laminated substrate primarily comprises a core layer, a first metal layer and a first solder mask disposed on the bottom surface of the core layer, and a second metal layer and a second solder mask disposed on the top surface of the core layer. The two solder masks have different CTEs to compensate potential substrate warpage caused by thermal stresses. Therefore, the manufacturing cost of the substrate can be reduced without adding extra stiffeners nor changing thicknesses of semiconductor packages to suppress substrate warpage during packaging processes. Especially, a die-attaching layer partially covers the second solder mask by printing and is planar after pre-curing for zero-gap die-attaching.

Abstract: The present invention provides a semiconductor device having a low-k film including an interconnect layer and a highly-reliable through-substrate contact plug. The semiconductor device includes: a semiconductor substrate having a first surface and a second surface facing each other; a first insulating film formed on the first surface of the semiconductor substrate and having a specific permittivity of 4 or higher; a circuit constituent element formed on the first surface of the semiconductor substrate and covered with the first insulating film); a contact plug formed in the first insulating film and electrically connected to the circuit constituent element; a through-substrate contact plug penetrating through the semiconductor substrate and the first insulating film; a second insulating film formed on the first insulating film and having a specific permittivity of 3.

Abstract: A hybrid module includes a silicon substrate having a plurality of part mounting openings formed therein, the plurality of part mounting openings composed of through holes, a plurality of mounted parts that are mounted in the part mounting openings such that input/output portion forming surfaces are substantially flush with a first main surface of the silicon substrate, a sealing layer that is formed of a sealing material filled into the part mounting openings and covers the mounted parts, with the input/output portion forming surfaces exposed from the first main surface of the silicon substrate, to fix the mounted parts in the part mounting openings, and a wiring layer that is formed on the first main surface of the silicon substrate, and has a wiring pattern connected to input/output portions that are provided on the input/output portion forming surfaces of the mounted parts exposed from the first main surface.

Abstract: A wafer level encapsulation chip and an encapsulation chip manufacturing method. The encapsulation chip includes a device substrate, a circuit module mounted on the device substrate, a bonding layer deposited on a predetermined area of the device substrate, a protection cap forming a cavity over the circuit module and bonded to the device substrate by the bonding layer and encapsulation portions formed on predetermined areas of the bonding layer and the protection cap. Thus, the present invention can minimize damages to a chip upon chip handling and prevent moisture from being introduced into the inside of the chip.

Abstract: An interposer includes a substrate, a conductive structure configured to contact the back side of a semiconductor device and contact pads. The interposer may include first and second sets of contact pads carried by the substrate. The interposer may also include conductive traces carried by the substrate to electrically connect corresponding contact pads of the first and second sets. The receptacles, which may be formed in a surface of the substrate and expose contacts of the second set, may be configured to at least partially receive conductive structures that are secured to the contact pads of the second set. Thus, the interposer may be useful in providing semiconductor device assemblies and packages of reduced height or profile. Such assemblies and packages are also described, as are multi-chip modules including such assemblies or packages.

Abstract: A semiconductor package includes a carrier, a chip, a stiffener and an encapsulant. The chip is disposed on the carrier. The stiffener is disposed around the chip, directly contacts the carrier, and is mounted on the carrier. The encapsulant is adapted to seal the chip and the stiffener.

Abstract: An apparatus for housing a micromechanical system includes a substrate with a surface on which the micromechanical system is formed, a transparent cover and a dry film layer arrangement between the surface of the substrate and the transparent cover. The dry film layer arrangement has an opening, so that the micromechanical system adjoins the opening.

Abstract: A process for packaging a number of micro-components on the same substrate wafer, in which each micro-component is enclosed in a cavity. This process includes making a covering plate comprising a re-useable matrix, a polymer layer, and a metal layer; covering the wafer with the covering plate; applying a contact pressure equal to at least one bar on the covering plate and on the wafer; heating the metal layer during pressing until sealing is obtained, each cavity thus being provided with a sealing area and closed by metal layer; and dissolving the polymer to recover and recycle the matrix.

Abstract: A package structure of a compound semiconductor device comprises a thin film substrate, a die, at least one metal wire and a transparent encapsulation material. The thin film substrate comprises a first conductive film, a second conductive film, and an insulating dielectric material. The die is mounted on the surface of the first conductive film, and is electrically connected to the first conductive film and the second conductive film through the metal wire. The transparent encapsulation material overlays the first conductive film, second conductive film, and die. The surfaces of the first conductive film and second conductive film which is opposite the transparent encapsulation material act as electrodes. The insulating dielectric material is between the first conductive film and second conductive film.

Abstract: Provided is a printed circuit board having air vents and a semiconductor package that uses the printed circuit board having the air vents. The printed circuit board includes a substrate layer having a circuit pattern and a protection layer formed on the substrate layer, a molding region on which at least one semiconductor chip is mounted and for which a molding for the semiconductor chip is performed, and a plurality of air vents extending towards edges of the printed circuit board from the molding region.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a base having a through-conductor spanning the height of the base, and having an insulator protecting the base and the through-conductor; mounting a chip over the base and connected to the base with a first interconnect; forming a second interconnect above the base and horizontally beside the chip; and encapsulating the chip, the first interconnect, and the second interconnect with an encapsulation.

Abstract: The invention provides a mounting for a printed circuit board which mounting is suitable for receiving a semiconductor assembly wherein the mounting comprises: a base support having a semiconductor assembly facing surface, and an opposed printed surface board facing surface; a cover having a semiconductor assembly facing surface, an opposed heat radiating surface; a connecting formation which joins the cover to the base support and provides an electrical and thermal communication between the cover and the base support wherein the connecting formation has a semiconductor assembly facing surface, an outer opposed surface and a thickness between the two surfaces; and a plurality of package connectors extending from the base support each of which package connectors have a printed surface board facing surface; an array of mountings; and a semiconductor package comprising a semiconductor assembly having one or more semiconductor chips, which assembly is mounted on the mounting wherein the package connectors of the

Abstract: The present invention provides a chip carrier structure having a semiconductor chip embedded therein and a protective metal layer formed thereon and a fabrication method thereof. The chip carrier structure includes a chip-embedded carrier structure, and a metal layer formed by electroplating on the bottom surface and side surfaces of the chip-embedded carrier structure. The metal layer prevents moisture from crossing the side surfaces of the chip-embedded carrier structure, so as to prevent delamination, provide a shielding effect, and improve heat dissipation through the metal layer.

Abstract: A semiconductor chip includes a die mounted on a packaging substrate. The die includes a semiconductor substrate; inter-metal dielectric layers on the semiconductor substrate; levels of metal interconnection, wherein at least two potential equivalent metal traces are formed in a level of the metal interconnection; a passivation layer disposed over the two metal traces, wherein two openings are formed in the passivation layer to expose portions of the two metal traces; a conductive member externally mounted on the passivation layer between the two openings; and a redistribution layer formed over the conductive member.

Abstract: With embodiments disclosed herein, the distribution of gated power is done using on-die layers without having to come back out and use package layers.

Abstract: A method for packaging micromachined devices fabricated by MEMS and semiconductor process is disclosed in this invention. The method employed etching technique to etch a trench surrounding the micromachined components on each chip of the first wafer down to the bottom interconnection metal layer. The said trench can accommodate the solder of flip-chip packaging. On each chip of the second wafer, or called as the second chip, a surrounding copper pillar wall corresponding to the trench on the first chip is deposited. By wafer-level packaging, the trench on the first chip is aligned to the pillar wall, and then bonded together with elevated temperature. The face-to-face chamber formed between two chips can allow the movement of the micromachined structures. Further, the signal or power connections between two chips can be established by providing several discrete pillar bumps.

Abstract: An optical device package comprises: a metal frame including a substrate and a rectangular die pad portion integrally connected to the substrate, wherein the substrate is a metal plate, and the die pad portion is bent from the substrate such that the die pad portion extends from the substrate at an angle of 90 degrees; signal lead pins extend in the opposite directions from the die pad portion relative to the substrate such that the first lead pins intersect the principal surfaces of the substrate at a right angle and are spaced apart from the metal frame; and a molded resin member including a plate-like resin base extending across and in contact with one of the principal surfaces of the substrate, wherein the signal lead pins protrude from a surface of the resin base; surfaces of the signal lead pins are covered with the molded resin member; and the metal frame and the signal lead pins are secured in place by the molded resin member.

Abstract: An electronic device includes an FPC, a circuit chip arranged on the flexible flat cable, a heat sink arranged on the circuit chip to release a heat of the circuit chip, and an elastic member arranged on a lower surface of the FPC. The upper surface of the FPC is large enough to cover a contact surface of the circuit chip. The elastic member does not overlap with an apex portion of the circuit chip, but overlaps with the circuit chip at an inner side of the apex portion. Therefore the elastic member does not press the FPC against the apex portion of the circuit chip. Accordingly, the FPC at a position corresponding to an apex of the circuit chip is suppressed from being distorted, and there is no fear of breaking of wire and exfoliation of the circuit chip.

Abstract: A semiconductor device of the invention includes a semiconductor substrate having a first insulating section formed on one surface thereof. A first conductive section is disposed on the one surface of the semiconductor substrate. A second insulating section is superimposed over the first insulating section and covers the first conductive section. A second conductive section is superimposed over the second insulating section. A third insulating section is disposed over the second insulating section and covers the second conductive section. These first conductive section, second insulating section, second conductive section, third insulating section, and terminal altogether constitute a structure. A third opening is formed between adjacent structures. The third opening is formed passing through the third and second insulating sections to expose the first insulating section.

Abstract: A technique for manufacturing a low-cost, small volume, and highly integrated semiconductor device is provided. A characteristic of the present invention is that a semiconductor element formed by using a semiconductor thin film is transferred over a semiconductor element formed by using a semiconductor substrate by a transfer technique in order to manufacture a semiconductor device. Compared with the conventional manufacturing method, mass production of semiconductor devices with lower cost and higher throughput can be realized, and production cost per semiconductor device can be reduced.

Abstract: The device has a carrier and an electric element. The carrier has a first and an opposed side and is provided with an connection layer, an intermediate layer and contact pads. The element is present at the first side and coupled to the connection layer. It is at least partially encapsulated by an encapsulation that extends into isolation areas between patterns in the intermediate layer. A protective layer is present at the second side of the carrier, which covers an interface between the contact pads and the intermediate layer.