Abstract: A disclosed method of manufacturing a camera module includes providing an image capture device, providing an electronic component, providing a flexible circuit substrate, mounting the image capture device on a first portion of the flexible circuit substrate, mounting the electronic component on the second portion of the flexible circuit substrate, and positioning the second portion above the first portion. The method further includes providing a chip carrier including a bottom surface defining a cavity and a top surface adapted to receive the image capture device and positioning the chip carrier between the image capture device and the flexible circuit substrate. The method further includes mounting a second electronic component within the cavity.

Abstract: A method includes preparing a cover member; preparing an image pickup element including a substrate including a pixel region including a plurality of photo detectors on a principal surface, a first concavo-convex portion including a plurality of first convex portions configured to concentrate light on the plurality of photo detectors, the first convex portions each having a lens shape, and a second concavo-convex portion surrounding the first concavo-convex portion, the second concavo-convex portion including a plurality of second convex portions; and fixing the cover member to a region of the image pickup element using a fixing member, the region being between the first concavo-convex portion and the second concavo-convex portion.

Abstract: An electronic assembly is disclosed. One embodiment includes at least one semiconductor chip and a package structure embedding the semiconductor chip. The package structure includes at least one conducting line extending into an area of the package structure outside of the outline of the chip. The electronic assembly further includes a substrate embedding the package structure.

Abstract: A package structure includes a substrate, a first die and at least one second die. The substrate includes a first pair of parallel edges and a second pair of parallel edges. The first die is mounted over the substrate. The first die includes a third pair of parallel edges and a fourth pair of parallel edges, wherein the third pair of parallel edges and the fourth pair of parallel edges are not parallel to the first pair of parallel edges and the second pair of parallel edges, respectively. The at least one second die is mounted over the first die.

Abstract: The present invention discloses a structure of device package comprising a first substrate with a die metal pad, a first wiring circuit on top surface of said first substrate and a second wiring circuit on bottom surface of said first substrate. A die is disposed on the die metal pad. A second substrate has a die opening window for receiving the die, a third wiring circuit on top surface of the second substrate and a fourth wiring circuit on bottom surface of the second substrate. An adhesive material is filled into the gap between back side of the die and top surface of the first substrate and between the side wall of the die and the side wall of the die receiving through hole and the bottom side of the second substrate.

Abstract: A power semiconductor module with segmented base plate. One embodiment provides a semiconductor module including a base plate and at least two circuit carriers. The base plate includes at least two base plate segments spaced distant from one another. Each of the circuit carriers includes a ceramic substrate provided with at least a first metallization layer. Each of the circuit carriers is arranged on exactly one of the base plate segments. At least two of the circuit carriers are spaced distant from one another.

Abstract: The image sensor package with dual substrates comprises a first substrate with a die receiving opening and a plurality of first through hole penetrated through the first substrate; a second substrate with a die opening window and a plurality of second through hole penetrated through the second substrate, formed on the first substrate. A part of the second wiring pattern is coupled to a part of the third wiring pattern; an image die having conductive pads and sensing array received within the die receiving opening and the sensing array being exposed by the die opening window; and a through hole conductive material refilled into the plurality of second through hole, some of the plurality of second through hole coupling to the conductive pads of the image sensor.

Abstract: An object of the present invention is to reduce a lateral width of an FPC also with evenly aligned and arranged plurality of ICs. The liquid crystal display device according to the present invention includes a glass substrate, a plurality of ICs of COG (Chip On Glass) configuration aligned on a glass substrate along a side thereof, and an FPC (Flexible Printed Circuit) that is arranged to extend along the side of the glass substrate and that is connected to the plurality of ICs. Specified ICs from among the plurality of ICs are arranged in that extending directions of their longer sides are inclined with respect to an extending direction of the side of the glass substrate such that the longer sides face towards a central side of the FPC.

Abstract: As a substrate for a semiconductor device, a metal substrate is used, and the metal substrate is composed of a metal base body made of a first metal and a connecting metal layer made of a second metal for covering the metal base body. The substrate has a structure wherein a diffusion preventing layer for preventing diffusion of the first metal is provided on the connecting metal layer.

Abstract: Affords a method of storing GaN substrates from which semiconductor devices of favorable properties can be manufactured, the stored substrates, and semiconductor devices and methods of manufacturing the semiconductor devices. In the GaN substrate storing method, a GaN substrate (1) is stored in an atmosphere having an oxygen concentration of 18 vol. % or less, and/or a water-vapor concentration of 12 g/m3 or less. Surface roughness Ra of a first principal face on, and roughness Ra of a second principal face on, the GaN substrate stored by the storing method are brought to no more than 20 nm and to no more than 20 ?m, respectively. In addition, the GaN substrates are rendered such that the principal faces form an off-axis angle with the (0001) plane of from 0.05° to 2° in the <1 100> direction, and from 0° to 1° in the <11 20> direction.

Abstract: A second output wiring and a third output wiring enter into a chip mounting portion while coming across a second side and a third side of the chip mounting portion. The other end portions of the second output wiring and the third output wiring enter into the chip mounting portion are bent toward a fourth side of the chip mounting portion, and are connected to an output pad and an output pad provided along a fourth side of the semiconductor chip. An input wiring extends along the fourth side of the chip mounting portion, is bent from a midstream to enter into the chip mounting portion while coming across the fourth side of the chip mounting portion, and is connected to an input pad provided along the fourth side of the semiconductor chip.

Abstract: A power supply unit of an arc discharge device includes a semiconductor module 1 and a radiator fitted onto the semiconductor module 1. The semiconductor module 1 includes a module casing 2 and common units 3a to 3c retained by the module casing 2. Each of the common units 3a to 3c has: a ceramic substrate 50 having a circuit surface disposed with a semiconductor element 54 and a radiation surface on a side opposite to the circuit surface and a package 35 that exposes the radiation surface and seals the circuit surface with heat resistant resin. The radiator is fitted onto the module casing 2 to be thereby brought into abutting contact with all of the radiation surfaces of the common units 3a to 3c.

Abstract: A panel with a reconfigured wafer including semiconductor chips arranged in rows and columns on semiconductor device positions includes: at least one semiconductor chip having a front, a rear and edge sides provided per semiconductor device position. The reconfigured wafer includes: a front side that forms a coplanar area with the front sides of the at least one semiconductor chip and a plastic housing composition embedding the edge sides and the rear side of the at least one semiconductor chip. The reconfigured wafer includes, on a rear side of the wafer, structures configured to stabilize the panel. The structures are composed of the plastic housing composition and are formed as thickenings of the reconfigured wafer.

Abstract: A semiconductor package is provided having reduced tensile stress. The semiconductor package includes a package substrate and a semiconductor die. The semiconductor die is coupled electrically and physically to the package substrate and includes a stress relieving layer incorporated therein. The stress relieving layer has a predetermined structure and a predetermined location within the semiconductor die for reducing tensile stress of the semiconductor package during heating and cooling of the semiconductor package.

Abstract: The semiconductor device 100 comprises a first semiconductor element 113 provided on a face on one side of a flat plate shaped interconnect component 101, an insulating resin 119 covering a face of a side where the first semiconductor element 113 of the interconnect component 101 is provided and a side face of the first semiconductor element 113, and a second semiconductor element 111 provided on a face on the other side of the interconnect component 101. The interconnect component 101 has a constitution where an interconnect layer 103, a silicon layer 105 and an insulating film 107 are sequentially formed. The interconnect layer 103 has a constitution where the interconnect layer 103 has a flat plate shaped insulating component and a conductive component extending through the insulating component. The first semiconductor element 113 is electrically connected with the second semiconductor element 111 through the conductive component.

Abstract: A MEMS device includes a chip carrier having an acoustic port extending from a first surface to a second surface of the chip carrier, a MEMS die disposed on the chip carrier to cover the acoustic port at the first surface of the chip carrier, and an enclosure bonded to the chip carrier and encapsulating the MEMS die.

Abstract: Microelectronic die packages, stacked systems of die packages, and methods of manufacturing them are disclosed herein. In one embodiment, a system of stacked packages includes a first die package having a bottom side, a first dielectric casing, and first metal leads; a second die package having a top side attached to the bottom side of the first package, a dielectric casing with a lateral side, and second metal leads aligned with and projecting towards the first metal leads and including an exterior surface and an interior surface region that generally faces the lateral side; and metal solder connectors coupling individual first leads to individual second leads. In a further embodiment, the individual second leads have an “L” shape and physically contact corresponding individual first leads. In another embodiment, the individual second leads have a “C” shape and include a tiered portion that projects towards the lateral side of the second casing.

Abstract: A method of manufacturing a printed wiring board includes preparing a wiring substrate having a conductive circuit, coating a solder-resist layer over the conductive circuit, leveling a surface of the solder-resist layer so as to obtain a maximum surface roughness in a predetermined range, removing the resin film from the surface of the solder-resist layer, and forming multiple openings in the surface of the solder-resist layer to expose multiple portions of the conductive circuit so as to form multiple conductive pads for mounting an electronic components.

Abstract: A modular package for a light emitting device includes a leadframe having a top surface and including a central region having a bottom surface and having a first thickness between the top surface of the leadframe and the bottom surface of the central region. The leadframe may further include an electrical lead extending away from the central region. The electrical lead has a bottom surface and has a second thickness from the top surface of the leadframe to the bottom surface of the electrical lead. The second thickness may be less than the first thickness. The package further includes a package body on the leadframe surrounding the central region and exposing the bottom surface of the central region. The package body may be at least partially provided beneath the bottom surface of the lead and adjacent the bottom surface of the central region. Methods of forming modular packages and leadframes are also disclosed.

Abstract: A semiconductor device includes an IPD structure, a first semiconductor die mounted to the IPD structure with a flipchip interconnect, and a plurality of first conductive posts that are disposed adjacent to the first semiconductor die. The semiconductor device further includes a first molding compound that is disposed over the first conductive posts and first semiconductor die, a core structure bonded to the first conductive posts over the first semiconductor die, and a plurality of conductive TSVs disposed in the core structure. The semiconductor device further includes a plurality of second conductive posts that are disposed over the core structure, a second semiconductor die mounted over the core structure, and a second molding compound disposed over the second conductive posts and the second semiconductor die. The second semiconductor die is electrically connected to the core structure.

Abstract: A semiconductor package assembly has a first semiconductor package. A plurality of first solder balls is attached to the first semiconductor package. A circuit board is provided having a plurality of mounting pads that is electrically connected to the plurality of first solder balls. A first underfill is disposed on each of the plurality of first solder balls. The first underfill is disposed on interfaces between each of the plurality of first solder balls and the first semiconductor package and each of the plurality of first solder balls and the circuit board. The first underfill is removed from an area between adjacent first solder balls.

Abstract: The present invention proposes a MEMS chip and a package method thereof. The package method comprises: making a capping wafer by: providing a first substrate and forming an etch stop layer on the first substrate; making a device wafer by: providing a second substrate and forming a MEMS device and a material layer surrounding the MEMS device on the second substrate; bonding the capping wafer and the device wafer; after bonding, etching the first substrate to form at least one via; etching the etch stop layer through the via; etch the material layer; and forming a sealing layer on the first substrate.

Abstract: A module includes a semiconductor chip and a conductive layer arranged over the semiconductor chip. The module also includes a spacer structure arranged to deflect the conductive layer away from the semiconductor chip.

Abstract: A sealing and bonding material structure for joining semiconductor wafers having monolithically integrated components. The sealing and bonding material are provided in strips forming closed loops. There are provided at least two concentric sealing strips on one wafer. The strips are laid out so as to surround the component(s) on the wafers to be sealed off when wafers are bonded together. The material in the strips is a material bonding the semiconductor wafers together and sealing off the monolithically integrated components when subjected to force and optionally heating. A monolithically integrated electrical and/or mechanical and/or fluidic and/or optical device including a first substrate and a second substrate, bonded together with the sealing and bonding structure, and a method of providing a sealing and bonding material structure on at least one of two wafers and applying a force and optionally heat to the wafers to join them are described.

Abstract: A semiconductor device including: a substrate formed with a concave portion at one surface thereof; and a first semiconductor chip provided in the concave portion of the substrate and is adhered to the substrate by an underfill in the concave portion, wherein the concave portion includes a chip arrangement region in which the first semiconductor chip is arranged, and an adjustment region which protrudes from at least a portion of the periphery of the chip arrangement region when seen in a plan view at a height of at least a portion of a region where the first semiconductor chip is placed in a stacked direction of the substrate, and has different shapes from the chip arrangement region is provided.

Abstract: A vertical mount pre-molded type package for use with a MEMS sensor may be formed with a low moisture permeable molding material that surrounds a portion of the leadframes and forms a cavity in which one or multiple dies may be held. The package includes structures to reduce package vibration, reduce die stress, increase vertical mount stability, and improve solder joint reliability. The vertical mount package includes a first leadframe having first leads and molding material substantially surrounding at least a portion of the first leads. The molding material forms a cavity for holding the MEMS sensor and forms a package mounting plane for mounting the package on a base. The cavity has a die mounting plane that is substantially non-parallel to the package mounting plane. The first leads are configured to provide electrical contacts within the cavity and to provide electrical contacts to the base.

Abstract: Methods and apparatuses for improved thermal, electrical and/or mechanical performance in integrated circuit (IC) packages are described. An IC circuit package comprises a substrate having a central opening. An IC die, resides within the opening in the substrate. Wirebonds couples a plurality of bond pads on a top surface of the IC die to a plurality of bond fingers on a top surface the substrate. An encapsulating material encapsulates at least the IC die and the wirebonds such that at least a bottom surface of the IC die is left exposed. The encapsulating material suspends the die such that at least a portion of the die is held within the opening in the substrate.

Abstract: A microelectronic assembly and a method for forming a microelectronic assembly are provided. A semiconductor substrate (22) is provided. The semiconductor substrate (22) has first and second opposing sides (24, 26) and first and second portions (28, 30). A tuning depression (32) is formed on the second opposing side and the second portion of the semiconductor substrate. A radio frequency conductor (34) is formed on the first opposing side (24) of the first semiconductor substrate. The radio frequency conductor (34) has a first end (46) on the first portion (28) of the first semiconductor substrate (22) and a second end (48) on the second portion (30) of the first semiconductor substrate (22). A microelectronic die (78) having an integrated circuit formed therein is attached to the first opposing side (24) and the first portion (28) of the semiconductor substrate (22) such that the integrated circuit is electrically connected to the first end (46) of the radio frequency conductor (34).

Abstract: A semiconductor module having one or more silicon carbide diode elements mounted on a switching element is provided in which the temperature rise is reduced by properly disposing each of the diode elements on the switching element, to thereby provide a thermal dissipation path for the respective diode elements. The respective diode elements are arranged on a non-central portion of the switching element, to facilitate dissipation of the heat produced by each of the diode elements, whereby the temperature rise in the semiconductor module is reduced.

Abstract: A noncontact IC tag label includes: a band-shaped label base material inclusive of a release surface formed at least at one end of the base material and releasably treated in advance, and a non-release surface; an electroconductive layer formed on the non-release surface of the band-shaped label base material and including a required antenna pattern; and an IC chip mounted on one face of the electroconductive layer. The electroconductive layer and the IC chip are shrouded by a surface protection sheet via a pressure-sensitive adhesive layer. A thermoadhesive resin layer bonded onto the non-release surface of the band-shaped label base material is provided on an opposite face of the electroconductive layer including the antenna pattern, with respect to the surface protection sheet. Also, the pressure-sensitive adhesive layer is bonded onto the non-release surface and release surface of the band-shaped label base material.

Abstract: An optical sensor package structure includes a substrate, a metal plate, an optical sensing chip, a plurality of bonding wires and a lens module. The substrate includes a top surface, a bottom surface and a hole penetrating the top surface and the bottom surface. The metal plate covers the hole from the bottom surface of the substrate. The optical sensing chip is received in the hole and mounted on the metal plate. The bonding wires interconnect the optical sensing chip and the top surface of substrate. The lens module is covering on the hole and mounting on the top surface of the substrate to enclose the optical sensing chip and the bonding wires. Because the optical sensing chip is received in the hole of the substrate, the height of the optical sensor package structure can be reduced to adapt to a compact size electrical device.

Abstract: Provided is an electronic device of high reliability having an exposed functional portion. An electronic device 10 comprises an electronic element 11 having an exposed functional portion 11a on a first surface, a frame member 12 having a first penetration hole 12a, and a board 13 having a second penetration hole 13a. The frame member 12 is provided on the first surface of the electronic element 11 such that the first penetration hole 12a faces at least a part of the functional portion 11a. The electronic element 11 is mounted on the board 13 such that at least a part of the functional portion 11a faces the second penetration hole 13a. The frame member 12 does not contact with the board 13.

Abstract: The mounting height of a semiconductor device is reduced. A wiring substrate has an upper surface with multiple bonding leads formed therein and a lower surface with multiple lands formed therein. This wiring substrate is a multilayer wiring substrate and multiple wiring layers and multiple insulating layers are alternately formed on the upper surface side and on the lower surface side of the core material of the wiring substrate. The bonding leads are formed of part of the uppermost wiring layer and the lands are formed of part of the lowermost wiring layer. The insulating layers include second insulating layers containing fiber and resin and third insulating layers smaller in fiber content than the second insulating layers. The second insulating layers are formed on the upper surface side and on the lower surface side of the core material. The third insulating layers are formed on the upper surface side and on the lower surface side of the core material with the second insulating layers in-between.

Abstract: The present invention includes a base, a rectification chip, a conductive element and a coupling collar. The base has an installation pedestal to hold the rectification chip. The conductive element has a root portion to hold the rectification chip. The coupling collar is located at one end of the base to hold a package. The coupling collar has a plurality of anchor portions in contact with the package. Each anchor portion has a convex portion and a concave portion extended to two ends of the coupling collar. The convex portion and concave portion of two neighboring anchor portions are formed in a staggered manner. The cross section area of the convex portion on the annular edge of the coupling collar is different from the cross section area of the inner wall of the coupling collar. Hence fabrication and assembly are easier. Turning and loosening of the package can be prevented.

Abstract: A light emitting module includes a semiconductor light source, a first lead with a bonding pad to which the light source is attached, and a second lead spaced from the first lead in a first direction contained in the plane of the first die bonding pad. The second lead includes a wire bonding pad connected to the light source via a wire. The module also includes a case formed with a space elongated in the first direction for accommodating the light source. The first lead includes an extension extending from the first die bonding pad, and a mounting terminal connected to the extension. The extension extends in a second direction that is perpendicular to the first direction and contained in the plane of the first die bonding pad. The mounting terminal extends perpendicularly to the second direction. The extension overlaps the light source in the first direction.

Abstract: In one embodiment, the present invention includes a semiconductor package having a substrate with a first surface to support a semiconductor die. A second surface of the substrate includes compliant conductive pads to provide electrical connections to the semiconductor die. In this way, improved connection between the semiconductor package and a socket is provided. Other embodiments are described and claimed.

Abstract: The present disclosure provides a device having a plurality of bonded substrates. The substrates are bonded by a first bond ring and a second bond ring. In an embodiment, the first bond ring is a eutectic bond and the second bond ring is at least one of an organic material and a eutectic bond. The second bond ring encircles the first bond ring. The first bond ring provides a hermetic region of the device. In a further embodiment, a plurality of wafers are bonded which include a third bond ring disposed at the periphery of the wafers.

Abstract: A semiconductor package comprises: a substrate comprising a semiconductor device; a cap comprising a seal ring disposed over a surface of the cap; and a gap between the substrate and the surface of the cap. The seal ring comprises a tread comprising at least two columns.

Abstract: Each of first base regions of sequentially layered first IGBT and second IGBT has a peripheral section in the vicinity of the side face of the semiconductor substrate. Each of the IGBTs includes a P-type peripheral base region that is adjacent to the peripheral section of the first base region of the N-type to form a diode and a diode electrode that is formed on an upper face of the peripheral section of the first base region, thereby electrically connecting the diode electrode and a collector electrode of each of the IGBTs. When the semiconductor device is ON, current flows at the center side of the semiconductor substrate separated from the side face. When current in a reverse direction is generated when the semiconductor device is OFF, current in a reverse direction flows in the vicinity of the side face of the semiconductor substrate.

Abstract: In one embodiment, a semiconductor structure including a first substrate, a semiconductor device on the first substrate, a second substrate, and a conductive bond between the first substrate and the second substrate that surrounds the semiconductor device to seal the semiconductor device between the first substrate and the second substrate. The conductive bond comprises metal, silicon, and germanium. A percentage by atomic weight of silicon in the conductive bond is greater than 5%.

Abstract: An integrated circuit package system comprising forming a trace frame including: fabricating a sacrificial substrate; forming a first series of bonding pads along a length of the sacrificial substrate; forming a second series of the bonding pads along a width of the sacrificial substrate; forming conductive traces for connecting the bonding pads of the first series to the bonding pads of the second series in a one to one correspondence; and removing the sacrificial substrate.

Abstract: A semiconductor device has a TSV semiconductor wafer with a cavity formed in a first surface of the wafer. A second cavity can be formed in a second surface of the wafer. A plurality of semiconductor die is mounted within the cavities. The semiconductor die can be mounted side-by-side and/or stacked within the cavity. Conductive TSV can be formed through the die. An encapsulant is deposited within the cavity over the die. A CTE of the die is similar to a CTE of the encapsulant. A first interconnect structure is formed over a first surface of the encapsulant and wafer. A second interconnect structure is formed over a second surface of the encapsulant and wafer. The first and second interconnect structure are electrically connected to the TSV wafer. A second semiconductor die can be mounted over the first interconnect structure with encapsulant deposited over the second die.

Abstract: A packaging substrate with an embedded photosensitive semiconductor chip and a method for fabricating the same are provided. The method includes the steps of: disposing the semiconductor chip in an through cavity of a core board with the photosensitive portion of the semiconductor chip being exposed from the through cavity; forming a first circuit layer on the core board at a side opposite to the photosensitive portion so as to electrically connect the electrode pads of the semiconductor chip; and forming a light-permeable layer on the core board at the same side with the photosensitive portion via an adhesion layer so as to allow light to penetrate through the light-permeable layer and reach the photosensitive portion of the semiconductor chip. When fabricated by the method, the packaging substrate dispenses with conductive wires and a surrounding dam and thus is efficiently downsized.

Abstract: An electronic component package, includes a package substrate portion constructed by a silicon substrate in which a through hole is provided, an insulating layer formed on both surface sides of the silicon substrate and an inner surface of the through hole, and a through electrode filled in the through hole, and a frame portion provided upright on a peripheral portion of the package substrate portion to constitute a cavity on the silicon substrate, wherein an upper surface of the through electrode in the cavity is planarized such that a height of the through electrode is set equal to a height of the insulating layer. The frame portion is joined to the package substrate portion by the low-temperature joining utilizing the plasma process after the through electrode is planarized.

Abstract: An alpha particle blocking structure and method of making the structure. The structure includes: a semiconductor substrate; a set of interlevel dielectric layers stacked from a lowermost interlevel dielectric layer closest to the substrate to a uppermost interlevel dielectric layer furthest from the substrate, each interlevel dielectric layer of the set of interlevel dielectric layers including electrically conductive wires, top surfaces of the wires substantially coplanar with top surfaces of corresponding interlevel dielectric layers; an electrically conductive tot final pad contacting a wire pad of the uppermost interlevel dielectric layer; an electrically conductive plating base layer contacting a top surface of the terminal pad; and a copper block on the plating base layer.

Abstract: In accordance with the present invention, there is provided a semiconductor package and a fabrication method thereof. The semiconductor package is provided with a substrate made of metal, thereby improving efficiency of thermal emission from a semiconductor die mounted to the substrate, and simplifying the fabrication process for the substrate which reduces fabricating costs. Further, unlike a conventional land, a rivet electrically insulated with the substrate is inserted into a corresponding hole of the substrate, the upper and lower surfaces of the rivet being removed to form land, thereby simplifying the fabrication process for the substrate which further reduces fabricating costs.

Abstract: A method for manufacturing a semiconductor device comprises dry-etching a thin film using a resist mask carrying patterns in which at least one of the width of each pattern and the space between neighboring two patterns ranges from 32 to 130 nm using a halogenated carbon-containing compound gas with the halogen being at least two members selected from the group consisting of F, I and Br. The ratio of at least one of I and Br is not more than 26% of the total amount of the halogen atoms as expressed in terms of the atomic compositional ratio to transfer the patterns onto the thin film. Such etching of a thin film avoids causing damage to the resist mask used. The resulting thin film carrying the transferred patterns is used as a mask for subjecting the underlying material to dry-etching.

Abstract: A dual wavelength laser device including a cap, a header, a first laser chip and a second laser chip. The cap includes a cap body and a lens embedded on the cap body. The header forms an accommodating space with the cap. The first laser chip is arranged in the accommodating space and emitting a first laser beam toward the lens. The second laser chip is arranged in the accommodating space and emitting a second laser beam toward the lens.

Abstract: A miniaturized semiconductor device has a package substrate, a semiconductor chip mounted on the main surface of the package substrate and having plural LNAs each for amplifying a signal, an RF VCO for converting the frequency of the signal supplied from each LNA, and an IF VCO for converting the frequency of a signal supplied from a baseband. A plurality of ball electrodes are provided on the back surface of the package substrate. The package substrate is provided with a first common GND wire for supplying a GND potential to each of the LNAs, with a second common GND wire for supplying the GND potential to the RF VCO, and with a third common GND wire for supplying the GND potential to the IF VCO. The first, second, and third common GND wires are separated from each other.

Abstract: A first semiconductor element is mounted on a base plate, and is in a sealed state by the periphery thereof being covered by an insulation member, and the upper surface thereof being covered by an upper insulation film. An upper wiring layer formed on the upper insulation film, and the lower wiring layer formed below the base plate via lower insulation films are connected by conductors. A second semiconductor element is mounted exposed, being connected to the lower wiring layer.