Multiple Housings Patents (Class 257/685)
  • Patent number: 10777540
    Abstract: A 3D semiconductor device and structure, including: a first die including first transistors and first interconnect, overlaid by a second die including second transistors and second interconnect, where the first die has a first die area and the second die has a second die area, where the first die area is at least 10% larger than the second die area, where the second die is aligned to the first die with less than 400 nm alignment error, and where the second die has a thickness of less than four microns.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: September 15, 2020
    Assignee: Monolithic 3D Inc.
    Inventor: Zvi Or-Bach
  • Patent number: 10748856
    Abstract: A fan-out semiconductor package includes: a core member having a first through-hole and including a dummy metal layer; a first semiconductor chip disposed in the first through-hole and having a first active surface having first connection pads disposed thereon and a first inactive surface opposing the first active surface; a first encapsulant covering at least portions of the core member and the first semiconductor chip and filling at least portions of the first through-hole; and a first connection member disposed on the core member and the first active surface of the first semiconductor chip and including a first redistribution layer electrically connected to the first connection pads, wherein the dummy metal layer is electrically insulated from signal patterns of the first redistribution layer.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: August 18, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seon Hee Moon, Myung Sam Kang, Jin Gu Kim
  • Patent number: 10734358
    Abstract: Processes for configuring a plurality of independent die packages for socketing. The packages are attached to a carrier wafer with a release film. The attached plurality of independent die packages are overmolded to provide a molded multi-die package. The molded multi-die package is planarized to expose the dies, singulated, and released from the carrier wafer. The singulated, molded multi-die packaging may be picked for further processing and placed into a socket. A plurality of molded, multi-die packages may be placed in a socket and operate as a computer system. The independent die packages may each perform and same computer application function or different computer application functions, and may have the same or different dimensions. The socket may have any of a number of configurations as may be needed.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: August 4, 2020
    Assignee: Intel Corporation
    Inventors: Jonathan L. Rosch, Amruthavalli Pallavi Alur, Arun Chandrasekhar, Shawna M. Liff
  • Patent number: 10734318
    Abstract: A fold in a semiconductor package substrate includes an embedded device that includes orthogonal electrical coupling through the package substrate by a bond-pad via that is configured to couple to a semiconductive device that is mounted on the semiconductor package substrate. The semiconductive device is coupled to the embedded device with the orthogonal electrical coupling.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: August 4, 2020
    Assignee: Intel Corporation
    Inventors: Bok Eng Cheah, Jackson Chung Peng Kong, Khang Choong Yong, Yun Rou Lim
  • Patent number: 10714452
    Abstract: The present invention provides a method of manufacturing a package structure. An array chip including a plurality of first dies is provided. A wafer including a plurality of second dies is provided. A package step is carried out to package the array chip onto the wafer so as to electrically connect the first die and the second die. The present invention further provides a semiconductor wafer and a package structure.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: July 14, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Chien-Li Kuo
  • Patent number: 10676344
    Abstract: An environmental-barrier layer can protect a die or an array of die. A substrate that includes various functional components can be coupled to a porous environmental-barrier layer to form an array of die prior to dividing the array into individual die. The porous environmental-barrier layer can be a layer that includes polymer or fluoropolymer. The porous environmental-barrier layer can also be a filter layer for allowing certain waves to pass through and blocking particles and other debris. The porous environmental-barrier layer can protect each die in the array and the functional components from damage by protecting the die and the functional components from mechanical, electrical, or environmental damage (e.g., contamination by fluid or dust) without impeding a function of the functional components.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: June 9, 2020
    Assignee: W. L. Gore & Associates, Inc.
    Inventors: Andrew J. Holliday, William A. Kinder, Nathaniel J. Hoover
  • Patent number: 10667396
    Abstract: Integrated multilayer structure (100, 200, 300, 400, 500, 600, 700) comprising a first substrate film (102) having a first side (102A), said first substrate film comprising electrically substantially insulating material, said first substrate film preferably being formable and optionally thermoplastic, a plastic layer (112) molded onto said first side of the first substrate film so as to at least partially cover it, and circuitry (104, 106, 204, 205), optionally comprising an electronic, electromechanical and/or electro-optical component, provided on the second side of the first substrate film, said circuitry being functionally connected to the first side of the first substrate film.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: May 26, 2020
    Assignee: TACTOTEK OY
    Inventors: Antti Keranen, Ronald Haag, Mikko Heikkinen
  • Patent number: 10651154
    Abstract: A semiconductor package includes a plurality of semiconductor chips on a substrate. The semiconductor chips include a first semiconductor chip, a second semiconductor chip, and a third semiconductor chip that are sequentially stacked on the substrate. The semiconductor package further includes a plurality of non-conductive layers between the substrate and the first semiconductor chip and between adjacent semiconductor chips among the semiconductor chips. The semiconductor chips include smaller widths as a distance from the substrate increases. Each of the non-conductive layers includes an extension protruding outward from a side surface of an overlying one of the semiconductor chips.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: May 12, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Sick Park, Geol Nam, Tae Hong Min, Jihwan Hwang
  • Patent number: 10610693
    Abstract: An encapsulation configuration for electronic components in a flexible implantable medical device, including at least one set of folded circuit boards and a filler material, the set of folded circuit boards including a plurality of circuit boards and a plurality of connection cables, each one of the circuit boards including at least one electronics component, each one of the circuit boards having a generally rectangular shape, the connection cables electrically coupling adjacent ones of the circuit boards and the circuit boards being folded over one another in a pleated manner, the filler material surrounding the set of folded circuit boards, the filler material and the set of folded circuit boards together having a cylindrical shape, the set of folded circuit boards being positioned lengthwise in the cylindrical shape and the electronics component being positioned on the set of folded circuit boards to achieve optimal volume consumption in the electronics encapsulation.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: April 7, 2020
    Assignee: NewPace Ltd.
    Inventors: Gera Strommer, Avi Broder, Moti Mocha, Robert S. Fishel, Nahum Natan
  • Patent number: 10600705
    Abstract: An electronic switching element includes at least one semiconductor switch inserted into a layer sequence of a conductor structure element; and at least two busbars which are configured to contact-connect the at least one semiconductor switch, wherein the at least two busbars run substantially above one another in the layer sequence of the conductor structure element.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: March 24, 2020
    Assignee: SCHWEIZER ELECTRONIC AG
    Inventors: Thomas Gottwald, Christian Rössle, Rainer Jäackle
  • Patent number: 10594355
    Abstract: Devices and methods related to radio-frequency (RF) filters on silicon-on-insulator (SOI) substrate. In some embodiments, an RF device can include a silicon die such as an SOI die including a first side and a second side. The silicon die can further include a plurality of vias, with each via configured to provide an electrical connection between the first side and the second side of the silicon die. The RF device can further include at least one RF flip chip mounted on the first side of the silicon die. The silicon die can include, for example, an RF circuit such as a switch circuit, and the RF flip chip can include, for example, a filter such as a surface acoustic wave (SAW) filter.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: March 17, 2020
    Assignee: Skyworks Solutions, Inc.
    Inventor: James Phillip Young
  • Patent number: 10573579
    Abstract: A semiconductor package includes a package substrate having a top surface and a bottom surface, an interposer mounted on the top surface of the package substrate, a first semiconductor die and a second semiconductor die mounted on the interposer in a side-by-side manner, and a stiffener ring secured to the top surface of the package substrate. The stiffener ring encircles the first semiconductor die and the second semiconductor die. The stiffener ring comprises a reinforcement rib striding across the interposer.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: February 25, 2020
    Assignee: MEDIATEK INC.
    Inventors: Tai-Yu Chen, Wen-Sung Hsu, Sheng-Liang Kuo, Chi-Wen Pan, Jen-Chuan Chen
  • Patent number: 10546952
    Abstract: The present invention provides a method of manufacturing a semiconductor device to improve the manufacturing yield of the semiconductor device. The manufacturing method includes the steps of: forming a groove extending in a first direction (y direction) across a first power transistor formation region and a second power transistor formation region, in a back surface of a semiconductor wafer; filling the groove with a conductor film by forming the conductor film on the back surface in which the groove is formed; and exposing the back surface of the semiconductor wafer by removing a portion of the conductor film.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: January 28, 2020
    Assignee: Renesas Electronics Corporation
    Inventor: Tetsuji Togami
  • Patent number: 10537018
    Abstract: One semiconductor device includes a wiring substrate, a first semiconductor chip that is mounted on one surface of the wiring substrate, a second semiconductor chip that is laminated on the first semiconductor chip so as to form exposed surfaces where the surface of the first semiconductor chip is partially exposed, silicon substrates that are mounted on the exposed surfaces and serve as warping control members, and an encapsulation body that is formed on the wiring substrate so as to cover the first semiconductor chip, the second semiconductor chip and the silicon substrates.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: January 14, 2020
    Assignee: Longitude Licensing Limited
    Inventor: Sensho Usami
  • Patent number: 10515937
    Abstract: A semiconductor device and method for providing an enhanced removal of heat from a semiconductor die within an integrated fan out package on package configuration is presented. In an embodiment a metal layer is formed on a backside of the semiconductor die, and the semiconductor die along and through vias are encapsulated. Portions of the metal layer are exposed and a thermal die is connected to remove heat from the semiconductor die.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: December 24, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jing-Cheng Lin, Po-Hao Tsai, Li-Hui Cheng, Porter Chen
  • Patent number: 10468356
    Abstract: A system module package is disclosed. The system module package includes: a substrate; a first electrical component and a second electrical component disposed on a top surface of the substrate; and a plurality of bond wires disposed adjacent to at least a first side of the first electrical component and in between the first and second electrical components. The plurality of bond wires are configured to attenuate EMI of a frequency of interest traveling from the first electrical component toward the second electrical component, or from the second electrical component toward the first electrical component. Each of the plurality of bond wires has at least a first end that is mechanically coupled to the top surface of the substrate and has a highest point that is a height, H, from the top surface of the substrate.
    Type: Grant
    Filed: February 18, 2019
    Date of Patent: November 5, 2019
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Ah Ron Lee, Deog Soon Choi, Young Ho Lee, Boon Keat Tan, Jin Ho Choi
  • Patent number: 10431550
    Abstract: A fan-out electronic component package includes a core, a first electronic component, a first encapsulant, a connection member, a second electronic component, and a second encapsulant. The core member includes a through-hole, wiring layers and vias configured to electrically connect the wiring layers to each other. The first electronic component is disposed in the through-hole, and comprising filters configured to filter different frequency bands. The first encapsulant covers portions of the core member and the first electronic component, and fills portions of the through-hole. The connection member is disposed on the core member and the first electronic component, and includes a redistribution layer electrically connected to the wiring layers and the first electronic component. The second electronic component is disposed on the connection member and electrically connects to the redistribution layer. The second encapsulant is disposed to cover the second electronic component.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: October 1, 2019
    Assignee: Samsung EIectro-Mechanics Co., Ltd.
    Inventors: Myeong Woo Han, Chan Yong Jeong
  • Patent number: 10403331
    Abstract: A semiconductor device includes a memory cell array, pad groups, a first option pad, a second option pad and a data input multiplexer block configured to transmit data, input through all or part of the pad groups, to the memory cell array based on whether the first option pad and a ground are connected to each other, wherein the data input multiplexer block is configured to select first pad groups among the pad groups or second pad groups among the pad groups as the part of the pad groups based on whether the second option pad and the ground are connected to each other.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: September 3, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yong Gyu Chu, Hyo Soon Kang, Seung Bum Ko, Sang Jae Rhee
  • Patent number: 10394211
    Abstract: An electronic safety switching device comprising at least a first and a second signal processing channel to which input signals may be supplied for signal processing. The first and second signal processing channels provide processed output signals, wherein the first and the second signal processing channels process the supplied input signals redundantly with respect to one other. The first and the second signal processing channels are each formed as integrated circuits, wherein the first signal processing channel is arranged monolithically on a first semiconductor substrate, and the second signal processing channel is arranged monolithically on a second semiconductor substrate. Furthermore, the first and the second semiconductor substrates are combined into a stack to form a one-piece electronic component.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: August 27, 2019
    Assignee: PILZ GMBH & CO. KG
    Inventors: Thorsten Godau, Norbert Froehlich, Matthias Holzaepfel, Hans Schwenkel
  • Patent number: 10383572
    Abstract: A method includes forming one or more vias in a substrate, forming a first photoresist layer on a top surface of the substrate and a second photoresist layer on a bottom surface of the substrate, patterning the first photoresist layer and the second photoresist layer to remove at least a first portion of the first photoresist layer and at least a second portion of the second photoresist layer, filling the one or more vias, the first portion and the second portion with solder material using injection molded soldering, and removing remaining portions of the first photoresist layer and the second photoresist layer.
    Type: Grant
    Filed: June 1, 2017
    Date of Patent: August 20, 2019
    Assignee: International Business Machines Corporation
    Inventors: John U. Knickerbocker, Shriya Kumar, Jae-Woong Nah
  • Patent number: 10388539
    Abstract: In accordance with an embodiment, a semiconductor component includes a support having a side in which a device receiving structure and an interconnect structure are formed and a side from which a plurality of leads extends. A semiconductor device having a control terminal and first and second current carrying terminals and configured from a III-N semiconductor material is mounted to the device receiving structure. The control terminal of the first electrical interconnect is coupled to a first lead by a first electrical interconnect. A second electrical interconnect is coupled between the first current carrying terminal of the semiconductor device and a second lead. The second current carrying terminal of the first semiconductor device is coupled to the device receiving structure or to the interconnect structure.
    Type: Grant
    Filed: July 6, 2016
    Date of Patent: August 20, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Chun-Li Liu, Ali Salih, Mingjiao Liu
  • Patent number: 10381328
    Abstract: A 3D semiconductor device and structure, including: a first die including first transistors and first interconnect, overlaid by a second die including second transistors and second interconnect, where the first die has a first die area and the second die has a second die area, where the first die area is at least 10% larger than the second die area, and where the second die has a thickness of less than four microns.
    Type: Grant
    Filed: June 24, 2017
    Date of Patent: August 13, 2019
    Assignee: MONOLITHIC 3D INC.
    Inventor: Zvi Or-Bach
  • Patent number: 10379155
    Abstract: In an example implementation, an integrated circuit (IC) includes: a plurality of transistors disposed in a plurality of locations on a die of the IC; conductors coupled to terminals of each of the plurality of transistors; a digital-to-analog converter (DAC), coupled to the conductors, to drive voltage signals to the plurality of transistors in response to a digital input; and an analog-to-digital converter (ADC), coupled to at least a portion of the conductors, to generate samples in response to current signals induced in the plurality of transistors in response to the voltage signals, the samples being indicative of at least one electrostatic characteristic for the plurality of transistors.
    Type: Grant
    Filed: October 2, 2014
    Date of Patent: August 13, 2019
    Assignee: XILINX, INC.
    Inventors: Ping-Chin Yeh, John K. Jennings, Rhesa Nathanael, Nui Chong, Cheang-Whang Chang, Daniel Y Chung
  • Patent number: 10342118
    Abstract: One semiconductor device includes a wiring substrate, a first semiconductor chip that is mounted on one surface of the wiring substrate, a second semiconductor chip that is laminated on the first semiconductor chip so as to form exposed surfaces where the surface of the first semiconductor chip is partially exposed, silicon substrates that are mounted on the exposed surfaces and serve as warping control members, and an encapsulation body that is formed on the wiring substrate so as to cover the first semiconductor chip, the second semiconductor chip and the silicon substrates.
    Type: Grant
    Filed: March 20, 2014
    Date of Patent: July 2, 2019
    Assignee: LONGITUDE LICENSING LIMITED
    Inventor: Sensho Usami
  • Patent number: 10329143
    Abstract: A packaged MEMS device, wherein at least two support structures are stacked on each other and are formed both by a support layer and a wall layer coupled to each other and delimiting a respective chamber. The chamber of the first support structure is upwardly delimited by the support layer of the second support structure. A first and a second dice are accommodated in a respective chamber, carried by the respective support layer of the first support structure. The support layer of the second support structure has a through hole allowing wire connections to directly couple the first and the second dice. A lid substrate, coupled to the second support structure, closes the chamber of the second support structure.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: June 25, 2019
    Assignee: STMicroelectronics (Malta) Ltd
    Inventor: Kevin Formosa
  • Patent number: 10325875
    Abstract: Disclosed is an integrated circuit packaging system that includes first and second microchips. Each microchip includes a top surface, a surface, one or more quilt package nodules fabricated on said top surface, and one or more bottom surface connectors. The system also includes a substrate to which the first and second microchips are mounted. The first and second microchips are connected via the quilt package nodules.
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: June 18, 2019
    Assignees: North Carolina State University, Indiana Integrated Circuits, LLC
    Inventors: Jason M. Kulick, Douglas Hopkins
  • Patent number: 10325882
    Abstract: A method of manufacturing a semiconductor package includes providing a substrate including a mounting region having a recess space for accommodating a semiconductor chip and a connection region surrounding the mounting region, providing a semiconductor chip in the mounting region, the semiconductor chip including a connection pad provided on a top surface of the semiconductor chip, forming a protective layer covering a top surface of the substrate and the top surface of the semiconductor chip, forming a photosensitive insulating layer on the protective layer after forming the protective layer, patterning the photosensitive insulating layer thereby exposing the protective layer, removing the exposed protective layer, and forming a redistribution line to be electrically connected to the connection pad.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: June 18, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tae-woo Kang, Byung-lyul Park, Kyoung-hwan Kim, Kun-sang Park, Young-gyu Ahn
  • Patent number: 10325856
    Abstract: An electronic component package includes first and second wiring parts including insulating layers, conductive patterns formed in the insulating layers, and conductive vias penetrating through the insulating layers, to be connected to the conductive patterns, respectively; a frame disposed between the first and second wiring parts and having conductive connection parts electrically connecting one or more through-holes with the first and second wiring parts and an electronic component disposed to be surrounded by the through-hole, to thereby be connected to the first wiring part, wherein the conductive patterns formed to be adjacent to the electronic component among the conductive patterns of the first wiring part are embedded in the insulating layer of the first wiring part.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: June 18, 2019
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Yong Ho Baek, Sang Kun Kim, Ye Jeong Kim, Jae Ean Lee, Jae Hoon Choi
  • Patent number: 10312179
    Abstract: The teachings of the present disclosure relate to electrical circuits and embodiments may include a circuit arrangement and a current converter comprising said circuit arrangement. An example circuit arrangement may include: a carrier part; a power component; a cooling channel for conveying a cooling agent; and a busbar conducting a current to the power component. The busbar may be arranged on the carrier part and have a region with a first surface and a second surface arranged opposite the first surface. The region may project away from the carrier part into the cooling channel. The power component may be arranged on the first surface of the region and connected to the region in an electrically conductive and mechanical manner.
    Type: Grant
    Filed: April 23, 2015
    Date of Patent: June 4, 2019
    Assignee: CONTI TEMIC MICROELECTRONIC GMBH
    Inventor: Olivier Pola
  • Patent number: 10312221
    Abstract: Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device includes a stack of plural semiconductor chips. Each two adjacent semiconductor chips of the plural semiconductor chips is electrically connected by plural interconnects and physically connected by a first insulating bonding layer. A first stack of dummy chips is positioned opposite a first side of the stack of semiconductor chips and separated from the plural semiconductor chips by a first gap. Each two adjacent of the first dummy chips are physically connected by a second insulating bonding layer. A second stack of dummy chips is positioned opposite a second side of the stack of semiconductor chips and separated from the plural semiconductor chips by a second gap. Each two adjacent of the second dummy chips are physically connected by a third insulating bonding layer.
    Type: Grant
    Filed: December 17, 2017
    Date of Patent: June 4, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Rahul Agarwal, Kaushik Mysore Srinivasa Setty, Milind S. Bhagavat, Brett P. Wilkerson
  • Patent number: 10304788
    Abstract: According to an aspect, a semiconductor power module includes a substrate, a semiconductor device coupled to the substrate, a bond wire coupled to the semiconductor device, and a first molding material layer disposed on the substrate. The first molding material layer encapsulates a first portion of the bond wire. The bond wire has a second portion disposed outside of the first molding material layer. The semiconductor power module includes a second molding material layer disposed on the first molding material layer. The second molding material layer encapsulates the second portion of the bond wire. The second molding material layer has a hardness less than a hardness of the second molding material layer.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: May 28, 2019
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Jihwan Kim, Heeyoung Song, Gwigyeon Yang, Olaf Zschieschang
  • Patent number: 10296347
    Abstract: Fusible instructions and logic provide OR-test and AND-test functionality on multiple test sources. Some embodiments include a processor decode stage to decode a test instruction for execution, the instruction specifying first, second and third source data operands, and an operation type. Execution units, responsive to the decoded test instruction, perform one logical operation, according to the specified operation type, between data from the first and second source data operands, and perform a second logical operation between the data from the third source data operand and the result of the first logical operation to set a condition flag. Some embodiments generate the test instruction dynamically by fusing one logical instruction with a prior-art test instruction. Other embodiments generate the test instruction through a just-in-time compiler. Some embodiments also fuse the test instruction with a subsequent conditional branch instruction, and perform a branch according to how the condition flag is set.
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: May 21, 2019
    Assignee: Intel Corporation
    Inventors: Maxim Loktyukhin, Robert Valentine, Julian C. Horn, Mark J. Charney
  • Patent number: 10276825
    Abstract: The present disclosure discloses an electroluminescent display and the encapsulation method thereof. The electroluminescent display comprises: a substrate having encapsulation units provided on a side surface of the substrate; a cover plate covering the substrate, wherein the cover plate together with the encapsulation units defines a first chamber and a second chamber, the second chamber surrounds the first chamber; an electronic device provided on the substrate and located within the first chamber, wherein the first chamber is filled with inert gas and the second chamber is filled with a hydrophobic liquid. The electroluminescent display according to an embodiment of the present disclosure can prevent water vapor and oxygen from entering the electronic device. The entire system has a good sealing performance, such that a service life of the electronic device can be greatly extended.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: April 30, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Shouzheng Wu, Qing Zhang, Tongmin Liu, Heng Zhang, Fusheng Huang
  • Patent number: 10269619
    Abstract: Presented herein is a WLCSP intermediate structure and method forming the same, the method comprising forming a first redistribution layer (RDL) on a carrier, the first RDL having mounting pads disposed on the first RDL, and mounting interposer dies on a second side of the first RDL. A second RDL is formed over a second side of the interposer dies, the second RDL having a first side adjacent to the interposer dies, one or more lands disposed on the second RDL, at least one of the one or more lands in electrical contact with at least one of the interposer dies or at least one of the mounting pads. A molding compound is formed around the interposer dies and over a portion of the first RDL prior to the forming the second RDL and the second RDL is formed over at least a portion of the molding compound.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Der-Chyang Yeh
  • Patent number: 10262926
    Abstract: A semiconductor die has internal circuitry formed on two more internal layers, and die bonding pads arranged on a top surface of the die. The bonding pads are connected to the internal circuitry for providing input and output signals to the internal circuitry. One or more connecting lines electrically connect one or more pairs of the die bonding pads, thereby defining a bonding pad layout. The die bonding pads are arranged and connected with the connecting lines such that the bonding pad layout is reversible, which allows the die to be used in different package types (e.g., TSSOP or DFN) yet maintain a standardized pin arrangement without the necessity for long or crossed bond wires.
    Type: Grant
    Filed: October 5, 2016
    Date of Patent: April 16, 2019
    Assignee: Nexperia B.V.
    Inventors: Kan Wae Lam, Harrie Martinus Maria Horstink, Sven Walczyk, Chi Ho Leung, Thierry Jans, Pompeo V. Umali, Shun Tik Yeung
  • Patent number: 10261118
    Abstract: A subset of mobile devices is selected from a set of mobile devices located in a local area. From a mobile device in the subset, a magnetic measurement value obtained by performing a magnetic measurement is received. The magnetic measurement value comprises a change in a magnetic property of an immediate surrounding ambient environment of the mobile device. When the magnetic measurement corresponds to a deviation in a network condition in a portion of a network, the portion being located in the local area, a conclusion is output that the deviation is caused by an electromagnetic disturbance (EMD), where an effect of the EMD causes the magnetic measurement value. A notification including an indication of the EMD and an identification of the local area is generated.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: April 16, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chumki Basu, Younghun Kim, Lloyd A. Treinish
  • Patent number: 10256178
    Abstract: In a general aspect, an apparatus can include a leadframe including a plurality of leads configured to be coupled with a printed circuit board. The plurality of leads can be disposed along a single edge of the apparatus. The apparatus can also include an assembly including a substrate and a plurality of semiconductor die disposed on the substrate. The assembly can being mounted on the leadframe. The apparatus can further include an inductor having a first terminal and a second terminal. The first terminal of the inductor can being coupled with the leadframe via a first contact pad, and the second terminal of the inductor can be coupled with the leadframe via a second contact pad. The leadframe, the assembly and the inductor can be arranged in a stacked configuration.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: April 9, 2019
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Jerome Teysseyre, Romel Manatad, Chung-Lin Wu, Bigildis Dosdos, Erwin Ian Almagro, Maria Cristina Estacio
  • Patent number: 10229888
    Abstract: A compartment EMI shield is provided that is suitable for use in system module packages having thin form factors and/or smaller widths and/or lengths. The compartment EMI shield comprises a fence arranged along a compartment boundary at least in between first and second sets of electrical components of the system module package. The fence being configured to attenuate EMI of a frequency of interest traveling in at least one of a first direction and a second direction, where the first direction is from the first set of electrical components toward the second set of electrical components and the second direction is from the second set of electrical components toward the first set of electrical components.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: March 12, 2019
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Ah Ron Lee, Deog Soon Choi, Young Ho Lee, Boon Keat Tan, Jin Ho Choi
  • Patent number: 10217709
    Abstract: The present disclosure relates to a semiconductor package, and more particularly, to a fan-out semiconductor package in which connection terminals may extend outwardly of a region in which a semiconductor chip is disposed. In the fan-out semiconductor package, a circuit density of a redistribution layer may be increased even in a limited area.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: February 26, 2019
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Seon Ha Kang, Myung Sam Kang
  • Patent number: 10204892
    Abstract: A semiconductor package may be composed of a variety of different types of semiconductor chips of different sizes and support structures stacked within the semiconductor package. Semiconductor chips having a larger chip size may be stacked above smaller semiconductor chips. Smaller chips may be included in a layer of the semiconductor package along with a support structure which may assist supporting upper semiconductor chips, such as during a wire bonding process connecting bonding wires to chip pads of the semiconductor chips above the support structure. Use of different thicknesses of die attach film may allow for a further reduction in height of the semiconductor package.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: February 12, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tae-young Lee, Joon-young Oh, Sung-wook Hwang, Yeoung-jun Cho
  • Patent number: 10177078
    Abstract: Chip package structures and methods for forming the same are provided. The chip package structure includes a first protection layer and a first chip disposed over the first protection layer. The chip package structure further includes a first photosensitive layer surrounding the first chip and covering the first chip and a redistribution layer formed over the first photosensitive layer.
    Type: Grant
    Filed: December 8, 2016
    Date of Patent: January 8, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Hua Yu, Kuo-Chung Yee, Chun-Hui Yu
  • Patent number: 10163874
    Abstract: A packaged semiconductor structure includes an interconnect layer and a first microelectronic device on a first major surface of the interconnect layer. The structure also includes a substrate having a cavity, wherein the cavity is defined by a vertical portion and a horizontal portion, wherein the vertical portion surrounds the first device, the horizontal portion is over the first device, and the first device is between the horizontal portion and the first major surface of the interconnect layer such that the first device is in the cavity. The structure further includes a second microelectronic device attached to the horizontal portion of the substrate, and encapsulant on the interconnect layer and surrounding the first device, the substrate, and the second device, such that the substrate is embedded in the encapsulant.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: December 25, 2018
    Assignee: NXP USA, INC.
    Inventors: Michael B. Vincent, Zhiwei Gong, Scott M. Hayes
  • Patent number: 10157858
    Abstract: Disclosed is a semiconductor package. The semiconductor package may include a substrate a semiconductor chip mounted over a surface of the substrate such that an active surface of the semiconductor chip faces the surface of the substrate. The semiconductor chip and substrate may be configured for shielding or scattering electromagnetic waves.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: December 18, 2018
    Assignee: SK hynix Inc.
    Inventors: Won Duck Jung, Sang Joon Lim, Sung Mook Lim
  • Patent number: 10153256
    Abstract: A micro-transfer printable electronic component includes one or more electronic components, such as integrated circuits or LEDs. Each electronic component has device electrical contacts for providing electrical power to the electronic component and a post side. A plurality of electrical conductors includes at least one electrical conductor electrically connected to each of the device electrical contacts. One or more electrically conductive connection posts protrude beyond the post side. Each connection post is electrically connected to at least one of the electrical conductors. Additional connection posts can form electrical jumpers that electrically connect electrical conductors on a destination substrate to which the printable electronic component is micro-transfer printed. The printable electronic component can be a full-color pixel in a display.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: December 11, 2018
    Assignee: X-Celeprint Limited
    Inventors: Ronald S. Cok, Christopher Bower, Matthew Meitl, Carl Prevatte, Jr.
  • Patent number: 10134717
    Abstract: According to an exemplary embodiment, a semiconductor package is provided. The semiconductor package includes at least one chip, and at least one component adjacent to the at least one chip, wherein the at least one chip and the at least one component are molded in a same molding body.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: November 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chung-Shi Liu, Chih-Fan Huang, Tsai-Tsung Tsai, Wei-Hung Lin, Ming-Da Cheng
  • Patent number: 10129986
    Abstract: The invention describes a printed circuit board with a top side and a bottom side, the printed circuit board comprising at least two electrically conductive layers (112, 114, 116, 212, 214, 312, 314, 212i, 214i, 212j, 214j) for transmitting electrical current and at least one electrically insulating layer (102, 104, 106, 108, 202, 204, 302, 304, 202i, 204i, 202j, 204j) comprising electrically insulating material, wherein the electrically conductive layers (112, 114, 116, 212, 214, 312, 314, 212i, 214i, 212j, 214j) and the electrically insulating layer (102, 104, 106, 108, 202, 204, 302, 304, 202i, 204i, 202j, 204j) are arranged in an alternating assembly such that the two electrically conductive layers (112, 114, 116, 212, 214, 312, 314, 212i, 214i, 212j, 214j) are electrically insulated with respect to each other by means of the electrically insulating layer (102, 104, 106, 108, 202, 204, 302, 304, 202i, 204i, 202j, 204j), wherein each of the electrically conductive layers (112, 114, 116, 212, 214, 312, 314,
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: November 13, 2018
    Assignee: KONINKLIJKE PHILIPS N.V.
    Inventors: Ralf Gordon Conrads, Hendrik Huisman, Carsten Deppe, Xi Gu, Gero Heusler
  • Patent number: 10090233
    Abstract: A semiconductor device has a first semiconductor die and second semiconductor die with a conductive layer formed over the first semiconductor die and second semiconductor die. The second semiconductor die is disposed adjacent to the first semiconductor die with a side surface and the conductive layer of the first semiconductor die contacting a side surface and the conductive layer of the second semiconductor die. An interconnect, such as a conductive material, is formed across a junction between the conductive layers of the first and second semiconductor die. The conductive layer may extend down the side surface of the first semiconductor die and further down the side surface of the second semiconductor die. An extension of the side surface of the first semiconductor die can interlock with a recess of the side surface of the second semiconductor die. The conductive layer extends over the extension and into the recess.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: October 2, 2018
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Francis J. Carney, Jefferson W. Hall, Michael J. Seddon
  • Patent number: 10074598
    Abstract: A lead frame includes a plurality of circuit patterns which each have a die pad and an electrode terminal portion and are disposed in a band shape, a tie bar, a frame portion and a suspension lead. Cut are a connection portion between electrode terminals and the frame portion, a connection portion between the frame portion and the tie bar at both end portions in a disposition direction of circuit patterns, and a connection portion from a connection part of the frame portion with the tie bar, between the circuit patterns to a part of the frame portion extending in the disposition direction. The electrode terminal portion is bent to extend to a direction of an upper surface of a semiconductor element. The lead frame is collectively resin-sealed while exposing the tie bar and the electrode terminal portion above the tie bar.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: September 11, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventors: Ken Sakamoto, Tetsuya Ueda, Keitaro Ichikawa, Yuki Yoshioka
  • Patent number: 10056335
    Abstract: In a method of forming an assembly including projecting or protruding nodules, a substrate is provided that supports an electrical circuit. One or more cavities are formed in the substrate, a conductive pad is formed in each cavity, and one or more conductive traces are formed on the substrate. Each conductive trace connects a conductive pad to a location, node, or terminal of the electrical circuit. A part of the substrate is removed to form the assembly that includes the electrical circuit, the one or more conductive traces, and a portion of each conductive pad projecting or protruding from the substrate. The electrical circuit can be formed on the substrate, which can be a PCB, or can be formed on a microchip supported by the substrate, which can be formed of semiconductor material, e.g., a semiconductor wafer.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: August 21, 2018
    Assignee: Indiana Integrated Circuits, LLC
    Inventors: Jason M. Kulick, Tian Lu
  • Patent number: 10049977
    Abstract: A package on package structure may be formed by fabricating or providing a bottom package having a substrate, at least one die on top of the substrate, and bonding pads on the top of the substrate. Next, a frame is formed on the bonding pads and connected to the bonding pads. Next, a package material is molded over the top of the substrate to encapsulate the frame, the die, and the pads or substantially encapsulates these components. Next, a portion of the molded package material is removed to expose at least a portion of the frame. The exposed frame portions are formed such that a desired fan in or fan out configuration is obtained. Next, a non-conductive layer is formed on the exposed frame. Last, a second package having a die or chip is connected to the exposed portion of the frame to form a package on package structure.
    Type: Grant
    Filed: August 1, 2014
    Date of Patent: August 14, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Hong Bok We, Dong Wook Kim, Jae Sik Lee, Kyu-Pyung Hwang, Young Kyu Song