Multiple Housings Patents (Class 257/685)
  • Patent number: 11145547
    Abstract: The present disclosure relates to a semiconductor chip that includes a substrate, a metal layer, and a number of component portions. Herein, the substrate has a substrate base and a number of protrusions protruding from a bottom surface of the substrate base. The substrate base and the protrusions are formed of a same material. Each of the protrusions has a same height. At least one via hole extends vertically through one protrusion and the substrate base. The metal layer selectively covers exposed surfaces at a backside of the substrate and fully covers inner surfaces of the at least one via hole. The component portions reside over a top surface of the substrate base, such that a certain one of the component portions is electrically coupled to a portion of the metal layer at the top of the at least one via hole.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: October 12, 2021
    Assignee: Qorvo US, Inc.
    Inventor: Deep C. Dumka
  • Patent number: 11133235
    Abstract: A package structure includes a first encapsulation member, a second encapsulation member, at least one semiconductor chip, a plurality of metal pins and a second insulation layer. The first encapsulation member includes a first metal layer, a first insulation layer and a second metal layer. The at least one semiconductor chip is disposed between the first encapsulation member and the second encapsulation member. The at least one semiconductor chip comprises a plurality of conductive terminals connected with the first metal layer or a third metal layer. The plurality of metal pins are disposed between and extended outward from the first encapsulation member and the second encapsulation member. The second insulation layer is disposed between the first encapsulation member and the second encapsulation layer for securing the first encapsulation member, the second encapsulation member, the at least one semiconductor chip, and the plurality of metal pins.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: September 28, 2021
    Assignee: DELTA ELECTRONICS INT'L (SINGAPORE) PTE LTD
    Inventors: Jie Song, Xiaofeng Xu, Beng Beng Lim
  • Patent number: 11127722
    Abstract: A stack package includes sub-packages vertically stacked. Each of the sub-packages includes a semiconductor chip having a power pad and a signal pad, a first interposer bridge having a signal through via and a second power through via, and a second interposer bridge having a first power through via. Each of the sub-packages further includes a signal redistributed layer pattern extending to electrically connect the signal pad to a signal connection part and a power redistributed layer pattern to electrically connect the power pad to the first and second power through vias. An upper sub-package of the sub-packages is rotated relative to a lower sub-package, and the rotated upper sub-package is stacked on a lower sub-package of the sub-packages.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: September 21, 2021
    Assignee: SK hynix Inc.
    Inventor: Bok Kyu Choi
  • Patent number: 11122692
    Abstract: A process of fabricating a circuit includes providing a first sheet of dielectric material including a first top surface having at least one first conductive trace and a second sheet of dielectric material including a second top surface having at least one second conductive trace, depositing a first solder bump on the at least one first conductive trace, applying the second sheet of dielectric material to the first sheet of dielectric material with bonding film sandwiched in between, bonding the first and second sheets of dielectric material to one another, and providing a conductive material to connect the first solder bump on the at least one first conductive trace to the at least one second conductive trace.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: September 14, 2021
    Assignee: RAYTHEON COMPANY
    Inventors: James E. Benedict, Gregory G. Beninati, Mikhail Pevzner, Thomas V. Sikina, Andrew R. Southworth
  • Patent number: 11114407
    Abstract: An integrated fan-out (InFO) package includes an encapsulant, a die, a plurality of conductive structures, and a redistribution structure. The die and the conductive structures are encapsulated by the encapsulant. The conductive structures surround the die. The redistribution structure is disposed on the encapsulant. The redistribution structure includes a plurality of routing patterns, a plurality of conductive vias, and a plurality of alignment marks. The conductive vias interconnects the routing patterns. At least one of the alignment mark is in physical contact with the encapsulant.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: September 7, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jhih-Yu Wang, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao, Yung-Chi Chu
  • Patent number: 11107766
    Abstract: A substrate with an embedded stacked through-silicon via die is described. For example, an apparatus includes a first die and a second die. The second die has one or more through-silicon vias disposed therein (TSV die). The first die is electrically coupled to the TSV die through the one or more through-silicon vias. The apparatus also includes a coreless substrate. Both the first die and the TSV die are embedded in the coreless substrate.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: August 31, 2021
    Assignee: Intel Corporation
    Inventors: Javier Soto Gonzalez, Houssam Jomaa
  • Patent number: 11014807
    Abstract: A method for producing a system, including a first microelectromechanical element and a second microelectromechanical element, including the following: providing, a substrate, having the first microelectromechanical element and the second microelectromechanical element, and a cap element, a getter material being situated on the substrate in a first region in a surrounding environment of the first microelectromechanical element and/or on the cap element in a first corresponding region; situating the cap element on the substrate using a wafer bonding technique so that a sealed first chamber is formed that contains the first microelectromechanical element and the first region and/or the first corresponding region, a sealed second chamber being formed that contains the second microelectromechanical element; producing an opening in the second chamber; and sealing the opening at a first ambient pressure, in particular a first gas pressure.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: May 25, 2021
    Assignee: Robert Bosch GmbH
    Inventor: Johannes Classen
  • Patent number: 11018066
    Abstract: A package and a method of forming the same are provided. The package includes: a die stack bonded to a carrier, the die stack including a first integrated circuit die, the first integrated circuit die being a farthest integrated circuit die of the die stack from the carrier, a front side of the first integrated circuit die facing the carrier; a die structure bonded to the die stack, the die structure including a second integrated circuit die, a backside of the first integrated circuit die being in physical contact with a backside of the second integrated circuit die, the backside of the first integrated circuit die being opposite the front side of the first integrated circuit die; a heat dissipation structure bonded to the die structure adjacent the die stack; and an encapsulant extending along sidewalls of the die stack and sidewalls of the heat dissipation structure.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: May 25, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Ming-Fa Chen, Chen-Hua Yu
  • Patent number: 11002626
    Abstract: Provided are a MEMS pressure sensor and a method for forming the same. The method includes: preparing a first substrate including a first surface and a second surface opposite to each other; preparing a second substrate including a third surface and a fourth surface opposite to each other; bonding the first surface and the third surface with each other and forming a cavity between the first substrate and the pressure sensing region of the second substrate; thinning the second substrate from the fourth surface by partially removing the second base, to form a fifth surface opposite to the third surface; and forming a first conductive plug passing through the second substrate from the side of the fifth surface of the second substrate to the at least one conductive layer.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: May 11, 2021
    Assignee: MEMSEN ELECTRONICS INC.
    Inventor: Manhing Chau
  • Patent number: 10971450
    Abstract: Hexagonally arranged connection patterns for device packaging allow high density circuitry dies to be assembled into packages of manufacturable size. The connection patterns may be patterns for solder ball arrays or other types of connection mechanisms under a semiconductor package. Despite the increased density of the connection patterns, the connection patterns meet the demanding crosstalk specifications for high speed operation of the high density circuitry.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: April 6, 2021
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Arun Ramakrishnan, Reza Sharifi, Dharmendra Saraswat
  • Patent number: 10950514
    Abstract: Packaged semiconductor devices and methods of packaging semiconductor devices are disclosed. In some embodiments, a packaged semiconductor device includes an integrated circuit die, a molding compound disposed around the integrated circuit die, and an interconnect structure disposed over the integrated circuit die and the molding compound. The molding compound is thicker than the integrated circuit die.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: March 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chen-Hua Yu, Chung-Shi Liu, Chih-Fan Huang, Chih-Wei Lin, Wei-Hung Lin, Ming-Da Cheng
  • Patent number: 10950529
    Abstract: A semiconductor device package includes a substrate, a first insulation layer and an electrical contact. The first insulation layer is disposed on the first surface of the substrate. The electrical contact is disposed on the substrate and has a first portion surrounded by the first insulation layer and a second portion exposed from the first insulation layer, and a neck portion between the first portion and the second portion of the electrical contact. Further, the second portion tapers from the neck portion.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: March 16, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING KOREA, INC.
    Inventors: Soonheung Bae, Hyunjoung Kim
  • Patent number: 10930608
    Abstract: A 3D semiconductor device, the device including: a first die including first transistors and first interconnect; and a second die including second transistors and second interconnect, where the first die is overlaid by the second die, where the first die has a first die area and the second die has a second die area, where the first die area is at least 10% larger than the second die area, where the second die is pretested, where the second die includes an array of memory cells, where the first die includes control logic to control reads and writes to the array of memory cells, where the second die is bonded to the first die, and where the bonded includes hybrid bonding.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: February 23, 2021
    Assignee: MONOLITHIC 3D Inc.
    Inventor: Zvi Or-Bach
  • Patent number: 10903169
    Abstract: A conductive structure includes a core portion, a plurality of electronic devices and a filling material. The core portion defines a cavity. The electronic devices are disposed in the cavity of the core portion. The filling material is disposed between the electronic devices and a sidewall of the cavity of the core portion.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: January 26, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen Hung Huang
  • Patent number: 10896898
    Abstract: A substrate assembly includes a first microchip including a first interconnecting structure and a second microchip including a second interconnecting structure, wherein the first and second interconnecting structures have keyed complementary, interlocking shapes. The first interconnecting structure is interlocked with the second interconnecting structure. Quilt package nodules on edges of the first and second microchips electrically connect circuitry formed on or supported by the first and second microchips.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: January 19, 2021
    Assignee: Indiana Integrated Circuits, LLC
    Inventors: Jason M. Kulick, Tian Lu
  • Patent number: 10867946
    Abstract: A multi-chip package may include a plurality of semiconductor chips and a printed circuit board (PCB). Each of the semiconductor chips may have an upper surface, a bottom surface, and a plurality of side surfaces. Circuit terminals may be arranged on the upper surface. A plurality of side bonding pads may be arranged on one or more selected side surface among the side surfaces. The semiconductor chips may be mounted on the PCB. The PCB may be configured to surround the selected side surface on which the side bonding pads may be arranged.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: December 15, 2020
    Assignee: SK hynix Inc.
    Inventor: Jin Ho Baek
  • Patent number: 10867919
    Abstract: An electronic device and the manufacturing method thereof are provided. The electronic device includes a semiconductor die, a conductive structure electrically coupled to the semiconductor die, an insulating encapsulant encapsulating the semiconductor die and the conductive structure, and a redistribution structure disposed on the insulating encapsulant and the semiconductor die. The conductive structure includes a first conductor, a second conductor, and a diffusion barrier layer between the first conductor and the second conductor. The redistribution structure is electrically connected to the semiconductor die and the first conductor of the conductive structure.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Fu Tsai, Hou-Ju Huang, Shih-Ting Lin, Szu-Wei Lu, Hung-Wei Tsai
  • Patent number: 10861824
    Abstract: A stackable microelectronic package includes a first microelectronic die attached to and electrically connecting with a first substrate. A second microelectronic die is attached to the first die on one side, and to a second substrate on the other side. Electrical connections are made between the first die and the first substrate, between the second die and the second substrate, and between the first and second substrates, e.g., via wire bonding. The electrical connecting elements are advantageously encased in a molding compound. Exposed contacts on the first and/or second substrates, not covered by the molding compound, provide for electrical connections between the package, and another package stacked onto the package. The package may avoid coplanarity factors, can be manufactured using existing equipment, allows for intermediate testing, and can also offer a thinner package height.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: December 8, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Seng Kim Dalson Ye, Chin Hui Chong
  • Patent number: 10833050
    Abstract: An interposer is capable of efficiently reinforcing the connecting portion between an electronic component and a substrate. The interposer is used for mounting a first electronic component on a substrate and includes a sheet-shaped spacer having at least one through-hole and including a material that does not flow during reflow soldering and a resin portion that covers at least a part of the spacer and is flowable during reflow soldering, and the through-hole is configured to store a bump of the first electronic component.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: November 10, 2020
    Assignee: LENOVO (SINGAPORE) PTE. LTD.
    Inventors: Tadashi Kosuga, Tin-Lup Wong
  • Patent number: 10825779
    Abstract: A 3D semiconductor device and structure, the device including: a first die including first transistors and first interconnect, overlaid by a second die including second transistors and second interconnect, where the first die has a first die area and the second die has a second die area, where the first die area is at least 10% larger than the second die area, where the second die is aligned to the first die with less than 400 nm alignment error, where second die includes an array of memory cells, and where the first die includes decoders for the array.
    Type: Grant
    Filed: June 20, 2020
    Date of Patent: November 3, 2020
    Assignee: MONOLITHIC 3D INC.
    Inventor: Zvi Or-Bach
  • Patent number: 10825764
    Abstract: A semiconductor device has a first semiconductor die and second semiconductor die with a conductive layer formed over the first semiconductor die and second semiconductor die. The second semiconductor die is disposed adjacent to the first semiconductor die with a side surface and the conductive layer of the first semiconductor die contacting a side surface and the conductive layer of the second semiconductor die. An interconnect, such as a conductive material, is formed across a junction between the conductive layers of the first and second semiconductor die. The conductive layer may extend down the side surface of the first semiconductor die and further down the side surface of the second semiconductor die. An extension of the side surface of the first semiconductor die can interlock with a recess of the side surface of the second semiconductor die. The conductive layer extends over the extension and into the recess.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: November 3, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Francis J. Carney, Jefferson W. Hall, Michael J. Seddon
  • Patent number: 10777540
    Abstract: A 3D semiconductor device and structure, including: a first die including first transistors and first interconnect, overlaid by a second die including second transistors and second interconnect, where the first die has a first die area and the second die has a second die area, where the first die area is at least 10% larger than the second die area, where the second die is aligned to the first die with less than 400 nm alignment error, and where the second die has a thickness of less than four microns.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: September 15, 2020
    Assignee: Monolithic 3D Inc.
    Inventor: Zvi Or-Bach
  • Patent number: 10748856
    Abstract: A fan-out semiconductor package includes: a core member having a first through-hole and including a dummy metal layer; a first semiconductor chip disposed in the first through-hole and having a first active surface having first connection pads disposed thereon and a first inactive surface opposing the first active surface; a first encapsulant covering at least portions of the core member and the first semiconductor chip and filling at least portions of the first through-hole; and a first connection member disposed on the core member and the first active surface of the first semiconductor chip and including a first redistribution layer electrically connected to the first connection pads, wherein the dummy metal layer is electrically insulated from signal patterns of the first redistribution layer.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: August 18, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seon Hee Moon, Myung Sam Kang, Jin Gu Kim
  • Patent number: 10734358
    Abstract: Processes for configuring a plurality of independent die packages for socketing. The packages are attached to a carrier wafer with a release film. The attached plurality of independent die packages are overmolded to provide a molded multi-die package. The molded multi-die package is planarized to expose the dies, singulated, and released from the carrier wafer. The singulated, molded multi-die packaging may be picked for further processing and placed into a socket. A plurality of molded, multi-die packages may be placed in a socket and operate as a computer system. The independent die packages may each perform and same computer application function or different computer application functions, and may have the same or different dimensions. The socket may have any of a number of configurations as may be needed.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: August 4, 2020
    Assignee: Intel Corporation
    Inventors: Jonathan L. Rosch, Amruthavalli Pallavi Alur, Arun Chandrasekhar, Shawna M. Liff
  • Patent number: 10734318
    Abstract: A fold in a semiconductor package substrate includes an embedded device that includes orthogonal electrical coupling through the package substrate by a bond-pad via that is configured to couple to a semiconductive device that is mounted on the semiconductor package substrate. The semiconductive device is coupled to the embedded device with the orthogonal electrical coupling.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: August 4, 2020
    Assignee: Intel Corporation
    Inventors: Bok Eng Cheah, Jackson Chung Peng Kong, Khang Choong Yong, Yun Rou Lim
  • Patent number: 10714452
    Abstract: The present invention provides a method of manufacturing a package structure. An array chip including a plurality of first dies is provided. A wafer including a plurality of second dies is provided. A package step is carried out to package the array chip onto the wafer so as to electrically connect the first die and the second die. The present invention further provides a semiconductor wafer and a package structure.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: July 14, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Chien-Li Kuo
  • Patent number: 10676344
    Abstract: An environmental-barrier layer can protect a die or an array of die. A substrate that includes various functional components can be coupled to a porous environmental-barrier layer to form an array of die prior to dividing the array into individual die. The porous environmental-barrier layer can be a layer that includes polymer or fluoropolymer. The porous environmental-barrier layer can also be a filter layer for allowing certain waves to pass through and blocking particles and other debris. The porous environmental-barrier layer can protect each die in the array and the functional components from damage by protecting the die and the functional components from mechanical, electrical, or environmental damage (e.g., contamination by fluid or dust) without impeding a function of the functional components.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: June 9, 2020
    Assignee: W. L. Gore & Associates, Inc.
    Inventors: Andrew J. Holliday, William A. Kinder, Nathaniel J. Hoover
  • Patent number: 10667396
    Abstract: Integrated multilayer structure (100, 200, 300, 400, 500, 600, 700) comprising a first substrate film (102) having a first side (102A), said first substrate film comprising electrically substantially insulating material, said first substrate film preferably being formable and optionally thermoplastic, a plastic layer (112) molded onto said first side of the first substrate film so as to at least partially cover it, and circuitry (104, 106, 204, 205), optionally comprising an electronic, electromechanical and/or electro-optical component, provided on the second side of the first substrate film, said circuitry being functionally connected to the first side of the first substrate film.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: May 26, 2020
    Assignee: TACTOTEK OY
    Inventors: Antti Keranen, Ronald Haag, Mikko Heikkinen
  • Patent number: 10651154
    Abstract: A semiconductor package includes a plurality of semiconductor chips on a substrate. The semiconductor chips include a first semiconductor chip, a second semiconductor chip, and a third semiconductor chip that are sequentially stacked on the substrate. The semiconductor package further includes a plurality of non-conductive layers between the substrate and the first semiconductor chip and between adjacent semiconductor chips among the semiconductor chips. The semiconductor chips include smaller widths as a distance from the substrate increases. Each of the non-conductive layers includes an extension protruding outward from a side surface of an overlying one of the semiconductor chips.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: May 12, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Sick Park, Geol Nam, Tae Hong Min, Jihwan Hwang
  • Patent number: 10610693
    Abstract: An encapsulation configuration for electronic components in a flexible implantable medical device, including at least one set of folded circuit boards and a filler material, the set of folded circuit boards including a plurality of circuit boards and a plurality of connection cables, each one of the circuit boards including at least one electronics component, each one of the circuit boards having a generally rectangular shape, the connection cables electrically coupling adjacent ones of the circuit boards and the circuit boards being folded over one another in a pleated manner, the filler material surrounding the set of folded circuit boards, the filler material and the set of folded circuit boards together having a cylindrical shape, the set of folded circuit boards being positioned lengthwise in the cylindrical shape and the electronics component being positioned on the set of folded circuit boards to achieve optimal volume consumption in the electronics encapsulation.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: April 7, 2020
    Assignee: NewPace Ltd.
    Inventors: Gera Strommer, Avi Broder, Moti Mocha, Robert S. Fishel, Nahum Natan
  • Patent number: 10600705
    Abstract: An electronic switching element includes at least one semiconductor switch inserted into a layer sequence of a conductor structure element; and at least two busbars which are configured to contact-connect the at least one semiconductor switch, wherein the at least two busbars run substantially above one another in the layer sequence of the conductor structure element.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: March 24, 2020
    Assignee: SCHWEIZER ELECTRONIC AG
    Inventors: Thomas Gottwald, Christian Rössle, Rainer Jäackle
  • Patent number: 10594355
    Abstract: Devices and methods related to radio-frequency (RF) filters on silicon-on-insulator (SOI) substrate. In some embodiments, an RF device can include a silicon die such as an SOI die including a first side and a second side. The silicon die can further include a plurality of vias, with each via configured to provide an electrical connection between the first side and the second side of the silicon die. The RF device can further include at least one RF flip chip mounted on the first side of the silicon die. The silicon die can include, for example, an RF circuit such as a switch circuit, and the RF flip chip can include, for example, a filter such as a surface acoustic wave (SAW) filter.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: March 17, 2020
    Assignee: Skyworks Solutions, Inc.
    Inventor: James Phillip Young
  • Patent number: 10573579
    Abstract: A semiconductor package includes a package substrate having a top surface and a bottom surface, an interposer mounted on the top surface of the package substrate, a first semiconductor die and a second semiconductor die mounted on the interposer in a side-by-side manner, and a stiffener ring secured to the top surface of the package substrate. The stiffener ring encircles the first semiconductor die and the second semiconductor die. The stiffener ring comprises a reinforcement rib striding across the interposer.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: February 25, 2020
    Assignee: MEDIATEK INC.
    Inventors: Tai-Yu Chen, Wen-Sung Hsu, Sheng-Liang Kuo, Chi-Wen Pan, Jen-Chuan Chen
  • Patent number: 10546952
    Abstract: The present invention provides a method of manufacturing a semiconductor device to improve the manufacturing yield of the semiconductor device. The manufacturing method includes the steps of: forming a groove extending in a first direction (y direction) across a first power transistor formation region and a second power transistor formation region, in a back surface of a semiconductor wafer; filling the groove with a conductor film by forming the conductor film on the back surface in which the groove is formed; and exposing the back surface of the semiconductor wafer by removing a portion of the conductor film.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: January 28, 2020
    Assignee: Renesas Electronics Corporation
    Inventor: Tetsuji Togami
  • Patent number: 10537018
    Abstract: One semiconductor device includes a wiring substrate, a first semiconductor chip that is mounted on one surface of the wiring substrate, a second semiconductor chip that is laminated on the first semiconductor chip so as to form exposed surfaces where the surface of the first semiconductor chip is partially exposed, silicon substrates that are mounted on the exposed surfaces and serve as warping control members, and an encapsulation body that is formed on the wiring substrate so as to cover the first semiconductor chip, the second semiconductor chip and the silicon substrates.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: January 14, 2020
    Assignee: Longitude Licensing Limited
    Inventor: Sensho Usami
  • Patent number: 10515937
    Abstract: A semiconductor device and method for providing an enhanced removal of heat from a semiconductor die within an integrated fan out package on package configuration is presented. In an embodiment a metal layer is formed on a backside of the semiconductor die, and the semiconductor die along and through vias are encapsulated. Portions of the metal layer are exposed and a thermal die is connected to remove heat from the semiconductor die.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: December 24, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jing-Cheng Lin, Po-Hao Tsai, Li-Hui Cheng, Porter Chen
  • Patent number: 10468356
    Abstract: A system module package is disclosed. The system module package includes: a substrate; a first electrical component and a second electrical component disposed on a top surface of the substrate; and a plurality of bond wires disposed adjacent to at least a first side of the first electrical component and in between the first and second electrical components. The plurality of bond wires are configured to attenuate EMI of a frequency of interest traveling from the first electrical component toward the second electrical component, or from the second electrical component toward the first electrical component. Each of the plurality of bond wires has at least a first end that is mechanically coupled to the top surface of the substrate and has a highest point that is a height, H, from the top surface of the substrate.
    Type: Grant
    Filed: February 18, 2019
    Date of Patent: November 5, 2019
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Ah Ron Lee, Deog Soon Choi, Young Ho Lee, Boon Keat Tan, Jin Ho Choi
  • Patent number: 10431550
    Abstract: A fan-out electronic component package includes a core, a first electronic component, a first encapsulant, a connection member, a second electronic component, and a second encapsulant. The core member includes a through-hole, wiring layers and vias configured to electrically connect the wiring layers to each other. The first electronic component is disposed in the through-hole, and comprising filters configured to filter different frequency bands. The first encapsulant covers portions of the core member and the first electronic component, and fills portions of the through-hole. The connection member is disposed on the core member and the first electronic component, and includes a redistribution layer electrically connected to the wiring layers and the first electronic component. The second electronic component is disposed on the connection member and electrically connects to the redistribution layer. The second encapsulant is disposed to cover the second electronic component.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: October 1, 2019
    Assignee: Samsung EIectro-Mechanics Co., Ltd.
    Inventors: Myeong Woo Han, Chan Yong Jeong
  • Patent number: 10403331
    Abstract: A semiconductor device includes a memory cell array, pad groups, a first option pad, a second option pad and a data input multiplexer block configured to transmit data, input through all or part of the pad groups, to the memory cell array based on whether the first option pad and a ground are connected to each other, wherein the data input multiplexer block is configured to select first pad groups among the pad groups or second pad groups among the pad groups as the part of the pad groups based on whether the second option pad and the ground are connected to each other.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: September 3, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yong Gyu Chu, Hyo Soon Kang, Seung Bum Ko, Sang Jae Rhee
  • Patent number: 10394211
    Abstract: An electronic safety switching device comprising at least a first and a second signal processing channel to which input signals may be supplied for signal processing. The first and second signal processing channels provide processed output signals, wherein the first and the second signal processing channels process the supplied input signals redundantly with respect to one other. The first and the second signal processing channels are each formed as integrated circuits, wherein the first signal processing channel is arranged monolithically on a first semiconductor substrate, and the second signal processing channel is arranged monolithically on a second semiconductor substrate. Furthermore, the first and the second semiconductor substrates are combined into a stack to form a one-piece electronic component.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: August 27, 2019
    Assignee: PILZ GMBH & CO. KG
    Inventors: Thorsten Godau, Norbert Froehlich, Matthias Holzaepfel, Hans Schwenkel
  • Patent number: 10383572
    Abstract: A method includes forming one or more vias in a substrate, forming a first photoresist layer on a top surface of the substrate and a second photoresist layer on a bottom surface of the substrate, patterning the first photoresist layer and the second photoresist layer to remove at least a first portion of the first photoresist layer and at least a second portion of the second photoresist layer, filling the one or more vias, the first portion and the second portion with solder material using injection molded soldering, and removing remaining portions of the first photoresist layer and the second photoresist layer.
    Type: Grant
    Filed: June 1, 2017
    Date of Patent: August 20, 2019
    Assignee: International Business Machines Corporation
    Inventors: John U. Knickerbocker, Shriya Kumar, Jae-Woong Nah
  • Patent number: 10388539
    Abstract: In accordance with an embodiment, a semiconductor component includes a support having a side in which a device receiving structure and an interconnect structure are formed and a side from which a plurality of leads extends. A semiconductor device having a control terminal and first and second current carrying terminals and configured from a III-N semiconductor material is mounted to the device receiving structure. The control terminal of the first electrical interconnect is coupled to a first lead by a first electrical interconnect. A second electrical interconnect is coupled between the first current carrying terminal of the semiconductor device and a second lead. The second current carrying terminal of the first semiconductor device is coupled to the device receiving structure or to the interconnect structure.
    Type: Grant
    Filed: July 6, 2016
    Date of Patent: August 20, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Chun-Li Liu, Ali Salih, Mingjiao Liu
  • Patent number: 10381328
    Abstract: A 3D semiconductor device and structure, including: a first die including first transistors and first interconnect, overlaid by a second die including second transistors and second interconnect, where the first die has a first die area and the second die has a second die area, where the first die area is at least 10% larger than the second die area, and where the second die has a thickness of less than four microns.
    Type: Grant
    Filed: June 24, 2017
    Date of Patent: August 13, 2019
    Assignee: MONOLITHIC 3D INC.
    Inventor: Zvi Or-Bach
  • Patent number: 10379155
    Abstract: In an example implementation, an integrated circuit (IC) includes: a plurality of transistors disposed in a plurality of locations on a die of the IC; conductors coupled to terminals of each of the plurality of transistors; a digital-to-analog converter (DAC), coupled to the conductors, to drive voltage signals to the plurality of transistors in response to a digital input; and an analog-to-digital converter (ADC), coupled to at least a portion of the conductors, to generate samples in response to current signals induced in the plurality of transistors in response to the voltage signals, the samples being indicative of at least one electrostatic characteristic for the plurality of transistors.
    Type: Grant
    Filed: October 2, 2014
    Date of Patent: August 13, 2019
    Assignee: XILINX, INC.
    Inventors: Ping-Chin Yeh, John K. Jennings, Rhesa Nathanael, Nui Chong, Cheang-Whang Chang, Daniel Y Chung
  • Patent number: 10342118
    Abstract: One semiconductor device includes a wiring substrate, a first semiconductor chip that is mounted on one surface of the wiring substrate, a second semiconductor chip that is laminated on the first semiconductor chip so as to form exposed surfaces where the surface of the first semiconductor chip is partially exposed, silicon substrates that are mounted on the exposed surfaces and serve as warping control members, and an encapsulation body that is formed on the wiring substrate so as to cover the first semiconductor chip, the second semiconductor chip and the silicon substrates.
    Type: Grant
    Filed: March 20, 2014
    Date of Patent: July 2, 2019
    Assignee: LONGITUDE LICENSING LIMITED
    Inventor: Sensho Usami
  • Patent number: 10329143
    Abstract: A packaged MEMS device, wherein at least two support structures are stacked on each other and are formed both by a support layer and a wall layer coupled to each other and delimiting a respective chamber. The chamber of the first support structure is upwardly delimited by the support layer of the second support structure. A first and a second dice are accommodated in a respective chamber, carried by the respective support layer of the first support structure. The support layer of the second support structure has a through hole allowing wire connections to directly couple the first and the second dice. A lid substrate, coupled to the second support structure, closes the chamber of the second support structure.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: June 25, 2019
    Assignee: STMicroelectronics (Malta) Ltd
    Inventor: Kevin Formosa
  • Patent number: 10325856
    Abstract: An electronic component package includes first and second wiring parts including insulating layers, conductive patterns formed in the insulating layers, and conductive vias penetrating through the insulating layers, to be connected to the conductive patterns, respectively; a frame disposed between the first and second wiring parts and having conductive connection parts electrically connecting one or more through-holes with the first and second wiring parts and an electronic component disposed to be surrounded by the through-hole, to thereby be connected to the first wiring part, wherein the conductive patterns formed to be adjacent to the electronic component among the conductive patterns of the first wiring part are embedded in the insulating layer of the first wiring part.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: June 18, 2019
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Yong Ho Baek, Sang Kun Kim, Ye Jeong Kim, Jae Ean Lee, Jae Hoon Choi
  • Patent number: 10325875
    Abstract: Disclosed is an integrated circuit packaging system that includes first and second microchips. Each microchip includes a top surface, a surface, one or more quilt package nodules fabricated on said top surface, and one or more bottom surface connectors. The system also includes a substrate to which the first and second microchips are mounted. The first and second microchips are connected via the quilt package nodules.
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: June 18, 2019
    Assignees: North Carolina State University, Indiana Integrated Circuits, LLC
    Inventors: Jason M. Kulick, Douglas Hopkins
  • Patent number: 10325882
    Abstract: A method of manufacturing a semiconductor package includes providing a substrate including a mounting region having a recess space for accommodating a semiconductor chip and a connection region surrounding the mounting region, providing a semiconductor chip in the mounting region, the semiconductor chip including a connection pad provided on a top surface of the semiconductor chip, forming a protective layer covering a top surface of the substrate and the top surface of the semiconductor chip, forming a photosensitive insulating layer on the protective layer after forming the protective layer, patterning the photosensitive insulating layer thereby exposing the protective layer, removing the exposed protective layer, and forming a redistribution line to be electrically connected to the connection pad.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: June 18, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tae-woo Kang, Byung-lyul Park, Kyoung-hwan Kim, Kun-sang Park, Young-gyu Ahn
  • Patent number: 10312221
    Abstract: Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device includes a stack of plural semiconductor chips. Each two adjacent semiconductor chips of the plural semiconductor chips is electrically connected by plural interconnects and physically connected by a first insulating bonding layer. A first stack of dummy chips is positioned opposite a first side of the stack of semiconductor chips and separated from the plural semiconductor chips by a first gap. Each two adjacent of the first dummy chips are physically connected by a second insulating bonding layer. A second stack of dummy chips is positioned opposite a second side of the stack of semiconductor chips and separated from the plural semiconductor chips by a second gap. Each two adjacent of the second dummy chips are physically connected by a third insulating bonding layer.
    Type: Grant
    Filed: December 17, 2017
    Date of Patent: June 4, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Rahul Agarwal, Kaushik Mysore Srinivasa Setty, Milind S. Bhagavat, Brett P. Wilkerson