Abstract: Interconnect structures with intermetallic palladium joints are disclosed herein. In one embodiment, a method of forming an interconnect structure includes depositing a first conductive material comprising nickel on a first conductive surface of a first die, and depositing a second conductive material comprising nickel on a second conductive surface of a second die spaced apart from the first surface. The method further includes depositing a third conductive material on the second conductive material, and thermally compressing tin/solder between the first and third conductive materials to form an intermetallic palladium joint that extends between the first conductive material and the second conductive material such that one end of the intermetallic palladium joint is bonded directly to the first conductive material and an opposite end of the intermetallic palladium joint is bonded directly to the second conductive material.

Abstract: A component built-in board of multi-layer structure that has a plurality of unit boards stacked therein and is configured having a plurality of electronic components built in thereto in a stacking direction, wherein the plurality of unit boards include: a double-sided board that includes a first insulating layer, a first wiring layer formed on both surfaces of the first insulating layer, and a first interlayer conductive layer that penetrates the first insulating layer and is connected to the first wiring layer, and that comprises an opening in which the electronic component is housed; and an intermediate board that includes a second insulating layer, a first adhesive layer provided on both surfaces of the second insulating layer, and a second interlayer conductive layer that penetrates the second insulating layer along with the first adhesive layer, and the double-sided board is disposed above and below the intermediate board.

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a cavity in a plating material to hold a die, attaching the die in the cavity, forming a dielectric material adjacent the die, forming vias in the dielectric material adjacent the die, forming PoP lands in the vias, forming interconnects in the vias, and then removing the plating material to expose the PoP lands and die, wherein the die is disposed above the PoP lands.

Abstract: A method for fabricating a MEMS-IC device structure can include receiving a CMOS substrate comprising a plurality of CMOS circuits and a surface portion. A MEMS substrate having at least one MEMS device can be received and coupled to the CMOS substrate. The MEMS substrate and the surface portion of the CMOS substrate can be encapsulated with a molding material, which forms a top surface. A first plurality of vias can be created in the molding material from the top surface to the surface portion of the CMOS substrate. A conductive material can be disposed within the first plurality of vias such that the conductive material is electrically coupled to a portion of the CMOS substrate. A plurality of interconnects can be formed from the conductive material to the top surface of the molding material and a plurality of solder balls can be formed upon these interconnects.

Abstract: A method of forming an integrated circuit, including providing a first substrate layer having a center piece and two side pieces on opposite sides of the center piece, assembling one or more circuit elements on a top side and a bottom side of the center piece of the first substrate layer, preparing two support pieces from a substrate, matching the size of the side pieces, coupling the support pieces to the bottom of the first substrate layer under the side pieces to form a second substrate layer with a void in the center under the center piece of the first substrate layer; and wherein the side pieces and support pieces include via connectors electrically connecting between a bottom side of the second substrate layer and the circuit elements.

Abstract: Semiconductor integrated circuits (110) or assemblies are disposed at least partially in cavities between two interposers (120). Conductive vias (204M) pass through at least one of the interposers or at least through the interposer's substrate, and reach a semiconductor integrated circuit or an assembly. Other conductive vias (204M.1) pass at least partially through multiple interposers and are connected to conductive vias that reach, or are capacitively coupled to, a semiconductor IC or an assembly. Other features are also provided.

Abstract: A microelectronic structure has active elements defining a storage array, and address inputs for receipt of address information specifying locations within the storage array. The structure has a first surface and can have terminals exposed at the first surface. The terminals may include first terminals and the structure may be configured to transfer address information received at the first terminals to the address inputs. Each first terminal can have a signal assignment which includes one or more of the address inputs. The first terminals are disposed on first and second opposite sides of a theoretical plane normal to the first surface, wherein the signal assignments of the first terminals disposed on the first side are a mirror image of the signal assignments of the first terminals disposed on the second side of the theoretical plane.

Abstract: A semiconductor package includes: a package base substrate; at least one first semiconductor chip disposed on the package base substrate; a first molding member disposed at a same level as the at least one first semiconductor chip and that does not cover an upper surface of the at least one first semiconductor chip; at least one second semiconductor chip stacked on the at least one first semiconductor chip so as to extend over the at least one first semiconductor chip and the first molding member, wherein the at least one first semiconductor chip and at least part of the first molding member are disposed between the package base substrate and the at least one second semiconductor chip; and a second molding member disposed at a same level as the at least one second semiconductor chip.

Abstract: A stress compensation for use in packaging, and a method of forming, is provided. The stress compensation layer is placed on an opposing side of a substrate from an integrated circuit die. The stress compensation layer is designed to counteract at least some of the stress exerted structures on the die side of the substrate, such as stresses exerted by a molding compound that at least partially encapsulates the first integrated circuit die. A package may also be electrically coupled to the substrate.

Abstract: A method of forming at least one Micro-Electro-Mechanical System (MEMS) includes forming a beam structure and an electrode on an insulator layer, remote from the beam structure. The method further includes forming at least one sacrificial layer over the beam structure, and remote from the electrode. The method further includes forming a lid structure over the at least one sacrificial layer and the electrode. The method further includes providing simultaneously a vent hole through the lid structure to expose the sacrificial layer and to form a partial via over the electrode. The method further includes venting the sacrificial layer to form a cavity. The method further includes sealing the vent hole with material. The method further includes forming a final via in the lid structure to the electrode, through the partial via.

Abstract: A package structure is provided, which includes: a substrate having opposite top and bottom surfaces and a plurality of conductive pads and a plurality of conductive posts formed therein, wherein the conductive pads are exposed from the bottom surface of the substrate, and the conductive posts are electrically connected to the conductive pads and each of the conductive posts has an end surface exposed from the top surface of the substrate; a plurality of first conductive bumps formed on the end surfaces of the conductive posts; a plurality of second conductive bumps formed on the top surface of the substrate, wherein the second conductive bumps are higher than the first conductive bumps; and at least a first electronic element disposed on and electrically connected to the first conductive bumps, thereby increasing the wiring flexibility and facilitating subsequent disposing of electronic elements without changing existing machines.

Abstract: Package assemblies for and methods of packaging integrated circuit chips are described. Disclosed package assemblies have spacers and recessed regions comprising IC chips. Architectural structures are provided that enable, for example, three dimensional (3D) packaging (or system in package (SiP) or multi-chip modules), systems-on-chip 3D packaging, and hybrid 3D bonding. Embodiments of the invention can be used, for example, to create logic-to-memory, memory-to-memory, and logic-to-logic interface stacking assemblies.

Abstract: Fusible instructions and logic provide OR-test and AND-test functionality on multiple test sources. Some embodiments include a processor decode stage to decode a test instruction for execution, the instruction specifying first, second and third source data operands, and an operation type. Execution units, responsive to the decoded test instruction, perform one logical operation, according to the specified operation type, between data from the first and second source data operands, and perform a second logical operation between the data from the third source data operand and the result of the first logical operation to set a condition flag. Some embodiments generate the test instruction dynamically by fusing one logical instruction with a prior-art test instruction. Other embodiments generate the test instruction through a just-in-time compiler. Some embodiments also fuse the test instruction with a subsequent conditional branch instruction, and perform a branch according to how the condition flag is set.

Abstract: A microelectronic package includes a subassembly including a first substrate and first and second microelectronic elements having contact-bearing faces facing towards oppositely-facing first and second surfaces of the first substrate and each having contacts electrically connected with the first substrate. The contact-bearing faces of the first and second microelectronic elements at least partially overlie one another. Leads electrically connect the subassembly with a second substrate, at least portions of the leads being aligned with an aperture in the second substrate. The leads can include wire bonds extending through an aperture in the first substrate and joined to contacts of the first microelectronic element aligned with the first substrate aperture. In one example, the subassembly can be electrically connected with the second substrate using electrically conductive spacer elements.

Abstract: A semiconductor device, and a method of its manufacture, are disclosed. The semiconductor device includes a semiconductor die, such as a controller die, mounted on a surface of a substrate. A spacer layer is also mounted to the substrate, with the semiconductor die fitting within an aperture or a notch formed through first and second major opposed surfaces of the spacer layer. Additional semiconductor die, such as flash memory die, may be mounted atop the spacer layer.

Abstract: A package structure includes a selective-electroplating epoxy compound, a first patterned circuit layer, second patterned circuit layers, metal studs, contact pads and conductive vias. The selective-electroplating epoxy compound includes cavities, a first surface and a second surface. The cavities disposed on the first surface in array arrangement. The selective-electroplating epoxy compound is formed by combining non-conductive metal complex. The metal studs are disposed in the cavities respectively and protruded from the first surface. The first patterned circuit layer is directly disposed on the first surface. The selective-electroplating epoxy compound exposes a top surface of the patterned circuit layer. The top surface is lower than or coplanar with the first surface. The second patterned circuit layers are directly disposed on the second surface.

Abstract: It is possible to provide a semiconductor device which can be obtained at a high reliability by warping an insulating substrate stably into a convex shape while ensuring a close contact between a cooling member and the insulating substrate. The semiconductor device includes an insulating substrate, a semiconductor element disposed on a first surface of the insulating substrate, a case connected to the insulating substrate, and a resin filled inside the case. Assuming that the thickness of the insulating substrate is denoted by t1, the thickness of the resin is denoted by t2, the linear expansion coefficient of the insulating substrate is denoted by ?1, and the linear expansion coefficient of the resin is denoted by ?2, the relationship therebetween satisfies t2?t1 and ?2??1, and a second surface of the insulating substrate opposite to the first surface thereof is warped into a convex shape.

Abstract: A thin design heat transfer device for thermal management is described herein. The heat transfer device uses a cold plate that is independent or “floating” relative to a spring mechanism employed to generate contact pressure with a heat-generating device. A bridge component associated with the spring mechanism is designed to span over the cold plate and contact the cold plate when the spring deforms, which therefore allows the cold plate to be independent of the spring mechanism. The independence between the cold plate and the spring mechanism enables deformation in the spring mechanism to drive contact pressure while eliminating or reducing corresponding deformation in the cold plate. Consequently, components of the heat transfer device may be made relatively thin and have less stiffness than traditional designs, but still provide acceptable contact pressure and quality for effective thermal management.

Abstract: Cardioprotective pacing is applied to prevent and/or reduce cardiac injury associated with myocardial infarction (MI) and revascularization procedure. Pacing pulses are generated from a flexible pacemaker circuit integrated with a percutaneous transluminal vascular intervention (PTVI) device and delivered through pacing electrodes incorporated onto the PTVI device during the revascularization procedure.

Abstract: There is provided an electronic device package including an electronic device including a first electrode and a second electrode disposed on a surface thereof, a package substrate having a first surface having the electronic device mounted thereon and a second surface opposed to the first surface. The package substrate includes a first electrode pattern and a second electrode pattern electrically connected to the first electrode and the second electrode on the first surface, respectively. The package substrate further includes at least one via hole disposed outside of a region for mounting the electronic device and an irregular portion disposed on the first surface to be adjacent to the via hole.

Abstract: A semiconductor device includes: a first output unit configured to output a first phase; a second output unit configured to output a second phase different from the first phase, the second output unit being disposed to be stacked on the first output unit; and a controller configured to control the output units.

Abstract: A system and method for packaging semiconductor device is provided. An embodiment comprises forming vias over a carrier wafer and attaching a first die over the carrier wafer and between a first two of the vias. A second die is attached over the carrier wafer and between a second two of the vias. The first die and the second die are encapsulated to form a first package, and at least one third die is connected to the first die or the second die. A second package is connected to the first package over the at least one third die.

Abstract: An electronic component device, includes, a plurality of wiring layers including a component connection pad in a center part and an external connection pad in a periphery, an insulating layer formed on the wiring layers, and the insulating layer in which the component connection pad and the external connection pad are exposed, a frame member arranged on the insulating layer, and the frame member in which an opening portion is provided in an area of the center part in which the component connection pad is arranged, and a connection hole is provided on the external connection pad, an electronic component arranged in the opening portion of the frame member and connected to the component connection pad, a sealing resin formed in the opening portion of the frame member and sealing the electronic component, and a metal bonding material formed on the external connection pad in the connection hole.

Abstract: A semiconductor package includes a lower package including a lower substrate, a lower semiconductor chip, and a lower molding layer exposing an upper surface of the lower semiconductor chip, bumps on the lower substrate, the bumps being spaced apart from the lower semiconductor chip, a lead frame on the lower semiconductor chip and on the bumps, the lead frame being electrically connected to the bumps and having a thermal conductivity of about 100 W/mk to about 10,000 W/mk, and an upper package on the lead frame and electrically connected to the lead frame.

Abstract: Systems, devices and methods related to improved radio-frequency (RF) modules. In some embodiments, an RF module can include a packaging substrate, a power amplifier (PA) assembly implemented on a first die mounted on the packaging substrate, and a controller circuit implemented on a second die mounted on the first die. The controller circuit can be configured to provide at least some control of the PA assembly. The RF module can further include one or more output matching network (OMN) devices mounted on the packaging substrate and configured to provide output matching functionality for the PA assembly. The RF module can further include a band selection switch device mounted on each OMN device.

Abstract: In a package-on-package (PoP) device according to the inventive concepts, an anisotropic conductive film is disposed between a lower semiconductor package and an upper semiconductor package to remove an air gap between the lower and upper semiconductor packages. Thus, heat generated from a lower semiconductor chip may be rapidly and smoothly transmitted toward the upper semiconductor package, thereby increasing or maximizing a heat exhaust effect of the PoP device.

Abstract: In a semiconductor device, a lower chip includes a first group of connection terminals provided on a straight region including a corner region and a region extending from the corner region along one side. An upper chip includes a second group of connection terminals. The upper chip and the lower chip are arranged so that the first group of connection terminals at least partially overlaps with the second group of connection terminals. The first group of connection terminals is at least partially electrically connected to the second group of connection terminals.

Abstract: Embodiments of methods for forming microelectronic device packages include forming a trench on a surface of a package body in an area adjacent to where first and second package surface conductors will be (or have been) formed on both sides of the trench. The method also includes forming the first and second package surface conductors to electrically couple exposed ends of various combinations of device-to-edge conductors. The trench may be formed using laser cutting, drilling, sawing, etching, or another suitable technique. The package surface conductors may be formed by dispensing (e.g., coating, spraying, inkjet printing, aerosol jet printing, stencil printing, or needle dispensing) one or more conductive materials on the package body surface between the exposed ends of the device-to-edge conductors.

Abstract: An electronic device may include leads, an IC having first and second bond pads, and an encapsulation material adjacent the leads and the IC so the leads extend to a bottom surface of the encapsulation material defining first contact pads. The electronic device may include bond wires between the first bond pads and corresponding ones of the leads, and conductors extending from corresponding ones of the second bond pads to the bottom surface of the encapsulation material defining second contact pads.

Abstract: A semiconductor device has a semiconductor die mounted to a carrier. A first encapsulant is deposited over the semiconductor die and carrier. A stiffening support member can be disposed over the carrier around the semiconductor die. A plurality of channels or recesses is formed in the first encapsulant. The recesses can be formed by removing a portion of the first encapsulant. Alternatively, the recesses are formed in a chase mold having a plurality of extended surfaces. A second encapsulant can be deposited into the recesses of the first encapsulant. The carrier is removed and an interconnect structure is formed over the semiconductor die and first encapsulant. The thickness of the first encapsulant provides sufficient stiffness to reduce warpage while the recesses provide stress relief during formation of the interconnect structure. A portion of the first encapsulant and recesses are removed to reduce thickness of the semiconductor device.

Abstract: A module can include a module card and first and second microelectronic elements having front surfaces facing a first surface of the module card. The module card can also have a second surface and a plurality of parallel exposed edge contacts adjacent an edge of at least one of the first and second surfaces for mating with corresponding contacts of a socket when the module is inserted in the socket. Each microelectronic element can be electrically connected to the module card. The front surface of the second microelectronic element can partially overlie a rear surface of the first microelectronic element and can be attached thereto.

Abstract: In one embodiment of the invention, a system in package (SiP) is described which includes a plurality of device components with different form factors embedded within a molding compound layer. A surface for each of the device components is coplanar with a surface of the molding compound layer, and a single redistribution layer (RDL) formed on the coplanar surfaces of the molding compound layer and the plurality of device components. An active device die is electrically bonded to the single RDL directly vertically adjacent the plurality of device components. In an embodiment, the SiP is electrically connected to a circuit board with the active device die between the single RDL and the circuit board. In an embodiment, the SiP is electrically connected to a circuit board with the active device die over the single RDL and the circuit board.

Abstract: Apparatus are disclosed, such as those involving a 3-D integrated circuit. One such apparatus includes a first die including a plurality of vertical connectors formed therethrough. The apparatus also includes a first circuit configured to encode multiple data bits into a multi-bit symbol, and provide the multi-bit symbol to two or more of the vertical connectors. The apparatus further includes a second circuit configured to receive the multi-bit symbol from at least one of the two or more vertical connectors, and decode the multi-bit symbol into the multiple data bits. The apparatus provides enhanced repairability with no or less redundant vertical connectors, thus avoiding the need for “on the fly” or field repair of defective vertical connectors.

Abstract: Methods of manufacturing semiconductor device assemblies include attaching a back side of a first semiconductor die to a substrate and structurally and electrically coupling a first end of laterally extending conductive elements to conductive terminals on or in a surface of the substrate. Second ends of the laterally extending conductive elements are structurally and electrically coupled to bond pads on or in an active surface of the first semiconductor die. Conductive structures are structurally and electrically coupled to bond pads of a second semiconductor die. At least some of the conductive structures are aligned with at least some of the bond pads of the first semiconductor die. An active surface of the second semiconductor die faces an active surface of the first semiconductor die. At least some of the conductive structures are structurally and electrically coupled to at least some of the bond pads of the first semiconductor die.

Abstract: A method and apparatus for packaging a semiconductor chip is presented. A semiconductor device includes a chip, a lead, and an encapsulant. The encapsulant includes a stabilization layer, a laminate molding layer connected to the stabilization layer, and a conductive strip connected to the laminate molding layer. The conductive strip electrically connects the contact area of the chip to the lead.

Abstract: A semiconductor device with a stacked power converter is described. In some examples, a semiconductor device includes: a first integrated circuit (IC) die having bond pads and solder bumps, the bond pads configured for wire-bonding; and a second IC die mounted on the first IC die, the second IC die having an active side and a backside opposite the active side, the second IC die including bond pads on the active side configured for wire-bonding, and solder bumps disposed on a backside opposite the active side; where the solder bumps of the first IC die are electrically and mechanically coupled to the solder bumps of the second IC die to form bump bonds.

Abstract: A semiconductor package includes a package substrate including a substrate connection pad. At least one semiconductor chip includes at least one redistribution layer. The at least one redistribution layer covers at least a portion of a chip connection pad and extends along an upper surface of the at least one semiconductor chip in a first direction in which the chip connection pad faces toward an edge of the at least one semiconductor chip. At least one interconnection line disposed on a side of the at least one semiconductor chip electrically connects the substrate connection pad to the at least one redistribution layer. The at least one redistribution layer includes a protruding portion protruding from the edge of the at least one semiconductor chip to contact the at least one interconnection line.

Abstract: The present invention provides a multi-axial acceleration sensor and a method of manufacturing the multi-axial acceleration sensor. The method includes: providing a substrate having a lead plane; disposing a first sensor chip onto the lead plane, wherein a wire bonding plane of the first sensor chip is perpendicular to the lead plane; and disposing a second sensor chip onto the lead plane, wherein a wire bonding plane of the second sensor chip is in parallel with the lead plane.

Abstract: An integrated circuit package includes a substrate having a heat conducting portion integrally formed with a heat dissipating portion. First and second integrated circuit dies are mounted to opposite sides of the heat conducting portion of the substrate. The first and second integrated circuit dies may each be packaged as flip-chip configurations. Electrical connections between contact pads on the first and second integrated circuit dies may be formed through openings formed in the heat conducting portion of the substrate. The heat dissipating portion may be positioned externally from a location between the first and second integrated circuit dies so that it dissipates heat away from the integrated circuit package into the surrounding environment.

Abstract: A semiconductor package includes a substrate having a substrate body possessing a first region, a second region which is defined around the first region and a third region which is defined around the second region. Wiring lines are placed on the substrate body, and the wiring lines have first ends that extend to the third region. Connection patterns are placed in the third region and are electrically connected to the first ends of the wiring lines. A to semiconductor chip is disposed in the first region and is electrically connected to the respective wiring lines, and a molding member is disposed in the first and second regions and covers the semiconductor chip.

Abstract: A device includes a first power semiconductor chip having a first face and a second face opposite to the first face with a first contact pad arranged on the first face. The first contact pad is an external contact pad. The device further includes a first contact clip attached to the second face of the first power semiconductor chip. A second power semiconductor chip is attached to the first contact clip, and a second contact clip is attached to the second power semiconductor chip.

Abstract: A method (70) of forming sensor packages (20) entails providing a sensor wafer (74) having sensors (30) formed on a side (26) positioned within areas (34) delineated by bonding perimeters (36), and providing a controller wafer (82) having control circuitry (42) at one side (38) and bonding perimeters (46) on an opposing side (40). The bonding perimeters (46) of the controller wafer (82) are bonded to corresponding bonding perimeters (36) of the sensor wafer (74) to form a stacked wafer structure (48) in which the control circuitry (42) faces outwardly. The controller wafer (82) is sawn to reveal bond pads (32) on the sensor wafer (74) which are wire bonded to corresponding bond pads (44) formed on the same side (38) of the wafer (82) as the control circuitry (42). The structure (48) is encapsulated in packaging material (62) and is singulated to produce the sensor packages (20).

Abstract: The stack package includes a first semiconductor package and a second semiconductor package. The first semiconductor package includes a first substrate having a first modulus and at least one semiconductor chip mounted on the first substrate. The second semiconductor package stacked on the first semiconductor package and includes a second substrate having a second modulus and at least one semiconductor chip mounted on the second substrate. The second modulus is less than the first modulus. Even in the event that the first semiconductor package is under severe warpage due to a temperature change, the flexible second substrate, which includes e.g., polyimide or poly ethylene terephthalate, of the second semiconductor package may be less sensitive to the temperature change, thereby improving reliability of the stack package.

Abstract: Some implementations provide a structure that includes a first package substrate, a first component, a second package substrate, a second component, and a third component. The first package substrate has a first area. The first component has a first height and is positioned on the first area. The second package substrate is coupled to the first package substrate. The second package substrate has second and third areas. The second area of the second package substrate vertically overlaps with the first area of the first package substrate The third area of the second package substrate is non-overlapping with the first area of the first package substrate. The second component has a second height and is positioned on the second area. The third component is positioned on the third area. The third component has a third height that is greater than each of the first and second heights.

Abstract: A three dimensional package includes a substrate having a columnar part including a sidewall, and stairs or steps arranged along the sidewall of the columnar part in the form of multiple helixes twisted around the columnar part. Semiconductor integrated circuits (IC dies) are attached on one or both of the supporting surfaces of the stairs. The columnar part, the stairs and the IC dies can be encapsulated with a mold compound.

Abstract: A package structure and a packaging method thereof are provided, in which an inductor is integrated into a substrate so as to save a packaging space and thus improve the integration level and packaging effect of the system.

Abstract: A semiconductor package includes a lower package including a lower semiconductor chip on a lower package substrate, an upper package on the lower package, and a heat interface material between the lower package and the upper package. The upper package includes an upper semiconductor chip on an upper package substrate including a center portion adjacent to the lower semiconductor chip and an edge portion. The heat interface material is in contact with a top surface of the lower semiconductor chip and the upper package substrate. The upper package substrate includes a heat diffusion via penetrating the center portion and an interconnection via penetrating the edge portion. The interconnection via is spaced apart from the heat diffusion via.

Abstract: A memory device with die stacking is provided. A plurality of substrates layers are stacked together into a stack. Each substrate layer may include a substrate having a plurality of cavities to receive integrated circuit components within the thickness of the substrate. A plurality of conductive spheres are arranged between at least two adjacent substrate layers and are electrically coupled to the integrated circuit components in at least one of the two adjacent substrates. The two adjacent substrate layers of the stack include: (a) a first substrate having a first plurality of cavities to receive integrated circuit components, and (b) a second substrate having a second plurality of cavities to receive integrated circuit components, wherein the first plurality of cavities is offset from a second plurality of cavities.

Abstract: A semiconductor device includes a substrate in which a cell region and a contact region are defined, a pad structure including a plurality of first conductive layers and a plurality of first insulating layers formed alternately with each other in the contact region of the substrate, wherein an end of the pad structure is patterned stepwise, portions of the first conductive layers exposed at the end of the pad structure are defined as a plurality of pad portions, and the plurality of pad portions have a greater thickness than unexposed portions of the plurality of first conductive layers.

Abstract: Systems and methods for improving thermal performance, such as thermal dissipation, of flip chip packages that include one or more flip chip dies are disclosed. In some embodiments, a thermal collection layer can be formed on a surface of a flip chip die. The thermal collection layer can be configured to dissipate heat generated by the flip chip die. In some variations, the thermal collection layer can be constructed using materials having high thermal conductivity.