Stacked Arrangement Patents (Class 257/686)
  • Patent number: 10854548
    Abstract: Inter-die passive interconnects are lengthened while locating I/O circuitry away from die edge, such that passive interconnect length is agglomerated toward the die edge, and inter-die communication is expedited.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: December 1, 2020
    Assignee: Intel Corporation
    Inventors: Zuoguo Wu, Debendra Das Sharma, Adel A. Elsherbini, Gerald Pasdast
  • Patent number: 10854530
    Abstract: The present disclosure describes heat dissipation structures formed in functional or non-functional areas of a three-dimensional chip structure. These heat dissipation structures are configured to route the heat generated within the three-dimensional chip structure to designated areas on or outside the three-dimensional chip structure. For example, the three-dimensional chip structure can include a plurality of chips vertically stacked on a substrate, a first passivation layer interposed between a first chip and a second chip of the plurality of chips, and a heat dissipation layer embedded in the first passivation layer and configured to allow conductive structures to pass through.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: December 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yun-Wei Cheng, Chun-Hao Chou, Kuo-Cheng Lee, Ying-Hao Chen
  • Patent number: 10854567
    Abstract: Embodiments of the present disclosure include a semiconductor device and methods of forming a semiconductor device. An embodiment is a method of forming a semiconductor device, the method comprising forming a conductive pad in a first substrate, forming an interconnecting structure over the conductive pad and the first substrate, the interconnecting structure comprising a plurality of metal layers disposed in a plurality of dielectric layers, bonding a die to a first side of the interconnecting structure, and etching the first substrate from a second side of the interconnecting structure, the etching exposing a portion of the conductive pad.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: December 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shang-Yun Hou, Sao-Ling Chiu, Ping-Kang Huang, Wen-Hsin Wei, Wen-Chih Chiou, Shin-Puu Jeng, Bruce C. S. Chou
  • Patent number: 10847505
    Abstract: A semiconductor package includes a first die; a first redistribution structure over the first die, the first redistribution structure being conterminous with the first die; a second die over the first die, a first portion of the first die extending beyond a lateral extent of the second die; a conductive pillar over the first portion of the first die and laterally adjacent to the second die, the conductive pillar electrically coupled to first die; a molding material around the first die, the second die, and the conductive pillar; and a second redistribution structure over the molding material, the second redistribution structure electrically coupled to the conductive pillar and the second die.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: November 24, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chia Lai, Kuo Lung Pan, Hung-Yi Kuo, Tin-Hao Kuo, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
  • Patent number: 10847499
    Abstract: Methods and systems for stacking multiple chips with high speed serializer/deserializer blocks are presented. These methods make use of Through Via (TV) to connect the dice to each other, and to the external pads.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: November 24, 2020
    Assignee: BroadPak Corporation
    Inventor: Farhang Yazdani
  • Patent number: 10847488
    Abstract: A semiconductor package includes a carrier substrate having a top surface, a semiconductor die mounted on the top surface, a plurality of bonding wires connecting an active surface of the semiconductor die to the top surface of the carrier substrate, an insulating material encapsulating the plurality of bonding wires, a component mounted on the insulating material, and a molding compound covering the top surface of the carrier substrate and encapsulating the semiconductor die, the plurality of bonding wires, the component and the insulating material.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: November 24, 2020
    Assignee: MediaTek Inc.
    Inventor: Shiann-Tsong Tsai
  • Patent number: 10840239
    Abstract: A 3D integrated circuit device, including: a first layer including first transistors, overlaid by a second layer including second transistors, overlaid by a third layer including third transistors, where the first layer, the second layer and the third layer are each thinner than 2 microns, where the first layer includes first circuits including at least one of the first transistors, where the second layer includes second circuits including at least one of the second transistors, and where the third layer includes a charge pump circuit and control circuits to control the first circuits and the second circuits.
    Type: Grant
    Filed: April 9, 2017
    Date of Patent: November 17, 2020
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist
  • Patent number: 10840883
    Abstract: An apparatus includes a microelectromechanical system (MEMS) die having a first surface and an opposing second surface. The MEMS die includes a surface-mounted resonator on the first surface and includes a first inductor. The apparatus also includes first and second dies. The first die has a third surface and an opposing fourth surface. The first die is coupled to the MEMS die such that the third surface of the first die faces the first surface of the MEMS die. The first and second surfaces are spaced apart. The first die includes an oscillator circuit and a second inductor. The oscillator circuit is coupled to the second inductor. The second inductor is inductively coupled to the first inductor. The second die is electrically coupled to the first die.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: November 17, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Bichoy Bahr, Ting-Ta Yen
  • Patent number: 10840201
    Abstract: Methods and apparatus for forming a semiconductor device package with a transmission line using a micro-bump layer are disclosed. The micro-bump layer may comprise micro-bumps and micro-bump lines, formed between a top device and a bottom device. A signal transmission line may be formed using a micro-bump line above a bottom device. A ground plane may be formed using a redistribution layer (RDL) within the bottom device, or using additional micro-bump lines. The RDL formed ground plane may comprise open slots. There may be RDLs at the bottom device and the top device above and below the micro-bump lines to form parts of the ground planes.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: November 17, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Wei Kuo, Hsiao-Tsung Yen, Min-Chie Jeng, Yu-Ling Lin
  • Patent number: 10840214
    Abstract: An integrated circuit (IC) chip carrier includes one or more memory devices therein. The memory is integrated into the carrier prior to the IC chip being connected to the carrier. Therefore, the IC chip may be connected to the memory at the same time as the IC chip is connected to the carrier. An access instruction may be sent from the IC chip to the memory through a wiring line of the IC chip carrier. Power potential may be sent from a system board to the memory through a vertical interconnect access (VIA). Alternatively, an access instruction may be sent from a first IC chip to the memory and power potential may be sent from a second IC chip to the memory.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: November 17, 2020
    Assignee: International Business Machines Corporation
    Inventors: Charles L. Arvin, Brian M. Erwin, Mark W. Kapfhammer, Brian W. Quinlan, Charles L. Reynolds, Thomas Weiss
  • Patent number: 10833001
    Abstract: A method of forming an interconnect that includes providing a sacrificial trace structure using an additive forming method. The sacrificial trace structure having a geometry for the interconnect. The method continuous with forming a continuous seed metal layer on the sacrificial trace structure; and removing the sacrificial trace structure, wherein the continuous seed metal layer remains. An interconnect metal layer may be formed on the continuous seed layer. A dielectric material may then be formed on the interconnect metal layer to encapsulate a majority of the interconnect metal layer, wherein ends of the interconnect metal layer are exposed through one surface of the dielectric material to provide an interconnect extending into a dielectric material.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: November 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Daniel J. Buvid, Eric J. Campbell, Sarah K. Czaplewski, Christopher W. Steffen
  • Patent number: 10832912
    Abstract: Direct-bonded native interconnects and active base dies are provided. In a microelectronic architecture, active dies or chiplets connect to an active base die via their core-level conductors. These native interconnects provide short data paths, which forgo the overhead of standard interfaces. The system saves redistribution routing as the native interconnects couple in place. The base die may contain custom logic, allowing the attached dies to provide stock functions. The architecture can connect diverse interconnect types and chiplets from various process nodes, operating at different voltages. The base die may have state elements for drive. Functional blocks aboard the base die receive native signals from diverse chiplets, and communicate with all attached chiplets. The chiplets may share processing and memory resources of the base die. Routing blockages are minimal, improving signal quality and timing. The system can operate at dual or quad data rates.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: November 10, 2020
    Assignee: Xcelsis Corporation
    Inventors: Javier A. Delacruz, Steven L. Teig, Shaowu Huang, William C. Plants, David Edward Fisch
  • Patent number: 10831963
    Abstract: A non-volatile dual-in-line memory module (NVDIMM) with a parallel architecture is described. It enables parallel access to on-board nonvolatile memory (NVM) to improve storage throughput and to alleviate layout design constraints.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: November 10, 2020
    Inventor: Kong-Chen Chen
  • Patent number: 10833051
    Abstract: Place a first semiconductor chip onto an alignment carrier with protrusions of the semiconductor chip inserted into corresponding cavities of the alignment carrier, so that the protrusions and cavities locate the semiconductor chip with interconnect contacts overlying a window that is formed through the alignment carrier. Place a second semiconductor chip onto the alignment carrier with protrusions of the second semiconductor chip inserted into cavities of the alignment carrier, so that the protrusions and cavities locate the second semiconductor chip with interconnect contacts of the second semiconductor chip adjacent to the interconnect contacts of the first semiconductor chip and overlying the window. Fasten the semiconductor chips to the alignment carrier. Touch contacts of a interconnect bridge against the interconnect contacts of the first and second semiconductor chips by putting the interconnect bridge through the window.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Charles L. Arvin, Thomas Weiss, Thomas Anthony Wassick, Steve Ostrander
  • Patent number: 10833031
    Abstract: A package includes a corner, a device die, a molding material molding the device die therein, and a plurality of bonding features. The plurality of bonding features includes a corner bonding feature at the corner, wherein the corner bonding feature is elongated. The plurality of bonding features further includes an additional bonding feature, which is non-elongated.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: November 10, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Hsien-Wei Chen
  • Patent number: 10825707
    Abstract: A stacking apparatus that stacks a first substrate and a second substrate includes: a plurality of holding members that hold the first substrate, wherein the plurality of holding members correct positional misalignment of the first substrate relative to the second substrate by preset amounts of correction, and the plurality of holding members include holding members having the amounts of correction that are different from each other. The stacking apparatus may further include a carrying unit that carries a holding member that is selected from among the plurality of holding members and holds the first substrate from a position where the holding member is housed to a position where the first substrate is held.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: November 3, 2020
    Assignee: Nikon Corporation
    Inventors: Hajime Mitsuishi, Isao Sugaya, Minoru Fukuda
  • Patent number: 10818372
    Abstract: A semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device controls a test mode. The first semiconductor device outputs a chip identification and receives external data. The second semiconductor device includes a plurality of memory chips. At least one of the plurality of memory chips are activated based on the chip identification to store input data into each of the plurality of memory chips that have been activated while a write operation is performed in the test mode. At least two of the plurality of memory chips are activated based on the chip identification to output the stored input data as the external data while a read operation is performed in the test mode.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: October 27, 2020
    Assignee: SK hynix Inc.
    Inventor: Seong Ju Lee
  • Patent number: 10818637
    Abstract: Methods and systems for a thin bonded interposer package are disclosed and may, for example, include bonding a semiconductor die to a first surface of a substrate, forming contacts on the first surface of the substrate, encapsulating the semiconductor die, formed contacts, and first surface of the substrate using a mold material while leaving a top surface of the semiconductor die not encapsulated by mold material, forming vias through the mold material to expose the formed contacts. A bond line may be dispensed on the mold material and the semiconductor die for bonding the substrate to an interposer. A thickness of the bond line may be defined by standoffs formed on the top surface of the semiconductor die.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: October 27, 2020
    Assignee: Amkor Technology, Inc.
    Inventors: Christopher J. Berry, Roger D. St. Amand, Jin Seong Kim
  • Patent number: 10818567
    Abstract: Integrated circuit substrates having features for containing liquid adhesive, and methods for fabricating such substrates, are provided. A device can include a first substrate layer and a second substrate layer adhered to the first substrate layer such that a portion of the top surface of the first substrate layer is exposed to define a bottom of a cavity, and an edge of the second substrate layer adjacent to the exposed top surface of the first substrate layer defines an edge of the cavity. The device can include an integrated circuit die adhered to the exposed top surface of first substrate layer with a liquid adhesive. The first substrate layer can define a trench in the bottom of the cavity between a region of the integrated circuit die and the edge of the cavity such that the trench can receive bleed-out of the liquid adhesive from between the integrated circuit die and the top surface of the first substrate layer.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: October 27, 2020
    Assignee: Google LLC
    Inventors: Woon Seong Kwon, Ryohei Urata, Teckgyu Kang
  • Patent number: 10816831
    Abstract: An optical modulator using an optical modulation element in which an optical waveguide and a plurality of electrodes for controlling light waves propagating through the optical waveguide are formed on a substrate, in which at least one stress relieving structure is provided on an upper surface of the electrode opposite to a surface of the substrate in order to relieve stress generated due to pressure applied at the time of wire-bonding of a metal wire.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: October 27, 2020
    Assignee: Sumitomo Osaka Cement Co., Ltd.
    Inventors: Minoru Shinozaki, Toru Sugamata
  • Patent number: 10811341
    Abstract: In accordance with the present description, there is provided multiple embodiments of a semiconductor device. In each embodiment, the semiconductor device comprises a substrate having a conductive pattern formed thereon. In addition to the substrate, each embodiment of the semiconductor device includes at least one semiconductor die which is electrically connected to the substrate, both the semiconductor die and the substrate being at least partially covered by a package body of the semiconductor device. In certain embodiments of the semiconductor device, through-mold vias are formed in the package body to provide electrical signal paths from an exterior surface thereof to the conductive pattern of the substrate. In other embodiments, through mold vias are also included in the package body to provide electrical signal paths between the semiconductor die and an exterior surface of the package body.
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: October 20, 2020
    Assignee: Amkor Technology Singapore Holding Pte Ltd.
    Inventors: Dong Joo Park, Jin Seong Kim, Ki Wook Lee, Dae Byoung Kang, Ho Choi, Kwang Ho Kim, Jae Dong Kim, Yeon Soo Jung, Sung Hwan Cho
  • Patent number: 10811384
    Abstract: A semiconductor package includes a redistribution structure, at least one semiconductor device, a heat dissipation component, and an encapsulating material. The at least one semiconductor device is disposed on and electrically connected to the redistribution structure. The heat dissipation component is disposed on the redistribution structure and includes a concave portion for receiving the at least one semiconductor device and an extending portion connected to the concave portion and contacting the redistribution structure, wherein the concave portion contacts the at least one semiconductor device. The encapsulating material is disposed over the redistribution structure, wherein the encapsulating material fills the concave portion and encapsulates the at least one semiconductor device.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: October 20, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Wei Chen, Chih-Hua Chen, Hsin-Yu Pan, Hao-Yi Tsai, Lipu Kris Chuang, Tin-Hao Kuo
  • Patent number: 10804256
    Abstract: A semiconductor die assembly in accordance with an embodiment of the present technology includes first and second semiconductor dies and a package substrate carrying the first and second semiconductor dies. The second semiconductor die includes a first peripheral portion extending laterally outward beyond a first edge surface of the first semiconductor die. Similarly, the package substrate includes a second peripheral portion extending laterally outward beyond a second edge surface of the second semiconductor die. The semiconductor die assembly further includes a first volume of molded underfill material between the first and second semiconductor dies, a second volume of molded underfill material between the package substrate and the second semiconductor die, a first molded peripheral structure laterally adjacent to the first edge surface of the first semiconductor die, and a second molded peripheral structure laterally adjacent to the second edge surface of the second semiconductor die.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: October 13, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Bradley R. Bitz, Xiao Li
  • Patent number: 10804209
    Abstract: A semiconductor package includes a package substrate, a first chip stack, a second chip stack, and a supporting block. The first chip stack includes first semiconductor chips stacked on the package substrate to be offset in a first direction, and the second chip stack includes second semiconductor chips stacked on the first chip stack to be offset in a second direction. The supporting block includes a through via structure. The second chip stack is supported by the first chip stack and the supporting block.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: October 13, 2020
    Assignee: SK hynix Inc.
    Inventor: Min Kyu Kang
  • Patent number: 10796988
    Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: October 6, 2020
    Assignee: Intel Corporation
    Inventors: Robert Starkston, Debendra Mallik, John S. Guzek, Chia-Pin Chiu, Deepak Kulkarni, Ravi V. Mahajan
  • Patent number: 10796982
    Abstract: To reduce a package size of a semiconductor device. According to embodiments, there is a semiconductor device comprising: a first die pad; a first inner lead arranged inside a molded resin; a second die pad; and a second inner lead arranged inside the resin, wherein a part of the first inner lead and a part of the second inner lead are adhered and electrically connected to each other, a first semiconductor chip mounted on the first die pad is electrically connected to a second semiconductor chip mounted on the second die pad via the first inner lead and the second inner lead, and an end face of one end of the first inner lead and the second inner lead that are adhered to each other is exposed to a side surface of the resin.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: October 6, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Toyokazu Shibata
  • Patent number: 10790263
    Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) die. In embodiments, the IC die may include a semiconductor substrate, a plurality of active components disposed on a first side of the semiconductor substrate, and a plurality of passive components disposed on a second side of the semiconductor substrate. In embodiments the second side may be disposed opposite the first side. The passive components may, in some embodiments, include capacitors and/or resistors while the active components may, in some embodiments, include transistors. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: September 29, 2020
    Assignee: Intel Corporation
    Inventor: Kevin J. Lee
  • Patent number: 10790242
    Abstract: According to the present invention, a semiconductor device includes a substrate having a metallic pattern formed on a top surface of the substrate, a semiconductor chip provided on the metallic pattern, a back surface electrode terminal in flat plate form connected to the metallic pattern with a wire, a front surface electrode terminal in flat plate form, the front surface electrode terminal being in parallel to the back surface electrode terminal above the back surface electrode terminal, extending immediately above the semiconductor chip, and being directly joined to a top surface of the semiconductor chip, a case surrounding the substrate and a seal material for sealing an inside of the case.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: September 29, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Tetsuo Yamashita, Tomohiro Hieda, Masaomi Miyazawa
  • Patent number: 10790254
    Abstract: A chip package structure is provided. The chip package structure includes a substrate having a first surface and a second surface opposite to the first surface. The chip package structure includes a first chip structure and a second chip structure over the first surface. The chip package structure includes a protective layer over the first surface and surrounding the first chip structure and the second chip structure. A portion of the protective layer is between the first chip structure and the second chip structure. The chip package structure includes a first anti-warpage bump over the second surface and extending across the portion of the protective layer. The chip package structure includes a conductive bump over the second surface and electrically connected to the first chip structure or the second chip structure. The first anti-warpage bump is wider than the conductive bump.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: September 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuan-Yu Huang, Sung-Hui Huang, Shu-Chia Hsu, Leu-Jen Chen, Yi-Wei Liu, Shang-Yun Hou, Jui-Hsieh Lai, Tsung-Yu Chen, Chien-Yuan Huang, Yu-Wei Chen
  • Patent number: 10785897
    Abstract: A cold plate compatible with the Open Compute Project Rack specification is disclosed. The cold plate is mounted in a compatible rack with removable trays mounted on support and coupling rails affixed to the underside of the cold plate thus supporting the trays during insertion and operation.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: September 22, 2020
    Inventors: Robert J Lipp, Phillip N Hughes
  • Patent number: 10784220
    Abstract: A package structure includes a first dielectric layer, a first semiconductor device, a first redistribution line, a second dielectric layer, a second semiconductor device, a second redistribution line, a first conductive feature, and a first molding material. The first semiconductor device is over the first dielectric layer. The first redistribution line is in the first dielectric layer and is electrically connected to the first semiconductor device. The second dielectric layer is over the first semiconductor device. The second semiconductor device is over the second dielectric layer. The second redistribution line is in the second dielectric layer and is electrically connected to the second semiconductor device. The first conductive feature electrically connects the first redistribution line and the second redistribution line. The first molding material molds the first semiconductor device and the first conductive feature.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: September 22, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shin-Puu Jeng, Shuo-Mao Chen, Feng-Cheng Hsu
  • Patent number: 10784219
    Abstract: A semiconductor device including a first die and a second die bonded to one another. The first die includes a first passivation layer over a substrate, and first bond pads in the first passivation layer. The second die includes a second passivation layer, which may be bonded to the first passivation layer, and second bond pads in the second passivation layer, which may be bonded to the first bond pads. The second bond pads include inner bond pads and outer bond pads. The outer bond pads may have a greater diameter than the inner bond pads as well as the first bond pads.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: September 22, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chia Hu, Ching-Pin Yuan, Sung-Feng Yeh, Sen-Bor Jan, Ming-Fa Chen
  • Patent number: 10784233
    Abstract: The present disclosure relates to a microelectronics package with a self-aligned stacked-die assembly and a process for making the same. The disclosed microelectronics package includes a module substrate, a first die with a first coupling component, a second die with a second coupling component, and a first mold compound. The first die is attached to the module substrate. The first mold compound resides over the module substrate, surrounds the first die, and extends above an upper surface of the first die to define a first opening. Herein, the first mold compound provides vertical walls of the first opening, which are aligned with edges of the first die in X-direction and Y-direction. The second die is stacked with the first die and in the first opening, such that the second coupling component is mirrored to the first coupling component.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: September 22, 2020
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, George Maxim
  • Patent number: 10777521
    Abstract: A printable component structure includes a chiplet having a semiconductor structure with a top side and a bottom side, one or more top electrical contacts on the top side of the semiconductor structure, and one or more bottom electrical contacts on the bottom side of the semiconductor structure. One or more electrically conductive spikes are in electrical contact with the one or more top electrical contacts. Each spike protrudes from the top side of the semiconductor structure or a layer in contact with the top side of the semiconductor structure.
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: September 15, 2020
    Assignee: X Display Company Technology Limited
    Inventors: Matthew Meitl, Christopher Bower, Ronald S. Cok
  • Patent number: 10777512
    Abstract: An activable electronic component destruction device includes a heater and a heat-activated expandable material arranged on top of the heater. Heating of the heater causes the heat-activated expandable material to expand. The device further includes activation electronics coupled to the heater. The activation electronics are configured to control supply of power to the heater, which causes the heater to heat the heat-activated expandable material, which breaks a semiconductor substrate arranged on top of the heat-activated expandable material.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: September 15, 2020
    Assignee: KING ABDULLAH UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Muhammad Mustafa Hussain, Abdurrahman Gumus
  • Patent number: 10777530
    Abstract: Semiconductor device packages for incorporation into semiconductor device assemblies may include a substrate including an array of electrically conductive elements located on a lower surface of the substrate. A window may extend through the substrate from the lower surface to an upper surface of the substrate. The array of electrically conductive elements may at least partially laterally surround a periphery of the window, and the substrate may extend laterally beyond the array of electrically conductive elements. At least a portion of a heat-management structure may be located within the window. At least a portion of an outer periphery of an underlying substrate may laterally overlap with an inner portion of the substrate defining the periphery of the window.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: September 15, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Matthew Monroe
  • Patent number: 10777474
    Abstract: A semiconductor device includes a semiconductor chip including a substrate having a first surface and a second surface arranged opposite to the first surface; and a microelectromechanical systems (MEMS) element, including a sensitive area, disposed at the first surface of the substrate. The semiconductor device further includes at least one electrical interconnect structure electrically connected to the first surface of the substrate, and a flexible carrier electrically connected to the at least one electrical interconnect structure, where the flexible carrier wraps around the semiconductor chip and extends over the second surface of the substrate such that a folded cavity is formed around the semiconductor chip.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: September 15, 2020
    Assignee: Infineon Technologies AG
    Inventor: Dirk Hammerschmidt
  • Patent number: 10770437
    Abstract: The present disclosure provides a semiconductor package, including a first layer, a second layer, and a conductive array. The first layer includes a packaged die having a carrier surface and a molding surface, and a first die structure in proximity to the carrier surface. An active region of the first die structure is electrically coupled to the packaged die through a solder. The second layer includes a second die structure, the second die structure being connected to the active region of the first die structure by a first redistributed layer (RDL). The conductive array is connected to an active region of the second die structure by a second RDL. The present disclosure also provides a method for manufacturing the aforesaid semiconductor package.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: September 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jui-Pin Hung, Feng-Cheng Hsu, Shuo-Mao Chen, Shin-Puu Jeng
  • Patent number: 10770429
    Abstract: A microelectronic package may be fabricated having a microelectronic die stack attached to a microelectronic substrate, wherein a first microelectronic die within the microelectronic die stack includes an opening or “window” formed therethrough. The first microelectronic die may be in electronic communication with a second microelectronic die within microelectronic die stack and/or in electrical communication with a microelectronic substrate upon which the microelectronic die stack may be attached, wherein the electronic communication may be created with a bond wire which extends through the opening or “window” in the first microelectronic die.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: September 8, 2020
    Assignee: Intel Corporation
    Inventors: Min-Tih Lai, Cory A. Runyan
  • Patent number: 10770795
    Abstract: An antenna device includes a package and at least one antenna. The package includes at least one radio frequency (RF) die and a molding compound in contact with at least one sidewall of the RF die. The antenna has at least one conductor at least partially in the molding compound and operatively connected to the RF die.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: September 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chuei-Tang Wang, Chung-Hao Tsai, Jeng-Shien Hsieh, Wei-Heng Lin, Kuo-Chung Yee, Chen-Hua Yu
  • Patent number: 10770365
    Abstract: An embodiment is a method including: attaching a first die to a first side of a first component using first electrical connectors, attaching a first side of a second die to first side of the first component using second electrical connectors, attaching a dummy die to the first side of the first component in a scribe line region of the first component, adhering a cover structure to a second side of the second die, and singulating the first component and the dummy die to form a package structure.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: September 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Hsien-Pin Hu, Jing-Cheng Lin, Szu-Wei Lu, Shang-Yun Hou, Wen-Hsin Wei, Ying-Ching Shih, Chi-Hsi Wu
  • Patent number: 10770408
    Abstract: A wiring board includes an insulating layer, a plurality of pads formed on a surface of the insulating layer, and a chip mounting region defined on a surface of the wiring board formed with the plurality of pads. The plurality of pads are arranged in the chip mounting region. A cavity is formed in a surface of at least some of the plurality of pads. The cavity caves in, from the surface of the at least some of the plurality of pads, toward the insulating layer. The chip mounting region is segmented into a plurality of segmented regions, and a depth of the cavity is different for each of the plurality of segmented regions.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: September 8, 2020
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Masayuki Ogawa
  • Patent number: 10770413
    Abstract: A chip packaging structure and method, and an electronic device, are provided. The chip packaging structure includes a support, a chip, at least one conductor, and a package for plastic packaging the support, the chip and the conductor. The chip is arranged on an upper surface of the support, a chip pad is formed on the upper surface of the chip, and the chip pad is connected to an external pad of the support by a bonding wire. The conductor is connected to the external pad or a ground pad of the chip pad, and the shortest distance from the conductor to the upper surface of the package is less than the shortest distance from the bonding wire to the upper surface of the package, whereby chip failure caused by static electricity discharge is greatly reduced.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: September 8, 2020
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Baoquan Wu, Xinfei Yu
  • Patent number: 10763241
    Abstract: A stacked package structure for a chip, can include: a substrate having a first surface and a second surface opposite thereto; a first die having an active and back faces, where the active face of the first die includes pads; a first enclosure that covers the first die; an interlinkage that extends to the first enclosure to electrically couple with the pads; a first redistribution body electrically coupled to the interlinkage, and being partially exposed on a surface of the stacked package structure to provide outer pins for electrically coupling to external circuitry; a penetrating body that penetrates the first enclosure and substrate; a second die having an electrode electrically coupled to a first terminal of the penetrating body; and a second terminal of the penetrating body that is exposed on the surface of the stacked package structure to provide outer pins for electrically coupling to the external circuitry.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: September 1, 2020
    Assignee: Silergy Semiconductor Technology (Hangzhou) LTD
    Inventor: Xiaochun Tan
  • Patent number: 10752499
    Abstract: A method for manufacturing a semiconductor device package includes providing an electrically insulating film having film terminal contacts on a surface thereof, and an opening therethrough. A semiconductor device arrangement at least including a carrier element having arranged thereon a projecting element and element terminal contacts is deposited on the film, wherein the projecting element is introduced into the opening and the element terminal contacts are arranged in contact with the film terminal contacts. The planarization layer is deposited over the carrier element and the film.
    Type: Grant
    Filed: November 3, 2018
    Date of Patent: August 25, 2020
    Assignee: FRAUNHOFER-GESELLSCHAFT ZUR FÖRDERUNG DER ANGEWANDTEN FORSCHUNG E.V.
    Inventors: Christof Landesberger, Indranil Bose
  • Patent number: 10757812
    Abstract: The present invention provides a printed circuit board and a layout method thereof and an electronic equipment. On the printed circuit board is arranged a first processor chip and a second processor chip, wherein the first processor chip is arranged on a first surface of the printed circuit board; the second processor chip is arranged on a second surface of the printed circuit board; and a first through-hole is disposed on the printed circuit board, part of pins of the first processor chip being connected to part of pins of the second processor chip via the first through-hole.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: August 25, 2020
    Assignee: NVIDIA CORPORATION
    Inventors: Joey Cai, Tiger Yan, Oliver Yi, Jacky Zhu, Roman Li
  • Patent number: 10756049
    Abstract: A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: August 25, 2020
    Assignee: Invensas Corporation
    Inventors: Ellis Chau, Reynaldo Co, Roseann Alatorre, Philip Damberg, Wei-Shun Wang, Se Young Yang
  • Patent number: 10756058
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first chip, a second chip, self-aligned structures, a bridge structure, and an insulating encapsulant. The first chip has a first rear surface opposite to a first active surface. The second chip is disposed beside the first chip and has a second rear surface opposite to a second active surface. The self-aligned structures are disposed on the first rear surface of the first chip and the second rear surface of the second chip. The bridge structure is electrically connected to the first chip and the second chip. The insulating encapsulant covers at least the side surfaces of the first and second chips, a side surface of the semiconductor substrate, and the side surfaces of the self-aligned structures.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: August 25, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ying-Ching Shih, Chih-Wei Wu, Szu-Wei Lu
  • Patent number: 10756292
    Abstract: A method of manufacturing an OLED panel and an OLED panel are provided. The method includes forming an anode connected to a source of a TFT, and a strap electrode connected to an auxiliary electrode on a TFT substrate. A sharp shaped corner is formed on the strap electrode, therefore an area of the electron transport layer and the electron injection layer corresponding to the sharp shaped corner have a thinner thickness. By applying a voltage between the auxiliary electrode and the cathode, the electron transport layer and the electron injection layer corresponding to the sharp shaped corner are punctured, the cathode is directly connected to the strap electrode and further conducted to the auxiliary electrode, resulting in a signal is inputted to the cathode through the auxiliary electrode during display. The problem of uneven display of the OLED panel due to the IR drop of the cathode is improved.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: August 25, 2020
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Jia Tang, Jangsoon Im, Xiaoxing Zhang
  • Patent number: 10748841
    Abstract: A method includes forming a plurality of dielectric layers, forming a plurality of redistribution lines in the plurality of dielectric layers, etching the plurality of dielectric layers to form an opening, filling the opening to form a through-dielectric via penetrating through the plurality of dielectric layers, forming a dielectric layer over the through-dielectric via and the plurality of dielectric layers, forming a plurality of bond pads in the dielectric layer, bonding a device die to the dielectric layer and a first portion of the plurality of bond pads through hybrid bonding, and bonding a die stack to through-silicon vias in the device die.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: August 18, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Co., Ltd.
    Inventors: Ming-Fa Chen, Chen-Hua Yu