Stacked Arrangement Patents (Class 257/686)
  • Patent number: 11189612
    Abstract: There is provided a semiconductor device including: a first semiconductor element including a first gate electrode, a first source electrode, and a first drain electrode; a second semiconductor element including a second gate electrode, a second source electrode, and a second drain electrode; a gate lead, a source lead, a first drain lead, and a second drain lead; and a resin part, wherein the first gate electrode and the first source electrode, and the first drain electrode are provided on opposite sides to each other in a first direction, wherein the second gate electrode and the second source electrode, and the second drain electrode are provided on opposite sides to each other in the first direction, wherein the first gate electrode and the second gate electrode are opposed to the first source electrode and the second source electrode, respectively, in the first direction.
    Type: Grant
    Filed: August 18, 2020
    Date of Patent: November 30, 2021
    Assignee: ROHM CO., LTD.
    Inventor: Kenta Suganuma
  • Patent number: 11189593
    Abstract: A package is disclosed. The package can include a package substrate that has an opening, such as a through hole, extending from a top side to a bottom side opposite the top side of the package substrate. The package can also include a component at least partially disposed in the through hole. The component can be an electrical component. The component can be exposed at a bottom surface of the package. The package can include a bonding material that mechanically couples the component and the package substrate.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: November 30, 2021
    Assignee: Analog Devices International Unlimited Company
    Inventors: Teik Tiong Toong, Mike J. Anderson
  • Patent number: 11188701
    Abstract: A stacked chip layout includes a central processing chip, a first active circuit block over the central processing chip, and a second active circuit block overlapping the first active circuit. The first and second active circuit blocks are within a perimeter of the central processing chip in a plan view. The stacked chip layout includes a first routing region on a same plane as the first active circuit block, and a second routing region on a same plane as the second active circuit block. The first routing region is between the second active circuit block and the central processing chip. The stacked chip layout includes a heat dissipation element over the second active circuit block and the second routing region. The second routing region is configured to convey heat from the first active circuit block to the heat dissipation element.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: November 30, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Ying-Yu Hsu
  • Patent number: 11182986
    Abstract: A method for an autonomous vehicle includes: controlling at least one system of the vehicle by a host system; monitoring, by a memory device, data associated with operation of the vehicle; determining, by the memory device based on the monitoring, first data to collect from the vehicle; collecting, by the memory device independently of the host system, the first data; and storing, by the memory device, the collected first data in a non-volatile memory.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: November 23, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Junichi Sato
  • Patent number: 11177240
    Abstract: The present disclosure relates to a radio frequency device that includes a transfer device die and a multilayer redistribution structure underneath the transfer device die. The transfer device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion and a transfer substrate. The FEOL portion includes isolation sections and an active layer surrounded by the isolation sections. A top surface of the device region is planarized. The transfer substrate including a porous silicon (PSi) region resides over the top surface of the device region. Herein, the PSi region has a porosity between 1% and 80%. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the transfer device die.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: November 16, 2021
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Michael Carroll
  • Patent number: 11177238
    Abstract: A semiconductor structure includes a plurality of first dies, a second die disposed over each of the first dies, and a dielectric material surrounding the first dies and the second die. The second dies overlaps a portion of each of the first dies. A dimension of the second die is different from a dimension of the first dies.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: November 16, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chen-Hua Yu, Chi-Hsi Wu, Der-Chyang Yeh, Hsien-Wei Chen, An-Jhih Su, Tien-Chung Yang
  • Patent number: 11175019
    Abstract: The invention refers to a carrier for at least one lighting module, the carrier comprising: at least one mounting portion for receiving the at least one lighting module, wherein the carrier has a triangular cross section at least in sections with the at least one mounting portion being arranged on an edge of the triangular cross section; and a heat sink body portion arranged adjacent to the at least one mounting portion, wherein the heat sink body portion protrudes sidewards from the at least one mounting portion. The invention further relates to a lighting device and a method for producing such lighting device.
    Type: Grant
    Filed: November 6, 2020
    Date of Patent: November 16, 2021
    Assignee: Lumileds LLC
    Inventors: Florent Grégoire Monestier, Michael Deckers
  • Patent number: 11177241
    Abstract: A semiconductor device is disclosed including a die stack including a number of dies aligned with each other with respect to an axis, and a top die that is offset along the axis the to prevent die cracking.
    Type: Grant
    Filed: March 10, 2020
    Date of Patent: November 16, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Junrong Yan, Jianming Zhang, Min Zhao, Kailei Zhang, Chee Keong Chin, Kim Lee Bock
  • Patent number: 11177201
    Abstract: In an embodiment, a package includes a first package structure including a first integrated circuit die having an active side and a back-side, the active side including die connectors, a second integrated circuit die adjacent the first integrated circuit die, the second integrated circuit die having an active side and a back-side, the active side including die connectors, a routing die including die connectors bonded to the active sides of the first integrated circuit die and the second integrated circuit die, the routing die electrically coupling the first integrated circuit die to the second integrated circuit die, an encapsulant encapsulating the first integrated circuit die, the second integrated circuit die, and the routing die, and a first redistribution structure on and electrically connected to the die connectors of the first integrated circuit die and the second integrated circuit die.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: November 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jie Chen, Ying-Ju Chen, Hsien-Wei Chen
  • Patent number: 11171082
    Abstract: A semiconductor package includes: a connection structure including a plurality of insulating layers and redistribution layers respectively disposed on the plurality of insulating layers; a semiconductor chip having connection pads connected to the redistribution layer; an encapsulant encapsulating the semiconductor chip; first and second pads arranged on at least one surface of the connection structure and each having a plurality of through-holes; a surface mount component disposed on the at least one surface of the connection structure and including first and second external electrodes positioned, respectively, in regions of the first and second pads; first and second connection vias arranged in the plurality of insulating layers and connecting the first and second pads to the redistribution layers, respectively; and first and second connection metals connecting the first and second pads and the first and second external electrodes to each other, respectively.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: November 9, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jihoon Kim, Mijin Park, Jinwon Lee
  • Patent number: 11169943
    Abstract: A master integrated circuit (IC) chip includes transmit circuitry and receiver circuitry. The transmit circuitry includes a timing signal generation circuit to generate a first timing signal, and a driver to transmit first data in response to the first timing signal. A timing signal path routes the first timing signal in a source synchronous manner with the first data. The receiver circuitry includes a receiver to receive second data from a slave IC chip, and sampling circuitry to sample the second data in response to a second timing signal that is derived from the first timing signal.
    Type: Grant
    Filed: May 5, 2020
    Date of Patent: November 9, 2021
    Assignee: Marvell Asia Pte, Ltd.
    Inventor: Ramin Farjadrad
  • Patent number: 11171114
    Abstract: An electronic assembly includes a plurality of electronic die arranged into shingles, each shingle having a multiple offset stacked die coupled by cascading connections. Each shingle is arranged in a stack of shingles with alternate shingles having die stacked in opposite directions and offset in a zigzag manner to facilitate vertical electrical connections from a top of the electronic assembly to a bottom die of each shingle.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: November 9, 2021
    Assignee: Intel Corporation
    Inventors: Min-Tih Ted Lai, Florence R. Pon, Yuhong Cai, John G. Meyers
  • Patent number: 11171121
    Abstract: Semiconductor devices having redistribution structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor package includes a first semiconductor die including a first redistribution structure and a second semiconductor die including a second redistribution structure. The first and second semiconductor dies can be mounted on a package substrate such that the first and second redistribution structures are aligned with each other. In some embodiments, an interconnect structure can be positioned between the first and second semiconductor dies to electrically couple the first and second redistribution structures to each other. The first and second redistribution structures can be configured such that signal routing between the first and second semiconductor dies can be altered based on the location of the interconnect structure.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: November 9, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Travis M. Jensen, David R. Hembree
  • Patent number: 11164833
    Abstract: Disclosed are a semiconductor device and a stacked semiconductor package. The semiconductor device may include a semiconductor chip and a plurality of chip pads disposed on the semiconductor chip in a second horizontal direction perpendicular to a first horizontal direction. The plurality of chip pads may include: a first chip pad connected to a wire extending in the first horizontal direction, when seen from the top; and a second chip pad connected to a diagonal wire extending in a direction at an angle to the first and second horizontal directions, when seen from the top. The width of the first chip pad in the second horizontal direction may be smaller than the width of the second chip pad in the second horizontal direction.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: November 2, 2021
    Assignee: SK hynix Inc.
    Inventors: Young Jo Park, Seung Yeop Lee
  • Patent number: 11164853
    Abstract: A chip package includes a first chip, a second chip, a first molding compound, and a first distribution line. The second chip vertically or laterally overlaps the first chip. The second chip has a conductive pad. The first molding compound covers the first and second chips, and surrounds the second chip. The first molding compound has a first through hole. The conductive pad is in the first through hole. The first distribution line is located on a surface of the first molding compound facing away from the second chip, and electrically connects the conductive pad in the first through hole.
    Type: Grant
    Filed: February 8, 2021
    Date of Patent: November 2, 2021
    Assignee: XINTEC INC.
    Inventors: Chia-Ming Cheng, Shu-Ming Chang
  • Patent number: 11166381
    Abstract: Solder-pinning metal pads for electronic components and techniques for use thereof to mitigate de-wetting are provided. In one aspect, a structure includes: a substrate; and a solder pad on the substrate, wherein the solder pad has sidewalls extending up from a surface thereof. For instance, the sidewalls can be present at edges of the solder pad, or inset from the edges of the solder pad. The sidewalls can be vertical or extend up from the solder pad at an angle. The sidewalls can be formed from the same material or a different material as the solder pad. A method is also provided that includes forming a solder pad on a substrate, the solder pad comprising sidewalls extending up from a surface thereof.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: November 2, 2021
    Assignee: International Business Machines Corporation
    Inventors: Yves Martin, Tymon Barwicz
  • Patent number: 11163453
    Abstract: A memory device comprises a smart buffer, and a memory area divided into a first memory area and a second memory area, wherein the smart buffer comprises a priority setting unit configured to receive a sensing data and a corresponding weight from a controller, determine a priority of the sensing data based on the weight, and classify the sensing data as one of first priority sensing data and second priority sensing data, and a channel controller configured to allocate at least one channel selected from among a plurality of channels to a first channel group, allocate at least another channel selected from among the plurality of channels to a second channel group, assign the first channel group to process the first priority sensing data in relation to the first memory area, and assign the second channel group to process the second priority sensing data in relation to the second memory area, wherein a number of data input/output (I/O) pins connected to the first channel group is greater than a number of data I/O
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: November 2, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Youngmin Jo, Daeseok Byeon, Tongsung Kim
  • Patent number: 11158573
    Abstract: Representative techniques and devices, including process steps may be employed to mitigate undesired dishing in conductive interconnect structures and erosion of dielectric bonding surfaces. For example, an embedded layer may be added to the dished or eroded surface to eliminate unwanted dishing or voids and to form a planar bonding surface. Additional techniques and devices, including process steps may be employed to form desired openings in conductive interconnect structures, where the openings can have a predetermined or desired volume relative to the volume of conductive material of the interconnect structures. Each of these techniques, devices, and processes can provide for the use of larger diameter, larger volume, or mixed-sized conductive interconnect structures at the bonding surface of bonded dies and wafers.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: October 26, 2021
    Assignee: Invensas Bonding Technologies, Inc.
    Inventors: Cyprian Emeka Uzoh, Gaius Gillman Fountain, Jr., Jeremy Alfred Theil
  • Patent number: 11158601
    Abstract: A laminating step includes a first bonding step of bonding a circuit layer of a second wafer to a circuit layer of a first wafer, a grinding step of grinding a semiconductor substrate of the second wafer, and a second bonding step of bonding a circuit layer of the third wafer to the semiconductor substrate of the second wafer. In a laser light irradiation step, a modified region is formed and a fracture extends from the modified region along a laminating direction of a laminated body by irradiating the semiconductor substrate of the first wafer with a laser light.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: October 26, 2021
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventors: Takeshi Sakamoto, Ryuji Sugiura, Yuta Kondoh, Naoki Uchiyama
  • Patent number: 11158594
    Abstract: A semiconductor package includes a first semiconductor chip having a through-electrode and an upper connection pad on an upper surface of the first semiconductor chip that is connected to the through-electrode; a second semiconductor chip stacked on the first semiconductor chip, and having a lower connection pad on a lower surface of the second semiconductor chip; a non-conductive film between the first semiconductor chip and the second semiconductor chip, with the non-conductive film including voids having an average diameter of 1 ?m to 100 ?m, the voids having a volume fraction of 0.1 to 5 vol %; and a connection conductor that penetrates the non-conductive film and connects the upper connection pad and the lower connection pad.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: October 26, 2021
    Inventors: Jiseok Hong, Hyuekjae Lee, Jongpa Hong, Jihwan Hwang, Taehun Kim
  • Patent number: 11152333
    Abstract: A semiconductor device package comprising a carrier substrate having a central well, a logic die facing and operably coupled to TSVs of the carrier substrate, and one or more memory dice in the well and operably coupled to the logic die proximate a surface thereof facing the carrier substrate. An electronic system is also disclosed.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: October 19, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Aron T. Lunde
  • Patent number: 11145626
    Abstract: A semiconductor package includes a base structure having a base pad, a first semiconductor chip on the base structure, and having a first connection pad bonded to the base pad, a first bonding structure including an base insulation layer of a base structure and a first lower insulation layer of the first semiconductor chip bonded to the base insulation layer, a second semiconductor chip on the first semiconductor chip, and having a second connection pad connected to the first through-electrode, and a second bonding structure including a first upper insulation layer of the first semiconductor chip, and a second lower insulation layer of the second semiconductor chip bonded to the first upper insulation layer, and the first upper insulation layer has a dummy insulation portion extending onto the base structure around the first semiconductor chip.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: October 12, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji Hwan Hwang, Ji Hoon Kim, Ji Seok Hong, Tae Hun Kim, Hyuek Jae Lee
  • Patent number: 11145624
    Abstract: A semiconductor device package includes a substrate, a stacked structure and an encapsulation layer. The substrate includes a circuit layer, a first surface and a second surface opposite to the first surface. The substrate defines at least one cavity through the substrate. The stacked structure includes a first semiconductor die disposed on the first surface and electrically connected on the circuit layer, and at least one second semiconductor die stacked on the first semiconductor die and electrically connected to the first semiconductor die. The second semiconductor die is at least partially inserted into the cavity. The encapsulation layer is disposed in the cavity and at least entirely encapsulating the second semiconductor die.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: October 12, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: You-Lung Yen, Bernd Karl Appelt, Kay Stefan Essig
  • Patent number: 11145632
    Abstract: A high density die package configuration is shown for use on system boards. In one example, an apparatus includes a system board, a first package mounted to the system board, a second package mounted to the system board, and an interface package mounted between the first and the second package and coupled directly to the first package and to the second package through the respective first and second packages.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: October 12, 2021
    Assignee: Intel Corporation
    Inventors: Juan E. Dominguez, Hyoung Il Kim, Bilal Khalaf, John Gary Meyers
  • Patent number: 11147170
    Abstract: A display panel and a display device are provided. The display panel includes a flexible screen body having a first region and a second region. The second region has a bending transitional region coplanar with the first region, a bending region, and an extending region connected in sequence. The first region is connected to the bending region through the bending transitional region and is at least a part of an active region. The bending region and the extending region are at least a part of a non-active region and not coplanar with the first region. The bending transitional region is another part of the active region or another part of the non-active region. The display panel further includes a buffer layer disposed on surfaces of the bending transitional region and the bending region at a stress concentration side thereof. At least two sections of the buffer layer have different hardnesses.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: October 12, 2021
    Assignee: KUNSHAN GO-VISIONOX OPTO-ELECTRONICS CO., LTD.
    Inventor: Lingyan Chen
  • Patent number: 11145645
    Abstract: Embodiments of three-dimensional (3D) memory devices having multiple memory stacks and methods for forming the 3D memory devices are disclosed. In an example, a 3D memory device includes a first device chip, a second device chip, and a bonding interface. The first device chip includes a peripheral device and a first interconnect layer. The second device chip includes a substrate, two memory stacks disposed on opposite sides of the substrate, two memory strings each extending vertically through one of the two memory stacks, and a second interconnect layer. The bonding interface is formed vertically between the first interconnect layer of the first device chip and the second interconnect layer of the second device chip.
    Type: Grant
    Filed: February 5, 2020
    Date of Patent: October 12, 2021
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Li Hong Xiao, Bin Hu
  • Patent number: 11139041
    Abstract: A stacked semiconductor device includes semiconductor chips, each including a signal transfer circuit respectively transferring a command, an address, and a chip select signal to first to third through electrodes, and respectively transferring a test address and a chip ID to the second and third through electrodes according to a test control signal; a command reception circuit transferring a test command or a signal transferred from the first through electrode to an internal circuit when a signal transferred from the third through electrode is identical to the chip ID coincide with each other; and a test control circuit activating the test control signal according to deactivation of a test control signal of an upper chip, and generating the test command and the test address according to the test control signal.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: October 5, 2021
    Assignee: SK hynix Inc.
    Inventor: Yo-Sep Lee
  • Patent number: 11139255
    Abstract: A first integrated circuit chip is assembled to a second integrated circuit chip with a back-to-back surface relationship. The back surfaces of the integrated circuit chips are attached to each other using one or more of an adhesive, solder or molecular bonding. The back surface of at least one the integrated circuit chips is processed to include at least one of a trench, a cavity or a saw cut.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: October 5, 2021
    Assignees: STMicroelectronics (Rousset) SAS, STMicroelectronics (Grenoble 2) SAS
    Inventors: Denis Farison, Romain Coffy, Jean-Michel Riviere
  • Patent number: 11139274
    Abstract: A semiconductor device package includes a substrate, a connection structure, a first package body and a first electronic component. The substrate has a first surface and a second surface opposite to the first surface. The connection structure is disposed on the first surface of the substrate. The first package body is disposed on the first surface of the substrate. The first package body covers the connection structure and exposes a portion of the connection structure. The first electronic component is disposed on the first package body and in contact with the portion of the connection structure exposed from the first package body.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: October 5, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Shang-Ruei Wu, Chien-Yuan Tseng, Meng-Jen Wang, Chen-Tsung Chang, Chih-Fang Wang, Cheng-Han Li, Chien-Hao Chen, An-Chi Tsao, Per-Ju Chao
  • Patent number: 11133261
    Abstract: An electronic device may be a first package. The first package may include a first substrate having a first mounting surface. A first die may be coupled to the first mounting surface. A first interconnect region may be laterally spaced from the first die. The first package may be interconnected with a second package. The second package may include a second die coupled to a second mounting surface. Interconnection of the first package with the second package may establish one or more electrical communication pathways between the first package and the second package. The interconnection of the first package with the second package may interconnect the first die with the second die such that the first die and second die are in communication only through the one or more electrical communication pathways.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: September 28, 2021
    Assignee: Intel Corporation
    Inventors: Eng Huat Goh, Min Suet Lim, Chee Kheong Yoon, Jia Yan Go
  • Patent number: 11133290
    Abstract: A chip package structure including a first chip stack and a redistribution layer is provided. The first chip stack includes a plurality of first chips, a first molding layer and at least one first vertical conductive element. The plurality of first chips are sequentially stacked, wherein each of the plurality of first chips includes at least one first bonding pad, and the first bonding pads are not covered by the plurality of first chips. The first molding layer encapsulates the plurality of first chips. The at least one first vertical conductive element penetrates through the first molding layer, wherein the at least one first vertical conductive element is disposed on and electrically connected to at least one of the first bonding pads. The redistribution layer is disposed on the first chip stack and electrically connected to the at least one first vertical conductive element.
    Type: Grant
    Filed: January 7, 2020
    Date of Patent: September 28, 2021
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: XinRu Zeng, Peng Chen, Houde Zhou
  • Patent number: 11133291
    Abstract: A chip package structure including a circuit board, a first die, a spacer, and a second die. The first die is disposed on the circuit board, and the spacer is disposed on the circuit board, in which the spacer includes a spacer part and at least one via structure penetrating through the spacer part. The second die is disposed on the first die and the spacer, and the second die is electrically connected to the circuit board through the spacer.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: September 28, 2021
    Assignee: POWERTECH TECHNOLOGY INC.
    Inventors: Chih-Yen Su, Chun-Te Lin
  • Patent number: 11133285
    Abstract: The present disclosure, in some embodiments, relates to a method of forming a package. The method includes coupling a first package component to a second package component using a first set of conductive elements. A first polymer-comprising material is formed over the second package component and surrounding the first set of conductive elements. The first polymer-comprising material is cured to solidify the first polymer-comprising material. A part of the first polymer-comprising material is removed to expose an upper surface of the second package component. The second package component is coupled to a third package component using a second set of conductive elements that are formed onto the upper surface of the second package component.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: September 28, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Tse Chen, Yu-Chih Liu, Hui-Min Huang, Wei-Hung Lin, Jing Ruei Lu, Ming-Da Cheng, Chung-Shi Liu
  • Patent number: 11133234
    Abstract: A semiconductor device includes: a wire including a first conductive member disposed at a semiconductor substrate and a second conductive member disposed at a surface of the first conductive member, the second conductive member having an ionization tendency less than the first conductive member, wherein the first conductive member includes a first surface disposed close to the second conductive member and having a width smaller than a width of a second surface of the first conductive member which is disposed close to the semiconductor substrate, and wherein the second conductive member has a width larger than the width of the first surface of the first conductive member and smaller than the width of the second surface of the first conductive member.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: September 28, 2021
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Taiichi Ogumi
  • Patent number: 11127604
    Abstract: A manufacturing method of semiconductor device includes providing a substrate, forming a sacrificial layer on the substrate, disposing first chips on the sacrificial layer, forming a first dielectric layer surrounding the first chips, forming trenches in the first dielectric layer, and forming a second dielectric layer in the trenches, wherein an upper surface of the first dielectric layer and an upper surface of the second dielectric layer are at a same plane.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: September 21, 2021
    Assignee: InnoLux Corporation
    Inventors: Chia-Chieh Fan, Chin-Lung Ting, Cheng-Chi Wang, Ming-Tsang Wu
  • Patent number: 11127699
    Abstract: A chip package structure including a first chip, an encapsulant, a first redistribution layer, a second redistribution layer, a second chip, and a third chip is provided. The first chip has an active surface, a back side surface opposite to the active surface, a plurality of conductive vias, and a plurality of conductive connectors disposed on the back side surface. The encapsulant covers the active surface, the back side surface, and the conductive connectors. The encapsulant has a first encapsulating surface and a second encapsulating surface opposite to the first encapsulating surface. The first redistribution layer is disposed on the first encapsulating surface. The second redistribution layer is disposed on the second encapsulating surface. The second chip is disposed on the second redistribution layer. The third chip is disposed on the second redistribution layer. A manufacturing method of a chip package structure is also provided.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: September 21, 2021
    Assignee: Powertech Technology Inc.
    Inventors: Nan-Chun Lin, Hung-Hsin Hsu, Shang-Yu Chang Chien
  • Patent number: 11127659
    Abstract: The invention discloses a parallel electrode combination, which includes a first power module electrode and a second power module electrode, wherein a soldering portion of the first power module electrode and a soldering portion of the second power module electrode are respectively used to connect a copper layer of a power source inside a power module, and a connecting portion of the first power module electrode and a connecting portion of the second power module electrode are opposite in parallel. The invention further discloses a power module and a power module group using the parallel electrode combination. In the invention, the connecting portion of the first power module electrode and the connecting portion of the second power module electrode are opposite in parallel.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: September 21, 2021
    Assignee: YANGZHOU GUOYANG ELECTRONIC CO., LTD.
    Inventors: Wenhui Xu, Yulin Wang, Hesong Teng
  • Patent number: 11122703
    Abstract: A system comprising modules. Each module includes: a presentation system including one or more of a speaker and a video screen; and a port. In use, if the presentation system includes the speaker, the system produces sounds derived from data obtained via the port. If the presentation system includes the screen, the system displays images derived from data obtained via the port. The module can also include connectors and the system can also include actuators. Each actuator, in use, can be coupled without soldering to a connector, and the presentation system of each module can operate in response to the actuator or actuators coupled to said each module. The system can also include data storage devices, each adapted to be releasably coupled to a respective port, and the port can be selected from: microchip socket and USB port. The system can be used as part of a method.
    Type: Grant
    Filed: January 8, 2015
    Date of Patent: September 14, 2021
    Inventor: Edgar Davin Salatandre
  • Patent number: 11121118
    Abstract: The present disclosure, in some embodiments, relates to a semiconductor package. The semiconductor package includes an interposer substrate laterally surrounding through-substrate-vias. A redistribution structure is on a first surface of the interposer substrate. The redistribution structure laterally extends past an outermost sidewall of the interposer substrate. A packaged die is bonded to the redistribution structure. One or more conductive layers are arranged along a second surface of the interposer substrate opposite the first surface. A molding compound vertically extends from the redistribution structure to laterally surround the one or more conductive layers.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: September 14, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Shang-Yun Hou
  • Patent number: 11121071
    Abstract: A semiconductor device structure, for example a 3D structure, and a method for fabricating a semiconductor device. As non-limiting examples, various aspects of this disclosure provide various semiconductor package structures, and methods for manufacturing thereof, that comprise interposer, interlayer, and/or heat dissipater configurations that provide for low cost, increased manufacturability, and high reliability.
    Type: Grant
    Filed: March 9, 2020
    Date of Patent: September 14, 2021
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Keun Soo Kim, Jae Yun Kim, Byoung Jun Ahn, Dong Soo Ryu, Dae Byoung Kang, Chel Woo Park
  • Patent number: 11121103
    Abstract: A semiconductor package is provided which includes a package substrate, a first die, a second die, an interconnection member and a plurality of bonding wires. The first die is disposed on the package substrate. The second die is disposed over the first die. The interconnection member includes a connection plate, a plurality of redistribution structures and a plurality of bumps. The connection plate is connected to the first die. The redistribution structures are connected to the second die. The bumps couple the connection plate to the redistribution structures. The bonding wires couple the interconnection member to the package substrate and the first die.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: September 14, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Wu-Der Yang
  • Patent number: 11114414
    Abstract: A wafer structure, a method for manufacturing the same and a chip structure are provided. A first capacitor plate is arranged in a first chip, a second capacitor plate is arranged in a second chip, and the first chip is stacked together via bonding layers with the second chip with a front surface of the first chip facing toward a front surface of the second chip. In this way, a capacitor structure formed by the first capacitor plate, the second capacitor plate and dielectric materials provided therebetween is formed while bonding the first chip and second chip together, and the capacitor plate and the dielectric materials may be formed while forming a device interconnection structure in the chip, such that no additional process is required, thereby improving device integration and process integration.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: September 7, 2021
    Assignee: Wuhan Xinxin Semiconductor Manufacturing Co., Ltd.
    Inventors: Yang Li, Sheng Hu
  • Patent number: 11114358
    Abstract: A semiconductor package includes a substrate, a plurality of electronic components mounted on a first surface of the substrate, and an encapsulant disposed on the first surface of the substrate so that at least one of the plurality of electronic components is embedded in the encapsulant. The substrate includes a flow preventing portion including at least one flow preventing groove disposed in the first surface and adjacent to the encapsulant and/or at least one dam disposed on the first surface and adjacent to the encapsulant.
    Type: Grant
    Filed: January 30, 2020
    Date of Patent: September 7, 2021
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Suk Youn Hong, Han Su Park
  • Patent number: 11107798
    Abstract: Embodiments of the present disclosure include semiconductor packages and methods of forming the same. An embodiment is a method including forming a first die package, the first die package including a first die, a first electrical connector, and a first redistribution layer, the first redistribution layer being coupled to the first die and the first electrical connector, forming an underfill over the first die package, patterning the underfill to have an opening to expose a portion of the first electrical connector, and bonding a second die package to the first die package with a bonding structure, the bonding structure being coupled to the first electrical connector in the opening of the underfill.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: August 31, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Jing-Cheng Lin, Po-Hao Tsai
  • Patent number: 11107782
    Abstract: A radio frequency module includes a mounting substrate, a low-noise amplifier including an amplifying element and amplifying a radio frequency signal, and an impedance matching circuit including an integrated first inductor, in which the first inductor is connected to an input terminal of the low-noise amplifier, the low-noise amplifier and the impedance matching circuit are laminated in a direction perpendicular to a main surface of the mounting substrate, and a first multilayer body on which the low-noise amplifier and the impedance matching circuit are laminated is mounted on the main surface.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: August 31, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Takanori Uejima
  • Patent number: 11101245
    Abstract: Multi-chip modules may include stacked semiconductor devices having spacers therebetween. Discrete conductive elements may extend over the active surface of an underlying semiconductor device from respective bond pads of the underlying semiconductor device, through a space formed by the spacers, to respective contact areas on a substrate. Each discrete conductive element extending through two side openings opposite one another may extend from a respective centrally located bond pad proximate to a central portion of the active surface of the underlying semiconductor device. Each discrete conductive element extending through another, perpendicular opening may extend from a respective peripheral bond pad located proximate to a peripheral portion of the active surface of the underlying semiconductor device.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: August 24, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Eric Tan Swee Seng
  • Patent number: 11101145
    Abstract: A semiconductor device is provided. The semiconductor device includes a base substrate, a die stacking unit, a number of dummy micro bumps, and an underfill material. The die stacking unit, which is mounted on the base substrate, includes a first die, a second die, and a number of first conductive joints. The first die and the second die are stacked on each other, and the first conductive joints are disposed between and connected to the first die and the second die. The dummy micro bumps, which are disposed between the first conductive joints, are connected to the first die but not to the second die. The underfill material is filled into a number of gaps between the base substrate, the first die, the second die, the first conductive joints, and the dummy micro bumps.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: August 24, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tsung-Fu Tsai, Chen-Hsuan Tsai, Chung-Chieh Ting, Shih-Ting Lin, Szu-Wei Lu
  • Patent number: 11101192
    Abstract: Disclosed herein is a device having an embedded heat spreader and method for forming the same. A carrier substrate may comprise a carrier, an adhesive layer, a base film layer, and a seed layer. A patterned mask is formed with a heat spreader opening and via openings. Vias and a heat spreader may be formed in the pattern mask openings at the same time using a plating process and a die attached to the head spreader by a die attachment layer. A molding compound is applied over the die and heat spreader so that the heat spreader is disposed at the second side of the molded substrate. A first RDL may have a plurality of mounting pads and a plurality of conductive lines is formed on the molded substrate, the mounting pads may have a bond pitch greater than the bond pitch of the die contact pads.
    Type: Grant
    Filed: December 24, 2018
    Date of Patent: August 24, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei Sen Chang, Tsung-Hsien Chiang, Yen-Chang Hu, Ching-Wen Hsiao
  • Patent number: 11101244
    Abstract: Stacked semiconductor die assemblies with die support members and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a package substrate, a first semiconductor die attached to the package substrate, and a support member attached to the package substrate. The support member can be separated from the first semiconductor die, and a second semiconductor die can have one region coupled to the support member and another region coupled to the first semiconductor die.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: August 24, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Seng Kim Ye, Hong Wan Ng
  • Patent number: 11101240
    Abstract: A semiconductor package including an improved isolation bonding film and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a first die bonded to a package substrate, the first die including vias extending through a substrate, the vias extending above a top surface of the substrate; a first dielectric film extending along a top surface of the package substrate, along the top surface of the substrate, and along sidewalls of the first die, the vias extending through the first dielectric film; a second die bonded to the first dielectric film and the vias; and an encapsulant over the package substrate, the first die, the first dielectric film, and the second die.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: August 24, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Tsu Chung, Ku-Feng Yang, Yung-Chi Lin, Wen-Chih Chiou, Chen-Hua Yu