Stacked Arrangement Patents (Class 257/686)
  • Patent number: 10420218
    Abstract: An electronic system including at least one component, two identical packages including a bottom from which a peripheral rim protrudes defining a recess, and electrical conductors passing through each package, the packages being attached to one another by the rim thereof so as to define a sealed cavity therebetween. An electronic device including two systems of this type superimposed on one another.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: September 17, 2019
    Assignee: SAFRAN ELECTRONICS & DEFENSE
    Inventor: Jean-Christophe Riou
  • Patent number: 10418331
    Abstract: An electronic component array includes a backplane substrate, and a plurality of integrated circuit elements on the backplane substrate. Each of the integrated circuit elements includes a chiplet substrate having a connection pad and a conductor element on a surface thereof. The connection pad and the conductor element are electrically separated by an insulating layer that exposes at least a portion of the connection pad. At least one of the integrated circuit elements is misaligned on the backplane substrate relative to a desired position thereon. A plurality of conductive wires are provided on the backplane substrate including the integrated circuit elements thereon, and the connection pad of each of the integrated circuit elements is electrically connected to a respective one of the conductive wires notwithstanding the misalignment of the at least one of the integrated circuit elements. Related fabrication methods are also discussed.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: September 17, 2019
    Assignee: X-Celeprint Limited
    Inventor: Christopher Bower
  • Patent number: 10419050
    Abstract: An electronic device may include processing circuitry having a first impedance coupled to a first circuit board, where the electronic device uses the processing circuity to generate one or more radio frequency signals. The electronic device may also include power circuitry to amplify the one or more radio frequency signals, where the power circuitry is coupled to a second circuit board. An interposer may be disposed between the first circuit board and the second circuit board. The interposer may include a via structure having a characteristic impedance to match the first impedance and the second impedance, where the via structure may transmit the one or more radio frequency signals through the interposer between the processing circuitry and the power circuitry.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: September 17, 2019
    Assignee: Apple Inc.
    Inventors: Berke Cetinoneri, James Tsung-Tai Yang, William J. Noellert, Jyotirmoy Hore, Bradley David Scoles
  • Patent number: 10418255
    Abstract: Semiconductor device packages may include a support structure having electrical connections therein. Semiconductor device modules may be located on a surface of the support structure. A molding material may at least partially surround each semiconductor module on the surface of the support structure. A thermal management device may be operatively connected to the semiconductor device modules on a side of the semiconductor device modules opposite the support structure. At least some of the semiconductor device modules may include a stack of semiconductor dice, at least two semiconductor dice in the stack being secured to one another by diffusion of electrically conductive material of electrically conductive elements into one another.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: September 17, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Eiichi Nakano
  • Patent number: 10411001
    Abstract: Donut-shaped Dynamic Random Access Memory (DRAM) includes a hole that fits around a processor, such that the DRAM and the processor are adjacent to one another on an Integrated Circuit (TC) package. In an embodiment, a heat spreader is mounted on top of the processor and covers a top of the DRAM without touching the DRAM.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: September 10, 2019
    Assignee: Intel Corporation
    Inventors: Eng Huat Goh, Hoay Tien Teoh
  • Patent number: 10410967
    Abstract: An electronic device. For example and without limitation, various aspects of the present disclosure provide an electronic device that comprises a die comprising a circuit side and a second die side opposite the circuit side, a through hole in the die that extends between the second side of the die and the circuit side of the die, an insulating layer coupled to the inner wall of the through hole, a through electrode inside of the insulating layer, a dielectric layer coupled to the second side of the die, and a conductive pad coupled to the through electrode. The through electrode and the insulating layer may, for example, extend substantially the same distance from the second side of the die.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: September 10, 2019
    Assignee: Amkor Technology, Inc.
    Inventors: Won Chul Do, Yong Jae Ko
  • Patent number: 10403556
    Abstract: A semiconductor device includes a drift structure formed in a semiconductor body. The drift structure forms a first pn junction with a body zone of a transistor cell. A gate structure extends from a first surface of the semiconductor body into the drift structure. A heat sink structure extends from the first surface into the drift structure. A thermal conductivity of the heat sink structure is greater than a thermal conductivity of the gate structure and/or a thermal capacity of the heat sink structure is greater than a thermal capacity of the gate structure.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: September 3, 2019
    Assignee: Infineon Technologies AG
    Inventors: Johannes Georg Laven, Peter Irsigler, Joachim Mahler, Guenther Ruhl, Hans-Joachim Schulze, Markus Zundel
  • Patent number: 10403606
    Abstract: A method for fabricating a semiconductor package including mounting a first semiconductor chip on a first substrate, disposing a first connector on the first substrate, placing a molding control film on the first semiconductor chip to horizontally extend over the first substrate, filling a space between the molding control film and the first substrate with a molding compound such that the molding compound contacts side surfaces of the first semiconductor chip and covers the first connector and does not cover a top surface of the first semiconductor chip, detaching the molding control film, forming an opening through the molding compound to expose a portion of the first connector, disposing a second connector and a second semiconductor chip on opposite surfaces of a second substrate, respectively, and placing the second substrate on the first substrate such that the second connector contacts the first connector may be provided.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: September 3, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Heung-Kyu Kwon, Min-Ok Na, Sung-Woo Park, Ji-Hyun Park, Su-Min Park
  • Patent number: 10403576
    Abstract: A method for manufacturing an electronic component can include the following steps: providing a semiconductor arrangement comprising a carrier structure which has at least one semiconductor chip incorporated into a potting compound, and a redistribution layer which comprises a flexible material and at least one strip conductor, wherein the carrier structure at least in regions is connected to the redistribution layer, and the at least one semiconductor chip is electrically conductively connected to the redistribution layer, and separating the carrier structure along at least one trench in a manner such that the carrier structure is divided into at least two singularized carrier elements, wherein two adjacent ones of the singularized carrier elements are connected to one another over the respective trench by way of the redistribution layer.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: September 3, 2019
    Assignee: Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.
    Inventors: Tanja Braun, Karl-Friedrich Becker, Ruben Kahle, Michael Töpper
  • Patent number: 10396022
    Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated circuit (IC) assemblies. In some embodiments, an IC package assembly may include a first package substrate configured to route input/output (I/O) signals and ground between a die and a second package substrate. The first package substrate may include a plurality of contacts disposed on one side of the first package substrate and at least two ground vias of a same layer of vias, and the at least two ground vias may form a cluster of ground vias electrically coupled with an individual contact. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: August 27, 2019
    Assignee: Intel Corporation
    Inventors: Zhiguo Qian, Kemal Aygun, Yu Zhang
  • Patent number: 10395721
    Abstract: Memory devices, systems including memory devices, and methods of operating memory devices and systems in which a memory device can include a voltage regulator for adjusting a supply voltage to an output voltage and providing the output voltage to other devices external to the memory device (e.g., other memory devices in the same memory system, processors, graphics chipsets, other logic circuits, expansion cards, etc.). A memory device may comprise one or more external inputs configured to receive a supply voltage having a first voltage level; a voltage regulator configured to receive the supply voltage from the one or more external inputs and to output an output voltage having a second voltage level different from the first voltage level; one or more memories configured to receive the output voltage from the voltage regulator; and one or more external outputs configured to supply the output voltage to one or more connected devices.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: August 27, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Matthew A. Prather, Thomas H. Kinsley
  • Patent number: 10396059
    Abstract: Microelectronic die packages, stacked systems of die packages, and methods of manufacturing them are disclosed herein. In one embodiment, a system of stacked packages includes a first die package having a bottom side, a first dielectric casing, and first metal leads; a second die package having a top side attached to the bottom side of the first package, a dielectric casing with a lateral side, and second metal leads aligned with and projecting towards the first metal leads and including an exterior surface and an interior surface region that generally faces the lateral side; and metal solder connectors coupling individual first leads to individual second leads. In a further embodiment, the individual second leads have an “L” shape and physically contact corresponding individual first leads. In another embodiment, the individual second leads have a “C” shape and include a tiered portion that projects towards the lateral side of the second casing.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: August 27, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Meow Koon Eng, Yong Poo Chia, Suan Jeung Boon
  • Patent number: 10390429
    Abstract: One example of a system includes a printed circuit board. The printed circuit board includes a switch chip footprint to receive a higher lane count switch chip or a lower lane count switch chip. The printed circuit board includes a plurality of transceiver module footprints. Each transceiver module footprint is electrically coupled to the switch chip footprint. Each transceiver module footprint may receive a higher lane count transceiver module or a lower lane count transceiver module.
    Type: Grant
    Filed: October 23, 2015
    Date of Patent: August 20, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Kevin B. Leigh, John Norton
  • Patent number: 10388683
    Abstract: A semiconductor device includes an organic substrate, an integrated circuit, a chip part, a molded section and a solid-state image pickup element. The integrated circuit and the chip part are on the organic substrate. The molded section, including a central portion and a peripheral portion, form a concave shape. The central portion seals the integrated circuit and the chip part. The peripheral portion is around the central portion. The solid-state image pickup element is on the central portion of the molded section. The solid-state image pickup element has a top edge that is lower in position in a thickness direction than a top edge of the peripheral portion of the molded section.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: August 20, 2019
    Assignee: SONY CORPORATION
    Inventor: Tsuyoshi Watanabe
  • Patent number: 10388516
    Abstract: One or more chips are transferred from one substrate to another by using one or more polymer layers to secure the one or more chips to an intermediate carrier substrate. While secured to the intermediate carrier substrate, the one or more chips may be transported or put through further processing or fabrication steps. To release the one or more chips, the adhesion strength of the one or more polymer layers is gradually reduced to minimize potential damage to the one or more chips.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: August 20, 2019
    Assignee: Facebook Technologies, LLC
    Inventors: Oscar Torrents Abad, Pooya Saketi, Daniel Brodoceanu, Karsten Moh
  • Patent number: 10381301
    Abstract: A semiconductor package including at least one semiconductor device, a first redistribution layer, a first molding compound, a second molding compound, conductive vias and a second redistribution layer. The first redistribution layer is disposed beneath the semiconductor device and electrically connected to the semiconductor device. The first molding compound is disposed over the first redistribution layer and surrounds the semiconductor device. The second molding compound surrounds the first redistribution layer and at least a part of the first molding compound. The conductive vias extend through the second molding compound. The second redistribution layer is disposed on a surface of the second molding compound away from the first redistribution layer. The second redistribution layer is electrically connected to the first redistribution layer through the conductive vias.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: August 13, 2019
    Assignee: Micro Technology, Inc.
    Inventor: Shing-Yih Shih
  • Patent number: 10381760
    Abstract: A system includes a first circuit board and a first card guide configured to receive the first circuit board. The first circuit board includes a plurality of first board conductive pads arranged in a first board pattern. The first card guide includes a plurality of first guide conductive pads arranged in a first guide pattern. The plurality of first board conductive pads and the plurality of first guide conductive pads mate to provide signal communication between the first circuit board and the first card guide.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: August 13, 2019
    Assignee: Hamilton Sundstrand Corporation
    Inventors: Damon L. Raynor, John A. Dickey, Alkesh R. Patel
  • Patent number: 10382042
    Abstract: An assembly including a carrier substrate and at least one group of interconnected integrated circuit modules mounted thereon is disclosed. The modules are provided with a connection for transmitting a clock signal through the group of interconnected modules. The modules are also provided with digital input ports and output ports and a logic circuit configured for identifying the position of the modules in the group on the basis of a count of the clock pulses, and on the basis of the logic state of the input and output ports. In one aspect, a method involves the transfer of a token in the form of one or more logic states, through the group of modules, from a first module to a last module, resulting in the identification of all modules in a progressive manner.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: August 13, 2019
    Assignee: IMEC vzw
    Inventors: Roeland Vandebriel, Geert Van der Plas, Vladimir Cherman
  • Patent number: 10383229
    Abstract: An electronic apparatus includes a first circuit board, a stacked circuit that is provided on the first circuit board through first coupling terminals and has a structure in which arithmetic elements and memory elements are stacked through inter-element coupling terminals and to which a signal is inputted from the first circuit board, and a second circuit board that is provided on the stacked circuit through second coupling terminals and to which a result of processing is outputted from the stacked circuit, wherein a number of the first coupling terminals and a number of the second coupling terminals are smaller than that of the inter-element coupling terminals.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: August 13, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Taiki Uemura, Taiji Sakai, Hideki Kitada
  • Patent number: 10373893
    Abstract: An integrated circuit (IC) package including a substrate comprising a dielectric, and at least one bridge die embedded in the first dielectric. The embedded bridge die comprises a plurality of through-vias extending from a first side to a second side and a first plurality of pads on the first side and a second plurality of pads on the second side. The first plurality of pads are interconnected to the second plurality of pads by the plurality of through-vias extending vertically through the bridge die. The second plurality of pads is coupled to a buried conductive layer in the substrate by solder joints or by an adhesive conductive film between the second plurality of pads of the bridge die and conductive structures in the buried conductive layer, and wherein the adhesive conductive film is over a second dielectric layer on the bridge die.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: August 6, 2019
    Assignee: Intel Corporation
    Inventors: Aditya S. Vaidya, Ravindranath V. Mahajan, Digvijay A. Raorane, Paul R. Start
  • Patent number: 10374419
    Abstract: An on-package interface. A first set of single-ended transmitter circuits on a first die. A first set of single-ended receiver circuits on a second die. The receiver circuits have a termination circuit comprising an inverter and a resistive feedback element. A plurality of conductive lines couple the first set of transmitter circuits and the first set of receiver circuits. The lengths of the plurality of conductive lines are matched.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: August 6, 2019
    Assignee: Intel Corporation
    Inventors: Todd W. Mellinger, Michael E. Griffith, Ganesh Balamurugan, Thomas P. Thomas
  • Patent number: 10373941
    Abstract: A package includes a package component, which further includes a top surface and a metal pad at the top surface of the package component. The package further includes a non-reflowable electrical connector over and bonded to the metal pad, and a molding material over the package component. The non-reflowable electrical connector is molded in the molding material and in contact with the molding material. The non-reflowable electrical connector has a top surface lower than a top surface of the molding compound.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: August 6, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuei-Wei Huang, Chih-Wei Lin, Hsiu-Jen Lin, Wei-Hung Lin, Ming-Da Cheng, Chung-Shi Liu
  • Patent number: 10373666
    Abstract: The present disclosure includes apparatuses and methods related to compute components formed over an array of storage elements. An example apparatus comprises a base substrate material and an array of memory cells formed over the base substrate material. The array can include a plurality of access transistors comprising a first semiconductor material. A compute component can be formed over and coupled to the array. The compute component can include a plurality of compute transistors comprising a second semiconductor material. The second semiconductor material can have a higher concentration of doping ions than the first semiconductor material.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: August 6, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Jason T. Zawodny
  • Patent number: 10373933
    Abstract: The present disclosure relates to a microelectronics package with a self-aligned stacked-die assembly and a process for making the same. The disclosed microelectronics package includes a module substrate, a first die with a first coupling component, a second die with a second coupling component, and a first mold compound. The first die is attached to the module substrate. The first mold compound resides over the module substrate, surrounds the first die, and extends above an upper surface of the first die to define a first opening. Herein, the first mold compound provides vertical walls of the first opening, which are aligned with edges of the first die in X-direction and Y-direction. The second die is stacked with the first die and in the first opening, such that the second coupling component is mirrored to the first coupling component.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: August 6, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, George Maxim
  • Patent number: 10366967
    Abstract: A semiconductor and a method of fabricating the semiconductor having multiple, interconnected die including: providing a semiconductor substrate having a plurality of disparate die formed within the semiconductor substrate, and a plurality of scribe lines formed between pairs of adjacent die of the plurality of disparate die; and fabricating, by a lithography system, a plurality of inter-die connections that extend between adjacent pair of die of the plurality of die.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: July 30, 2019
    Assignee: Cerebras Systems Inc.
    Inventors: Jean-Philippe Fricker, Philip Ferolito
  • Patent number: 10367031
    Abstract: A sequential integration process is described. An example process involves forming a wafer stack by bonding a first wafer to a second wafer with a front side of the first wafer facing a front side of the second wafer, the first wafer including a first device region formed on the front side of the first wafer and including a set of semiconductor devices. The example process involves, subsequent to forming the wafer stack, forming a second device region on a back side of the first wafer, the second device region including a set of semiconductor devices. The example process involves forming at least one interconnection layer on the second device region for electrically interconnecting the semiconductor devices of the second device region. The example process also involves forming at least one via extending through the wafer stack from the at least one interconnection layer and through the first wafer.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: July 30, 2019
    Assignee: IMEC VZW
    Inventors: Amey Mahadev Walke, Anne Vandooren, Nadine Collaert
  • Patent number: 10361172
    Abstract: A semiconductor and a method of fabricating the semiconductor having multiple, interconnected die including: providing a semiconductor substrate having a plurality of disparate die formed within the semiconductor substrate, and a plurality of scribe lines formed between pairs of adjacent die of the plurality of disparate die; and fabricating, by a lithography system, a plurality of inter-die connections that extend between adjacent pair of die of the plurality of die.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: July 23, 2019
    Assignee: Cerebras Systems Inc.
    Inventors: Jean-Philippe Fricker, Philip Ferolito
  • Patent number: 10361650
    Abstract: One example includes a half-bridge switching circuit system. The system includes a first plurality of switches arranged between a first rail voltage and an output on which an output voltage is provided and a second plurality of switches arranged between a second rail voltage and the output, the first and second pluralities of switches being controlled via a plurality of switching signals. The system also includes a plurality of flying capacitors arranged to interconnect the first and second pluralities of switches, and further includes a plurality of snubber circuits that are each arranged in parallel with a respective one of the plurality of flying capacitors, the first plurality of switches, and the second plurality of switches.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: July 23, 2019
    Assignee: LCDRIVES CORP.
    Inventors: Russel Hugh Marvin, David H. Leach
  • Patent number: 10354980
    Abstract: Multiple semiconductor chips can be bonded through copper-to-copper bonding. The multiple semiconductor chips include a logic chip and multiple memory chips. The logic chip includes a peripheral circuitry for operation of memory devices within the multiple memory chips. The memory chips can include front side bonding pad structures, backside bonding pad structures, and sets of metal interconnect structures providing electrically conductive paths between pairs of a first side bonding pad structure and a backside bonding pad structure. Thus, electrical control signal can vertically propagate between the logic chip and an overlying memory chip through at least one intermediate memory chip located between them. The backside bonding pad structures can be formed as portions of integrated through-substrate via and pad structures that extend through a respective semiconductor substrate.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: July 16, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Mitsuteru Mushiga, Akio Nishida, Kenji Sugiura, Hisakazu Otoi, Masatoshi Nishikawa
  • Patent number: 10347552
    Abstract: A semiconductor device includes first and second semiconductor components mounted on an interposer mounted on a wiring substrate, and electrically connected to each other via the interposer. Also, a plurality of wiring layers of the interposer include first, second and third wiring layers which are stacked in order from a main surface side to be a reference. In addition, in a first region of the interposer sandwiched between the first semiconductor component and the second semiconductor component, a ratio of a reference potential wiring in the third wiring layer is higher than a ratio of a reference potential wiring in the first wiring layer. Further, in the first region, a ratio of a signal wiring in the first wiring layer is higher than a ratio of a signal wiring in the third wiring layer.
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: July 9, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Ryuichi Oikawa, Toshihiko Ochiai, Shuuichi Kariyazaki, Yuji Kayashima, Tsuyoshi Kida
  • Patent number: 10347558
    Abstract: Embodiments herein generally relate to the field of package assembly to facilitate thermal conductivity. A package may have a hanging die, and attach to a printed circuit board (PCB). The package may have an active side plane and an inactive side plane opposite the first active side plane. The package may also have a ball grid array (BGA) matrix having a height determined by a distance of a furthest point of the BGA matrix from the active side plane of the package. The package may have a hanging die attached to the active side plane of the package, the hanging die having a z-height greater than the BGA matrix height. When package is attached to the PCB, the hanging die may fit into an area on the PCB that is recessed or has been cut away, and a thermal conductive material may connect the hanging die and the PCB.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: July 9, 2019
    Assignee: INTEL IP CORPORATION
    Inventors: Christian Geissler, Georg Seidemann, Sonja Koller, Jan Proschwitz
  • Patent number: 10347575
    Abstract: This disclosure provides a package substrate and its fabrication method. The package substrate comprises: a first dielectric material layer have an opening; a first conductive unit including a first part in the opening of the first dielectric material layer and a second part on the first dielectric material layer; and a second dielectric material layer covering the first conductive unit and the first dielectric material layer; wherein a height of the first conductive unit is larger than a thickness of the first dielectric material layer; wherein a cross-section of the second part is larger than that of the first part in the first conductive unit.
    Type: Grant
    Filed: August 3, 2016
    Date of Patent: July 9, 2019
    Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.
    Inventors: Chun-Hsien Yu, Shih-Ping Hsu, Pao-Hung Chou, Chi-Feng Peng
  • Patent number: 10347562
    Abstract: A package includes a substrate having an electronic component flip chip mounted thereto by flip chip bumps. The electronic component includes an active surface and an inactive surface. Electrically conductive columns (TSV) extend through the electronic component between the active surface and the inactive surface. A RDL structure is coupled to the inactive surface, the RDL structure redistributing the pattern of the electrically conductive columns at the inactive surface to a pattern of inactive surface RDL lands. The inactive surface RDL lands are exposed through via apertures of a package body. By using the inactive surface of the electronic component to distribute the inactive surface RDL lands, the allowable size of the electronic component is maximized.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: July 9, 2019
    Assignee: Amkor Technology, Inc.
    Inventors: Louis W. Nicholls, Roger D. St. Amand, Jin Seong Kim, Woon Kab Jung, Sung Jin Yang, Robert F. Darveaux
  • Patent number: 10340254
    Abstract: The method of producing an interposer-chip-arrangement, comprises providing an interposer (1) with an integrated circuit (25), arranging a dielectric layer (2) with metal layers embedded in the dielectric layer above a main surface (10) of the interposer, connecting the integrated circuit with at least one of the metal layers, forming an interconnection (7) through the interposer, the interconnection contacting one of the metal layers, arranging a further dielectric layer (3) above a further main surface (11) of the interposer opposite the main surface and arranging a further metal layer in or on the further dielectric layer, the further metal layer being connected with the interconnection, arranging a chip provided with at least one contact pad at the main surface or at the further main surface, and electrically conductively connecting the contact pad with the interconnection.
    Type: Grant
    Filed: October 6, 2017
    Date of Patent: July 2, 2019
    Assignee: ams AG
    Inventors: Jochen Kraft, Martin Schrems, Franz Schrank
  • Patent number: 10340216
    Abstract: A semiconductor package includes a chip and a circuit substrate having leads. Each of the leads has an upper wide portion and a lower wide portion in a bonding area so as there are an upper notch and a lower notch in the bonding area. The upper and lower notches face toward the upper and lower wide portions of the adjacent lead, respectively. The upper and lower wide portions are designed to prevent defective bonding caused by shifting between the leads and the chip humps. Additionally, there are adequate etching spaces between the leads because the wide portions and the notches are staggered with each other such that incomplete etching between the leads is preventable during etching process.
    Type: Grant
    Filed: May 28, 2018
    Date of Patent: July 2, 2019
    Assignee: CHIPBOND TECHNOLOGY CORPORATION
    Inventor: Chin-Tang Hsieh
  • Patent number: 10332854
    Abstract: A microelectronic package can include a substrate having a first surface and a second surface opposite therefrom, the substrate having a first conductive element at the first surface, and a plurality of wire bonds, each of the wire bonds having a base electrically connected to a corresponding one of the first conductive elements and having a tip remote from the base, each wire bond having edge surfaces extending from the tip toward the base. The microelectronic package can also include an encapsulation having a major surface facing away from the first surface of the substrate, the encapsulation having a recess extending from the major surface in a direction toward the first surface of the substrate, the tip of a first one of the wire bonds being disposed within the recess, and an electrically conductive layer overlying an inner surface of the encapsulation exposed within the recess, the electrically conductive layer overlying and electrically connected with the tip of the first one of the wire bonds.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: June 25, 2019
    Assignee: Invensas Corporation
    Inventors: Rajesh Katkar, Gabriel Z. Guevara, Xuan Li, Cyprian Emeka Uzoh, Guilian Gao, Liang Wang
  • Patent number: 10333519
    Abstract: Local on-die termination controllers for effecting termination of a high-speed signaling links simultaneously engage on-die termination structures within multiple integrated-circuit memory devices disposed on the same memory module, and/or within the same integrated-circuit package, and coupled to the high-speed signaling link. A termination control bus is coupled to memory devices on a module, and provides for peer-to-peer communication of termination control signals.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: June 25, 2019
    Assignee: Rambus Inc.
    Inventor: Ian Shaeffer
  • Patent number: 10325840
    Abstract: An apparatus including a circuit structure including a device stratum; and a contact coupled to a supply line and routed through the device stratum and coupled to at least one device on a first side. A method including providing a supply from a package substrate to at least one transistor in a device stratum of a circuit structure; and distributing the supply to the at least one transistor using a supply line on an underside of the device stratum and contacting the at least one transistor on a device side by routing a contact from the supply line through the device stratum. A system including a package substrate, and a die including at least one supply line disposed on an underside of a device stratum and routed through the device stratum and coupled to at least one of a plurality of transistor devices on the device side.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: June 18, 2019
    Assignee: Intel Corporation
    Inventors: Donald W. Nelson, Mark T. Bohr, Patrick Morrow
  • Patent number: 10325883
    Abstract: A method includes attaching a first semiconductor package on a carrier, wherein the first semiconductor package comprises a plurality of stacked semiconductor dies and a plurality of contact pads, depositing a first molding compound layer over the carrier, wherein the first semiconductor package is embedded in the first molding compound layer, forming a plurality of vias over the plurality of contact pads, attaching a semiconductor die on the first molding compound layer, depositing a second molding compound layer over the carrier, wherein the semiconductor die and the plurality of vias are embedded in the second molding compound layer, forming an interconnect structure over the second molding compound layer and forming a plurality of bumps over the interconnect structure.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: June 18, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Hsiang Chiu, Meng-Tse Chen, Ching-Hua Hsieh, Chung-Shi Liu, Sheng-Feng Weng, Ming-Da Cheng
  • Patent number: 10319708
    Abstract: An electronic system supports superior coupling by implementing a communication mechanism that provides at least for horizontal communication for example, on the basis of wired and/or wireless communication channels, in the system. Hence, by enhancing vertical and horizontal communication capabilities in the electronic system, a reduced overall size may be achieved, while nevertheless reducing complexity in printed circuit boards coupled to the electronic system. In this manner, overall manufacturing costs and reliability of complex electronic systems may be enhanced.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: June 11, 2019
    Assignee: STMicroelectronics S.r.l.
    Inventor: Alberto Pagani
  • Patent number: 10319702
    Abstract: A semiconductor package includes a substrate including a signal pattern on an upper surface thereof, a chip stack on the substrate, and a first semiconductor chip and one or more spacers between the substrate and the chip stack. The chip stack includes one or more second semiconductor chips stacked on the substrate. The one or more spacers and the first semiconductor chip are adjacent to respective corners of a lowermost second semiconductor chip, in plan view. The one or more spacers have the same planar shape as the first semiconductor chip.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: June 11, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chul Park, Seonggwan Lee, Minkyeong Park
  • Patent number: 10319670
    Abstract: In a general aspect, an apparatus can include a package including a common gate conductor, a first silicon carbide die having a die gate conductor, and a second silicon carbide die having a die gate conductor. The apparatus can include a first conductive path between the common gate conductor and the die gate conductor of the first silicon carbide die and a second conductive path between the common gate conductor and the die gate conductor of the second silicon carbide die where the first conductive path has a length substantially equal to a length of the second conductive path.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: June 11, 2019
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Jerome Teysseyre, Maria Cristina Estacio, Seungwon Im
  • Patent number: 10321580
    Abstract: Embodiments of the present invention are directed to an integrated circuit (IC) package assembly. The IC package assembly includes a base printed circuit board (PCB), and a set of IC packages. Each of the IC packages includes at least one IC chip, mounted on or partly in a support component, which mechanically supports and electrically connects to the IC chip. In addition, each of the IC packages is laterally soldered to the base PCB (e.g., a motherboard PCB) and arranged transversally to the base PCB and forms an angle ? therewith. As a result, a slanted stack of IC packages is obtained, wherein the IC packages are essentially parallel to each other. Further embodiments are directed to related devices, including the above assembly, and to related fabrication methods.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: June 11, 2019
    Assignee: International Business Machines Corporation
    Inventors: Ralph Heller, Patricia Maria Sagmeister, Martin Leo Schmatz
  • Patent number: 10319699
    Abstract: Structures and formation methods of a chip package are provided. The chip package includes a chip stack including a number of semiconductor dies. The chip package also includes a semiconductor chip, and the semiconductor chip is higher than the chip stack. The chip package further includes a package layer covering a top and sidewalls of the chip stack and sidewalls of the semiconductor chip.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: June 11, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wen-Hsin Wei, Chi-Hsi Wu, Chen-Hua Yu, Hsien-Pin Hu, Shang-Yun Hou, Weiming Chris Chen
  • Patent number: 10319607
    Abstract: A device comprises a substrate having a die mounted on the first side of the substrate and a moldable underfill (MUF) disposed on the first side of the substrate and around the die. An interposer is mounted on the first side of the substrate, with the interposer having lands disposed on a first side of the interposer. The interposer mounted to the substrate by connectors bonded to a second side of the interposer, the connectors providing electrical connectivity between the interposer and the substrate. A package is mounted on the first side of the interposer and is electrically connected to the lands. At least one of the lands is aligned directly over the die and wherein a pitch of the connectors is different than a pitch of the lands.
    Type: Grant
    Filed: August 22, 2014
    Date of Patent: June 11, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiun Yi Wu, Yu-Min Liang, Mirng-Ji Lii, Chien-Hsun Lee, Tsung-Ding Wang, Jung Wei Cheng
  • Patent number: 10312216
    Abstract: A method of ultrasonically bonding semiconductor elements includes the steps of: (a) aligning surfaces of a plurality of first conductive structures of a first semiconductor element to respective surfaces of a plurality of second conductive structures of a second semiconductor element, wherein the surfaces of each of the plurality of first conductive structures and the plurality of second conductive structures include aluminum; and (b) ultrasonically bonding ones of the first conductive structures to respective ones of the second conductive structures.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: June 4, 2019
    Assignee: KULICKE AND SOFFA INDUSTRIES, INC.
    Inventors: Robert N. Chylak, Dominick A. DeAngelis
  • Patent number: 10312112
    Abstract: An integrated fan-out package having a multi-band antenna and a method of forming the same are disclosed. An integrated fan-out package includes a semiconductor die, a molding layer and a plurality of through integrated fan-out vias. The molding layer is aside the semiconductor die. The through integrated fan-out vias are through the molding layer and arranged to form a plurality of dipole antennas. At least one of the plurality of dipole antennas includes two dipole arms each having a transmitting strip and a radiating strip connected to the transmitting part, and the radiating strip has a first part, a second part and a filter part between and in contact with the first part and the second part. The cross-sectional area of the filter part is less than the cross-sectional area of the first part or the second part of the radiating strip.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: June 4, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Nan-Chin Chuang, Ching-Feng Yang, Kai-Chiang Wu
  • Patent number: 10306751
    Abstract: An electronic module assembly has a memory module that includes a memory module and an electronic module. The memory module includes a first board having a first board first surface disposed opposite a first board second surface. The electronic module is operatively connected to the memory module. The electronic module includes a mounting plate having a mounting plate first surface that is disposed opposite a mounting plate second surface that faces towards the first board first surface. The mounting plate has a first post and a second post spaced apart from the first post.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: May 28, 2019
    Assignee: HAMILTON SUNDSTRAND CORPORATION
    Inventors: Jason C. Duffy, James A. Gosse, Shun-Tien Lin, Michael Maynard, An Nguyen
  • Patent number: 10304786
    Abstract: A composite carrier is disclosed for warpage management as a temporary carrier in semiconductor process. Warpage is reduced for a product, semi-product, or build-up layer processed on the temporary composite carrier which is peeled off the temporary carrier in a later step. The composite carrier comprises a top substrate and a bottom substrate, an adhesive layer is configured in between the top substrate and a bottom substrate. One of the embodiments discloses the top substrate of the composite carrier having a lower CTE and the bottom substrate of the composite carrier having a higher CTE.
    Type: Grant
    Filed: September 13, 2018
    Date of Patent: May 28, 2019
    Inventor: Dyi-Chung Hu
  • Patent number: 10297574
    Abstract: There is provided a semiconductor device assembly with an interposer and method of manufacturing the same. More specifically, in one embodiment, there is provided a semiconductor device assembly comprising a semiconductor substrate, at least one semiconductor die attached to the semiconductor substrate, an interposer disposed on the semiconductor die, and a controller attached to the interposer. There is also provided a method of manufacturing comprising forming a first subassembly by coupling a substrate and a semiconductor die, and forming second subassembly by attaching a controller to an interposer, and coupling the first subassembly to the second subassembly.
    Type: Grant
    Filed: April 22, 2014
    Date of Patent: May 21, 2019
    Assignee: Micron Technology, Inc.
    Inventors: David J. Corisis, Matt Schwab