Stacked Arrangement Patents (Class 257/686)
  • Patent number: 11901263
    Abstract: A semiconductor device includes a package and a cooling cover. The package includes a first die having an active surface and a rear surface opposite to the active surface. The rear surface has a cooling region and a peripheral region enclosing the cooling region. The first die includes micro-trenches located in the cooling region of the rear surface. The cooling cover is stacked on the first die. The cooling cover includes a fluid inlet port and a fluid outlet port located over the cooling region and communicated with the micro-trenches.
    Type: Grant
    Filed: March 15, 2023
    Date of Patent: February 13, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Jung Wu, Chih-Hang Tung, Tung-Liang Shao, Sheng-Tsung Hsiao, Jen-Yu Wang
  • Patent number: 11887967
    Abstract: A semiconductor device package includes a substrate, a connection structure, a first package body and a first electronic component. The substrate has a first surface and a second surface opposite to the first surface. The connection structure is disposed on the firs surface of the substrate. The first package body is disposed on the first surface of the substrate. The first package body covers the connection structure and exposes a portion of the connection structure. The first electronic component is disposed on the first package body and in contact with the portion of the connection structure exposed by the first package body.
    Type: Grant
    Filed: October 4, 2021
    Date of Patent: January 30, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Shang-Ruei Wu, Chien-Yuan Tseng, Meng-Jen Wang, Chen-Tsung Chang, Chih-Fang Wang, Cheng-Han Li, Chien-Hao Chen, An-Chi Tsao, Per-Ju Chao
  • Patent number: 11876039
    Abstract: In one example, a semiconductor device includes a substrate with a top side, a bottom side, and a conductive structure. A first electronic component includes a first side, a second side, and first component terminals adjacent to the first side. The first component terminals face the substrate bottom side and are connected to the conductive structure. A second electronic component comprises a first side, a second side, and second component terminals adjacent to the second electronic component first side. The second electronic component second side is connected to the first electronic component second side with a coupling structure so that the first component terminals and the second component terminals face opposite directions. Interconnects are connected to the conductive structure. The second component terminals and the interconnects are configured for connecting to a next level assembly. Other examples and related methods are also disclosed herein.
    Type: Grant
    Filed: June 11, 2022
    Date of Patent: January 16, 2024
    Assignee: Amkor Technol Singapore Holding Pte. Ltd.
    Inventors: Roger D. St. Amand, Louis W. Nicholls
  • Patent number: 11869869
    Abstract: A method includes putting a first package component into contact with a second package component. The first package component comprises a first dielectric layer including a first dielectric material, and the first dielectric material is a silicon-oxide-based dielectric material. The second package component includes a second dielectric layer including a second dielectric material different from the first dielectric material. The second dielectric material comprises silicon and an element selected from the group consisting of carbon, nitrogen, and combinations thereof. An annealing process is performed to bond the first dielectric layer to the second dielectric layer.
    Type: Grant
    Filed: December 6, 2021
    Date of Patent: January 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Hua Yu, Wen-Chih Chiou, Ku-Feng Yang, Ming-Tsu Chung
  • Patent number: 11869890
    Abstract: An apparatus is provided which comprises: a first transistor comprising a source region and a drain region with a channel region therebetween, a first dielectric layer over the first transistor, a second transistor comprising a source region and a drain region with a channel region therebetween, wherein the second transistor is over the first dielectric layer, a second dielectric layer over the second transistor, and a contact coupled to the source region or the drain region of the first transistor, wherein the contact comprises a metal having a straight sidewall that extends from through both the first and second dielectric layers. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: January 9, 2024
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Willy Rachmady, Gilbert Dewey, Rishabh Mehandru, Jack T. Kavalieros
  • Patent number: 11830853
    Abstract: Semiconductor devices may include a first semiconductor chip, a first redistribution layer on a bottom surface of the first semiconductor chip, a second semiconductor chip on the first semiconductor chip, a second redistribution layer on a bottom surface of the second semiconductor chip, a mold layer extending on sidewalls of the first and second semiconductor chips and on the bottom surface of the first semiconductor chip, and an external terminal extending through the mold layer and electrically connected to the first redistribution layer. The second redistribution layer may include an exposed portion. The first redistribution layer may include a first conductive pattern electrically connected to the first semiconductor chip and a second conductive pattern electrically insulated from the first semiconductor chip. The exposed portion of the second redistribution layer and the second conductive pattern of the first redistribution layer may be electrically connected by a first connection wire.
    Type: Grant
    Filed: January 24, 2022
    Date of Patent: November 28, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ae-Nee Jang, Young Lyong Kim
  • Patent number: 11804443
    Abstract: A method includes encapsulating a plurality of package components in an encapsulant, and forming a first plurality of redistribution layers over and electrically coupling to the plurality of package components. The first plurality of redistribution layers have a plurality of power/ground pad stacks, with each of the plurality of power/ground pad stacks having a pad in each of the first plurality of redistribution layers. The plurality of power/ground pad stacks include a plurality of power pad stacks, and a plurality of ground pad stacks. At least one second redistribution layer is formed over the first plurality of redistribution layers. The second redistribution layer(s) include power lines and electrical grounding lines electrically connecting to the plurality of power/ground pad stacks.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: October 31, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shu-Rong Chun, Tin-Hao Kuo, Chi-Hui Lai, Kuo Lung Pan, Yu-Chia Lai, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
  • Patent number: 11798865
    Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a base substrate. The base substrate may have a plurality of through substrate vias. In an embodiment, a first die is over the base substrate. In an embodiment a first cavity is disposed into the base substrate. In an embodiment, the first cavity is at least partially within a footprint of the first die. In an embodiment, a first component is in the first cavity.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: October 24, 2023
    Assignee: Intel Corporation
    Inventors: Ravindranath Mahajan, Debendra Mallik, Sujit Sharan, Digvijay Raorane
  • Patent number: 11798899
    Abstract: In some embodiments, the present disclosure relates to a semiconductor structure. The semiconductor structure includes a stacked semiconductor substrate having a semiconductor material disposed over a base semiconductor substrate. The base semiconductor substrate has a first coefficient of thermal expansion and the semiconductor material has a second coefficient of thermal expansion that is different than the first coefficient of thermal expansion. The stacked semiconductor substrate includes one or more sidewalls defining a crack stop ring trench that continuously extends in a closed path between a central region of the stacked semiconductor substrate and a peripheral region of the stacked semiconductor substrate surrounding the central region. The peripheral region of the stacked semiconductor substrate includes a plurality of cracks and the central region is substantially devoid of cracks.
    Type: Grant
    Filed: August 2, 2021
    Date of Patent: October 24, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiun-Yu Chen, Chun-Lin Tsai, Yun-Hsiang Wang, Chia-Hsun Wu, Jiun-Lei Yu, Po-Chih Chen
  • Patent number: 11792922
    Abstract: An electronic circuit assembly includes an interposer substrate, a wiring substrate, an electrical connective part and an electronic component. The interposer substrate with a first coefficient of thermal expansion (CTE) includes a first surface, a second surface opposite to the first surface, and a first side surface connecting to the first surface and the second surface. The wiring substrate with a second CTE is disposed below the second surface. The first CTE is lower than the second CTE. The electrical connective part is disposed in the interposer substrate and extends to the first side surface. The electronic component is attached to the first side surface and is electrically connected to the electrical connective part.
    Type: Grant
    Filed: May 8, 2022
    Date of Patent: October 17, 2023
    Assignee: Unimicron Technology Corp.
    Inventor: Chun-Hung Kuo
  • Patent number: 11764179
    Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a conductive pillar having a first surface, a second surface, and a lateral surface extending between the first surface and the second surface. The lateral surface has a first part and a second part connected to the first part. The semiconductor device package also includes a barrier layer in contact with the first part of the lateral surface of the conductive pillar and an encapsulant in contact with the second part of the lateral surface of the conductive pillar. The semiconductor device package also includes a first flowable conductive material disposed on the first surface of the conductive pillar. A method of manufacturing a semiconductor device package is also disclosed.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: September 19, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Zhi-Yuan Lin
  • Patent number: 11756873
    Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package at least has a semiconductor die and a redistribution layer disposed on an active surface of the semiconductor die and electrically connected with the semiconductor die. The redistribution layer has a wiring-free zone arranged at a location below a corner of the semiconductor die. An underfill is disposed between the semiconductor die and the redistribution layer. The wiring-free zone is located below the underfill and is in contact with the underfill. The wiring-free zone extends horizontally from the semiconductor die to the underfill.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: September 12, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Kuei Hsu, Ming-Chih Yew, Tsung-Yen Lee, Po-Yao Lin, Shin-Puu Jeng
  • Patent number: 11749653
    Abstract: A vertical-wire package-in-package includes at least two memory-die stacks that form respective memory modules that are stacked vertically on a bond-wire board. Each memory die in the memory-die stack includes a vertical bond wire that emerges from a matrix for connection. The matrix encloses the memory-die stack, the spacer, and a redistribution layer. At least two memory modules are assembled in a vertical-wire package-in-package.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: September 5, 2023
    Assignee: Intel Corporation
    Inventors: Hyoung Il Kim, Florence R. Pon, Yi Elyn Xu
  • Patent number: 11742326
    Abstract: Stacked superconducting integrated circuits with three dimensional resonant clock networks are described. An apparatus, including a first superconducting integrated circuit having a first clock distribution network for distributing a first clock signal in the first superconducting integrated circuit, is provided. The apparatus further includes a second superconducting integrated circuit, stacked on top of the first superconducting integrated circuit, having a second clock distribution network for distributing a second clock signal in the second superconducting integrated circuit, where each of the first clock distribution network and the second clock distribution network comprises a clock structure having a plurality of unit cells, where each of the plurality of unit cells includes at least one spine and at least one stub, the at least one stub inductively coupled to a first superconducting circuit, and where each of the first clock signal and the second clock signal has a same resonant frequency.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: August 29, 2023
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Vladimir V. Talanov, Anna Y. Herr
  • Patent number: 11735538
    Abstract: A semiconductor device configured for a radio frequency (RF) application and further configured for passive device integration and/or improved cooling includes a substrate; an active region portion arranged on the substrate, the active region portion includes at least one radio frequency (RF) transistor amplifier; a cavity arranged within the substrate; and one or more radio frequency (RF) devices arranged in the cavity.
    Type: Grant
    Filed: February 17, 2020
    Date of Patent: August 22, 2023
    Assignee: WOLFSPEED, INC.
    Inventor: Fabian Radulescu
  • Patent number: 11722221
    Abstract: An optical module includes: photoelectric elements including first terminal groups; an integrated circuit including second terminal groups and ground terminals; a carrier substrate; a housing; and a common ground pad. Further, the carrier substrate is fixed to one surface of the housing, the carrier substrate includes signal wiring parts and a ground wiring part, the ground wiring part includes terminal pattern parts, a common pattern part, and a coupling part, each of the terminal pattern parts being disposed between the corresponding signal wiring parts and electrically connected with one of the ground terminals, the common pattern part being disposed on a side where the common ground pad is provided on the carrier substrate, the coupling part electrically connecting each terminal pattern part and the common pattern part, and the ground terminals of the integrated circuit are electrically connected with the common ground pad through the ground wiring part.
    Type: Grant
    Filed: August 12, 2021
    Date of Patent: August 8, 2023
    Assignee: FURUKAWA ELECTRIC CO., LTD.
    Inventors: Kazuya Nagashima, Yozo Ishikawa, Atsushi Izawa
  • Patent number: 11721577
    Abstract: A method of manufacturing a semiconductor package may include forming a first substrate including a redistribution layer, providing a second substrate including a semiconductor chip and an interconnection layer on the first substrate to connect the semiconductor chip to the redistribution layer, forming a first encapsulation layer covering the second substrate, and forming a via structure penetrating the first encapsulation layer. The forming the via structure may include forming a first via hole in the first encapsulation layer, forming a photosensitive material layer in the first via hole, exposing and developing the photosensitive material layer in the first via hole to form a second encapsulation layer having a second via hole, and filling the second via hole with a conductive material. A surface roughness of a sidewall of the first encapsulation layer may be greater than a surface roughness of a sidewall of the second encapsulation layer.
    Type: Grant
    Filed: April 6, 2022
    Date of Patent: August 8, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dowan Kim, Doohwan Lee, Seunghwan Baek
  • Patent number: 11705428
    Abstract: The present disclosure relates to a radio frequency device that includes a transfer device die and a multilayer redistribution structure underneath the transfer device die. The transfer device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion and a transfer substrate. The FEOL portion includes isolation sections and an active layer surrounded by the isolation sections. A top surface of the device region is planarized. The transfer substrate including a porous silicon (PSi) region resides over the top surface of the device region. Herein, the PSi region has a porosity between 1% and 80%. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the transfer device die.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: July 18, 2023
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Michael Carroll
  • Patent number: 11701019
    Abstract: Intraocular physiological sensor implants include a physiological sensor, and a housing comprising a faceplate. The physiological sensor is integrated with the faceplate. The physiological sensor typically comprises an intraocular pressure sensor, such as a capacitive pressure sensor that may further include a flexible diaphragm electrode spaced apart from a counter electrode. The intraocular pressure sensor detects intraocular pressure, to identify patient conditions such as glaucoma.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: July 18, 2023
    Assignee: GLAUKOS CORPORATION
    Inventors: Nicholas Gunn, Andrew Johnson, David S. Haffner, Cesario Dos Santos
  • Patent number: 11664340
    Abstract: An electronic module is disclosed. The electronic module can include a package substrate, an integrated device die, a dam structure, and a mounting compound. The integrated device die can have an upper side, a lower side, and an outer side edge. The dam structure can have a first sidewall and a second sidewall opposite the first sidewall. The second sidewall can be nearer to the outer side edge than the first sidewall. The first sidewall can be laterally positioned between a center of the lower side of the integrated device die and the outer side edge. The dam structure can be disposed between a portion of the package substrate and a portion of the lower side of the integrated device die. The mounting compound can be disposed between the lower side of the integrated device die and the package substrate. The dam structure can be positioned between the mounting compound and the outer side edge of the integrated device die.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: May 30, 2023
    Assignee: ANALOG DEVICES, INC.
    Inventors: Vikram Venkatadri, David Frank Bolognia
  • Patent number: 11658154
    Abstract: Semiconductor devices with controllers under stacks of semiconductor packages and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a package substrate, a controller attached to the package substrate, and at least two semiconductor packages disposed over the controller. Each semiconductor package includes a plurality of semiconductor dies. The semiconductor device further includes an encapsulant material encapsulating the controller and the at least two semiconductor packages.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: May 23, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Seng Kim Ye, Hong Wan Ng
  • Patent number: 11659674
    Abstract: A display device includes a display panel, a frame disposed on a rear surface of the display panel, a plurality of panel magnets disposed in the frame, a plurality of panel ferromagnetic substances disposed on both side surfaces of each of the plurality of magnets, and a connecting module disposed on the rear surface of the display panel and having a connecting plate for supplying power to the display panel, in which the connecting plate is configured to protrude outside the frame or be positioned more inward than the rear surface of the frame depending on the detachment from the panel ferromagnetic substances of the connecting module.
    Type: Grant
    Filed: December 17, 2021
    Date of Patent: May 23, 2023
    Assignee: LG DISPLAY CO., LTD.
    Inventors: HanSeok Kim, Hyeongkyu Kim
  • Patent number: 11652011
    Abstract: A method to manufacture a semiconductor device includes: bonding a first wafer and a second wafer to be stacked vertically with one another, in which the first wafer provides a plurality of memory components and the second wafer provides a control circuit; forming a plurality of input/output channels on a surface of one of the first and second wafers; and cutting the bonded first and second wafers into a plurality of dices; wherein a plurality of first conductive contacts in the first wafer are electrically connected to the control circuit and the first conductive contacts in combinations with a plurality of first conductive vias in the first wafer form a plurality of transmission channels through which the control circuit is capable to access the memory components.
    Type: Grant
    Filed: August 12, 2021
    Date of Patent: May 16, 2023
    Assignee: AP Memory Technology Corp.
    Inventors: Wen Liang Chen, Lin Ma, Chien-An Yu, Chun Yi Lin
  • Patent number: 11652064
    Abstract: Improve EM coupling for the wafer-bonding process from a first wafer to a second wafer by a shielding technique. Examples may include building an EM shield implemented by BEOL-stacks/routings, bonding contacts, and TSVs for a closed-loop shielding platform for the integrated device to minimize EM interference from active devices due to eddy currents. The shield may be implemented in the active device layer during a wafer-to-wafer bonding-process that uses two different device layers/wafers, an active device layer/wafer and a passive device layer/wayer. The shield may be designed by the patterned routings for both I/O ports and the GND contacts.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: May 16, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Jonghae Kim, Je-Hsiung Lan, Ranadeep Dutta
  • Patent number: 11631644
    Abstract: A semiconductor device assembly can include a semiconductor device having a substrate and vias electrically connected to circuitry of the semiconductor device. Individual vias can have an embedded portion extending from the first side to the second side of the substrate and an exposed portion projecting from the second side of the substrate. The assembly can include a density-conversion connector comprising a connector substrate and a first array of contacts formed at the first side thereof, the first array of contacts occupying a first footprint area on the first side thereof, and wherein individual contacts of the first array are electrically connected to the exposed portion of a corresponding via of the semiconductor device. The assembly can include a second array of contacts electrically connected to the first array, formed at the second side of the connector substrate, and occupying a second footprint area larger than the first footprint area.
    Type: Grant
    Filed: April 2, 2021
    Date of Patent: April 18, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Owen R. Fay, Kyle K. Kirby, Akshay N. Singh
  • Patent number: 11626359
    Abstract: A three-dimensional (3D) integrated circuit (IC) includes a first die. The first die includes a 3D stacked capacitor on a first surface of the first die and coupled to a power distribution network (PDN) of the first die. The 3D IC also includes a second die stacked on the first surface of the first die, proximate the 3D stacked capacitor on the first surface of the first die. The 3D IC further includes active circuitry coupled to the 3D stacked capacitor through the PDN of the first die.
    Type: Grant
    Filed: April 27, 2021
    Date of Patent: April 11, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Biancun Xie, Shree Krishna Pandey, Irfan Khan, Miguel Miranda Corbalan, Stanley Seungchul Song
  • Patent number: 11610878
    Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The method includes providing a bottom substrate; bonding a first stacking chip and a second stacking chip onto the bottom substrate; conformally forming a first isolation layer to cover the first and second stacking chips and to at least partially fill a gap between the first and second stacking chips; performing a thinning process to expose back surfaces of the first and second stacking chips; performing a removal process to expose through substrate vias of the first and second stacking chips; forming a first capping layer to cover the through substrate vias of the first and second stacking chips; and performing a planarization process to expose the through substrate vias of the first and second stacking chips and provide a substantially flat surface.
    Type: Grant
    Filed: September 2, 2021
    Date of Patent: March 21, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Yi-Jen Lo
  • Patent number: 11610863
    Abstract: The present disclosure relates to a radio frequency device that includes a transfer device die and a multilayer redistribution structure underneath the transfer device die. The transfer device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion and a transfer substrate. The FEOL portion includes isolation sections and an active layer surrounded by the isolation sections. A top surface of the device region is planarized. The transfer substrate including a porous silicon (PSi) region resides over the top surface of the device region. Herein, the PSi region has a porosity between 1% and 80%. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the transfer device die.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: March 21, 2023
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Michael Carroll
  • Patent number: 11600653
    Abstract: Methods for forming via last through-vias. A method includes providing an active device wafer having a front side including conductive interconnect material disposed in dielectric layers and having an opposing back side; providing a carrier wafer having through vias filled with an oxide extending from a first surface of the carrier wafer to a second surface of the carrier wafer; bonding the front side of the active device wafer to the second surface of the carrier wafer; etching the oxide in the through vias in the carrier wafer to form through oxide vias; and depositing conductor material into the through oxide vias to form conductors that extend to the active carrier wafer and make electrical contact to the conductive interconnect material. An apparatus includes a carrier wafer with through oxide vias extending through the carrier wafer to an active device wafer bonded to the carrier wafer.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: March 7, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Szu-Ying Chen, Pao-Tung Chen, Dun-Nian Yaung, Jen-Cheng Liu
  • Patent number: 11598850
    Abstract: An apparatus has an illumination layer having an array of a plurality of illuminators, and a circuit layer having one or more drivers for controlling the plurality of illuminators. The laser layer and the circuit layer overlap at least partially, and each driver of the one or more drivers controls at least one illuminator of the plurality of illuminators.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: March 7, 2023
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Daniel Van Nieuwenhove, Ward Van Der Tempel
  • Patent number: 11600525
    Abstract: A method for fabricating a three-dimensional (3D) stacked integrated circuit. Pick-and-place strategies are used to stack the source wafers with device layers fabricated using standard two-dimensional (2D) semiconductor fabrication technologies. The source wafers may be stacked in either a sequential or parallel fashion. The stacking may be in a face-to-face, face-to-back, back-to-face or back-to-back fashion. The source wafers that are stacked in a face-to-back, back-to-face or back-to-back fashion may be connected using Through Silicon Vias (TSVs). Alternatively, source wafers that are stacked in a face-to-face fashion may be connected using Inter Layer Vias (ILVs).
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: March 7, 2023
    Assignee: Board of Regents, The University of Texas System
    Inventors: Sidlgata V. Sreenivasan, Paras Ajay, Aseem Sayal, Ovadia Abed, Mark McDermott, Jaydeep Kulkarni, Shrawan Singhal
  • Patent number: 11600567
    Abstract: A semiconductor device package includes a first circuit layer, a second circuit layer, a first semiconductor die and a second semiconductor die. The first circuit layer includes a first surface and a second surface opposite to the first surface. The second circuit layer is disposed on the first surface of the first circuit layer. The first semiconductor die is disposed on the first circuit layer and the second circuit layer, and electrically connected to the first circuit layer and the second circuit layer. The second semiconductor die is disposed on the second circuit layer, and electrically connected to the second circuit layer.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: March 7, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chih-Cheng Lee, Kuang Hsiung Chen
  • Patent number: 11588210
    Abstract: Methods of forming a controllable resistive element include forming source and drain regions in a substrate. A battery stack is formed on a substrate between the source and drain regions. Respective anode and cathode electrical connections are formed to the battery stack. Respective source and drain electrical connections are formed.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: February 21, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen W. Bedell, Joel P. De Souza, Yun Seog Lee, Ning Li, Devendra K. Sadana
  • Patent number: 11581288
    Abstract: The present disclosure relates to a radio frequency device that includes a transfer device die and a multilayer redistribution structure underneath the transfer device die. The transfer device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion and a transfer substrate. The FEOL portion includes isolation sections and an active layer surrounded by the isolation sections. A top surface of the device region is planarized. The transfer substrate including a porous silicon (PSi) region resides over the top surface of the device region. Herein, the PSi region has a porosity between 1% and 80%. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the transfer device die.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: February 14, 2023
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Michael Carroll
  • Patent number: 11573121
    Abstract: A sensor element comprises: a first substrate; a detector disposed on the first substrate; and a second substrate surrounding the first substrate and supporting the first substrate. The second substrate is thicker than the first substrate. The second substrate has a connection part which is connected to the first substrate and a non-connection part which is not connected to the first substrate. The detector is located in the vicinity of the connection part.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: February 7, 2023
    Assignee: KYOCERA Corporation
    Inventor: Atsuomi Fukuura
  • Patent number: 11570898
    Abstract: The invention relates to a multi-layer 3D foil package and to a method for manufacturing such a multi-layer 3D foil package. The 3D foil package has a foil substrate stack having at least two foil planes, wherein a first electrically insulating foil substrate is arranged in a first foil plane, and wherein a second electrically insulating foil substrate is arranged in a second foil plane, wherein the first foil substrate has a first main surface region on which at least one functional electronic component is arranged, wherein the second foil substrate has a cavity having at least one opening in the second main surface region, wherein the foil substrates within the foil substrate stack are arranged one above the other such that the functional electronic component arranged on the first foil substrate is arranged within the cavity provided in the second foil substrate.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: January 31, 2023
    Assignee: FRAUNHOFER-GESELLSCHAFT ZUR FÖRDERUNG DER ANGEWANDTEN FORSCHUNG E.V.
    Inventors: Christof Landesberger, Erwin Yacoub-George, Martin König
  • Patent number: 11569172
    Abstract: Semiconductor devices and methods of manufacture are provided. In embodiments the semiconductor device includes a substrate, a first interposer bonded to the substrate, a second interposer bonded to the substrate, a bridge component electrically connecting the first interposer to the second interposer, two or more first dies bonded to the first interposer; and two or more second dies bonded to the second interposer.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: January 31, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shang-Yun Hou, Hsien-Pin Hu
  • Patent number: 11569173
    Abstract: Systems and methods of conductively coupling at least three semiconductor dies included in a semiconductor package using a multi-die interconnect bridge that is embedded, disposed, or otherwise integrated into the semiconductor package substrate are provided. The multi-die interconnect bridge is a passive device that includes passive electronic components such as conductors, resistors, capacitors and inductors. The multi-die interconnect bridge communicably couples each of the semiconductor dies included in the at least three semiconductor dies to each of at least some of the remaining at least three semiconductor dies. The multi-die interconnect bridge occupies a first area on the surface of the semiconductor package substrate. The smallest of the at least three semiconductor dies coupled to the multi-die interconnect bridge 120 occupies a second area on the surface of the semiconductor package substrate, where the second area is greater than the first area.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: January 31, 2023
    Assignee: Intel Corporation
    Inventors: Andrew P. Collins, Digvijay A. Raorane, Wilfred Gomes, Ravindranath V. Mahajan, Sujit Sharan
  • Patent number: 11553601
    Abstract: A wiring board includes a resin insulating layer having a component mounting surface, first connection pads formed on the component mounting surface of the resin insulating layer, second connection pads formed on the component mounting surface of the resin insulating layer such that the second connection pads are surrounding the first connection pads, and a protruding part including a metal material and formed on the component mounting surface of the resin insulating layer such that a portion of the protruding part is embedded in the resin insulating layer and that the protruding part is positioned between the first connection pads and the second connection pads and surrounding the first connection pads.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: January 10, 2023
    Assignee: IBIDEN CO., LTD.
    Inventors: Kazuyuki Ueda, Shota Tachibana
  • Patent number: 11552062
    Abstract: A package-on-package (PoP) semiconductor package includes an upper package and a lower package. The lower package includes a first semiconductor device in a first area, a second semiconductor device in a second area, and a command-and-address vertical interconnection, a data input-output vertical interconnection, and a memory management vertical interconnection adjacent to the first area.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: January 10, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tong-suk Kim, Byeong-yeon Cho
  • Patent number: 11552051
    Abstract: Electronic device package technology is disclosed. An electronic device package in accordance with the present disclosure can include a substrate, a plurality of electronic components in a stacked relationship, and an encapsulant material encapsulating the electronic components. Each of the electronic components can be electrically coupled to the substrate via a wire bond connection and spaced apart from an adjacent electronic component to provide clearance for the wire bond connection. The encapsulant can be disposed between center portions of adjacent electronic components. Associated systems and methods are also disclosed.
    Type: Grant
    Filed: April 1, 2017
    Date of Patent: January 10, 2023
    Assignee: Intel Corporation
    Inventors: Florence R. Pon, John G. Meyers
  • Patent number: 11552634
    Abstract: An apparatus that includes an interposer, first power connectors that are disposed on a first surface and that receive respective power inputs from one or more power sources, second power connectors that are disposed on the second surface and that receive a respective third power connecter of an integrated circuit when the integrated circuit is mounted on the second surface of the interposer, a plurality of switches formed within the interposer, control circuitry formed within the interposer, and a sequencer circuit coupled to the control input of the control circuitry and that generates a different values for a control input signal that causes the control logic of the control circuitry to generate a corresponding set of switch signals, and the plurality of different values for the control input signal are generated according to a predefined sequence to provide power to the integrated circuit according to power up sequence.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: January 10, 2023
    Assignee: Google LLC
    Inventors: Houle Gan, Mikhail Popovich, Shuai Jiang, Gregory Sizikov, Chee Yee Chung
  • Patent number: 11553591
    Abstract: An electronic device includes a circuit board, a driving member, and a working member. The circuit board has a board body, conductive lines, and conductive pads. The board body has a working surface. The driving member includes a substrate, a thin film circuit, a thin film element, and connection pads. The thin film circuit corresponds to thin film element and is electrically connected to the connection pads, and the connection pads are connected to partial conductive pads. The substrate has a first top surface. The working member has at least one electrode electrically connected to one of the conductive pads. The working member has a second top surface. A first height is defined between the first top surface and the working surface, and a second height is defined between the second top surface and the working surface. The second height is greater than or equal to the first height.
    Type: Grant
    Filed: April 14, 2021
    Date of Patent: January 10, 2023
    Assignee: GIO OPTOELECTRONICS CORP.
    Inventor: Chin-Tang Li
  • Patent number: 11543376
    Abstract: The present invention relates to a method for manufacturing a sample for thin film property measurement and analysis, and a sample manufactured thereby and, more specifically, to: a method for manufacturing a sample capable of measuring or analyzing various properties in one sample; and a sample manufactured thereby.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: January 3, 2023
    Assignee: SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
    Inventors: Ki-Bum Kim, Min-Sik Kim, Hyun-Mi Kim, Ki-Ju Kim
  • Patent number: 11543868
    Abstract: In an embodiment, a processor includes at least one core and power management logic. The power management logic is to receive temperature data from a plurality of dies within a package that includes the processor, and determine a smallest temperature control margin of a plurality of temperature control margins. Each temperature control margin is to be determined based on a respective thermal control temperature associated with the die and also based on respective temperature data associated with the die. The power management logic is also to generate a thermal report that is to include the smallest temperature control margin, and to store the thermal report. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: January 3, 2023
    Assignee: Intel Corporation
    Inventors: Tessil Thomas, Robin A. Steinbrecher, Sandeep Ahuja, Michael Berktold, Timothy Y. Kam, Howard Chin, Phani Kumar Kandula, Krishnakanth V. Sistla
  • Patent number: 11545303
    Abstract: Disclosed herein is an electronic component that includes a substrate; and a plurality of conductive layers and a plurality of insulating layers which are alternately laminated on the substrate. The side surface of a predetermined one of the plurality of insulating layers has a recessed part set back from a side surface of the substrate and a projecting part projecting from the recessed part. The recessed part is covered with a first dielectric film made of an inorganic insulating material.
    Type: Grant
    Filed: January 7, 2021
    Date of Patent: January 3, 2023
    Assignee: TDK CORPORATION
    Inventors: Kazuhiro Yoshikawa, Kenichi Yoshida, Takashi Ohtsuka, Yuichiro Okuyama, Takeshi Oohashi, Hajime Kuwajima
  • Patent number: 11538746
    Abstract: A system in package includes a memory-die stack in memory module that is stacked vertically with respect to a processor die. Each memory die in the memory-die stack includes a vertical bond wire that emerges from a matrix for connection. Some configurations include the vertical bond wire emerging orthogonally beginning from a bond-wire pad. The matrix encloses the memory-die stack, the spacer, and at least a portion of the processor die.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: December 27, 2022
    Assignee: Intel Corporation
    Inventors: Zhicheng Ding, Yong She, Bin Liu, Aiping Tan, Li Deng
  • Patent number: 11532597
    Abstract: The present disclosure relates to a radio frequency device that includes a transfer device die and a multilayer redistribution structure underneath the transfer device die. The transfer device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion and a transfer substrate. The FEOL portion includes isolation sections and an active layer surrounded by the isolation sections. A top surface of the device region is planarized. The transfer substrate including a porous silicon (PSi) region resides over the top surface of the device region. Herein, the PSi region has a porosity between 1% and 80%. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the transfer device die.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: December 20, 2022
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Michael Carroll
  • Patent number: 11527415
    Abstract: There is provided a method of manufacturing a multilayer wiring board including: alternately stacking wiring layers and insulating layers; stacking a reinforcing sheet having openings on one surface of the resulting multilayer laminate with a soluble adhesive layer therebetween; contacting or infiltrating the soluble adhesive layer with a liquid capable of dissolving the soluble adhesive layer through the openings to thereby dissolve or soften the soluble adhesive layer; and releasing the reinforcing sheet from the multilayer laminate at the position of the soluble adhesive layer. This method enables the multilayer wiring layer to be reinforced so as to generate no large local warpage, thereby improving the reliable connection in the multilayer wiring layer and the flatness (coplanarity) on the surface of the multilayer wiring layer. The reinforcing sheet having finished its role can be released in a significantly short time, while minimizing the stress applied to the multilayer laminate.
    Type: Grant
    Filed: November 24, 2017
    Date of Patent: December 13, 2022
    Assignee: MITSUI MINING & SMELTING CO., LTD.
    Inventors: Yoshinori Matsuura, Tetsuro Sato, Takenori Yanai, Toshimi Nakamura
  • Patent number: 11527694
    Abstract: A thermoelectric element to convert thermal energy into electrical energy includes a first electrode part, a second electrode part having a different work function than the first electrode part and arranged at a distance from the first electrode part, on a same surface of a substrate as the first electrode part, and a middle part provided between the first electrode part and the second electrode part.
    Type: Grant
    Filed: February 18, 2019
    Date of Patent: December 13, 2022
    Assignees: GCE INSTITUTE INC., NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Hiroshi Goto, Minoru Sakata, Ryutaro Maeda, Jian Lu