Stacked Arrangement Patents (Class 257/686)
  • Patent number: 11509234
    Abstract: A power conversion apparatus has a positive electrode bus bar and a negative electrode bus bar. The power conversion apparatus has a first semiconductor module incorporating an upper-arm switching element and including a positive electrode terminal and a second semiconductor module incorporating a lower-arm switching element and including a negative electrode terminal. The first semiconductor module and the second semiconductor module are placed such that the positive electrode terminal and the negative electrode terminal face each other in a direction orthogonal to a protruding direction. The positive electrode bus bar and the negative electrode bus bar respectively have coexisting parts placed together between the positive electrode terminal and the negative electrode terminal as seen in the protruding direction of power terminals. The coexisting parts are at least partially placed in a space between the positive electrode terminal and the negative electrode terminal.
    Type: Grant
    Filed: February 5, 2020
    Date of Patent: November 22, 2022
    Assignee: DENSO CORPORATION
    Inventors: Tetsuya Matsuoka, Ryota Tanabe, Yuu Yamahira, Kazuma Fukushima, Kosuke Kamiya
  • Patent number: 11502062
    Abstract: In an embodiment, a device includes: a bottom integrated circuit die having a first front side and a first back side; a top integrated circuit die having a second front side and a second back side, the second back side being bonded to the first front side, the top integrated circuit die being free from through substrate vias (TSVs); a dielectric layer surrounding the top integrated circuit die, the dielectric layer being disposed on the first front side, the dielectric layer and the bottom integrated circuit die being laterally coterminous; and a through via extending through the dielectric layer, the through via being electrically coupled to the bottom integrated circuit die, surfaces of the through via, the dielectric layer, and the top integrated circuit die being planar.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: November 15, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Fa Chen, Tzuan-Horng Liu, Chao-Wen Shih, Sung-Feng Yeh, Nien-Fang Wu
  • Patent number: 11495531
    Abstract: A semiconductor device package and a method for manufacturing the semiconductor device package are provided. The semiconductor device package includes a carrier, an electronic component, a first encapsulant and a conductive via. The carrier has a first surface and a second surface opposite to the first surface. The semiconductor device is mounted at the second surface of the carrier. The first encapsulant encapsulates the first surface of the carrier and has a surface facing away from the first surface of the carrier. The conductive via extends from the surface of the first encapsulant into the carrier.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: November 8, 2022
    Assignee: ADVANCED SEMICONDUCTORE ENGINEERING KOREA, INC.
    Inventors: Seokbong Kim, Eunshim Lee
  • Patent number: 11495575
    Abstract: The present disclosure relates to a radio frequency device that includes a transfer device die and a multilayer redistribution structure underneath the transfer device die. The transfer device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion and a transfer substrate. The FEOL portion includes isolation sections and an active layer surrounded by the isolation sections. A top surface of the device region is planarized. The transfer substrate including a porous silicon (PSi) region resides over the top surface of the device region. Herein, the PSi region has a porosity between 1% and 80%. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the transfer device die.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: November 8, 2022
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Michael Carroll
  • Patent number: 11495544
    Abstract: Semiconductor devices and methods of manufacture are provided. In embodiments the semiconductor device includes a substrate, a first interposer bonded to the substrate, a second interposer bonded to the substrate, a bridge component electrically connecting the first interposer to the second interposer, two or more first dies bonded to the first interposer; and two or more second dies bonded to the second interposer.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: November 8, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shang-Yun Hou, Hsien-Pin Hu
  • Patent number: 11469213
    Abstract: In accordance with disclosed embodiments, there are provided methods, systems, and apparatuses for implementing reduced height semiconductor packages for mobile electronics. For instance, there is disclosed in accordance with one embodiment a stacked die package having therein a bottom functional silicon die; a recess formed within the bottom functional silicon die by a thinning etch partially reducing a vertical height of the bottom functional silicon die at the recess; and a top component positioned at least partially within the recess formed within the bottom functional silicon die. Other related embodiments are disclosed.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: October 11, 2022
    Assignee: Intel Corporation
    Inventors: Georg Seidemann, Thomas Wagner, Klaus Reingruber, Bernd Waidhas, Andreas Wolter
  • Patent number: 11456268
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first semiconductor die, an insulating encapsulation laterally encapsulating the first semiconductor die, and a redistribution structure disposed on the first semiconductor die and the insulating encapsulation. The first semiconductor die includes a first contact region and a first non-contact region in proximity to the first contact region. The first semiconductor die includes a first electrical connector disposed on the first contact region and a first dummy conductor disposed on the first non-contact region, and the first electrical connector is electrically connected to a first integrated circuit (IC) component in the first semiconductor die. The first electrical connector is electrically connected to the redistribution structure, and the first dummy conductor is electrically insulated from the first IC component in the first semiconductor die and the redistribution structure.
    Type: Grant
    Filed: January 21, 2019
    Date of Patent: September 27, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jung-Hua Chang, Chin-Fu Kao
  • Patent number: 11456257
    Abstract: A method includes forming a redistribution structure over a carrier, the redistribution structure having conductive features on a surface of the redistribution structure distal the carrier; forming a conductive pillar over the surface of the redistribution structure; attaching a die to the surface of the redistribution structure adjacent to the conductive pillar, where die connectors of the die are electrically coupled to the conductive features of the redistribution structure; and attaching a pre-made substrate to the conductive pillar through a conductive joint, where the conductive joint is on the conductive pillar and comprises a different material from the conductive pillar, where the conductive joint and the conductive pillar electrically couple the redistribution structure to the pre-made substrate.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: September 27, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shin-Puu Jeng, Shuo-Mao Chen, Hsien-Wen Liu, Po-Yao Chuang, Feng-Cheng Hsu, Po-Yao Lin
  • Patent number: 11456282
    Abstract: The present disclosure relates to a radio frequency device that includes a transfer device die and a multilayer redistribution structure underneath the transfer device die. The transfer device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion and a transfer substrate. The FEOL portion includes isolation sections and an active layer surrounded by the isolation sections. A top surface of the device region is planarized. The transfer substrate including a porous silicon (PSi) region resides over the top surface of the device region. Herein, the PSi region has a porosity between 1% and 80%. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the transfer device die.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: September 27, 2022
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Michael Carroll
  • Patent number: 11456289
    Abstract: Semiconductor device assemblies can include a substrate having a substrate contact. The assemblies can include a first semiconductor device and a second semiconductor device arranged in a face-to-face configuration. The assemblies can include a fan-out porch on the substrate at a lateral side of the first semiconductor device and including a wirebond contact, the wirebond contact being electrically coupled to the first semiconductor device. The assemblies can include a wirebond operably coupling the wirebond contact to the substrate contact. The assemblies can include a pillar or bump operably coupling the active side of the first semiconductor device to the active side of the second semiconductor device. In some embodiments, the wirebond contact is operably couple to the active side of the first semiconductor device.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: September 27, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Jong Sik Paek, Yeongbeom Ko
  • Patent number: 11450588
    Abstract: A method for forming a chip package structure is provided. The method includes disposing a chip over a substrate. The method includes forming a heat-spreading wall structure over the substrate. The heat-spreading wall structure is adjacent to the chip, and there is a first gap between the chip and the heat-spreading wall structure. The method includes forming a first heat conductive layer in the first gap. The method includes forming a second heat conductive layer over the chip. The method includes disposing a heat-spreading lid over the substrate to cover the heat-spreading wall structure, the first heat conductive layer, the second heat conductive layer, and the chip. The heat-spreading lid is bonded to the substrate, the heat-spreading wall structure, the first heat conductive layer, and the second heat conductive layer.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: September 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shin Chi, Chien-Hao Hsu, Kuo-Chin Chang, Cheng-Nan Lin, Mirng-Ji Lii
  • Patent number: 11444007
    Abstract: A semiconductor device includes a chip carrier, a first semiconductor chip arranged on the chip carrier, the first semiconductor chip being located in a first electrical potential domain when the semiconductor device is operated, a second semiconductor chip arranged on the chip carrier, the second semiconductor chip being located in a second electrical potential domain different from the first electrical potential domain when the semiconductor device is operated, and an electrically insulating structure arranged between the first semiconductor chip and the second semiconductor chip, which is designed to galvanically isolate the first semiconductor chip and the second semiconductor chip from each other.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: September 13, 2022
    Inventor: Rainer Markus Schaller
  • Patent number: 11437327
    Abstract: The present disclosure provides a packaged device that includes a first dielectric layer; a second dielectric layer, formed over the first dielectric layer, that includes a device substrate and a via extending from the first dielectric layer and through the second dielectric layer; and a third dielectric layer, formed over the second dielectric layer, that includes a conductive pillar extending through the third dielectric layer, wherein the conductive pillar is electrically coupled to the via of the second dielectric layer.
    Type: Grant
    Filed: December 15, 2020
    Date of Patent: September 6, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Han-Ping Pu, Hsiao-Wen Lee
  • Patent number: 11437293
    Abstract: A semiconductor package is disclosed. The disclosed semiconductor package includes a substrate having bonding pads at an upper surface thereof, a lower semiconductor chip, at least one upper semiconductor chip disposed on the lower semiconductor chip, and a dam structure having a closed loop shape surrounding the lower semiconductor chip. The dam structure includes narrow and wide dams disposed between the lower semiconductor chip and the bonding pads. The wide dam has a greater inner width than the narrow dam. The semiconductor packages further includes an underfill disposed inside the dam structure and being filled between the substrate and the lower semiconductor chip.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: September 6, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dongho Kim, Jongbo Shim, Hwanpil Park, Jangwoo Lee
  • Patent number: 11430767
    Abstract: A semiconductor package may include: a chip stack including a plurality of semiconductor chips stacked in a vertical direction; vertical interconnectors, each having first ends that are connected to the plurality of semiconductor chips, respectively, and extending in the vertical direction; a molding layer covering the chip stack and the vertical interconnectors while exposing second ends of the vertical interconnectors; landing pads formed over one surface of the molding layer to be in contact with the second ends of the vertical interconnectors, respectively, wherein the landing pads are conductive and overlap the first ends of the vertical interconnectors, respectively; and a package redistribution layer electrically connected to the vertical interconnectors through the landing pads.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: August 30, 2022
    Assignee: SK hynix Inc.
    Inventors: Chaesung Lee, Jonghoon Kim, Bokkyu Choi, Kijun Sung
  • Patent number: 11428250
    Abstract: An electronic device includes a chassis housing one or more electronic components, a module configured to be inserted into a channel defined by the chassis, and an alignment mechanism disposed in the channel. The alignment mechanism has a body portion that defines an aperture. When the module is initially inserted into the channel in a first orientation, a first portion of the module passes over the aperture and compresses the body portion of the alignment mechanism along a first axis, to allow the module to be fully inserted into the channel. When the module is initially inserted into the channel in a second orientation, a second portion of the module passes through the aperture and does not compress the body portion of the alignment mechanism along the first axis, to prevent the module from being fully inserted into the channel.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: August 30, 2022
    Assignee: QUANTA COMPUTER INC.
    Inventors: Yaw-Tzorng Tsorng, Hung-Wei Chen, Chun Chang, Ming-Lung Wang
  • Patent number: 11424212
    Abstract: A semiconductor package structure includes a conductive structure, at least one semiconductor element, an encapsulant, a redistribution structure and a plurality of bonding wires. The semiconductor element is disposed on and electrically connected to the conductive structure. The encapsulant is disposed on the conductive structure to cover the semiconductor element. The redistribution structure is disposed on the encapsulant, and includes a redistribution layer. The bonding wires electrically connect the redistribution structure and the conductive structure.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: August 23, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chien-Wei Chang, Shang-Wei Yeh, Chung-Hsi Wu, Min Lung Huang
  • Patent number: 11417632
    Abstract: The present disclosure relates to a radio frequency device that includes a transfer device die and a multilayer redistribution structure underneath the transfer device die. The transfer device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion and a transfer substrate. The FEOL portion includes isolation sections and an active layer surrounded by the isolation sections. A top surface of the device region is planarized. The transfer substrate including a porous silicon (PSi) region resides over the top surface of the device region. Herein, the PSi region has a porosity between 1% and 80%. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the transfer device die.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: August 16, 2022
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Michael Carroll
  • Patent number: 11410915
    Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a carrier, a first encapsulant, and an interposer. The first encapsulant is on the carrier and defines a cavity. The interposer is disposed between the first encapsulant and the cavity. The first encapsulant covers a portion of the interposer.
    Type: Grant
    Filed: November 3, 2020
    Date of Patent: August 9, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yu-Che Huang, Chang Chin Tsai
  • Patent number: 11410932
    Abstract: A semiconductor device includes a stacked structure, first conductive terminals and second conductive terminals. The stacked structure includes a first semiconductor component having a first area and a second semiconductor component stacked on the first semiconductor component and having a second area smaller than the first area, wherein an extending direction of the first area and an extending direction of the second area are perpendicular to a stacking direction of the first semiconductor component and the second semiconductor component. The first conductive terminals are located on the stacked structure, electrically coupled to the first semiconductor component and aside of the second semiconductor component. The second conductive terminals are located on the stacked structure and electrically coupled to the second semiconductor component.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: August 9, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Hung Tseng, Cheng-Chieh Hsieh, Hao-Yi Tsai
  • Patent number: 11399434
    Abstract: Embodiments disclosed herein include modular electronics packages and methods of forming such packages. In an embodiment, the electronics package comprises a first connector module having a notch on a first end and a plurality of surface mount technology (SMT) pads on a second end. In an embodiment, the electronics package further comprises a second connector module having a keyed connector on a first end and a plurality of SMT pads on a second end. In an embodiment, the electronics package further comprises a system in package (SIP) module between the first connector module and the second connector module, the component module electrically and mechanically coupled to the SMT pads of the first connector and the SMT pads of the second connector.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: July 26, 2022
    Inventors: Florence Pon, Tyler Leuten, Maria Angela Damille Ramiso
  • Patent number: 11398408
    Abstract: A semiconductor substrate and a method of manufacturing the same are provided. The semiconductor substrate includes a dielectric layer, at least one first conductive trace, and a conductive via. The dielectric layer has a first dielectric surface and a second dielectric surface opposite to the first dielectric surface. The first conductive trace is disposed adjacent to the first dielectric surface of the dielectric layer. The conductive via is disposed adjacent to the second dielectric surface of the dielectric layer and connected to the first conductive trace, where the conductive via and the first conductive trace are connected at a first interface leveled with about a half thickness of the dielectric layer.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: July 26, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen-Long Lu
  • Patent number: 11398457
    Abstract: A device is disclosed which includes at least one integrated circuit die, at least a portion of which is positioned in a body of encapsulant material, and at least one conductive via extending through the body of encapsulant material.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: July 26, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Tongbi Jiang, Yong Poo Chia
  • Patent number: 11393808
    Abstract: Examples of semiconductor packages with stacked RDLs described herein may include, for example, a first RDL comprising multiple RDL layers coupled to a second RDL comprising multiple RDL layers using copper pillars and an underfill in place of a conventional substrate. The examples herein may use RDLs instead of substrates to achieve smaller design feature size (x, y dimensions reduction), thinner copper layers and less metal usage (z dimension reduction), flexibility to attach semiconductor dies and surface mount devices (SMD) on either side of the package, and less number of built-up RDL layers.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: July 19, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Aniket Patil, Hong Bok We, David Fraser Rae
  • Patent number: 11387164
    Abstract: A semiconductor device includes a package and a cooling cover. The package includes a first die having an active surface and a rear surface opposite to the active surface. The rear surface has a cooling region and a peripheral region enclosing the cooling region. The first die includes micro-trenches located in the cooling region of the rear surface. The cooling cover is stacked on the first die. The cooling cover includes a fluid inlet port and a fluid outlet port located over the cooling region and communicated with the micro-trenches.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: July 12, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Jung Wu, Chih-Hang Tung, Tung-Liang Shao, Sheng-Tsung Hsiao, Jen-Yu Wang
  • Patent number: 11387186
    Abstract: A system integrating a fan-out package, including a first semiconductor die, with a second semiconductor die. In some embodiments the fan-out package includes the first semiconductor die, a mold compound, covering the first semiconductor die on at least two sides, and an electrical contact, on a lower surface of the first semiconductor die. The fan-out package may have a rabbet along a portion of a lower edge of the fan-out package.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: July 12, 2022
    Assignee: Rockley Photonics Limited
    Inventors: Seungjae Lee, Brett Sawyer, Chia-Te Chou
  • Patent number: 11387198
    Abstract: Techniques and mechanisms for providing an inductor with an integrated circuit (IC) die. In an embodiment, the IC die comprises integrated circuitry and one or more first metallization layers. The IC die is configured to couple to a circuit device including one or more second metallization layers, where such coupling results in the formation of an inductor which is coupled to the integrated circuitry. One or more loop structures of the inductor each span both some or all of the one or more first metallization layers and some or all of the one or more second metallization layers. In another embodiment, the IC die or the circuit device includes a ferromagnetic material to concentrate a magnetic flux which is provided with the inductor.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: July 12, 2022
    Assignee: Intel Corporation
    Inventors: Wilfred Gomes, Mark Bohr, Doug Ingerly, Rajesh Kumar, Harish Krishnamurthy, Nachiket Venkappayya Desai
  • Patent number: 11387222
    Abstract: In an embodiment, a structure includes: a processor device including logic devices; a first memory device directly face-to-face bonded to the processor device by metal-to-metal bonds and by dielectric-to-dielectric bonds; a first dielectric layer laterally surrounding the first memory device; a redistribution structure over the first dielectric layer and the first memory device, the redistribution structure including metallization patterns; and first conductive vias extending through the first dielectric layer, the first conductive vias connecting the metallization patterns of the redistribution structure to the processor device.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: July 12, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Hua Yu, Wei Ling Chang, Chuei-Tang Wang, Chieh-Yen Chen
  • Patent number: 11387215
    Abstract: The present disclosure relates to a radio frequency device that includes a transfer device die and a multilayer redistribution structure underneath the transfer device die. The transfer device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion and a transfer substrate. The FEOL portion includes isolation sections and an active layer surrounded by the isolation sections. A top surface of the device region is planarized. The transfer substrate including a porous silicon (PSi) region resides over the top surface of the device region. Herein, the PSi region has a porosity between 1% and 80%. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the transfer device die.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: July 12, 2022
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Michael Carroll
  • Patent number: 11380632
    Abstract: A semiconductor device includes a semiconductor substrate and an interconnect structure over the semiconductor substrate. The interconnect structure includes a magnetic core and a conductive coil winding around the magnetic core and electrically insulated from the magnetic core. The conductive coil includes horizontally-extending conductive lines and vertically-extending conductive vias electrically connecting the conductive lines.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: July 5, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Wen-Shiang Liao, Huan-Neng Chen
  • Patent number: 11380606
    Abstract: A semiconductor device includes a semiconductor substrate having an active surface on which semiconductor elements are provided. An interlayer insulating film is provided on the semiconductor substrate. A first via structure passes through the semiconductor substrate. The first via structure has a first diameter. A second via structure passes through the semiconductor substrate. The second via structure has a second diameter that is greater than the first diameter. The first via structure has a step portion that is in contact with the interlayer insulating film.
    Type: Grant
    Filed: July 18, 2020
    Date of Patent: July 5, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Eunji Kim, Sungdong Cho, Kwangwuk Park, Sangjun Park, Daesuk Lee, Hakseung Lee
  • Patent number: 11380620
    Abstract: A semiconductor package and methods of forming the same are disclosed. In an embodiment, a package includes a substrate; a first die disposed within the substrate; a redistribution structure over the substrate and the first die; and an encapsulated device over the redistribution structure, the redistribution structure coupling the first die to the encapsulated device.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: July 5, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiun Yi Wu, Chen-Hua Yu
  • Patent number: 11380653
    Abstract: A die stack structure including a first die, an encapsulant, a redistribution layer and a second die is provided. The encapsulant laterally encapsulates the first die. The redistribution layer is disposed below the encapsulant, and electrically connected with the first die. The second die is disposed between the redistribution layer and the first die, wherein the first and second dies are electrically connected with each other, the second die comprises a body portion having a first side surface, a second side surface and a curved side surface therebetween, and the curved side surface connects the first side surface and the second side surface.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: July 5, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Hsien-Wei Chen, Ming-Fa Chen, Sung-Feng Yeh, Tzuan-Horng Liu
  • Patent number: 11373959
    Abstract: Shielding for flip chip devices. In some embodiments, a shielded assembly can include a substrate and a flip chip die having a front side and a back side, with the including an integrated circuit implemented on the front side, and the front side of the flip chip die being mounted to the substrate. The shielded assembly can further include a shielding component implemented over the back side of the flip chip die to provide electromagnetic shielding between a first region within or on the flip chip die and a second region away from the flip chip die.
    Type: Grant
    Filed: April 18, 2020
    Date of Patent: June 28, 2022
    Assignee: Skyworks Solutions, Inc.
    Inventor: Pietro Natale Alessandro Chyurlia
  • Patent number: 11373933
    Abstract: A semiconductor package includes; a lower semiconductor chip mounted on a lower package substrate, an interposer on the lower package substrate and including an opening, connection terminals spaced apart from and at least partially surrounding the lower semiconductor chip and extending between the lower package substrate and the interposer, a first molding member including a first material and covering at least a portion of a top surface of the lower semiconductor chip and at least portions of edge surfaces of the lower semiconductor chip, wherein the first molding member includes a protrusion that extends upward from the opening to cover at least portions of a top surface of the interposer proximate to the opening, and a second molding member including a second material, at least partially surrounding the first molding member, and covering side surfaces of the first molding member and the connection terminals, wherein the first material has thermal conductivity greater than the second material.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: June 28, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Heeseok Lee, Yunhyeok Im
  • Patent number: 11367709
    Abstract: A semiconductor-chip stack package includes a plurality of semiconductor chips disposed in a stack arrangement and at least one connecting substrate which connects the semiconductor chips. The semiconductor chips include a chip terminal face on a chip edge extending at least partially as a side terminal face in a side surface of the semiconductor chip. The side surfaces of the semiconductor chips provided with the side terminal face are arranged in a shared side surface plane S of the semiconductor-chip stack arrangement. The connecting substrate is arranged with a contact surface parallel to the side surface plane S of the semiconductor chips. Substrate terminal faces are formed on the contact surface for connecting a connection conductor structure formed in the connecting substrate and which are connected to the side terminal faces via a connecting material in a connection plane V1 parallel to the contact surface.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: June 21, 2022
    Assignee: PAC TECH—PACKAGING TECHNOLOGIES GMBH
    Inventors: Matthias Fettke, Andrej Kolbasow
  • Patent number: 11367707
    Abstract: Embodiments herein may relate to a semiconductor package or a semiconductor package structure. The package or package structure may include an interposer with a memory coupled to one side and a processing unit coupled to the other side. A third chip may be coupled with the interposer adjacent to the processing unit. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: June 21, 2022
    Assignee: Intel Corporation
    Inventors: Shawna M. Liff, Adel A. Elsherbini, Johanna M. Swan, Gerald S. Pasdast
  • Patent number: 11367714
    Abstract: A semiconductor package device may include a first package substrate, a first semiconductor chip on the first package substrate, an interposer on the first semiconductor chip, a warpage prevention member on the interposer, a molding member on the interposer and the first package substrate, and a second package substrate on the molding member. At least a portion of a top surface of the molding member may be spaced apart from a bottom surface of the second package substrate.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: June 21, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jangwoo Lee, Jongbo Shim, Ji Hwang Kim, Yungcheol Kong, Youngbae Kim, Taehwan Kim, Hyunglak Ma
  • Patent number: 11367710
    Abstract: A multi-chip package structure includes outer leads, a first chip and a second chip. The outer leads are disposed on four sides of a chip bonding area of a package carrier thereof, respectively. The first chip is fixed on the chip bonding area and includes a core and a seal ring. Input/output units, and first bonding pads are disposed, in an outward order, on the sides of the core. Each first bonding pad is electrically connected to a corresponding outer lead through a first wire. Dummy pads are disposed between the input/output units and the at least one side of the core. The second chip is stacked on the core and includes second bonding pads connected to the corresponding outer leads through second wires and dummy pads, so as to prevent from short circuit caused by soldering overlap and contact between the wires.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: June 21, 2022
    Assignee: EGALAX_EMPIA TECHNOLOGY INC.
    Inventor: Po-Chuan Lin
  • Patent number: 11362027
    Abstract: In one example, a semiconductor device includes a substrate with a top side, a bottom side, and a conductive structure. A first electronic component includes a first side, a second side, and first component terminals adjacent to the first side. The first component terminals face the substrate bottom side and are connected to the conductive structure. A second electronic component comprises a first side, a second side, and second component terminals adjacent to the second electronic component first side. The second electronic component second side is connected to the first electronic component second side so that the first component terminals and the second component terminals face opposite directions. Substrate interconnects are connected to the conductive structure, and a bottom encapsulant covers the substrate bottom side, the first electronic component, the second electronic component, and the substrate interconnects.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: June 14, 2022
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Roger D. St. Amand, Louis W. Nicholls
  • Patent number: 11361140
    Abstract: Automated routing of signal nets for interposer designs. Signal nets are defined by their endpoints (bumps). The nets and their corresponding bumps are assigned to bump groups, based on the relative locations of the bumps and also based on length-matching constraints for the nets. Some of the bump groups may be “clones,” where the routing for one bump group may also be applied to its clone. In order for two bump groups to be clones, the bumps in the two bump groups must have a same relative position (i.e., same bump pattern), and the nets in the two bump groups must be subject to the same length-matching constraint. The routing through the interposer for one of the clones is determined, and that routing is then replicated for the other clones.
    Type: Grant
    Filed: November 10, 2020
    Date of Patent: June 14, 2022
    Assignee: Synopsys, Inc.
    Inventors: Jitendra Kumar Gupta, Ksenia Roze, Xun Liu, Paul Chang, Lan Luo
  • Patent number: 11355449
    Abstract: An electronic device structure having a shielding structure includes a substrate with an electronic component electrically connected to the substrate. The shielding structure includes conductive spaced-apart pillar structures that have proximate ends connected to the substrate and distal ends spaced apart from the substrate, and that are laterally spaced apart from the first electronic component. In one embodiment, the conductive pillar structures are conductive wires attached at one end to the substrate with an opposing end extending away from the substrate so that the conductive wires are provided generally perpendicular to the substrate. A package body encapsulates the electronic component and the conductive spaced-apart pillar structures. In one embodiment, the shielding structure further includes a shielding layer disposed adjacent the package body, which is electrically connected to the conductive spaced-apart pillar structures. In one embodiment, the electrical connection is made through the package.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: June 7, 2022
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Young Woo Lee, Jae Ung Lee, Byong Jin Kim, EunNaRa Cho, Ji Hoon Oh, Young Seok Kim, Jin Young Khim, Tae Kyeong Hwang, Jin Seong Kim, Gi Jung Kim
  • Patent number: 11355450
    Abstract: A semiconductor package includes a carrier substrate having a top surface; a semiconductor die mounted on the top surface; a plurality of first bonding wires connecting the semiconductor die to the carrier substrate; an insulating material encapsulating the plurality of first bonding wires; a component having a metal layer mounted on the insulating material; a plurality of second bonding wires connecting the metal layer of the component to the carrier substrate; and a molding compound covering the top surface of the carrier substrate and encapsulating the semiconductor die, the component, the plurality of first bonding wires, the plurality of second bonding wires, and the insulating material. The metal layer and the plurality of second bonding wires constitute an electromagnetic interference (EMI) shielding structure.
    Type: Grant
    Filed: July 15, 2020
    Date of Patent: June 7, 2022
    Assignee: MEDIATEK INC.
    Inventor: Shiann-Tsong Tsai
  • Patent number: 11355476
    Abstract: A multi-chip package structure includes outer leads, a first chip and a second chip. The outer leads are disposed on a side of a chip bonding area of a package carrier thereof. The first chip is fixed on the chip bonding area and includes a core and a seal ring. Input/output units, and first bonding pads are disposed, in an outward order, on at a side of the core. Each first bonding pad is electrically connected to a corresponding outer lead through a first wire. Dummy pads are disposed between the input/output units and adjacent first bonding pads on the side of the core. The second chip is stacked on the core and includes second bonding pads connected to the corresponding outer leads through second wires and dummy pads, so as to prevent from short circuit caused by soldering overlap and contact between the wires.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: June 7, 2022
    Assignee: EGALAX_EMPIA TECHNOLOGY INC.
    Inventor: Po-Chuan Lin
  • Patent number: 11355454
    Abstract: A package structure includes a redistribution circuit structure, a wiring substrate, a semiconductor device, an insulating encapsulation, and a reinforcement structure. The redistribution circuit structure has a first surface and a second surface opposite to the first surface. The wiring substrate is disposed on the first surface of the redistribution circuit structure. The semiconductor device is disposed on the second surface of the redistribution circuit structure. The insulating encapsulation laterally encapsulates the wiring substrate. The reinforcement structure is directly in contact with the insulating encapsulation.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: June 7, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Fu Tsai, Shih-Ting Lin, Szu-Wei Lu, Chen-Hsuan Tsai, I-Ting Huang
  • Patent number: 11348893
    Abstract: A semiconductor package includes a first semiconductor die, a first substrate, a second semiconductor die, and a second substrate. The first substrate is disposed on the first semiconductor die and includes a plurality of first metal line layers vertically spaced apart from each other, and each of the first metal line layers is electrically connected to one of the followings: a ground source and a plurality of power sources of different types. The second semiconductor die is disposed on the first substrate. The second substrate is disposed on the second semiconductor die and includes a plurality of second metal line layers vertically spaced apart from each other, and each of the second metal line layers is electrically connected to one of the followings: the ground source and the power sources of different types.
    Type: Grant
    Filed: May 13, 2020
    Date of Patent: May 31, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Wu-Der Yang
  • Patent number: 11348899
    Abstract: The present disclosure relates to a radio frequency device that includes a transfer device die and a multilayer redistribution structure underneath the transfer device die. The transfer device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion and a transfer substrate. The FEOL portion includes isolation sections and an active layer surrounded by the isolation sections. A top surface of the device region is planarized. The transfer substrate including a porous silicon (PSi) region resides over the top surface of the device region. Herein, the PSi region has a porosity between 1% and 80%. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the transfer device die.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: May 31, 2022
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Michael Carroll
  • Patent number: 11348831
    Abstract: A semiconductor assembly manufacturing method includes: providing a substrate including a first conductive circuit; disposing a first electronic component on a side of the substrate; forming a first plastic seal layer covering the substrate and the first electronic component; setting up a plurality of grooves in the first plastic seal layer, the groove exposes at least a portion of the first conductive circuit of the substrate; and filling a conductive material in each of the grooves by vacuum printing so as to form a second conductive circuit electrically connected to the first conductive circuit of the substrate, and a second electronic component pad position thereof in the first plastic seal layer.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: May 31, 2022
    Assignee: UNIVERSAL GLOBAL TECHNOLOGY (SHANGHAI) CO., LTD
    Inventors: Chia-Cheng Liu, Xiao-Lei Zhou
  • Patent number: 11348911
    Abstract: An electronic device may include a first die that may include a first set of die contacts. The electronic device may include a second die that may include a second set of die contacts. The electronic device may include a bridge interconnect that may include a first set of bridge contacts and may include a second set of bridge contacts. The first set of bridge contacts may be directly coupled to the first set of die contacts (e.g., with an interconnecting material, such as solder). The second set of bridge contacts may be directly coupled to the second set of die contacts (e.g., with solder). The bridge interconnect may help facilitate electrical communication between the first die and the second die.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: May 31, 2022
    Assignee: Intel Corporation
    Inventors: Robert L. Sankman, Sairam Agraharam, Shengquan Ou, Thomas J De Bonis, Todd Spencer, Yang Sun, Guotao Wang
  • Patent number: 11347342
    Abstract: A substrate conductive bonding structure includes a lower substrate including a connection pad exposed to outside the lower substrate, an upper substrate including a transfer pad overlapping the connection pad, exposed to outside the upper substrate and including an upper surface, and a slit defined in the transfer pad, overlapping the connection pad and open at the upper surface of the transfer pad, the slit including an extending portion extending along a first direction and having a first slit width along a second direction crossing the first direction, and an expansion portion connected to the extending portion and having a second slit width along the second direction which is larger than the first slit width, and a solder contacting the upper surface of the connection pad, extending to the upper surface of the transfer pad and into the slit.
    Type: Grant
    Filed: July 2, 2021
    Date of Patent: May 31, 2022
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Seong-Sik Park, Gyutae Kim, San Park, Sung Soo Lee