Abstract: A wiring substrate includes an insulating substrate being square in plan view, the insulating substrate including one main surface with a recess, and the other main surface opposite to the one main surface, and external electrodes located on the other main surface of the insulating substrate. The external electrodes are arranged in a row in a peripheral section of the insulating substrate. In plan view, an area of one of the external electrodes located at a center of each side of the insulating substrate is larger than an area of one of the external electrodes located at an edge of the each side.

Abstract: Methods and apparatus relating to processor and chipset continuity testing of package interconnect for functional safety applications are described. In an embodiment, voltage divider logic circuitry divides a reference voltage. Controller logic circuitry compares a divided voltage value from a node of the voltage divider logic circuitry and a threshold voltage value. A first end of the voltage divider logic circuitry is coupled to receive the reference voltage and a second end of the voltage divider logic circuitry is coupled to a Non-Critical-To-Function (NCTF) solder ball. The controller logic circuitry generates an error signal in response to a mismatch between the divided voltage value and the threshold voltage value. Other embodiments are also disclosed and claimed.

Abstract: An assembly includes a wafer having a top wafer surface and a wafer circumference. The assembly further includes a device arrangement structure. The device arrangement structure includes a first surface having a perimeter, the perimeter being encircled by the wafer circumference in a plan view; and an array of devices, each device of the array of devices having an electrical contact on the first surface. The assembly further includes an adhesive element configured to affix the device arrangement structure in a stationary position relative to the wafer, wherein the adhesive element includes a tape layer having an adhesive surface attached to the top surface of the device arrangement structure and attached to a surface of the wafer.

Abstract: Various embodiments may provide a semiconductor package. The semiconductor package may include a routing layer including a plurality of first layer contact elements on a first side and a plurality of second layer contact elements on a second side opposite the first side, and a first semiconductor die including a plurality of first electrical die contact elements coupled to the plurality of first layer contact elements. The semiconductor package may further include a second semiconductor die including a plurality of second electrical die contact elements coupled to the plurality of second layer contact elements, and a mold structure covering the second semiconductor die. A first pitch between neighbouring first electrical die contact elements may be greater than a second pitch between neighbouring second electrical die contact elements.

Abstract: A component carrier which includes a stack having at least one electrically conductive layer structure and/or at least one electrically insulating layer structure, a deformed layer connected to and/or forming part of the stack and being bent so as to define accommodation volumes for components, and the components, wherein each of the components is accommodated in a respective one of the accommodation volumes.

Abstract: A method of three-dimensionally integrating elements such as singulated die or wafers and an integrated structure having connected elements such as singulated dies or wafers. Either or both of the die and wafer may have semiconductor devices formed therein. A first element having a first contact structure is bonded to a second element having a second contact structure. First and second contact structures can be exposed at bonding and electrically interconnected as a result of the bonding. A via may be etched and filled after bonding to expose and form an electrical interconnect to interconnected first and second contact structures and provide electrical access to this interconnect from a surface.

Abstract: Direct-bonded optoelectronic interconnects for high-density integrated photonics are provided. A combined electrical and optical interconnect enables direct-bonding of fully-processed optoelectronic dies or wafers to wafers with optoelectronic driver circuitry. The photonic devices may be III-V semiconductor devices. Direct-bonding to silicon or silicon-on-insulator (SOI) wafers enables the integration of photonics with high-density CMOS and other microelectronics packages. Each bonding surface has an optical window to be coupled by direct-bonding. Coplanar electrical contacts lie to the outside, or may circumscribe the respective optical windows and are also direct-bonded across the interface using metal-to-metal direct-bonding, without interfering with the optical windows. Direct hybrid bonding can accomplish both optical and electrical bonding in one overall operation, to mass-produce mLED video displays.

Abstract: An embodiment is a method including forming a first package. The forming the first package includes forming a through via adjacent a first die, at least laterally encapsulating the first die and the through via with an encapsulant, and forming a first redistribution structure over the first die, the through via, and the encapsulant. The forming the first redistribution structure including forming a first via on the through via, and forming a first metallization pattern on the first via, at least one sidewall of the first metallization pattern directly overlying the through via.

Abstract: A 3D semiconductor device, the device including: a first die comprising first transistors and a first interconnect; and a second die comprising second transistors and a second interconnect, wherein said first die is overlaid by said second die, wherein said first die has a first die area and said second die has a second die area, wherein said first die area is at least 10% larger than said second die area, wherein said second die is pretested, wherein said second die is bonded to said first die, wherein said bonded comprises metal to metal bonding, wherein said first die comprises at least two first alignment marks positioned close to a first die edge of said first die, and wherein said second die comprises at least two second alignment marks positioned close to a second die edge of said second die.

Abstract: A high-reliability electronic packaging structure includes a plurality of packaging layers and mechanical support layers. An electrically functional solder joint is provided in a first area of each of the packaging layers, and any two adjacent packaging layers are coupled using electrically functional solder joints. A mechanical support layer is disposed in a second area of each of the packaging layers, and the mechanical support layer is configured to support the two adjacent packaging layers. The first area is provided on a periphery of the second area. Hence, a problem that an internal silicon chip at an upper packaging layer or a lower packaging layer fractures and fails when the upper packaging layer or the lower packaging layer is subject to a mechanical load can be resolved.

Abstract: An electronic device and a method of making an electronic device. As non-limiting examples, various aspects of this disclosure provide various methods of manufacturing electronic devices, and electronic devices manufactured thereby, that comprise utilizing an adhesive layer to attach an upper electronic package to a lower die and/or utilizing metal pillars for electrically connecting the upper electronic package to a lower substrate, wherein the metal pillars have a smaller height above the lower substrate than the lower die.

Abstract: A semiconductor memory includes a substrate, a memory controller, a plurality of memory modules, and a cover layer. The memory controller is provided on an upper surface of the substrate. Each of the memory modules partially covers an upper surface of the memory controller and the upper surface of the substrate through at least an adhesive layer. The cover layer is on the upper surface of the substrate and encloses the memory controller and the plurality of memory modules between the substrate and the cover layer.

Abstract: A stack package includes a package substrate and a fan-out sub-package mounted on the package substrate using first and second connection bumps. The fan-out sub-package includes a first semiconductor die and redistributed line (RDL) patterns. Second semiconductor dies are stacked on the package substrate to provide a first step structure, and third semiconductor dies are stacked on the second semiconductor dies to provide a second step structure. The second and third semiconductor dies are connected to the package substrate by bonding wires.

Abstract: Provided is a semiconductor package of a package on package (PoP) type having an improved electromagnetic wave shielding property. The semiconductor package includes: a first sub-package including a first package base substrate on which a first semiconductor chip is mounted, and an electromagnetic wave shielding member having a top portion and side portions respectively at a top surface and side surfaces of the first sub-package, wherein a groove space extends inward from a bottom surface of the first sub-package; and a second sub-package including a second package base substrate in the groove space and on which a second semiconductor chip is mounted, wherein the second sub-package is connected to the first sub-package through an inter-package connection terminal attached to a first package connection pad at a bottom surface of the groove space of the first sub-package.

Abstract: A method for producing a wired circuit board includes a step (1) of forming a seed layer on one surface in a thickness direction of a peeling layer, a step (2) of forming a conductive pattern on one surface in the thickness direction of the seed layer, a step (3) of covering the seed layer and the conductive pattern with an insulating layer, a step (4) of peeling the peeling layer from the seed layer, and a step (5) of removing the seed layer. The insulating layer has the number of times of folding endurance measured in conformity with JIS P8115 (2001) of 10 times or more.

Abstract: An embedded silicon bridge system including tall interconnect via pillars is part of a system in package device. The tall via pillars may span a Z-height distance to a subsequent bond pad from a bond pad that is part of an organic substrate that houses the embedded silicon bridge.

Abstract: A semiconductor package includes a plurality of stacked first semiconductor chips disposed over a substrate. At least a portion of the plurality of stacked first semiconductor chips is encapsulated in a first mold layer. The semiconductor package also includes a plurality of stacked second semiconductor chips disposed over the topmost chip of the stacked first semiconductor chips and the first mold layer. The semiconductor package also includes a third semiconductor chip disposed over the first mold layer and adjacent to the stacked second semiconductor chips. At least a portion of the third semiconductor chip overlaps with a portion of one or more of the stacked second semiconductor chips.

Abstract: A semiconductor device assembly can include a semiconductor device having a substrate and vias electrically connected to circuitry of the semiconductor device. Individual vias can have an embedded portion extending from the first side to the second side of the substrate and an exposed portion projecting from the second side of the substrate. The assembly can include a density-conversion connector comprising a connector substrate and a first array of contacts formed at the first side thereof, the first array of contacts occupying a first footprint area on the first side thereof, and wherein individual contacts of the first array are electrically connected to the exposed portion of a corresponding via of the semiconductor device. The assembly can include a second array of contacts electrically connected to the first array, formed at the second side of the connector substrate, and occupying a second footprint area larger than the first footprint area.

Abstract: Representative techniques and devices including process steps may be employed to mitigate the potential for delamination of bonded microelectronic substrates due to metal expansion at a bonding interface. For example, a metal pad may be disposed at a bonding surface of at least one of the microelectronic substrates, where the contact pad is positioned offset relative to a TSV in the substrate and electrically coupled to the TSV.

Abstract: A device includes a substrate, a first vertical cavity surface emitting laser (VCSEL) array on the substrate, a second VCSEL array on the substrate and adjacent to the first VCSEL array, and an isolation structure between the first VCSEL array and the second VCSEL array. The isolation structure provides electrical isolation between the first VCSEL array and the second VCSEL array.

Abstract: A semiconductor device package includes a first substrate, a second substrate disposed over the first substrate, and a surface mount device (SMD) component disposed between the first substrate and the second substrate. The SMD component includes a plurality of connection electrodes electrically connecting the first substrate to the second substrate, and the plurality of connection electrodes are electrically disconnected from each other.

Abstract: A semiconductor package includes a first semiconductor die and a stack of second semiconductor dies disposed on a package substrate. The semiconductor package further includes a first bridge die having first through vias that electrically connect the first semiconductor die to the package substrate, a second bridge die having second through vias that electrically connect the stack of the second semiconductor dies to the package substrate, and a third semiconductor die disposed to overlap with the first semiconductor die and the stack of the second semiconductor dies. Moreover, the semiconductor package further includes redistribution lines electrically connecting the third semiconductor die to the second bridge die.

Abstract: A system in package includes a stair-stacked memory module that is stacked vertically with respect to a processor die. A spacer is used adjacent to the processor die to create a bridge for the stair-stacked memory module. Each memory die in the stair-stacked memory module includes a vertical bond wire that emerges from a matrix for connection. The matrix encloses the stair-stacked memory module and at least a portion of the processor die.

Abstract: An ultrasonic device unit includes an ultrasonic device, and a flexible printed wiring board to be connected to the ultrasonic device, the flexible printed wiring board is provided with a device connection to which the ultrasonic device is connected, a first connector including external connection terminals to be connected to the ultrasonic device, a second connector including external connection terminals to be connected to the ultrasonic device, a first inflective part adapted to link the device connection and the first connector to each other, and a second inflective part adapted to link the device connection and the second connector to each other, and a distance between the device connection and the first connector in the first inflective part and a distance between the device connection and the first connector in the second inflective part are different from each other.

Abstract: A semiconductor device has a substrate including a terminal and an insulating layer formed over the terminal. An electrical component is disposed over the substrate. An encapsulant is deposited over the electrical component and substrate. A portion of the insulating layer over the terminal is exposed from the encapsulant. A shielding layer is formed over the encapsulant and terminal. A portion of the shielding layer is removed to expose the portion of the insulating layer. The portion of the insulating layer is removed to expose the terminal. The portion of the shielding layer and the portion of the insulating layer can be removed by laser ablation.

Abstract: Stitched die structures, and methods for interconnecting die are described. In an embodiment, a stitched die structure includes a semiconductor substrate that includes a first die area of a first die and a second die area of a second die separate from the first die area. A back-end-of-the-line (BEOL) build-up structure spans over the first die area and the second die area, and includes a first metallic seal directly over a first peripheral area of the first die area, a second metallic seal directly over a second peripheral area of the second die area, and a die-to-die routing extending through the first metallic seal and the second metallic seal to electrically connect the first die to the second die.

Abstract: A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a recess portion having a stopper layer; a semiconductor chip having connection pads, an active surface on which the connection pads are disposed, and an inactive surface opposing the active surface, and disposed in the recess portion so that the inactive surface is connected to the stopper layer; an encapsulant covering at least portions of the semiconductor chip and filling at least portions of the recess portion; and a connection member disposed on the frame and the active surface of the semiconductor chip and including a redistribution layer electrically connecting the wiring layers of the frame and the connection pads of the semiconductor chip to each other, wherein the stopper layer includes an insulating material.

Abstract: A microelectronic package may be fabricated having a microelectronic die stack attached to a microelectronic substrate, wherein the microelectronic die stack may include a first microelectronic die having an active surface and an opposing back surface, a first side and an opposing second side, wherein the first microelectronic die may include a plurality of primary bond pads on the active surface proximate the first side and at least one secondary bond pad on the active surface proximate the second side. The microelectronic die stack may further include a second microelectronic die having an active surface and an opposing back surface, wherein the back surface of the second microelectronic die is attached to the active surface of the first microelectronic die and wherein the second microelectronic die is rotated relative to the first microelectronic die to expose the at least one secondary bond pad of the first microelectronic die.

Abstract: A memory card comprising a first main surface and a second main surface opposing each other, and including a printed circuit board (PCB) constituting the first main surface, the PCB including a plurality of first external connection terminals, the plurality of first external connection terminals exposed on the first main surface, a plurality of memory devices stacked on the PCB, a memory controller configured to control the plurality of memory devices, a molding layer encapsulating the plurality of memory devices and the memory controller, the molding layer constituting the second main surface, and one or more second external connection terminals electrically connected to the memory controller, the one or more second external connection terminals embedded in the molding layer and exposed by the molding layer on the second main surface may be provided.

Abstract: A semiconductor package includes a lower substrate, a connection substrate coupled to the lower substrate, the connection substrate having a lateral portion surrounding a cavity, and a first conductive pattern on a top surface of the lateral portion, a lower semiconductor chip on the lower substrate, the lower semiconductor chip being in the cavity of the connection substrate, and the lower semiconductor chip including a second conductive pattern on a top surface of the lower semiconductor chip, a bonding member connecting the first conductive pattern and the second conductive pattern to each other, and a top package on the first conductive pattern and the second conductive pattern.

Abstract: A package structure includes a first substrate, a second substrate, a plurality of dies, a plurality of first conductive elements, and a plurality of second conductive elements. The first substrate has a recessed region. The second substrate is disposed in the recessed region and protrudes from the first substrate. The dies are disposed on the first substrate and the second substrate, such that the second substrate is disposed between the first substrate and the dies. The first conductive elements are disposed between the dies and the first substrate. The dies are electrically connected with the first substrate through the first conductive elements. The second conductive elements are disposed between the dies and the second substrate. The dies are electrically connected with the second substrate through the second conductive elements.

Abstract: A semiconductor package includes a package substrate having an upper surface and a lower surface and including a plurality of substrate pads formed on the upper surface, a capacitor structure arranged on the upper surface of the package substrate and including a semiconductor substrate and at least one decoupling capacitor formed in the upper surface of the semiconductor substrate, a plurality of first semiconductor chips mounted on the package and supported by the capacitor structure, first conductive connection members electrically connecting chip pads of the first semiconductor chips to the substrate pads, and second conductive connection members electrically connecting capacitor pads of the decoupling capacitor to the substrate pad.

Abstract: Various embodiments disclosed relate to a semiconductor package. The present semiconductor package includes a substrate. The substrate is formed from alternating conducting layers and dielectric layers. A first active electronic component is disposed on an external surface of the substrate, and a second active electronic component is at least partially embedded within the substrate. A first interconnect region is formed from a plurality of interconnects between the first active electronic component and the second active electronic component. Between the first active electronic component and the substrate a second interconnect region is formed from a plurality of interconnects. Additionally, a third interconnect region is formed from a plurality of interconnects between the second active electronic component and the substrate.

Abstract: Reliability of joining between semiconductor chips is improved by promoting filling of a sealing resin into a gap formed between the semiconductor chips. A semiconductor device includes: a first semiconductor chip, which has a plurality of first electrodes on a surface; a second semiconductor chip, which is disposed to be separated by a gap from the surface of the first semiconductor chip, and which includes an inner peripheral area that has a plurality of second electrodes connected to each of the first electrodes on a surface and an outer peripheral area that surrounds the inner peripheral area and has a thickness thinner than the thickness of the inner peripheral area; and a sealing resin, which is respectively filled between the surface of the first semiconductor chip and the inner peripheral area, and between the surface of the first semiconductor chip and the outer peripheral area.

Abstract: According to one embodiment, a semiconductor device includes a substrate, first stacked components, second stacked components, and a coating resin. The first stacked components include first chips and are stacked on a surface of the substrate. The second stacked components include second chips and are stacked on the surface. The coating resin covers the surface, the first stacked components, and the second stacked components. A first top surface of a second farthest one of the first chips away from the surface differs in position in a first direction from a second top surface of second farthest one of the second chips away from the surface.

Abstract: Embodiments of mechanisms for testing a die package with multiple packaged dies on a package substrate use an interconnect substrate to provide electrical connections between dies and the package substrate and to provide probing structures (or pads). Testing structures, including daisy-chain structures, with metal lines to connect bonding structures connected to signals, power source, and/or grounding structures are connected to probing structures on the interconnect substrate. The testing structures enable determining the quality of bonding and/or functionalities of packaged dies bonded. After electrical testing is completed, the metal lines connecting the probing structures and the bonding structures are severed to allow proper function of devices in the die package. The mechanisms for forming test structures with probing pads on interconnect substrate and severing connecting metal lines after testing could reduce manufacturing cost.

Abstract: An electronic device includes a switching element, a first common-electrode wiring, at least a part of the first common-electrode wiring being covered with the switching element, a plurality of second common-electrode wirings branched from the part of the first common-electrode wiring covered with the switching element, a plurality of individual power-output terminals arranged in a row in the switching element, and a plurality of individual-electrode wirings arranged in a row, the plurality of individual-electrode wirings being connected to the plurality of individual power-output terminals, respectively. Each of the plurality of second common-electrode wirings is disposed between the plurality of individual-electrode wirings.

Abstract: The present disclosure provides a light emitting diode (LED) package, which ensures the reliability during use while adopting an LED chip of higher output. The LED package includes an LED chip, which has a front and a back facing opposite sides in the thickness direction z, and a first back electrode provided at the back surface; a first terminal in conduction with the first back electrode; and a first bonding layer, configured to bond the first back electrode and the first terminal 201; wherein the composition of the first bonding layer includes a metal eutectic composition containing Au, and when the LED chip is viewed in the thickness direction z, a first bent portion which is recessed toward the inner side of the periphery of the first back electrode is formed in the first bonding layer.

Abstract: Some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes: a bottom package; wherein an area of a contact surface between the conductor and the through via substantially equals a cross-sectional area of the through via, and the bottom package includes: a molding compound; a through via penetrating through the molding compound; a die molded in the molding compound; and a conductor on the through via. An associated method of manufacturing the semiconductor device is also disclosed.

Abstract: A circuit carrier with embedded substrate includes a circuit structure and an embedded substrate. The circuit structure includes a first dielectric layer, a first patterned circuit layer, a trench, and a plurality of first bumps. The first dielectric layer has a first surface and a second surface opposite to each other. The first patterned circuit layer is embedded in the first surface. The first bumps are disposed on the first surface and electrically connected to the first patterned circuit layer. The trench exposes a portion of the first dielectric layer. The embedded substrate is disposed in the trench and includes a plurality of second bumps. A chip package structure includes the above circuit carrier with embedded substrate.

Abstract: Methods, systems, and devices related to a memory system or scheme that includes a first memory device configured for low-energy access operations and a second memory device configured for storing high-density information and operations of the same are described. The memory system may include an array configured for high-density information and may interface with a host via a controller and a cache or another array of a relatively fast memory type. The memory system may support signals communicated according to one or several modulation schemes, including a modulation scheme or schemes that employ two, three, or more voltage levels (e.g., NRZ, PAM4). The memory system may include, e.g., separate channels configured to communicate using different modulation schemes between a host and between memory arrays or memory types within the memory system.

Abstract: A semiconductor package includes a package substrate, a flip chip coupled to the package substrate, an interposer stacked on the flip chip and including a first terminal and a second terminal at an upper surface thereof, a bonding wire which connects the first terminal and the package substrate and a mold layer which covers the interposer, the flip chip and the bonding wire. The mold layer has a signal hole which exposes the second terminal, and at least one dummy hole spaced apart from the signal hole on an upper surface of the interposer.

Abstract: An array of pixels, wherein each pixel comprises: a CHEMFET sensor; and a sigma delta ADC.

Abstract: A semiconductor package is provided which includes a package substrate, a first die, a second die, an interconnection member and a number of bonding wires. The first die is disposed on the package substrate. The second die is disposed over the first die. The interconnection member is configured for coupling the first die and the second die and comprises a first connection plate, a second connection plate and a bump. The first connection plate is connected to the first die. The second connection plate is connected to the second die. The bump couples the first connection plate and the second connection plate. The bonding wires couple the interconnection member to the package substrate, the first die and the second die.

Abstract: The subject disclosure relates to 3D microelectronic chip packages with embedded coolant channels. The disclosed 3D microelectronic chip packages provide a complete and practical mechanism for introducing cooling channels within the 3D chip stack while maintaining the electrical connection through the chip stack. According to an embodiment, a microelectronic package is provided that comprises a first silicon chip comprising first coolant channels interspersed between first thru-silicon-vias (TSVs). The microelectronic chip package further comprises a silicon cap attached to a first surface of the first silicon chip, the silicon cap comprising second TSVs that connect to the first TSVs. A second silicon chip comprising second coolant channels can further be attached to the silicon cap via interconnects formed between a first surface of the second silicon chip and the silicon cap, wherein the interconnects connect to the second TSVs.

Abstract: A packaged assembly and a method of producing the packaged assembly is disclosed. The packaged assembly includes a redistribution layer (RDL), an integrated circuit (IC), one or more memory modules, and an interposer comprising a plurality of vias from a list of through-silicon-vias (TSVs), through-mold-via (TMVs), and plated-through-hold-via (PTHs). In some implementations, the IC is electrically and mechanically attached to a first side of the RDL. In some implementations, the one or more memory modules and the interposer are disposed on a second side of the RDL. The packaged assembly also includes a mold having a mold material encapsulating the IC, the one or more memory modules, the interposer, and the RDL to form the packaged assembly. In some implementations, the IC is electrically conductively connected an external circuit board via a series of electrical connections between the IC, the RDL, the vias, and the external circuit board.

Abstract: A package-on-package includes a first semiconductor package including a first semiconductor chip and a second semiconductor package, disposed on the first semiconductor package, including a second semiconductor chip electrically connected to the first semiconductor chip. Each of the first and second semiconductor chips includes one or more units. The number of units of the first semiconductor chip is greater than the number of units of the second semiconductor chip. The one or more units of the first semiconductor chip and the one or more units of the second semiconductor chip implement a function of an application processor chip.

Abstract: A method for encapsulating an integrated circuit includes: forming first and second electrically insulating supports each having a planar surface, so as to form a recess in the first support with respect to its planar surface, and so as to form, with respect to the planar surface of each of the first and second supports, first and second reliefs, so that the first and second reliefs of the supports interact; forming a first electrical contact in the recess; positioning a chip in the recess; forming a second electrical contact on the second carrier; and superposing the first and second carriers so as to superpose their reliefs.

Abstract: A semiconductor package includes a first semiconductor chip having a first through substrate via (TSV), a second semiconductor chip stacked on the first semiconductor chip and a first adhesive layer disposed between the first semiconductor chip and the second semiconductor chip. The second semiconductor chip includes a second through substrate via connected to the first through substrate via. A side surface of the first adhesive layer is recessed from side surfaces of the first and second semiconductor chips.

Abstract: A multi-chip package includes a first group of memory chips that includes a first memory chip and a second memory chip, a second group of memory chips that includes at least one memory chip, a first internal wiring system that couples the first memory chip and the second memory chip to a first terminal configured to receive a chip-enable signal, a second internal wiring system that couples the at least one memory chip to a second terminal configured to receive the chip-enable signal. The first memory chip and the second memory chip each include a chip address memory region configured to store an address associated with the memory chip, and an address rewrite module configured to rewrite the address associated with the memory chip and stored in the chip address memory region in response to an external operation.