Having Power Distribution Means (e.g., Bus Structure) Patents (Class 257/691)
  • Patent number: 10312198
    Abstract: A semiconductor device package includes a lead frame, an electronic component, a package body, at least one conductive via and a conductive layer. The lead frame includes a paddle, a connection element and a plurality of leads. The electronic component is disposed on the paddle. The package body encapsulates the electronic component and the lead frame. The at least one conductive via is disposed in the package body, electrically connected to the connection element, and exposed from the package body. The conductive layer is disposed on the package body and the conductive via.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: June 4, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Shao-Lun Yang, Yu-Shun Hsieh, Chia Yi Cheng, Hong Jie Chen, Shih Yu Huang
  • Patent number: 10312210
    Abstract: The invention provides a semiconductor package. The semiconductor package includes a base having a device-attach surface and a solder-ball attach surface opposite to the device-attach surface. A conductive via is disposed passing through the base. The conductive via includes a first terminal surface aligned to the device-attach surface of the base. A semiconductor die is mounted on the base by a conductive structure. The conductive structure is in contact with the first terminal surface of the conductive via.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: June 4, 2019
    Assignee: MediaTek Inc.
    Inventors: Ching-Liou Huang, Ta-Jen Yu
  • Patent number: 10304767
    Abstract: An object of the present invention is to improve the degree of freedom in the wiring design of a wiring substrate configuring a semiconductor device. Lands having an NSMD structure and a land-on-through-hole structure are arranged at positions not overlapping with a plurality of leads arranged on a chip loading surface of a wiring substrate in transparent plan view on the outer peripheral side of a mounting surface of the wiring substrate configuring a semiconductor device having a BGA package structure. On the other hand, land parts having the NSMD structure and to which lead-out wiring parts are connected are arranged at positions overlapping with the leads arranged on the chip loading surface of the wiring substrate in transparent plan view on the inner side than the group of lands in the mounting surface of the wiring substrate.
    Type: Grant
    Filed: April 17, 2018
    Date of Patent: May 28, 2019
    Assignee: Renesas Electronics Corporation
    Inventor: Tatsuya Kobayashi
  • Patent number: 10297522
    Abstract: A semiconductor package structure and manufacturing method thereof are provided. Firstly, a first surface mounting unit, a first printed circuit board, and a second printed circuit board are provided. The first surface mounting unit includes a first chip and a first conductive frame, and the first conductive frame has a first carrier board and a first metal member connected to the first carrier board. A first side of the first chip is electrically connected to the first carrier board of the first conductive frame. A second side of the first chip and the first metal member are connected to the first circuit board by a first pad and a second pad respectively. The second circuit board is connected to the first carrier board and hence, the first surface mounting unit is located between the first circuit board and the second circuit board.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: May 21, 2019
    Assignee: NIKO SEMICONDUCTOR CO., LTD.
    Inventor: Chih-Cheng Hsieh
  • Patent number: 10284109
    Abstract: An electronic device includes a first substrate, a wiring substrate (second substrate) disposed over the first substrate, and an enclosure (case) in which the first substrate and the wiring substrate are accommodated and that has a first side and a second side. A driver component (semiconductor component) is mounted on the wiring substrate. A gate electrode of a first semiconductor component is electrically connected to the driver component via a lead disposed on a side of the first side and a wiring disposed between the driver component and the first side. A gate electrode of a second semiconductor component is electrically connected to the driver component via a lead disposed on a side of the second side and a wiring disposed between the driver component and the second side.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: May 7, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Koji Bando, Kuniharu Muto, Hideaki Sato
  • Patent number: 10283488
    Abstract: A semiconductor module includes: a substrate having an insulating layer and a connecting portion connecting front and rear surfaces of the insulating layer; a first pattern on a front surface of the substrate; a second pattern on a rear surface of the substrate; a first semiconductor device disposed adjacent to the front surface of the substrate and including a first switching device having a lateral structure; a second semiconductor device disposed adjacent to the rear surface of the substrate and including a second switching device having the lateral structure; and a capacitor. A path formed by the first pattern and the first semiconductor device and a path formed by the second pattern and the second semiconductor device are opposed to each other across the substrate, and in the paths, currents flow in directions opposite to each other.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: May 7, 2019
    Assignee: DENSO CORPORATION
    Inventor: Akihiro Yamaguchi
  • Patent number: 10269728
    Abstract: A method includes embedding a die in a molding material; forming a first dielectric layer over the molding material and the die; forming a conductive line over an upper surface of the first dielectric layer facing away from the die; and forming a second dielectric layer over the first dielectric layer and the conductive line. The method further includes forming a first trench opening extending through the first dielectric layer or the second dielectric layer, where a longitudinal axis of the first trench is parallel with a longitudinal axis of the conductive line, and where no electrically conductive feature is exposed at a bottom of the first trench opening; and filling the first trench opening with an electrically conductive material to form a first ground trench.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Ya Huang, Chung-Hao Tsai, Chuei-Tang Wang, Chen-Hua Yu, Chih-Yuan Chang
  • Patent number: 10229895
    Abstract: An electronic sub-assembly (36) comprising at least one electronic component (14) embedded in a sequence of layers, wherein the electronic component (14) is arranged in a recess of an electrically conductive central layer (16) and directly adjoins a resin layer (12, 20) on each side.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: March 12, 2019
    Assignee: SCHWEIZER ELECTRONIC AG
    Inventors: Thomas Gottwald, Alexander Neumann
  • Patent number: 10231324
    Abstract: Some novel features pertain to an integrated device that includes a first metal layer and a second metal layer. The first metal layer includes a first set of regions. The first set of regions includes a first netlist structure for a power distribution network (PDN) of the integrated device. The second metal layer includes a second set of regions. The second set of regions includes a second netlist structure of the PDN of the integrated device. In some implementations, the second metal layer further includes a third set of regions comprising the first netlist structure for the PDN of the integrated device. In some implementations, the first metal layer includes a third set of regions that includes a third netlist structure for the PDN of the integrated device. The third set of regions is non-overlapping with the first set of regions of the first metal layer.
    Type: Grant
    Filed: April 29, 2014
    Date of Patent: March 12, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Ryan David Lane, Yue Li, Charles David Paynter, Ruey Kae Zang
  • Patent number: 10217711
    Abstract: A semiconductor package includes a ground electrode formed on an upper surface of a substrate, a first electronic component disposed on the upper surface of the substrate, a sealing member sealing the electronic component, and a shielding member surrounding the first electronic component and disposed in the sealing member.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: February 26, 2019
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Sung Jae Yoon, Seong Jong Cheon
  • Patent number: 10218290
    Abstract: An inverter has an inverter bridge connected between two DC busbars on the input side and connected to an AC output on the output side. The two DC busbars run, in a manner overlapping one another, in planes which are parallel to one another. The inverter bridge has a subcircuit having a plurality of semiconductor switches between the AC output and each DC busbar. Semiconductor modules which form the two subcircuits are connected, in a manner arranged beside one another, to the two DC busbars and to the AC output via connections. A connection element which leads to the AC output begins on that side of the DC busbar which faces the semiconductor modules in a region overlapped by the DC busbars and connects the semiconductor modules of the two subcircuits to one another there.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: February 26, 2019
    Assignee: SMA Solar Technology AG
    Inventors: Karl Nesemann, Andreas Falk, Henning Schneider
  • Patent number: 10211170
    Abstract: A system and method for a packaged device with harmonic control are presented. In one embodiment, a device includes a substrate and a transistor die coupled to the substrate. The transistor die includes a plurality of transistor cells. Each transistor cell in the plurality of transistor cells includes a control (e.g., gate) terminal. The device includes a second die coupled to the substrate. The second die includes a plurality of individual shunt capacitors coupled between the control terminals of the plurality of transistor cells and a ground reference node. The capacitance values of at least two of the shunt capacitors are significantly different.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: February 19, 2019
    Assignee: NXP USA, INC.
    Inventors: Pascal Peyrot, Olivier Lembeye, Sai Sunil Mangaonkar
  • Patent number: 10199567
    Abstract: A sensor includes: an integrated circuit having a power supply lead, a ground lead and a signal lead; a power supply terminal connected to the power supply lead; a ground terminal connected to the ground lead; a first signal terminal connected to the signal lead; a second signal terminal connected to the first signal terminal; a filter member having one end connected to one of the terminals and another end connected to another one of the terminals; and a sealing body sealing the integrated circuit, the terminals and the filter member. A part of each terminal is exposed from the sealing body.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: February 5, 2019
    Assignee: DENSO CORPORATION
    Inventors: Takeshi Itou, Takamitsu Kubota, Yoshiyuki Kono
  • Patent number: 10188010
    Abstract: This seal ring (1) is made of a clad material in which a base material layer (10) and a brazing filler metal layer (11) arranged on a first surface (10b) of the base material layer are bonded to each other, and a side brazing filler metal portion (11f) of the brazing filler metal layer covering a side surface (10c) of the base material layer is removed.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: January 22, 2019
    Assignee: HITACHI METALS, LTD.
    Inventors: Junya Nishina, Keiichiro Maeda, Ken Asada
  • Patent number: 10186979
    Abstract: An electric power converter includes a semiconductor module and a DC bus bar. The semiconductor module includes a main body portion having a built-in semiconductor element therein and a DC terminal to which a DC voltage is applied projecting from the main body portion. A DC bus bar is connected to the DC terminal. The DC bus bar is disposed such that a thickness direction of the DC bus bar matches a projecting direction of the DC terminal. The penetrating portion penetrating the projecting direction is formed in the DC bus bar. The DC terminal is connected to the DC bus bar in a state where at least a part of the DC terminal is disposed in a position that can be seen from the penetrating portion when viewed from the projection direction. The penetrating portion is formed in a hole shape.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: January 22, 2019
    Assignee: DENSO CORPORATION
    Inventors: Naohisa Harada, Akira Nakasaka, Tsuyoshi Kurauchi
  • Patent number: 10177085
    Abstract: A power commutation module includes a printed circuit board, a first plate-shaped bus bar, and a first plurality of power switches each including a plurality of connection pins which are connected on the upper face of the printed circuit board and a metal base plate which is applied against the bus bar. The first plurality of power switches is mounted on the first bus bar. The power switches are generally aligned along a longitudinal edge of the first bus bar, in that said longitudinal edge of the first bus bar is arranged along a first longitudinal edge of the printed circuit board, and the portion of the first bus bar on which the power switches are mounted is arranged next to the printed circuit board.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: January 8, 2019
    Assignee: APTIV TECHNOLOGIES LIMITED
    Inventors: Aymeric Perot, Erwan Guillanton
  • Patent number: 10162925
    Abstract: A cell layout, a cell layout library and a synthesizing method are disclosed. The cell layout includes a cell block and a tapping connector. The cell block has a pin. The pin being disposed at a Nth metal layer in the cell layout. The tapping connector is disposed at a (N+1)th metal layer and a (N+2)th metal layer and stacked above the pin of the cell block. The tapping connector is electrically connected to the pin and forms an equivalent tapping point of the pin of the cell block. N is a positive integer greater than or equal to 1.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Lin Chuang, Huang-Yu Chen, Yun-Han Lee
  • Patent number: 10163770
    Abstract: A device comprises a semiconductor structure in a molding compound layer, a first polymer layer on the molding compound layer, a second polymer layer on the first polymer layer, a first interconnect structure having a first via portion in the first polymer layer and a first metal line portion in the second polymer layer, a third polymer layer on the second polymer layer, a fourth polymer layer on the third polymer layer and a second interconnect structure having a second via portion in the third polymer layer and a second metal line portion in the fourth polymer layer, wherein the second via portion is vertically aligned with the first via portion.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Wei Chiu, Sao-Ling Chiu
  • Patent number: 10163851
    Abstract: A package includes an Integrated Voltage Regulator (IVR) die, wherein the IVR die includes metal pillars at a top surface of the first IVR die. The package further includes a first encapsulating material encapsulating the first IVR die therein, wherein the first encapsulating material has a top surface coplanar with top surfaces of the metal pillars. A plurality of redistribution lines is over the first encapsulating material and the IVR die. The plurality of redistribution lines is electrically coupled to the metal pillars. A core chip overlaps and is bonded to the plurality of redistribution lines. A second encapsulating material encapsulates the core chip therein, wherein edges of the first encapsulating material and respective edges of the second encapsulating material are vertically aligned to each other. An interposer or a package substrate is underlying and bonded to the IVR die.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Shang-Yun Hou, Yun-Han Lee
  • Patent number: 10153177
    Abstract: A wiring component electrically connects a first semiconductor element, including first and second electrode terminals, and a second semiconductor element, including third and fourth electrode terminals. The wiring component includes first and second connection terminals respectively connected to the first and third electrode terminals. A third connection terminal is connected to the second electrode terminal, and a fourth connection terminal is connected to the fourth electrode terminal. An insulation layer embeds the wiring component and the third and fourth connection terminals. A wiring layer is formed on a lower surface of the insulation layer and connected to an internal connection terminal and the third and fourth external terminals. Upper surfaces of the first to fourth external terminals are located coplanar with one another.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: December 11, 2018
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Haruo Sorimachi
  • Patent number: 10134683
    Abstract: A semiconductor device package includes a first circuit layer having a first surface and a second surface opposite the first side, a first electronic component, a shielding element, a shielding layer and a molding layer. The first electronic component is disposed over the first surface of the first circuit layer, and electrically connected to the first circuit layer. The shielding element is disposed over the first surface of the first circuit layer, and is electrically connected to the first circuit layer. The shielding element is disposed adjacent to at least one side of the first electronic component. The shielding layer is disposed over the first electronic component and the shielding element, and the shielding layer is electrically connected to the shielding element. The molding layer encapsulates the first electronic component, the shielding element and a portion of the shielding layer.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: November 20, 2018
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Tien-Szu Chen, Kuang-Hsiung Chen, Sheng-Ming Wang, I-Cheng Wang, Wun-Jheng Syu, Yu-Tzu Peng
  • Patent number: 10116025
    Abstract: An electronic apparatus includes a transmission line member and a mount circuit board. The transmission line member includes a dielectric base body, a first signal conductor, a first ground conductor, a second ground conductor, and a first transmission line that transmits a first high frequency signal and is defined by the first signal conductor interposed between the first and second ground conductors. The mount circuit board is wrapped by the transmission line member such that the transmission line member covers the mount circuit board from a top surface to a back surface via a side surface of the mount circuit board. At least one of an IC chip, a mount component, and a battery pack is mounted on the mount circuit board and is wrapped by the transmission line member so as to be disposed on an inner peripheral side of the transmission line member.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: October 30, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Kuniaki Yosui, Takahiro Baba, Kosuke Nishino
  • Patent number: 10109542
    Abstract: A solid-state contactor includes a housing, a lead, a bus plate, and an end connector. The lead extends through the housing and into an interior of the housing. The bus plate is disposed within the housing interior and mounts a die which is electrically connected to the lead through the bus plate. The end connector extends between the bus plate and the lead, attaching to the bus plate at an angle for coupling a plurality of bus plates with die to the lead in a stacked arrangement.
    Type: Grant
    Filed: April 4, 2014
    Date of Patent: October 23, 2018
    Assignees: Hamilton Sundstrand Corporation, HS Elektronik Systeme GmbH
    Inventors: Pal Debabrata, John Horowy, Eric Karlen, Rainer J. Seidel
  • Patent number: 10103080
    Abstract: The present disclosure relates to a thermally enhanced semiconductor package, which includes a module substrate, a thinned flip chip die over the substrate, a first mold compound component, and a thermally enhanced mold compound component. The first mold compound component resides over the module substrate, surrounds the thinned flip chip die, and extends above an upper surface of the thinned flip chip die to form a cavity over the upper surface of the thinned flip chip die. The thermally enhanced mold compound component includes a lower portion filling a lower region of the cavity and residing over the upper surface of the thinned flip chip die, and an upper portion filling an upper region of the cavity and residing over the lower portion. A first average thermal conductivity of the lower portion is at least 1.2 times greater than a second average thermal conductivity of the upper portion.
    Type: Grant
    Filed: November 16, 2016
    Date of Patent: October 16, 2018
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, George Maxim, Dirk Robert Walter Leipold, Baker Scott, Merrill Albert Hatcher, Jr., Stephen Mobley
  • Patent number: 10104006
    Abstract: In the bus system, bus interface apparatuses and routers are connected together through packet exchange buses which have been established on the integrated circuit. The bus interface apparatuses are respectively connected to transmission nodes which transmit data of mutually different numbers of bits in one cycle of operation of the bus system. Each of the bus interface apparatuses generates and transmits a packet based on data received from the transmission node connected and header information including size information indicating the number of bits with respect to the transmission node connected. The router analyzes the packet, gets the size information from the header information, determines how to allocate a space in the buffer for storage by reference to the size information gotten, and stores the received packet in the buffer.
    Type: Grant
    Filed: September 22, 2014
    Date of Patent: October 16, 2018
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO. LTD
    Inventors: Atsushi Yoshida, Satoru Tokutsu, Tomoki Ishii, Takao Yamaguchi, Yuuki Soga
  • Patent number: 10083948
    Abstract: In order to form, in a wide band gap semiconductor device, a high field resistant sealing material having a large end portion film thickness, said high field resistant sealing material corresponding to a reduced termination region having a high field intensity, and to improve accuracy and shorten time of manufacturing steps, this semiconductor device is configured as follows. At least a part of a cross-section of a high field resistant sealing material formed close to a termination region at the periphery of a semiconductor chip has a perpendicular shape at a chip outer peripheral end portion, said shape having, on the chip inner end side, a film thickness that is reduced toward the inner side. In a semiconductor device manufacturing method for providing such semiconductor device, the high field resistant sealing material is formed in a semiconductor wafer state, then, heat treatment is performed, and after dicing is performed, a chip is mounted.
    Type: Grant
    Filed: December 26, 2014
    Date of Patent: September 25, 2018
    Assignee: Hitachi, Ltd.
    Inventors: Kan Yasui, Kazuhiro Suzuki, Takafumi Taniguchi
  • Patent number: 10085368
    Abstract: An electronic device includes a heat dissipation member, a power element that is thermally coupled to the heat dissipation member, and a first conductive layer to which the power element is electrically coupled. The electronic device further includes a control element that controls a switching operation of the power element, a second conductive layer to which the control element is electrically coupled, and a resin layer arranged between the first conductive layer and the second conductive layer. The power element is embedded in the resin layer. The first conductive layer, the resin layer, and the second conductive layer are stacked on the heat dissipation member in this order from the ones closer to the heat dissipation member.
    Type: Grant
    Filed: November 6, 2015
    Date of Patent: September 25, 2018
    Assignee: KABUSHIKI KAISHA TOYOTA JIDOSHOKKI
    Inventors: Shogo Mori, Naoki Kato, Hiroshi Yuguchi, Yoshitaka Iwata, Masahiko Kawabe, Yuri Otobe
  • Patent number: 10078358
    Abstract: A power delivery network (PDN) including a battery, a set of regulators for generating supply voltages, and an integrated circuit (IC) including power rails configured to receive the supply voltages. The IC further includes an IC chip having a set of cores. The power rails includes a larger rail configured to provide a full range of currents, and the other smaller power rails each configured to provide lower range of currents. The IC includes multiplexers having first inputs coupled respectively to the smaller rails, second inputs coupled to the larger rail, and outputs coupled to the cores. When the smaller rail is able to supply the current needed by a core, the multiplexer is configured to couple the smaller rail to the core. When the smaller rail cannot supply the current needed by the core, the multiplexer is configured to couple the larger rail to the core.
    Type: Grant
    Filed: June 2, 2016
    Date of Patent: September 18, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Juan Ochoa Munoz, Yuancheng Chris Pan, Mikhail Popovich, Joon Hyung Chung
  • Patent number: 10080301
    Abstract: A power die module using a compression connection to a power die in a small package with corona extenders positioned around short efficient path exterior electrical connections. The module is built from a baseplate with connected sidewalls forming an interior compartment holding a power substrate with attached threaded inserts. A printed circuit board bolted to the power substrate with high voltage power die compressively held between the board and the substrate. The compressive hold enhances the electrical connections between the contacts on the top and bottom of the power die and either the power substrate or the printed circuit board. Exterior blade connectors extend upward from the printed circuit board through blade apertures in a lid that covers the interior compartment. The lid includes corona extenders positioned around the blade apertures to allow for high voltage applications while maintaining a small size lightweight package.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: September 18, 2018
    Assignee: Cree, Inc.
    Inventors: Brandon Passmore, Zachary Cole, Brice McPherson
  • Patent number: 10074600
    Abstract: Various resistor circuits and methods of making and using the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a resistor onboard an interposer. The resistor is adapted to dampen a capacitive network. The capacitive network has at least one capacitor positioned external to the interposer.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: September 11, 2018
    Assignees: ATI Technologies ULC, Advanced Micro Devices, Inc.
    Inventors: Fei Guo, Feng Zhu, Julius Din, Anwar Kashem, Sally Yeung
  • Patent number: 10070527
    Abstract: When a nut housing member is inserted from a first opening portion into a case (terminal housing area) in a semiconductor device, first and second protrusions of the nut housing member slide on and pass through the first and second opening portions. Ultimately, the nut housing member is housed in the case (terminal housing area), with the first protrusion being in contact with a lower end of the second opening portion and the second protrusion being in contact with a lower end of the first opening portion. Even if the nut housing member is not inserted in parallel with the terminal housing area, the forefront does not hit against a first beam. Therefore, the nut housing member is inserted stably and housed reliably in the terminal housing area of the case, and the assemblability of the nut housing member with respect to the case is improved.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: September 4, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Yoshihiro Kodaira
  • Patent number: 10049252
    Abstract: A chip package includes a substrate, a capacitive sensing layer and a computing chip. The substrate has a first surface and a second surface opposite to the first surface, and the capacitive sensing layer is disposed above the second surface and having a third surface opposite to the second surface, which the capacitive sensing layer includes a plurality of capacitive sensing electrodes and a plurality of metal wires. The capacitive sensing electrodes are on the second surface, and the metal wires are on the capacitive sensing electrodes. The computing chip is disposed above the third surface and electrically connected to the capacitive sensing electrodes.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: August 14, 2018
    Assignee: XINTEC INC.
    Inventors: Yen-Shih Ho, Shu-Ming Chang, Tsang-Yu Liu, Hsing-Lung Shen
  • Patent number: 10037892
    Abstract: A device includes a redistribution layer over a molding compound layer, a first chip over the fan-out structure, wherein the first chip comprise a plurality of first through vias connected to the redistribution layer and a second chip over the first chip, the second chip being connected to the first chip through a plurality of bumps, wherein the first chip and the second chip are in the molding compound layer, and wherein a center line of the first chip is not vertically aligned with a center line of the second chip.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: July 31, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Der-Chyang Yeh
  • Patent number: 10026669
    Abstract: The present disclosure relates to a thermally enhanced semiconductor package, which includes a module substrate, a thinned flip chip die over the substrate, a first mold compound component, and a thermally enhanced mold compound component. The first mold compound component resides over the module substrate, surrounds the thinned flip chip die, and extends above an upper surface of the thinned flip chip die to form a cavity over the upper surface of the thinned flip chip die. The thermally enhanced mold compound component includes a lower portion filling a lower region of the cavity and residing over the upper surface of the thinned flip chip die, and an upper portion filling an upper region of the cavity and residing over the lower portion. A first average thermal conductivity of the lower portion is at least 1.2 times greater than a second average thermal conductivity of the upper portion.
    Type: Grant
    Filed: November 16, 2016
    Date of Patent: July 17, 2018
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, George Maxim, Dirk Robert Walter Leipold, Baker Scott, Merrill Albert Hatcher, Jr., Stephen Mobley
  • Patent number: 10015882
    Abstract: Embodiments described herein relate generally to a microelectronic packaging and the manufacture thereof. A carrier may have a die attached to a top face thereof. A printed circuit board may be attached to the top face of the carrier. The printed circuit board may have a hole in which the die is disposed. A lid may be attached to the printed circuit board opposite the carrier so that the die is enclosed by the carrier, the printed circuit board, and the lid. The printed circuit board may form a seal ring around the die. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: January 5, 2015
    Date of Patent: July 3, 2018
    Assignee: Qorvo US, Inc.
    Inventors: Dylan Murdock, Binh K. Le, Michael J. Arnold, Walid Meliane
  • Patent number: 10014266
    Abstract: A method and structure, the structure having a substrate, an active device in an active device semiconductor region; of the substrate, a microwave transmission line, on the substrate, electrically connected to the active device, and microwave energy absorbing “dummy” fill elements on the substrate. The method includes providing a structure having a substrate, an active device region on a surface of the structure, an ohmic contact material on the active device region, and a plurality of “dummy” fill elements on the surface to provide uniform heating of the substrate during a rapid thermal anneal process, the ohmic contact material and the “dummy” fill elements having the same radiant energy reflectivity. The rapid thermal anneal processing forms an ohmic contact between an ohmic contact material and the active device region and simultaneously converts the “dummy” fill elements into microwave lossy “dummy” fill elements.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: July 3, 2018
    Assignee: Raytheon Company
    Inventors: Fikret Altunkilic, Adrian D. Williams, Christopher J. MacDonald, Kamal Tabatabaie Alavi
  • Patent number: 10015878
    Abstract: In various embodiments, apparatuses and methods are disclosed that may be able to implement a multi-layer, three dimensional routing between a decoupling component and an input port for a SoC or MCM. A three dimensional (3D) structure may provide a defined current return path from the decoupling component to the input port. The current return path may be constrained by design to provide an equal and opposite electromagnetic flux to the input port thereby reducing series inductance between the input port and the decoupling component.
    Type: Grant
    Filed: November 19, 2015
    Date of Patent: July 3, 2018
    Assignee: INTEL CORPORATION
    Inventors: William L. Barber, Keith Pinson, Andrew P. Collins, Boping Wu, Isaac Ali, Colin L. Perry
  • Patent number: 9997426
    Abstract: The present disclosure relates to a thermally enhanced semiconductor package, which includes a module substrate, a thinned flip chip die over the substrate, a first mold compound component, and a thermally enhanced mold compound component. The first mold compound component resides over the module substrate, surrounds the thinned flip chip die, and extends above an upper surface of the thinned flip chip die to form a cavity over the upper surface of the thinned flip chip die. The thermally enhanced mold compound component includes a lower portion filling a lower region of the cavity and residing over the upper surface of the thinned flip chip die, and an upper portion filling an upper region of the cavity and residing over the lower portion. A first average thermal conductivity of the lower portion is at least 1.2 times greater than a second average thermal conductivity of the upper portion.
    Type: Grant
    Filed: November 16, 2016
    Date of Patent: June 12, 2018
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, George Maxim, Dirk Robert Walter Leipold, Baker Scott, Merrill Albert Hatcher, Jr., Stephen Mobley
  • Patent number: 9991609
    Abstract: An electrical connection module system includes a first connection plate with a first connection end and at least one first foot section, a first screw nut, and a dielectric holder. The dielectric holder has a first reception region for receiving the first screw nut. The first connection plate can, when the first screw nut is placed in the first reception region, be pushed onto the dielectric holder and be brought into a first target position such that the first screw nut is arranged between the dielectric holder and the first connection end and is held by the first connection end in the first reception region in such a way that the first screw nut cannot fall out.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: June 5, 2018
    Assignee: Infineon Technologies AG
    Inventors: Alexander Hoehn, Georg Borghoff
  • Patent number: 9991032
    Abstract: A method for manufacturing a thin film chip resistor device includes the steps of: disposing a magnetic fixing member on a first surface of a substrate, and disposing a magnetic shadow mask on a second surface of the substrate opposite to the first surface, such that the magnetic shadow mask detachably and fixedly contacts the second surface of the substrate by virtue of an attractive magnetic force between the magnetic fixing member and the magnetic shadow mask; and depositing at least one resistor unit on the second surface of the substrate with the use of the magnetic shadow mask, the resistor unit including two separated first electrode elements and a resistor element that electrically interconnects the first electrode elements.
    Type: Grant
    Filed: November 19, 2015
    Date of Patent: June 5, 2018
    Assignee: RALEC ELECTRONIC CORPORATION
    Inventor: Wan-Ping Wang
  • Patent number: 9966317
    Abstract: A semiconductor device may include a first terminal electrically connected to a first semiconductor chip, a second terminal electrically connected to a second semiconductor chip, which is different from the first semiconductor chip, a first signal line electrically connecting the first terminal and the second terminal and including a first node, a third terminal connected to a tester monitoring a signal transmitted between the first semiconductor chip and the second semiconductor chip, a fourth terminal applied a reference voltage, a second signal line electrically connecting the third terminal and the fourth terminal and including a second node, a first resistor connected between the first node and the second node and a second resistor directly connected to the second node different from the first resistor.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: May 8, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joung-Yeal Kim, Dae-Hyun Kwon, Mi-Young Woo, Joon-Sun Yoon, Jong-Hyun Choi
  • Patent number: 9960095
    Abstract: The present disclosure relates to a thermally enhanced semiconductor package, which includes a module substrate, a thinned flip chip die over the substrate, a first mold compound component, and a thermally enhanced mold compound component. The first mold compound component resides over the module substrate, surrounds the thinned flip chip die, and extends above an upper surface of the thinned flip chip die to form a cavity over the upper surface of the thinned flip chip die. The thermally enhanced mold compound component includes a lower portion filling a lower region of the cavity and residing over the upper surface of the thinned flip chip die, and an upper portion filling an upper region of the cavity and residing over the lower portion. A first average thermal conductivity of the lower portion is at least 1.2 times greater than a second average thermal conductivity of the upper portion.
    Type: Grant
    Filed: November 16, 2016
    Date of Patent: May 1, 2018
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, George Maxim, Dirk Robert Walter Leipold, Baker Scott, Merrill Albert Hatcher, Jr., Stephen Mobley
  • Patent number: 9961791
    Abstract: This seal ring (1) is made of a clad material in which a base material layer (10) and a brazing filler metal layer (11) arranged on a first surface (10b) of the base material layer are bonded to each other, and a side brazing filler metal portion (11f) of the brazing filler metal layer covering a side surface (10c) of the base material layer is removed.
    Type: Grant
    Filed: January 15, 2013
    Date of Patent: May 1, 2018
    Assignee: HITACHI METALS, LTD.
    Inventors: Junya Nishina, Keiichiro Maeda, Ken Asada
  • Patent number: 9953935
    Abstract: Disclosed are chip packaging structures for high speed chip to chip and chip to carrier communications and methods of making such structures. The chip packaging structures do not require an interposer containing through silicon vias and/or provide structures having reduced warping.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: April 24, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Shidong Li
  • Patent number: 9935036
    Abstract: Some embodiments of the present disclosure describe an integrated circuit (IC) package assembly having first, second, and third insulated wires wire bonded with die pads on an IC die, with an outer surface of the second insulated wire located at a distance of less than an outer cross-sectional diameter of the second insulated wire from an outer surface of the first insulated wire at a first location and located at a distance of less than the outer cross-sectional diameter from an outer surface of the third insulated wire at a second location. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: April 3, 2018
    Assignee: Intel Corporation
    Inventors: Gong Ouyang, Beom-Taek Lee
  • Patent number: 9930772
    Abstract: Printed circuit includes a planar substrate having opposite sides and a thickness extending therebetween. The sides extend parallel to a lateral plane. The printed circuit also includes a plurality of conductive vias extending through the planar substrate in a direction that is perpendicular to the lateral plane. The conductive vias include ground vias and signal vias. The signal vias form a plurality of quad groups in which each quad group includes a two-by-two array of the signal vias. Optionally, the printed circuit also includes signal traces that electrically couple to the signal vias. The signal traces may form a plurality of quad lines in which each quad line includes four of the signal traces. The four signal traces of each quad line may extend parallel to one another and be in a two-by-two formation.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: March 27, 2018
    Assignees: TE CONNECTIVITY CORPORATION, TYCO ELECTRONICS JAPAN G.K.
    Inventors: Chad William Morgan, Masayuki Aizawa, Arash Behziz, Brian Patrick Costello, Nathan Lincoln Tracy, Michael David Herring
  • Patent number: 9930793
    Abstract: Generally discussed herein are systems and apparatuses that can include a flexible substrate with a hermetic seal formed thereon. The disclosure also includes techniques of making and using the systems and apparatuses. According to an example a technique of making a hermetic seal on a flexible substrate can include (1) forming an interconnect on a flexible substrate, (2) situating a device on the substrate near the interconnect, or (3) selectively depositing a first hermetic material on the device or interconnect so as to hermetically seal the device within the combination of the interconnect and first hermetic material.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: March 27, 2018
    Assignee: Intel Corporation
    Inventors: Chuan Hu, Siddarth Kumar
  • Patent number: 9922898
    Abstract: The present disclosure relates to a thermally enhanced semiconductor package, which includes a module substrate, a thinned flip chip die over the substrate, a first mold compound component, and a thermally enhanced mold compound component. The first mold compound component resides over the module substrate, surrounds the thinned flip chip die, and extends above an upper surface of the thinned flip chip die to form a cavity over the upper surface of the thinned flip chip die. The thermally enhanced mold compound component includes a lower portion filling a lower region of the cavity and residing over the upper surface of the thinned flip chip die, and an upper portion filling an upper region of the cavity and residing over the lower portion. A first average thermal conductivity of the lower portion is at least 1.2 times greater than a second average thermal conductivity of the upper portion.
    Type: Grant
    Filed: November 16, 2016
    Date of Patent: March 20, 2018
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, George Maxim, Dirk Robert Walter Leipold, Baker Scott, Merrill Albert Hatcher, Jr., Stephen Mobley
  • Patent number: 9913363
    Abstract: A structure for delivering power is described. In some embodiments, the structure can include conductors disposed on two or more layers. Specifically, the structure can include a first set of interdigitated conductors disposed on a first layer and oriented substantially along an expected direction of current flow. At least one conductor in the first set of interdigitated conductors may be maintained at a first voltage, and at least one conductor in the first set of interdigitated conductors may be maintained at a second voltage, wherein the second voltage is different from the first voltage. The structure may further include a conducting structure disposed on a second layer, wherein the second layer is different from the first layer, and wherein at least one conductor in the conducting structure is maintained at the first voltage.
    Type: Grant
    Filed: August 14, 2012
    Date of Patent: March 6, 2018
    Assignee: Rambus Inc.
    Inventors: Kyung Suk Oh, Ralf M. Schmitt, Yijiong Feng
  • Patent number: 9899280
    Abstract: A method of forming a temporary test structure for device fabrication is provided. The method allows for electrically testing conductive interconnects during controlled collapse chip connections (C4) fabrication and/or through-silicon vias (TSVs) during interposer fabrication. The method includes providing a substrate containing a plurality of electrically conductive interconnects extending vertically to top surface of the substrate. A temporary test structure is formed to connect the plurality of interconnects for electrical testing. Electrical testing is performed on the substrate by probing at different test locations on the temporary test structure. All or part of the temporary test structure is removed so as not to affect product performance. The temporary test structure can contain electrical test pads which provide a way to make temporary connections to small interconnect landings or features at extreme tight pitch to fan them out to testable pads sizes and pitches.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: February 20, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Charles L. Arvin, Brian Michael Erwin, Gary W. Maier