Having Power Distribution Means (e.g., Bus Structure) Patents (Class 257/691)
  • Patent number: 11907791
    Abstract: Smartcards with metal layers manufactured according to various techniques disclosed herein. One or more metal layers of a smartcard stackup may be provided with slits overlapping at least a portion of a module antenna in an associated transponder chip module disposed in the smartcard so that the metal layer functions as a coupling frame. One or more metal layers may be pre-laminated with plastic layers to form a metal core or clad subassembly for a smartcard, and outer printed and/or overlay plastic layers may be laminated to the front and/or back of the metal core. Front and back overlays may be provided. Various constructions of and manufacturing techniques (including temperature, time, and pressure regimes for laminating) for smartcards are disclosed herein.
    Type: Grant
    Filed: July 19, 2022
    Date of Patent: February 20, 2024
    Assignee: Amatech Group Lijited
    Inventors: Mustafa Lotya, David Finn, Darren Molloy
  • Patent number: 11901344
    Abstract: A manufacturing method of a semiconductor package is provided as follows. A semiconductor die is provided, wherein the semiconductor die comprises a semiconductor substrate, an interconnection layer and a through semiconductor via, the interconnection layer is disposed on an active surface of the semiconductor substrate, the through semiconductor via penetrates the semiconductor substrate from a back surface of the semiconductor substrate to the active surface of the semiconductor substrate. An encapsulant is provided to laterally encapsulate the semiconductor die. A through encapsulant via penetrating through the encapsulant is formed.
    Type: Grant
    Filed: October 21, 2021
    Date of Patent: February 13, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Shing-Yih Shih
  • Patent number: 11901348
    Abstract: A semiconductor package includes a mold substrate, at least one first semiconductor chip in the mold substrate and including chip pads, wiring bonding pads formed at a first surface of the mold substrate and connected to the chip pads by bonding wires, and a redistribution wiring layer covering the first surface of the mold substrate and including redistribution wirings connected to the wiring bonding wirings.
    Type: Grant
    Filed: July 15, 2021
    Date of Patent: February 13, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-Ho Kang, Bo-Seong Kim
  • Patent number: 11887953
    Abstract: A package for power electronics includes a power substrate, a number of power semiconductor die, and a Kelvin connection contact. Each one of the power semiconductor die are on the power substrate and include a first power switching pad, a second power switching pad, a control pad, a semiconductor structure, and a Kelvin connection pad. The semiconductor structure is between the first power switching pad, the second power switching pad, and the control pad, and is configured such that a resistance of a power switching path between the first power switching pad and the second power switching pad is based on a control signal provided at the control pad. The Kelvin connection pad is coupled to the power switching path. The Kelvin connection contact is coupled to the Kelvin connection pad of each one of the power semiconductor die via a Kelvin conductive trace on the power substrate.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: January 30, 2024
    Assignee: Wolfspeed, Inc.
    Inventors: Brice McPherson, Daniel Martin, Jennifer Stabach
  • Patent number: 11880321
    Abstract: A master integrated circuit (IC) chip includes transmit circuitry and receiver circuitry. The transmit circuitry includes a timing signal generation circuit to generate a first timing signal, and a driver to transmit first data in response to the first timing signal. A timing signal path routes the first timing signal in a source synchronous manner with the first data. The receiver circuitry includes a receiver to receive second data from a slave IC chip, and sampling circuitry to sample the second data in response to a second timing signal that is derived from the first timing signal.
    Type: Grant
    Filed: November 8, 2021
    Date of Patent: January 23, 2024
    Assignee: Marvell Asia Pte, Ltd.
    Inventor: Ramin Farjadrad
  • Patent number: 11881248
    Abstract: The present invention provides a semiconductor module, a semiconductor member, and a method for manufacturing the same that make it possible to improve heat dissipation efficiency. This semiconductor module 1 comprises: a power supply unit 40; a RAM unit 50, which is a RAM module having a facing surface disposed so as to face an exposed surface of a logic chip 20 and an exposed surface of the power supply unit 40, the RAM module being disposed across some of a plurality of logic chip signal terminals 22 and some of a plurality of power supply unit power supply terminals 41; and a support substrate 10 having a power feeding circuit capable of feeding electrical power to the logic chip and to the power supply unit 40, one main surface of the support substrate 10 being disposed adjacent to a heat dissipation surface of the RAM unit 50, which is the surface of the RAM unit 50 opposite the facing surface.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: January 23, 2024
    Assignee: ULTRAMEMORY INC.
    Inventors: Fumitake Okutsu, Takao Adachi
  • Patent number: 11860699
    Abstract: An electrical transmitter (100) is provided that comprises an ethernet connection (118) and a power source. Electronics (112) are configured to receive the ethernet connection (118) and the power source. The electronics (112) comprise logic operable to detect the power source and accept power from either the ethernet connection (118) or a dedicated power connection (116). A remappable power connection terminal (114) with the electronics (112) is operable to accept power when the dedicated power connection (116) is detected, and operable to accept a non-power connection when power from the ethernet connection (118) is detected.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: January 2, 2024
    Assignee: MICRO MOTION, INC.
    Inventors: Andrew S. Kravitz, Tonya L. Wyatt, Anthony Gentile
  • Patent number: 11854925
    Abstract: According to one embodiment, a semiconductor device includes a plurality of stacked semiconductor chips each of which has a first surface having an electrode formed thereon, a plurality of wires each of which has one end portion connected to each of the electrodes of the plurality of semiconductor chips and extends in a stacking direction of the semiconductor chips, a sealing resin that covers the plurality of semiconductor chips, has a second surface having recesses formed therein, and is formed so that the other end portions of the plurality of wires and the recesses overlap each other when viewed from the stacking direction, and a plurality of terminals that is provided so as to fill the recesses, each of which has one end portion connected to the other end portion of each of the plurality of wires and has the other end portion exposed from the sealing resin.
    Type: Grant
    Filed: September 7, 2021
    Date of Patent: December 26, 2023
    Assignee: Kioxia Corporation
    Inventor: Satoshi Kato
  • Patent number: 11847852
    Abstract: A fingerprint sensor includes a die, a plurality of conductive structures, an encapsulant, a plurality of conductive patterns, a first dielectric layer, a second dielectric layer, and a redistribution structure. The die has an active surface and a rear surface opposite to the active surface. The conductive structures surround the die. The encapsulant encapsulates the die and the conductive structures. The conductive patterns are over the die and are electrically connected to the die and the conductive structures. Top surfaces of the conductive patterns are flat. The first dielectric layer is over the die and the encapsulant. A top surface of the first dielectric layer is coplanar with top surfaces of the conductive patterns. The second dielectric layer covers the first dielectric layer and the conductive patterns. The redistribution structure is over the rear surface of the die.
    Type: Grant
    Filed: December 22, 2022
    Date of Patent: December 19, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsuan Tai, Chih-Hua Chen, Hao-Yi Tsai, Yu-Chih Huang, Chia-Hung Liu, Ting-Ting Kuo, Ying-Cheng Tseng
  • Patent number: 11815546
    Abstract: Embodiments of the present application disclose a fixing device and fixing method for chip test and a chip tester. The fixing device for chip test includes: a carrier with a fixing chamber for fixing a chip formed inside, a plurality of adjustors being disposed on sidewalls of the fixing chamber and configured to be extended or retracted to adjust a position of the chip in two orthogonal directions within a horizontal plane; and a top cover configured to cooperate with the carrier to fix the chip in a vertical direction, wherein at least one adjustable pressing cover is disposed at a bottom of the top cover, so as to autonomously adjust a pressing force applied to the chip by the pressing cover in the vertical direction. The present application is suitable for fixing chips with various overall dimensions, and can adaptively adjust a pressing force.
    Type: Grant
    Filed: October 18, 2021
    Date of Patent: November 14, 2023
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Jinrong Huang
  • Patent number: 11810833
    Abstract: A packaged semiconductor device and a method and apparatus for forming the same are disclosed. In an embodiment, a method includes bonding a device die to a first surface of a substrate; depositing an adhesive on the first surface of the substrate; depositing a thermal interface material on a surface of the device die opposite the substrate; placing a lid over the device die and the substrate, the lid contacting the adhesive and the thermal interface material; applying a clamping force to the lid and the substrate; and while applying the clamping force, curing the adhesive and the thermal interface material.
    Type: Grant
    Filed: July 12, 2021
    Date of Patent: November 7, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wensen Hung, Tsung-Yu Chen, Tsung-Shu Lin, Chen-Hsiang Lao, Wen-Hsin Wei, Hsien-Pin Hu
  • Patent number: 11798897
    Abstract: A package structure includes a circuit substrate, a semiconductor device and a ring structure. The circuit substrate has a first region and a second region connected thereto. The circuit substrate includes at least one routing layer including a dielectric portion and a conductive portion disposed thereon. A first ratio of a total volume of the conductive portion of the routing layer within the first region to a total volume of the dielectric and conductive portions of the routing layer within the first region is less than a second ratio of a total volume of the conductive portion of the routing layer within the second region to a total volume of the dielectric and conductive portions of the routing layer within the second region. The semiconductor device is disposed over the circuit substrate within the first region, and is electrically coupled to the circuit substrate. The ring structure is disposed over the circuit substrate within the second region.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: October 24, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu-Shen Yeh, Po-Yao Lin, Chin-Hua Wang, Chia-Kuei Hsu, Shin-Puu Jeng
  • Patent number: 11799503
    Abstract: A semiconductor device including a radio-frequency amplifier circuit and a band selection switch are mounted on or in a module substrate. An output matching circuit includes at least one passive element disposed on or in the module substrate. The output matching circuit is coupled between the radio-frequency amplifier circuit and the band selection switch. The semiconductor device includes a first member having a semiconductor portion made of an elemental semiconductor and a second member joined to the first member in surface contact with the first member. The radio-frequency amplifier circuit including a semiconductor element made of a compound semiconductor is formed at the second member. The semiconductor device is disposed in close proximity to the output matching circuit in plan view. The output matching circuit is disposed in close proximity to the band selection switch.
    Type: Grant
    Filed: December 9, 2021
    Date of Patent: October 24, 2023
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Satoshi Goto, Shunji Yoshimi, Mitsunori Samata
  • Patent number: 11778730
    Abstract: A printed circuit board includes a dielectric substrate which is formed in a plate-like shape, ground conductor layers which are respectively provided on a top surface and a back surface of the dielectric substrate, a signal line which is provided on a side surface of the dielectric substrate, and transmits a high frequency signal, and a plurality of connection conductors which are provided in the dielectric substrate, connects the ground conductor layer provided on the top surface and the ground conductor layer provided on the back surface, and are aligned and disposed along the signal line.
    Type: Grant
    Filed: May 5, 2023
    Date of Patent: October 3, 2023
    Assignee: FCNT LIMITED
    Inventors: Takahiro Shinojima, Hirofumi Sakamoto, Yohei Koga, Manabu Yoshikawa, Fuyuki Hikita
  • Patent number: 11756859
    Abstract: A package which comprises a carrier, electronic components mounted on the carrier, an encapsulant at least partially encapsulating the carrier and the electronic components, a clip connected to upper main surfaces of the electronic components, and an electrically conductive bulk connector which is electrically connected with and mounted above the electronic components.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: September 12, 2023
    Assignee: Infineon Technologies AG
    Inventor: Tomasz Naeve
  • Patent number: 11756857
    Abstract: An electronic circuit has three circuit carriers and two semiconductor components. A first semiconductor component contacts with its upper side an underside of a first circuit carrier, and with its underside an upper side of a second circuit carrier. The first circuit carrier has vias, with a first via connecting the first semiconductor component to a first conducting path and a second via connecting a connection element forming a second conducting path providing an integral connection between the circuit carriers. A second semiconductor component contacts the underside of the first circuit carrier and is electrically connected to the first or second conducting path. An underside of the second semiconductor component contacts an upper side of the third circuit carrier. A lateral thermal expansion coefficient of the first circuit carrier is greater than a lateral thermal expansion coefficient of both the second and the third circuit carrier.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: September 12, 2023
    Assignee: Siemens Aktiengesellschaft
    Inventors: Thomas Bigl, Alexander Hensler, Stephan Neugebauer, Stefan Pfefferlein
  • Patent number: 11728313
    Abstract: Representative techniques and devices including process steps may be employed to mitigate the potential for delamination of bonded microelectronic substrates due to metal expansion at a bonding interface. For example, a metal pad may be disposed at a bonding surface of at least one of the microelectronic substrates, where the contact pad is positioned offset relative to a TSV in the substrate and electrically coupled to the TSV.
    Type: Grant
    Filed: May 3, 2021
    Date of Patent: August 15, 2023
    Assignee: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
    Inventors: Bongsub Lee, Guilian Gao
  • Patent number: 11728318
    Abstract: A method for assembling an LED apparatus using an epitaxial layered structure comprising a first-type doped semiconductor layer, a second-type doped semiconductor layer, and an active layer between the doped semiconductor layers. The method involves depositing a conductive layer adjacent to and in ohmic contact with the first-type doped semiconductor layer. After forming a pattern masked layer on the conductive layer to expose one or more unprotected mask regions, the unprotected mask region(s) are processed to form a micropixellated structure having micropixel contact areas that are electrically isolated from each other. The method further involves placing a first contact pad over the micropixellated structure to overlap the micropixel contact areas and form a first electrode shared by a set of micro-LEDs. The micropixellated structure is also electrically coupled to a second contact pad that forms a second electrode shared by the set of micro-LEDs.
    Type: Grant
    Filed: May 9, 2022
    Date of Patent: August 15, 2023
    Assignee: META PLATFORMS TECHNOLOGIES, LLC
    Inventor: Gareth John Valentine
  • Patent number: 11721633
    Abstract: A circuit pattern, which is a second negative electrode wiring, and a horizontally extending area of a circuit pattern, which is a first negative electrode wiring, are connected electrically and mechanically by a vertically extending area of the circuit pattern and wires, which are an inter-negative-electrode wiring. As a result, N terminals and N1 terminals are equal in potential in a semiconductor device. The N terminals of a converter circuit section and the N1 terminals of an inverter circuit section are electrically connected to make the N terminals and the N1 terminals equal in potential.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: August 8, 2023
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Masaki Takahashi, Kousuke Komatsu, Rikihiro Maruyama
  • Patent number: 11710726
    Abstract: Power control and decoupling capacitance arrangements for integrated circuit devices are discussed herein. In one example, an assembly includes a first circuit assembly comprising a first circuit board coupled to an integrated circuit device, wherein the first circuit board is coupled to first surface of a system circuit board. The assembly also includes a second circuit assembly comprising a second circuit board having one or more voltage adjustment units configured to supply at least one input voltage to the integrated circuit device, wherein the second circuit board is coupled to a second surface of the system circuit board and positioned at least partially under a footprint of the integrated circuit device with respect to the system circuit board.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: July 25, 2023
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: William Paul Hovis, Gregory M. Daly, Rich Tat An, Andres Felipe Hernandez Mojica, Garrett Douglas Blankenburg
  • Patent number: 11710680
    Abstract: The present disclosure relates to a radio frequency device that includes a transfer device die and a multilayer redistribution structure underneath the transfer device die. The transfer device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion and a transfer substrate. The FEOL portion includes isolation sections and an active layer surrounded by the isolation sections. A top surface of the device region is planarized. The transfer substrate resides over the top surface of the device region. Herein, silicon crystal does not exist within the transfer substrate or between the transfer substrate and the active layer. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the transfer device die.
    Type: Grant
    Filed: December 17, 2021
    Date of Patent: July 25, 2023
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Michael Carroll
  • Patent number: 11710714
    Abstract: The present disclosure relates to a radio frequency (RF) device that includes a mold device die and a multilayer redistribution structure underneath the mold device die. The mold device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion, and a first mold compound. The FEOL portion includes an active layer formed from a strained silicon epitaxial layer, in which a lattice constant is greater than 5.461 at a temperature of 300K. The first mold compound resides over the active layer. Herein, silicon crystal does not exist between the first mold compound and the active layer. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the mold device die.
    Type: Grant
    Filed: January 11, 2022
    Date of Patent: July 25, 2023
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Michael Carroll
  • Patent number: 11706883
    Abstract: A power semiconductor module contains a power semiconductor assembly, a housing which in a housing side with an outer surface has a recess with a direction of passage in the normal direction of the outer surface, having an internal contact device which has an electrically conducting contact inside the housing to an external connection element, designed as a load terminal element, with one section in the recess and having a spring element. The connection element is designed as a rigid metallic shaped body with an inner and an outer contact surface, and the outer contact surface is accessible from the outside, and the connection element is connected to the housing via an electrically insulating and mechanically elastic retaining device such that the connection element is moveable in the direction of passage, and wherein the spring element is arranged and designed in such a way that the spring action thereof acts directly or indirectly on the connection element in the direction of passage.
    Type: Grant
    Filed: March 18, 2020
    Date of Patent: July 18, 2023
    Assignee: SEMIKRON ELEKTRONIK GMBH & CO. KG
    Inventors: Sandro Bulovic, Harald Kobolla
  • Patent number: 11705362
    Abstract: The present disclosure relates to a radio frequency (RF) device including a device substrate, a thinned device die with a device region over the device substrate, a first mold compound, and a second mold compound. The device region includes an isolation portion, a back-end-of-line (BEOL) portion, and a front-end-of-line (FEOL) portion with a contact layer and an active section. The contact layer resides over the BEOL portion, the active section resides over the contact layer, and the isolation portion resides over the contact layer to encapsulate the active section. The first mold compound resides over the device substrate, surrounds the thinned device die, and extends vertically beyond the thinned device die to define an opening over the thinned device die and within the first mold compound. The second mold compound fills the opening and directly connects the isolation portion of the thinned device die.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: July 18, 2023
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Michael Carroll
  • Patent number: 11699649
    Abstract: An electronic device (e.g., integrated circuit) and method of making the electronic device is provided that reduces a strength of an electric field generated outside a package of the electronic device proximate to the low voltage lead pins. The electronic device includes a low voltage side and a high voltage side. The low voltage side includes a low voltage die attached to a low voltage die attach pad. Similarly, the high voltage side includes a high voltage die attached to a high voltage die attach pad. Lead pins are attached to each of the low and high voltage attach pads and extend out from a package of the electronic device in an inverted direction.
    Type: Grant
    Filed: November 12, 2021
    Date of Patent: July 11, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Chang-Yen Ko, J K Ho
  • Patent number: 11693459
    Abstract: The disclosure provides a system of providing power to a chip on a mainboard, including: a first power supply, located on the mainboard, and configured to receive a first voltage and to provide a second voltage; and a second power supply and a third power supply, located on the mainboard, wherein the second power supply and the third power supply are electrically connected to the first power supply; so as to receive the second voltage, the second power supply is disposed at a first side of the chip, the third power supply is disposed at a second side of the chip, the second power supply provides a third voltage to the chip, and the third power supply provides a fourth voltage to the chip.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: July 4, 2023
    Assignee: Delta Electronics (Shanghai) CO., LTD
    Inventors: Haoyi Ye, Jianhong Zeng, Xiaoni Xin
  • Patent number: 11682651
    Abstract: Disclosed herein is a bump-on-trace interconnect with a wetted trace sidewall and a method for fabricating the same. A first substrate having conductive bump with solder applied is mounted to a second substrate with a trace disposed thereon by reflowing the solder on the bump so that the solder wets at least one sidewall of the trace, with the solder optionally wetting between at least half and all of the height of the trace sidewall. A plurality of traces and bumps may also be disposed on the first substrate and second substrate with a bump pitch of less than about 100 ?m, and volume of solder for application to the bump calculated based on at least one of a joint gap distance, desired solder joint width, predetermined solder joint separation, bump geometry, trace geometry, minimum trace sidewall wetting region height and trace separation distance.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: June 20, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY
    Inventors: Chen-Hua Yu, Chen-Shien Chen
  • Patent number: 11669671
    Abstract: A semiconductor structure includes a power grid layer (including a first metallization layer) and a set of cells. The first metallization layer includes: conductive first and second portions which provide correspondingly a power-supply voltage and a reference voltage, and which have corresponding long axes oriented substantially parallel to a first direction; and conductive third and fourth portions which provide correspondingly the power-supply voltage and the reference voltage, and which have corresponding long axes oriented substantially parallel to a second direction substantially perpendicular to the first direction. The set of cells is located below the PG layer. Each cell is monostate cell which lacks an input signal and has a single output state. The cells are arranged to overlap at least one of the first and second portions in a repeating relationship with respect to at least one of the first or second portions of the first metallization layer.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: June 6, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hiranmay Biswas, Chung-Hsing Wang, Kuo-Nan Yang
  • Patent number: 11670572
    Abstract: A semiconductor device includes a first conductive plate, a second conductive plate, first switching elements, second switching elements, a first supply terminal and a second supply terminal. The first and second conductive plates are spaced apart from each other in a first direction. The first switching elements are bonded to the first conductive plate, and are electrically connected to the second conductive plate. The second switching elements are bonded to the second conductive plate. The first supply terminal is bonded to the first conductive plate. The second supply terminal has a region that overlaps with the first supply terminal as viewed in a plan view. The second supply terminal is spaced apart from the first conductive plate and the first supply terminal in a thickness direction perpendicular to the first direction. The second supply terminal is electrically connected to the second switching elements.
    Type: Grant
    Filed: November 18, 2021
    Date of Patent: June 6, 2023
    Assignee: ROHM CO., LTD.
    Inventors: Takumi Kanda, Masaaki Matsuo, Soichiro Takahashi, Yoshitoki Inami, Kaito Inoue
  • Patent number: 11664269
    Abstract: The present disclosure relates to a radio frequency (RF) device including a device substrate, a thinned device die with a device region over the device substrate, a first mold compound, and a second mold compound. The device region includes an isolation portion, a back-end-of-line (BEOL) portion, and a front-end-of-line (FEOL) portion with a contact layer and an active section. The contact layer resides over the BEOL portion, the active section resides over the contact layer, and the isolation portion resides over the contact layer to encapsulate the active section. The first mold compound resides over the device substrate, surrounds the thinned device die, and extends vertically beyond the thinned device die to define an opening over the thinned device die and within the first mold compound. The second mold compound fills the opening and directly connects the isolation portion of the thinned device die.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: May 30, 2023
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Michael Carroll
  • Patent number: 11664319
    Abstract: A method for forming a silicon photonics interposer having through-silicon vias (TSVs). The method includes forming vias in a front side of a silicon substrate and defining primary structures for forming optical devices in the front side. Additionally, the method includes bonding a first handle wafer to the front side and thinning down the silicon substrate from the back side and forming bumps at the back side to couple with a conductive material in the vias. Furthermore, the method includes bonding a second handle wafer to the back side and debonding the first handle wafer from the front side to form secondary structures based on the primary structures. Moreover, the method includes forming pads at the front side to couple with the bumps at the back side before completing final structures based on the secondary structures and debonding the second handle wafer from the back side.
    Type: Grant
    Filed: June 17, 2022
    Date of Patent: May 30, 2023
    Assignee: MARVELL ASIA PTE LTD.
    Inventors: Liang Ding, Radhakrishnan L. Nagarajan
  • Patent number: 11658101
    Abstract: In a described example, an apparatus includes: a package substrate having a die pad configured for mounting a semiconductor die, a first lead connected to the die pad, and a second lead spaced from and electrically isolated from the die pad; a spacer dielectric mounted on the die pad; a semiconductor die including a temperature sensor mounted on the spacer dielectric; electrical connections coupling the semiconductor die to the second lead; and mold compound covering the semiconductor die, the die pad, the electrical connections, and a portion of the package substrate, with portions of the first lead and portions of the second lead exposed from the mold compound to form terminals for a packaged temperature sensor device.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: May 23, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Enis Tuncer
  • Patent number: 11647600
    Abstract: Various embodiments of a sealed package and a method of forming such package are disclosed. The package includes a housing having an inner surface and an outer surface, a dielectric substrate having a first major surface and a second major surface, and a dielectric bonding ring disposed between the first major surface of the dielectric substrate and the housing, where the dielectric bonding ring is hermetically sealed to both the first major surface of the dielectric substrate and the housing. The package further includes an electronic device disposed on the first major surface of the dielectric substrate, and a power source disposed at least partially within the housing and electrically connected to the electronic device.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: May 9, 2023
    Assignee: Medtronic, Inc.
    Inventors: Christian S. Nielsen, Rajesh V. Iyer, Gordon O. Munns, Andrew J. Ries, Andrew J. Thom
  • Patent number: 11631610
    Abstract: The present disclosure relates to a radio frequency (RF) device including a device substrate, a thinned device die with a device region over the device substrate, a first mold compound, and a second mold compound. The device region includes an isolation portion, a back-end-of-line (BEOL) portion, and a front-end-of-line (FEOL) portion with a contact layer and an active section. The contact layer resides over the BEOL portion, the active section resides over the contact layer, and the isolation portion resides over the contact layer to encapsulate the active section. The first mold compound resides over the device substrate, surrounds the thinned device die, and extends vertically beyond the thinned device die to define an opening over the thinned device die and within the first mold compound. The second mold compound fills the opening and directly connects the isolation portion of the thinned device die.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: April 18, 2023
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Michael Carroll
  • Patent number: 11626813
    Abstract: The invention relates to a half bridge module in a traction inverter for a power electronics unit in an electric or hybrid vehicle, comprising a substrate, semiconductor switching elements on a first side of the substrate, power connections, to which power lines that conduct electrical traction energy are connected, signal connections, to which signal lines are connected for switching the semiconductor switching elements, and a casting compound, which encompasses the substrate and the semiconductor switching elements on the first side of the substrate, wherein the power connections and the signal connections are accessed from the first side of the substrate, such that the power connections and the signal connections extend through the casting compound, seen from the first side of the substrate, and are located within a base area spanning the substrate, seen from the direction they pass through the casting compound.
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: April 11, 2023
    Assignee: ZF Friedrichshafen AG
    Inventors: Manuel Raimann, Michael Kohr, Marcus Berner
  • Patent number: 11625070
    Abstract: A display device includes a display panel in which a plurality of pixels is defined, a back cover disposed on a rear surface of the display panel, a roller which is connected to the back cover to wind or unwind the back cover and the display panel, and a protective sheet which is disposed on a rear surface of the back cover and has a relatively small tensile strength in a rolling direction of the roller to reduce the stress generated during rolling and improve the lateral rigidity of the display unit.
    Type: Grant
    Filed: July 13, 2021
    Date of Patent: April 11, 2023
    Assignee: LG Display Co., Ltd.
    Inventors: ChounSung Kang, GeunChang Park
  • Patent number: 11621215
    Abstract: In a described example, an apparatus includes: a lead frame having a first portion and having a second portion electrically isolated from the first portion, the first portion having a side surface normal to a planar opposite surface, and having a recessed edge that is notched or chamfered and extending between the side surface and a planar device side surface; a spacer dielectric mounted to the planar device side surface and partially covered by the first portion, and extending beyond the first portion; a semiconductor die mounted to the spacer dielectric, the semiconductor die partially covered by the spacer dielectric and extending beyond the spacer dielectric; the second portion of the lead frame comprising leads coupled to the semiconductor die by electrical connections; and mold compound covering the semiconductor die, the electrical connections, the spacer dielectric, and partially covering the first portion and the second portion.
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: April 4, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Enis Tuncer
  • Patent number: 11605613
    Abstract: According to an embodiment, provided is a semiconductor device includes an insulating substrate; a first main terminal; a second main terminal; an output terminal; a first metal layer connected to the first main terminal; a second metal layer connected to the second main terminal; a third metal layer disposed between the first metal layer and the second metal layer and connected to the output terminal; a first semiconductor chip and a second semiconductor chip provided on the first metal layer; and a third semiconductor chip and a fourth semiconductor chip provided on the third metal layer. The second metal layer includes a first slit. Alternatively, the third metal layer includes a second slit.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: March 14, 2023
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Tomohiro Iguchi
  • Patent number: 11581232
    Abstract: A semiconductor device having a channel between active sections or portions of the device is disclosed. An elastic material, such as dielectric or a polymer, is deposited into the channel and cured to increase flexibility and thermal expansion properties of the semiconductor device. The elastic material reduces the thermal and mechanical mismatch between the semiconductor device and the substrate to which the semiconductor device is coupled in downstream processing to improve reliability. The semiconductor device may also include a plurality of channels formed transverse with respect to each other. Some of the channels extend all the way through the semiconductor device, while other channels extend only partially through the semiconductor device.
    Type: Grant
    Filed: May 21, 2020
    Date of Patent: February 14, 2023
    Assignee: STMICROELECTRONICS PTE LTD
    Inventor: Jing-En Luan
  • Patent number: 11581809
    Abstract: A power converter circuit included in a computer system that regulated a power supply voltage used by other circuits in the computer system. The power converter includes a primary control circuit that selectively activates multiple phase circuits coupled to respective driver circuits, which are coupled to a power supply node via respective inductors. Some of the driver circuits are located on a separate integrated circuit from the primary control circuit and the multiple phase circuits.
    Type: Grant
    Filed: June 9, 2021
    Date of Patent: February 14, 2023
    Assignee: Apple Inc.
    Inventors: Debashish Mahapatra, Vincenzo Bisogno, Francesco Griseta, Sarfraz Shaikh
  • Patent number: 11569161
    Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a package substrate, that comprises a bumpout region on a first surface of the package substrate, and a pin region on a second surface of the package substrate. In an embodiment, a data path from the bumpout region to the pin region is included in the electronic package. In an embodiment, a ground path brackets the data path from the bumpout region to the pin region.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: January 31, 2023
    Assignee: Intel Corporation
    Inventors: Chong Zhao, James McCall, Michael Gutzmann
  • Patent number: 11569634
    Abstract: A light emitting device includes: a base having a first stepped portion and a second stepped portion; a light emitting element; an electronic member configured to be irradiated by light emitted from the light emitting element; a first wiring region located on the first stepped portion; a second wiring region located on the second stepped portion; wires connected to the light emitting element and the electronic member. The wires includes a first and second wires. The first wire has a first end that is connected to the first wiring region, and a second end. The second wire has a first end that is connected to the second wiring region, and a second end. A position of the second end of the first wire relative to the bottom face is lower than a position of the second end of the second wire relative to the bottom face.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: January 31, 2023
    Assignee: NICHIA CORPORATION
    Inventors: Shota Murakami, Soichiro Miura
  • Patent number: 11552003
    Abstract: The present disclosure relates to a radio frequency device that includes a transfer device die and a multilayer redistribution structure underneath the transfer device die. The transfer device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion and a transfer substrate. The FEOL portion includes isolation sections and an active layer surrounded by the isolation sections. A top surface of the device region is planarized. The transfer substrate resides over the top surface of the device region. Herein, silicon crystal does not exist within the transfer substrate or between the transfer substrate and the active layer. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the transfer device die.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: January 10, 2023
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Michael Carroll
  • Patent number: 11552036
    Abstract: The present disclosure relates to a radio frequency (RF) device that includes a mold device die and a multilayer redistribution structure underneath the mold device die. The mold device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion, and a first mold compound. The FEOL portion includes an active layer formed from a strained silicon epitaxial layer, in which a lattice constant is greater than 5.461 at a temperature of 300K. The first mold compound resides over the active layer. Herein, silicon crystal does not exist between the first mold compound and the active layer. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the mold device die.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: January 10, 2023
    Assignee: QORVO US, INC.
    Inventors: Julio C. Costa, Michael Carroll
  • Patent number: 11552124
    Abstract: A display apparatus includes at least one substrate with several penetration holes, several displaying units and several switch devices disposed at different sides of the at least one substrate, and at least one bonding material filling up the penetration holes, wherein the displaying units and the switch devices are connected to each other through the at least one bonding material.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: January 10, 2023
    Assignee: INNOLUX CORPORATION
    Inventor: Kuan-Feng Lee
  • Patent number: 11545418
    Abstract: A device includes a relative temperature detector configured to determine a temperature difference between a device temperature sensed near a switch device and an ambient temperature sensed outside the switch device. The relative temperature detector is configured to generate a relative temperature output signal based on comparing the temperature difference to a relative temperature threshold. A power detector is configured to generate a power level signal based on comparing an indication of switch power of the switch device to a power threshold. The power level signal specifies whether the indication of switch power is above or below the power threshold. A thermal capacity control is configured to disable the switch device based on the power level signal specifying that the indication of switch power is above the power threshold and based on the relative temperature output signal indicating the temperature difference is above the relative temperature threshold.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: January 3, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ankur Chauhan, Paragkumar Chaudhari, Vishal Gupta
  • Patent number: 11533012
    Abstract: An integrated power control assembly mounted on an axial end of a three-phase motor includes a substrate, two input busbars each of positive and negative polarities alternatively spaced apart on the substrate, a plurality of sets of paired devices, and three output busbars corresponding to the three phases of the motor, wherein a set of paired devices includes a switching semiconductor and a diode. An inner input busbar has edges adjacent to an inner input busbar of opposite polarity and an outer input busbar of opposite polarity and configured to have at least twice as many devices as the outer input busbars. One or more sets of paired devices are disposed axially on outer input busbars and on inner input busbars along the edges. An individual output busbar is disposed over and electrically coupled to one or more sets of paired devices disposed on adjacent input busbars of opposite polarity.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: December 20, 2022
    Assignee: TOYOTA MOTOR ENGINEERING & MANUFACTURING NORTH AMERICA, INC.
    Inventors: Shohei Suenaga, Shailesh N. Joshi, Danny J. Lohan, Yanghe Liu
  • Patent number: 11528044
    Abstract: A radio frequency module includes a module board; a first semiconductor device containing a first power amplifier and a second power amplifier; and a second semiconductor device containing a first switch, the first switch including a first terminal connected to the first power amplifier and a second terminal connected to the second power amplifier. In the radio frequency module, the first semiconductor device and the second semiconductor device are stacked together and disposed on the module board. An aspect of such a radio frequency module is that it is possible to achieve a compact form factor, although still provide RF transmit and receive capability. The RF module also includes external-connection terminals and a LNA, and the first semiconductor device and the low noise amplifier are disposed on mutually opposite surfaces of the module board.
    Type: Grant
    Filed: March 24, 2021
    Date of Patent: December 13, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Naoya Matsumoto, Takayuki Shinozaki
  • Patent number: 11528029
    Abstract: An IC, operable at a first clock phase, includes first and second IOs and a PLL. The PLL includes a control circuit, an input to receive a first clock signal, an output to output a second clock signal, and a first detector to generate a first phase difference signal from the first and second clock signals. The IC includes a second phase detector that is coupled to the PLL's output to receive the second clock signal and is coupled to the first IO to receive a third clock single from a second IC, which is operable at a second clock phase. The second detector generates a second phase difference signal from the second and third clock signals. If the PLL uses the second phase difference signal to generate the second clock signal, then the second clock signal is synchronized with the third clock signal for synchronous data transfer.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: December 13, 2022
    Assignee: Intel Corporation
    Inventors: Lai Guan Tang, Ankireddy Nalamalpu, Dheeraj Subbareddy
  • Patent number: 11528809
    Abstract: A BGA structure having larger solder balls in high stress regions of the array is disclosed. The larger solder balls have higher solder joint reliability (SJR) and as such may be designated critical to function (CTF), whereby the larger solder balls in high stress regions carry input/output signals between a circuit board and a package mounted thereon. The larger solder balls are accommodated by recessing each ball in the package substrate, the circuit board, or both the package substrate and the circuit board. Additionally, a ball attach method for mounting a plurality of solder balls having different average diameters is disclosed.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: December 13, 2022
    Assignee: Tahoe Research, Ltd.
    Inventors: Md Altaf Hossain, Scott A. Gilbert