Having Power Distribution Means (e.g., Bus Structure) Patents (Class 257/691)
  • Patent number: 10734319
    Abstract: In some implementations, a substrate for coupling to an integrated circuit includes multiple layers. Each of the multiple layers has, in a particular region of the substrate, a repeating pattern of regions corresponding to power and ground. The multiple layers include (i) a top layer having, in the particular region, power contacts and ground contacts for coupling to an integrated circuit and (ii) a bottom layer having, in the particular region, power contacts and ground contacts for coupling to another device. At least one layer of the multiple layers has a repeating pattern of signal traces that extend along and are located between the regions corresponding to ground in the at least one layer.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: August 4, 2020
    Assignee: Google LLC
    Inventors: Jin Young Kim, Zhonghua Wu
  • Patent number: 10707753
    Abstract: The present disclosure describes aspects of power regulation with charge pumps. In some aspects, an integrated circuit (IC) includes multiple processor cores and a power input connected to an internal power rail of the IC. The IC may also comprise embedded charge pumps coupled between the internal power rail of the IC and respective input power rails of the multiple processor cores. Capacitors of the embedded charge pumps may be implemented with on-die capacitors suitable for integration with a die of the circuit to facilitate the embedding of the charge pumps. Alternately or additionally, separate input power rails of the processor cores and the embedded charge pumps may enable more-efficient power regulation or power management on a per-processor core basis, such as when a processor core is throttled or idled to reduce power consumption.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: July 7, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Marko Koski, Charles Tuten
  • Patent number: 10707143
    Abstract: A plug-in type power module includes a power unit and a heat-transfer unit vertically disposed on the power unit and extending outwardly away from two sides of the power unit. A first ceramic layer is disposed between the power unit and the heat-transfer unit. Therefore, heat generated by the power unit can be transferred from the first ceramic layer to the heat-transfer unit to increase the speed of heat dissipation. A subsystem having the plug-in type power module is also provided.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: July 7, 2020
    Assignee: Industrial Technology Research Institute
    Inventors: Shu-Jung Yang, Yu-Lin Chao, Chun-Kai Liu, Ming Kaan Liang, Jiin Shing Perng
  • Patent number: 10692817
    Abstract: A method includes embedding a die in a molding material; forming a first dielectric layer over the molding material and the die; forming a conductive line over an upper surface of the first dielectric layer facing away from the die; and forming a second dielectric layer over the first dielectric layer and the conductive line. The method further includes forming a first trench opening extending through the first dielectric layer or the second dielectric layer, where a longitudinal axis of the first trench is parallel with a longitudinal axis of the conductive line, and where no electrically conductive feature is exposed at a bottom of the first trench opening; and filling the first trench opening with an electrically conductive material to form a first ground trench.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: June 23, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Ya Huang, Chung-Hao Tsai, Chuei-Tang Wang, Chen-Hua Yu, Chih-Yuan Chang
  • Patent number: 10685925
    Abstract: Systems and methods that facilitate resistance and capacitance balancing are presented. In one embodiment, a system comprises: a plurality of ground lines configured to ground components; and a plurality of signal bus lines interleaved with the plurality of ground lines, wherein the interleaving is configured so that plurality of signal bus lines and plurality of ground lines are substantially evenly spaced and the plurality of signal bus lines convey a respective plurality of signals have similar resistance and capacitance constants that are balanced. The plurality of signals can see a substantially equal amount ground surface and have similar amounts of capacitance. The plurality of signal bus lines can have similar cross sections and lengths with similar resistances. The plurality of signal bus lines interleaved with the plurality of ground lines can be included in a two copper layer interposer design with one redistribution layer (RDL).
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: June 16, 2020
    Assignee: NVIDIA CORPORATION
    Inventors: Jim Dobbins, Sheetal Jain, Don Templeton, Yaping Zhou, Wenjun Shi, Sunil Sudhakaran
  • Patent number: 10660201
    Abstract: An example sensor interposer employing castellated through-vias formed in a PCB includes a planar substrate defining a plurality of castellated through-vias; a first electrical contact formed on the planar substrate and electrically coupled to a first castellated through-via; a second electrical contact formed on the planar substrate and electrically coupled to a second castellated through-via, the second castellated through-via electrically isolated from the first castellated through-via; and a guard trace formed on the planar substrate, the guard trace having a first portion formed on a first surface of the planar substrate and electrically coupling a third castellated through-via to a fourth castellated through-via, the guard trace having a second portion formed on a second surface of the planar substrate and electrically coupling the third castellated through-via to the fourth castellated through-via, the guard trace formed between the first and second electrical contacts to provide electrical isolation b
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: May 19, 2020
    Assignee: DexCom, Inc.
    Inventors: Sean Frick, Louis Jung, David Lari
  • Patent number: 10651127
    Abstract: Ring-in-ring stiffeners on a semiconductor package substrate includes a passive device that is seated across the ring stiffeners. The ring-in-ring stiffeners are also electrically coupled to traces in the semiconductor package substrate through electrically conductive adhesive that bonds a given ring stiffener to the semiconductor package substrate. The passive device is embedded between the two ring stiffeners to create a smaller X-Y footprint as well as a lower Z-direction profile.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: May 12, 2020
    Assignee: Intel Corporation
    Inventors: Jackson Chung Peng Kong, Bok Eng Cheah, Kooi Chi Ooi, Paik Wen Ong
  • Patent number: 10615097
    Abstract: A chip carrier which comprises a thermally conductive and electrically insulating sheet, a first electrically conductive structure on a first main surface of the sheet, and a second electrically conductive structure on a second main surface of the sheet, wherein the first electrically conductive structure and the second electrically conductive structure extend beyond a lateral edge of the sheet.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: April 7, 2020
    Assignee: Infineon Technologies AG
    Inventors: Andreas Grassmann, Wolfram Hable, Juergen Hoegerl, Angela Kessler, Ivan Nikitin, Achim Strass
  • Patent number: 10600765
    Abstract: A technique disclosed in the specification relates to a semiconductor device capable of minimizing restrictions on wire bonding activities and to a method for producing the semiconductor device. The semiconductor device of the present technique includes: a plurality of semiconductor chips disposed on a circuit pattern within a case defined by an outer frame in a plan view; and bonding wires for electrically connecting the semiconductor chips and the circuit pattern together. The semiconductor chips are arranged along a longer-side direction of the case. The bonding wires are strung along the longer-side direction of the case.
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: March 24, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventor: Mituharu Tabata
  • Patent number: 10580734
    Abstract: A ground isolation transmission line package device includes (1) ground isolation planes between, (2) ground isolation lines surrounding, or (3) such ground planes between and such ground isolation lines surrounding horizontal data signal transmission lines (e.g., metal signal traces) that are horizontally routed through the package device. The (1) ground isolation planes between, and/or (2) ground isolation lines electrically shield the data signals transmitted in signal lines, thus reducing signal crosstalk between and increasing electrical, isolation of the data signal transmission lines. In addition, data signal transmission lines may be tuned using eye diagrams to select signal line widths and ground isolation line widths that provide optimal data transmission performance.
    Type: Grant
    Filed: December 26, 2015
    Date of Patent: March 3, 2020
    Assignee: Intel Corporation
    Inventors: Yu Amos Zhang, Gabriel Regalado Silva, Zhiguo Qian, Kemal Aygun
  • Patent number: 10515891
    Abstract: A radial solder ball pattern is described for a printed circuit board and for a chip to be attached to the printed circuit board is described. In one example, the pattern comprises a central power connector area having a plurality of power connectors to provide power to an attached chip, a signal area having a plurality of signal connectors to communicate signals to the attached chip, an edge area surrounding the signal area and the central power connector area, and a plurality of traces each coupled to a signal connector, the traces extending from the respective coupled signal connector away from the central power connector to connect to an external component, wherein the signal connectors are placed in rows, the rows having a greater separation near the edge area than near the central area.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: December 24, 2019
    Assignee: Intel Corporation
    Inventors: Eng Fook Chan, Wei Chung Lee, Zhi Wei Low
  • Patent number: 10506744
    Abstract: Insulating properties between a metallic member supporting a power semiconductor module and an input/output terminal of the power semiconductor module are secured. In a power conversion device in which a bus bar of a connecting member is connected to an input/output terminal and the like of a semiconductor module protruding through an opening of a metallic member, the connecting member includes extended portions which extend in a space between the bus bar and the opening of the metallic member.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: December 10, 2019
    Assignee: Hitachi Automotive Systems, Ltd.
    Inventors: Masashi Kosuga, Takeshi Tajiri, Hidehiko Takahara
  • Patent number: 10497642
    Abstract: The present disclosure relates to an integrated power semiconductor packaging apparatus and a power converter containing the integrated power semiconductor packaging apparatus. The integrated power semiconductor packaging apparatus comprises a plurality of power semiconductor devices and an electrically insulative substrate formed integrally. The electrically insulative substrate comprises a flat surface, at least one separation wall protruding from the flat surface and a flow channel inside the electrically insulative substrate. The at least one separation wall is configured to separate the flat surface into a plurality of flat areas, and each of the plurality of flat areas is configured to receive one of the plurality of power semiconductor devices. The flow channel is configured for allowing a coolant flowing through to remove heat from the plurality of power semiconductor devices.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: December 3, 2019
    Assignee: General Electric Company
    Inventors: Saijun Mao, Bo Qu, Jingkui Shi, He Xu, Jie Shen, Lin Lan, Rui Li, Zhihui Yuan, Alistair Martin Waddell, Stefan Schroeder, Marius Michael Mechlinski, Mark Aaron Chan
  • Patent number: 10490502
    Abstract: A power distribution network adapted to provide power to a plurality of components in an integrated circuit is provided. The power distribution network includes a power distribution trunk path, a plurality of first power distribution branch paths, and a plurality of second power distribution branch paths. The power distribution trunk path is used for transmitting the power. A long axis direction of the power distribution trunk path is a first direction. The first power distribution branch paths and the second power distribution branch paths are electrically connected to the power distribution trunk path. A long axis direction of the first power distribution branch paths is a second direction different from the first direction. A long axis direction of the second power distribution branch paths is a third direction different from the first direction and the second direction.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: November 26, 2019
    Assignee: Faraday Technology Corp.
    Inventors: Yi-Yeh Yang, Wang-Chin Chen, Po-Chen Lo, Shang-Ru Lin, Jen-Hsing Lin, Jin-Cheng Chen
  • Patent number: 10485093
    Abstract: Provided are both a flexible printed board, in which heat dissipation performance can be improved in without using an aluminum heal dissipating material, which is light in weight, has good processability and can be reduced in cost, and a method for manufacturing such a flexible printed board. The flexible printed board is a flexible printed board 10 on which a power consuming load is mounted, including: a front surface heat dissipation layer 30 made of a copper foil and having a circuit portion on which the load is mounted; a thermally conductive resin layer 20 having the front surface heat dissipation layer 30 laminated to a front surface side thereof and having a thermal conductivity of 0.49 W/mK or more; and a rear surface heat dissipation layer made of a copper foil, laminated to a rear surface side of the thermally conductive resin layer 20, and having a thickness of 100 to 400% with respect to the front surface heat dissipation layer 30.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: November 19, 2019
    Assignee: NIPPON MEKTRON, LTD.
    Inventors: Satoshi Ebihara, Takahisa Kato, Nobuto Sasaki, Kazuyuki Azuma, Tomohiro Shimokawaji, Takeo Wakabayashi
  • Patent number: 10461032
    Abstract: A substrate with an embedded stacked through-silicon via die is described. For example, an apparatus includes a first die and a second die. The second die has one or more through-silicon vias disposed therein (TSV die). The first die is electrically coupled to the TSV die through the one or more through-silicon vias. The apparatus also includes a coreless substrate. Both the first die and the TSV die are embedded in the coreless substrate.
    Type: Grant
    Filed: February 1, 2013
    Date of Patent: October 29, 2019
    Assignee: Intel Corporation
    Inventors: Javier Soto Gonzalez, Houssam Jomaa
  • Patent number: 10461009
    Abstract: A package includes a substrate having a conductive layer, and the conductive layer comprises an exposed portion. A die stack is disposed over the substrate and electrically connected to the conductive layer. A high thermal conductivity material is disposed over the substrate and contacting the exposed portion of the conductive layer. The package further includes a contour ring over and contacting the high thermal conductivity material.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: October 29, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wensen Hung, Szu-Po Huang, Hsiang-Fan Lee, Kim Hong Chen, Chi-Hsi Wu, Shin-Puu Jeng
  • Patent number: 10439317
    Abstract: The interposer can include a substrate and first and second electrical connectors mounted to the substrate. The first electrical connector is configured to mate with a hard disk drive subassembly, and the second electrical connector is configured to mate with a flat flex circuit subassembly. The hard disk drive subassembly includes a hard disk drive case, a printed circuit board, and a third electrical connector mounted to the printed circuit board. The first and third electrical connectors are configured to mate with each other through the hard disk drive case so as to mate the interposer to the hard disk drive subassembly.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: October 8, 2019
    Assignee: FCI USA LLC
    Inventors: David C. Horchler, Robert E. Marshall
  • Patent number: 10418357
    Abstract: A protection circuit may include a first power line and a second power line, a plurality of high voltage interconnections, a plurality of low voltage interconnections, first and second pickup active regions, a high voltage protection transistor, and a low voltage protection transistor. The first power line and the second power line extending in parallel to each other while facing each other, and a plurality of high voltage interconnections are coupled to the first power line and extend toward the second power line while being spaced apart from each other. The plurality of low voltage interconnections are coupled to the second power line and extend toward the first power line while being spaced apart from each other. The first pickup active region extends across the plurality of high voltage interconnections and the second pickup active region extends across the plurality of low voltage interconnections.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: September 17, 2019
    Assignee: SK hynix Inc.
    Inventor: Yun Soo Han
  • Patent number: 10403558
    Abstract: A power system has a single-side-cooled power module including a contiguous five-layer substrate of two insulative layers interleaved with three conductive layers. A center one of the conductive layers is partitioned to define discrete spaced apart positive terminal and output terminal portions, and an outer of the conductive layers defines a negative terminal portion such that the positive terminal and negative terminal portions overlap. The power system also has semiconductors respectively in direct contact with the positive terminal and output terminal portions without directly contacting the other layers.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: September 3, 2019
    Assignee: Ford Global Technologies, LLC
    Inventors: Fan Xu, Lihua Chen, Sadashi Seto, Shuitao Yang, Yan Zhou, Baoming Ge
  • Patent number: 10398031
    Abstract: An aspect includes one or more board layers. A first chip cavity is formed within the one or more board layers, wherein a first Josephson amplifier or Josephson mixer is disposed within the first chip cavity. The first Josephson amplifier or Josephson mixer comprises at least one port, each port connected to at least one connector disposed on at least one of the one or more board layers, wherein at least one of the one or more board layers comprises a circuit trace formed on the at least one of the one or more board layers.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: August 27, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Baleegh Abdo, Nicholas T. Bronn, Oblesh Jinka, Salvatore B. Olivadese
  • Patent number: 10381295
    Abstract: Embodiments of a packaged semiconductor device are provided, which includes a flag of a lead frame having a top surface and a bottom surface; a redistribution layer (RDL) structure formed on the top surface of the flag, the RDL structure including a first connection path having a first exposed bonding surface in a top surface of the RDL structure; and a first wirebond connected to the first exposed bonding surface and to a lead of the lead frame.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: August 13, 2019
    Assignee: NXP USA, Inc.
    Inventors: Michael Vincent, Ryan Hooper, Dwight Daniels
  • Patent number: 10373894
    Abstract: The invention discloses a package structure made of the combination of a device carrier and a modifiable substrate. In one embodiment, a recess is formed in the device carrier and a conductive element is disposed on the substrate, wherein the substrate is disposed on the device carrier and the conductive element is located in the recess of the device carrier. The conductive pattern in the substrate is electrically connected to the device carrier and I/O terminals of the first conductive element. The invention also discloses a method for manufacturing a package structure made of the combination of a device carrier and a modifiable substrate. In one embodiment, a portion of the conductive pattern in the substrate can be modified.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: August 6, 2019
    Assignee: CYNTEC CO., LTD
    Inventors: Bau-Ru Lu, Jeng-Jen Li, Kun-Hong Shih, Kaipeng Chiang
  • Patent number: 10373951
    Abstract: Disclosed embodiments include an embedded thin-film capacitor and a magnetic inductor that are assembled in two adjacent build-up layers of a semiconductor package substrate. The thin-film capacitor is seated on a surface of a first of the build-up layers and the magnetic inductor is partially disposed in a recess in the adjacent build up layer. The embedded thin-film capacitor and the integral magnetic inductor are configured within a die shadow that is on a die side of the semiconductor package substrate.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: August 6, 2019
    Assignee: Intel Corporation
    Inventors: Cheng Xu, Rahul Jain, Seo Young Kim, Kyu Oh Lee, Ji Yong Park, Sai Vadlamani, Junnan Zhao
  • Patent number: 10356966
    Abstract: An electronic module is provided. The electronic module includes a bracket, a first electronic component and a second electronic component. The bracket includes a housing and a barrier rib, and a conductive paste is coated on the barrier rib. The first electronic component and a second electronic component, are accommodated in the bracket and spaced from each other by the barrier rib, and electrically connected to each other through the conductive paste. A terminal device and a bracket are also provided.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: July 16, 2019
    Assignee: Guangdong Oppo Mobile Telecommunications Corp., LTD.
    Inventors: Yi Wei, Yong Li, Peiju Chen
  • Patent number: 10345939
    Abstract: A display panel includes a display substrate including a display region and a non-display region surrounding the display region, a pad unit being positioned on a side region of the non-display region, and a touch substrate on the display substrate and bonded to the display substrate, the touch substrate including an input sensing unit overlapping the display region of the display substrate, a first extended portion extending from a side portion of the input sensing unit and overlapping the pad unit of the display substrate, and a second extended portion extending from a side portion of the input sensing unit and overlapping the pad unit of the display substrate, the second extended portion being spaced apart from the first extended portion, wherein a portion of the pad unit is exposed between the first and second extended portions.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: July 9, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Yun-ho Kim
  • Patent number: 10347608
    Abstract: A power module includes a first bus bar having a first plurality of tabs, wherein each of the first plurality of tabs is electrically coupled to a respective conductive trace of a plurality of conductive traces disposed on a first side; a second bus bar having a second plurality of tabs, wherein each of the second plurality of tabs is electrically coupled to a respective conductive trace of a plurality of conductive traces disposed on a second side; and a third bus bar having a third plurality of tabs, wherein at least one tab of the third plurality of tabs is electrically coupled to a respective conductive trace of the plurality of conductive traces disposed on the first side and at least one tab of the third plurality of tabs is electrically coupled to a respective conductive trace of the plurality of conductive traces disposed on the second side.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: July 9, 2019
    Assignee: GENERAL ELECTRIC COMPANY
    Inventors: Brian Lynn Rowden, Ljubisa Dragoljub Stevanovic
  • Patent number: 10347596
    Abstract: The application provides an apparatus, including a first section, a second section, and a first bonding wire group, where the first bonding wire group includes at least three first bonding wire units. The first bonding wire unit includes at least one arc-shaped bonding wire, one end and the other end of the first bonding wire unit are electrically connected to electrodes of the first section and the second section, respectively, where arc heights of first bonding wire units located at two sides of the first bonding wire group are higher than an arc height of a first bonding wire unit at another position, and an arc height of a first bonding wire unit located in a central area of the first bonding wire group is lower than an arc height of a first bonding wire unit at another position.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: July 9, 2019
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: An Huang, Yanhai Lin, Wei Liu
  • Patent number: 10340199
    Abstract: A packaging substrate includes a core layer having a first surface and a second surface. A group of ground pads is disposed on the second surface within a central region. A group of first power pads is disposed on the second surface within the central region. A plurality of signal pads is disposed on the second surface within a peripheral region that encircles the central region on the second surface. A first block-type via is embedded in the core layer within the central region. The group of ground pads is electrically connected to the first block-type via. A second block-type via is embedded in the core layer within the central region. The group of first power pads is electrically connected to the second block-type via.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: July 2, 2019
    Assignee: MediaTek Inc.
    Inventors: Wen-Sung Hsu, Tai-Yu Chen
  • Patent number: 10338031
    Abstract: A component-embedded substrate includes a multilayer body including a plurality of insulating layers stacked in a stacking direction, an embedded component embedded in the multilayer body, and planar conductors disposed on both sides of the embedded component in the stacking direction, the planar conductors overlapping the embedded component. The planar conductors each include a plurality of openings that overlap the embedded component over substantially the entire region occupied by the embedded component, as seen in the stacking direction.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: July 2, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Shigeru Tago, Hirofumi Shinagawa, Toshiro Adachi
  • Patent number: 10312210
    Abstract: The invention provides a semiconductor package. The semiconductor package includes a base having a device-attach surface and a solder-ball attach surface opposite to the device-attach surface. A conductive via is disposed passing through the base. The conductive via includes a first terminal surface aligned to the device-attach surface of the base. A semiconductor die is mounted on the base by a conductive structure. The conductive structure is in contact with the first terminal surface of the conductive via.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: June 4, 2019
    Assignee: MediaTek Inc.
    Inventors: Ching-Liou Huang, Ta-Jen Yu
  • Patent number: 10312198
    Abstract: A semiconductor device package includes a lead frame, an electronic component, a package body, at least one conductive via and a conductive layer. The lead frame includes a paddle, a connection element and a plurality of leads. The electronic component is disposed on the paddle. The package body encapsulates the electronic component and the lead frame. The at least one conductive via is disposed in the package body, electrically connected to the connection element, and exposed from the package body. The conductive layer is disposed on the package body and the conductive via.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: June 4, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Shao-Lun Yang, Yu-Shun Hsieh, Chia Yi Cheng, Hong Jie Chen, Shih Yu Huang
  • Patent number: 10304767
    Abstract: An object of the present invention is to improve the degree of freedom in the wiring design of a wiring substrate configuring a semiconductor device. Lands having an NSMD structure and a land-on-through-hole structure are arranged at positions not overlapping with a plurality of leads arranged on a chip loading surface of a wiring substrate in transparent plan view on the outer peripheral side of a mounting surface of the wiring substrate configuring a semiconductor device having a BGA package structure. On the other hand, land parts having the NSMD structure and to which lead-out wiring parts are connected are arranged at positions overlapping with the leads arranged on the chip loading surface of the wiring substrate in transparent plan view on the inner side than the group of lands in the mounting surface of the wiring substrate.
    Type: Grant
    Filed: April 17, 2018
    Date of Patent: May 28, 2019
    Assignee: Renesas Electronics Corporation
    Inventor: Tatsuya Kobayashi
  • Patent number: 10297522
    Abstract: A semiconductor package structure and manufacturing method thereof are provided. Firstly, a first surface mounting unit, a first printed circuit board, and a second printed circuit board are provided. The first surface mounting unit includes a first chip and a first conductive frame, and the first conductive frame has a first carrier board and a first metal member connected to the first carrier board. A first side of the first chip is electrically connected to the first carrier board of the first conductive frame. A second side of the first chip and the first metal member are connected to the first circuit board by a first pad and a second pad respectively. The second circuit board is connected to the first carrier board and hence, the first surface mounting unit is located between the first circuit board and the second circuit board.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: May 21, 2019
    Assignee: NIKO SEMICONDUCTOR CO., LTD.
    Inventor: Chih-Cheng Hsieh
  • Patent number: 10284109
    Abstract: An electronic device includes a first substrate, a wiring substrate (second substrate) disposed over the first substrate, and an enclosure (case) in which the first substrate and the wiring substrate are accommodated and that has a first side and a second side. A driver component (semiconductor component) is mounted on the wiring substrate. A gate electrode of a first semiconductor component is electrically connected to the driver component via a lead disposed on a side of the first side and a wiring disposed between the driver component and the first side. A gate electrode of a second semiconductor component is electrically connected to the driver component via a lead disposed on a side of the second side and a wiring disposed between the driver component and the second side.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: May 7, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Koji Bando, Kuniharu Muto, Hideaki Sato
  • Patent number: 10283488
    Abstract: A semiconductor module includes: a substrate having an insulating layer and a connecting portion connecting front and rear surfaces of the insulating layer; a first pattern on a front surface of the substrate; a second pattern on a rear surface of the substrate; a first semiconductor device disposed adjacent to the front surface of the substrate and including a first switching device having a lateral structure; a second semiconductor device disposed adjacent to the rear surface of the substrate and including a second switching device having the lateral structure; and a capacitor. A path formed by the first pattern and the first semiconductor device and a path formed by the second pattern and the second semiconductor device are opposed to each other across the substrate, and in the paths, currents flow in directions opposite to each other.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: May 7, 2019
    Assignee: DENSO CORPORATION
    Inventor: Akihiro Yamaguchi
  • Patent number: 10269728
    Abstract: A method includes embedding a die in a molding material; forming a first dielectric layer over the molding material and the die; forming a conductive line over an upper surface of the first dielectric layer facing away from the die; and forming a second dielectric layer over the first dielectric layer and the conductive line. The method further includes forming a first trench opening extending through the first dielectric layer or the second dielectric layer, where a longitudinal axis of the first trench is parallel with a longitudinal axis of the conductive line, and where no electrically conductive feature is exposed at a bottom of the first trench opening; and filling the first trench opening with an electrically conductive material to form a first ground trench.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Ya Huang, Chung-Hao Tsai, Chuei-Tang Wang, Chen-Hua Yu, Chih-Yuan Chang
  • Patent number: 10229895
    Abstract: An electronic sub-assembly (36) comprising at least one electronic component (14) embedded in a sequence of layers, wherein the electronic component (14) is arranged in a recess of an electrically conductive central layer (16) and directly adjoins a resin layer (12, 20) on each side.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: March 12, 2019
    Assignee: SCHWEIZER ELECTRONIC AG
    Inventors: Thomas Gottwald, Alexander Neumann
  • Patent number: 10231324
    Abstract: Some novel features pertain to an integrated device that includes a first metal layer and a second metal layer. The first metal layer includes a first set of regions. The first set of regions includes a first netlist structure for a power distribution network (PDN) of the integrated device. The second metal layer includes a second set of regions. The second set of regions includes a second netlist structure of the PDN of the integrated device. In some implementations, the second metal layer further includes a third set of regions comprising the first netlist structure for the PDN of the integrated device. In some implementations, the first metal layer includes a third set of regions that includes a third netlist structure for the PDN of the integrated device. The third set of regions is non-overlapping with the first set of regions of the first metal layer.
    Type: Grant
    Filed: April 29, 2014
    Date of Patent: March 12, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Ryan David Lane, Yue Li, Charles David Paynter, Ruey Kae Zang
  • Patent number: 10217711
    Abstract: A semiconductor package includes a ground electrode formed on an upper surface of a substrate, a first electronic component disposed on the upper surface of the substrate, a sealing member sealing the electronic component, and a shielding member surrounding the first electronic component and disposed in the sealing member.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: February 26, 2019
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Sung Jae Yoon, Seong Jong Cheon
  • Patent number: 10218290
    Abstract: An inverter has an inverter bridge connected between two DC busbars on the input side and connected to an AC output on the output side. The two DC busbars run, in a manner overlapping one another, in planes which are parallel to one another. The inverter bridge has a subcircuit having a plurality of semiconductor switches between the AC output and each DC busbar. Semiconductor modules which form the two subcircuits are connected, in a manner arranged beside one another, to the two DC busbars and to the AC output via connections. A connection element which leads to the AC output begins on that side of the DC busbar which faces the semiconductor modules in a region overlapped by the DC busbars and connects the semiconductor modules of the two subcircuits to one another there.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: February 26, 2019
    Assignee: SMA Solar Technology AG
    Inventors: Karl Nesemann, Andreas Falk, Henning Schneider
  • Patent number: 10211170
    Abstract: A system and method for a packaged device with harmonic control are presented. In one embodiment, a device includes a substrate and a transistor die coupled to the substrate. The transistor die includes a plurality of transistor cells. Each transistor cell in the plurality of transistor cells includes a control (e.g., gate) terminal. The device includes a second die coupled to the substrate. The second die includes a plurality of individual shunt capacitors coupled between the control terminals of the plurality of transistor cells and a ground reference node. The capacitance values of at least two of the shunt capacitors are significantly different.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: February 19, 2019
    Assignee: NXP USA, INC.
    Inventors: Pascal Peyrot, Olivier Lembeye, Sai Sunil Mangaonkar
  • Patent number: 10199567
    Abstract: A sensor includes: an integrated circuit having a power supply lead, a ground lead and a signal lead; a power supply terminal connected to the power supply lead; a ground terminal connected to the ground lead; a first signal terminal connected to the signal lead; a second signal terminal connected to the first signal terminal; a filter member having one end connected to one of the terminals and another end connected to another one of the terminals; and a sealing body sealing the integrated circuit, the terminals and the filter member. A part of each terminal is exposed from the sealing body.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: February 5, 2019
    Assignee: DENSO CORPORATION
    Inventors: Takeshi Itou, Takamitsu Kubota, Yoshiyuki Kono
  • Patent number: 10188010
    Abstract: This seal ring (1) is made of a clad material in which a base material layer (10) and a brazing filler metal layer (11) arranged on a first surface (10b) of the base material layer are bonded to each other, and a side brazing filler metal portion (11f) of the brazing filler metal layer covering a side surface (10c) of the base material layer is removed.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: January 22, 2019
    Assignee: HITACHI METALS, LTD.
    Inventors: Junya Nishina, Keiichiro Maeda, Ken Asada
  • Patent number: 10186979
    Abstract: An electric power converter includes a semiconductor module and a DC bus bar. The semiconductor module includes a main body portion having a built-in semiconductor element therein and a DC terminal to which a DC voltage is applied projecting from the main body portion. A DC bus bar is connected to the DC terminal. The DC bus bar is disposed such that a thickness direction of the DC bus bar matches a projecting direction of the DC terminal. The penetrating portion penetrating the projecting direction is formed in the DC bus bar. The DC terminal is connected to the DC bus bar in a state where at least a part of the DC terminal is disposed in a position that can be seen from the penetrating portion when viewed from the projection direction. The penetrating portion is formed in a hole shape.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: January 22, 2019
    Assignee: DENSO CORPORATION
    Inventors: Naohisa Harada, Akira Nakasaka, Tsuyoshi Kurauchi
  • Patent number: 10177085
    Abstract: A power commutation module includes a printed circuit board, a first plate-shaped bus bar, and a first plurality of power switches each including a plurality of connection pins which are connected on the upper face of the printed circuit board and a metal base plate which is applied against the bus bar. The first plurality of power switches is mounted on the first bus bar. The power switches are generally aligned along a longitudinal edge of the first bus bar, in that said longitudinal edge of the first bus bar is arranged along a first longitudinal edge of the printed circuit board, and the portion of the first bus bar on which the power switches are mounted is arranged next to the printed circuit board.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: January 8, 2019
    Assignee: APTIV TECHNOLOGIES LIMITED
    Inventors: Aymeric Perot, Erwan Guillanton
  • Patent number: 10163770
    Abstract: A device comprises a semiconductor structure in a molding compound layer, a first polymer layer on the molding compound layer, a second polymer layer on the first polymer layer, a first interconnect structure having a first via portion in the first polymer layer and a first metal line portion in the second polymer layer, a third polymer layer on the second polymer layer, a fourth polymer layer on the third polymer layer and a second interconnect structure having a second via portion in the third polymer layer and a second metal line portion in the fourth polymer layer, wherein the second via portion is vertically aligned with the first via portion.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Wei Chiu, Sao-Ling Chiu
  • Patent number: 10162925
    Abstract: A cell layout, a cell layout library and a synthesizing method are disclosed. The cell layout includes a cell block and a tapping connector. The cell block has a pin. The pin being disposed at a Nth metal layer in the cell layout. The tapping connector is disposed at a (N+1)th metal layer and a (N+2)th metal layer and stacked above the pin of the cell block. The tapping connector is electrically connected to the pin and forms an equivalent tapping point of the pin of the cell block. N is a positive integer greater than or equal to 1.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Lin Chuang, Huang-Yu Chen, Yun-Han Lee
  • Patent number: 10163851
    Abstract: A package includes an Integrated Voltage Regulator (IVR) die, wherein the IVR die includes metal pillars at a top surface of the first IVR die. The package further includes a first encapsulating material encapsulating the first IVR die therein, wherein the first encapsulating material has a top surface coplanar with top surfaces of the metal pillars. A plurality of redistribution lines is over the first encapsulating material and the IVR die. The plurality of redistribution lines is electrically coupled to the metal pillars. A core chip overlaps and is bonded to the plurality of redistribution lines. A second encapsulating material encapsulates the core chip therein, wherein edges of the first encapsulating material and respective edges of the second encapsulating material are vertically aligned to each other. An interposer or a package substrate is underlying and bonded to the IVR die.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Shang-Yun Hou, Yun-Han Lee
  • Patent number: 10153177
    Abstract: A wiring component electrically connects a first semiconductor element, including first and second electrode terminals, and a second semiconductor element, including third and fourth electrode terminals. The wiring component includes first and second connection terminals respectively connected to the first and third electrode terminals. A third connection terminal is connected to the second electrode terminal, and a fourth connection terminal is connected to the fourth electrode terminal. An insulation layer embeds the wiring component and the third and fourth connection terminals. A wiring layer is formed on a lower surface of the insulation layer and connected to an internal connection terminal and the third and fourth external terminals. Upper surfaces of the first to fourth external terminals are located coplanar with one another.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: December 11, 2018
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Haruo Sorimachi