Abstract: A method and system for generating a clock distribution circuit for each macro circuit in an ASIC design are disclosed herein. In some embodiments, a method for generating a clock distribution circuit receives the ASIC design specified in a hardware description language (HDL), places each macro circuit in allocated locations on a semiconductor substrate, generates a custom clock skew information for each macro circuit based on a macro clock delay model, generates a clock distribution circuit for each macro circuit placed on the semiconductor substrate based on the generated custom clock skew information, modifies the clock distribution circuit if the generated clock distribution circuit does not meet timing requirements of the ASIC design, and outputs a physical layout of the ASIC design for manufacturing under a semiconductor fabrication process.

Abstract: The present disclosure relates to a radio frequency (RF) device including a device substrate, a thinned device die with a device region over the device substrate, a first mold compound, and a second mold compound. The device region includes an isolation portion, a back-end-of-line (BEOL) portion, and a front-end-of-line (FEOL) portion with a contact layer and an active section. The contact layer resides over the BEOL portion, the active section resides over the contact layer, and the isolation portion resides over the contact layer to encapsulate the active section. The first mold compound resides over the device substrate, surrounds the thinned device die, and extends vertically beyond the thinned device die to define an opening over the thinned device die and within the first mold compound. The second mold compound fills the opening and directly connects the isolation portion of the thinned device die.

Abstract: A power semiconductor device in which the size of an insulating substrate is reduced and connection failure can be suppressed includes an insulating substrate, a semiconductor element, and a printed circuit board. The semiconductor element is bonded to one main surface of the insulating substrate. The printed circuit board is bonded to face the semiconductor element. The semiconductor element has a main electrode and a signal electrode. The printed circuit board includes a core member, a first conductor layer, and a second conductor layer. The second conductor layer has a bonding pad. The printed circuit board has a missing portion. A metal column portion is arranged to pass through the inside of the missing portion and reach the insulating substrate. The signal electrode and the bonding pad are connected by a metal wire. The metal column portion and the insulating substrate are bonded.

Abstract: The present disclosure relates to a radio frequency device that includes a transfer device die and a multilayer redistribution structure underneath the transfer device die. The transfer device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion and a transfer substrate. The FEOL portion includes isolation sections and an active layer surrounded by the isolation sections. A top surface of the device region is planarized. The transfer substrate resides over the top surface of the device region. Herein, silicon crystal does not exist within the transfer substrate or between the transfer substrate and the active layer. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the transfer device die.

Abstract: Multi-component modules (MCMs), including configurable electromagnetic interference (EMI) shield structures and related methods, are disclosed. An EMI shield enclosing an IC or another electrical component in an MCM can protect other components within the MCM from EMI generated by the enclosed component. The EMI shield also protects the enclosed component from the EMI generated by other electrical components. An EMI shield with sidewall structures, in which vertical conductors supported by a wall medium electrically couple a lid of the EMI shield to a ground layer in a substrate, provides configurable EMI protection in an MCM. The EMI shield may also be employed to increase heat dissipation. The sidewall structures of the EMI shield are disposed on one or more sides of an electrical component and are configurable to provide a desired level of EMI isolation.

Abstract: A power stage, comprising of multiple power MOSFETs and control and monitoring circuits, is an important part of voltage regulators. The voltage regulator controller typically monitors the power stage output current to implement control and protection functions. Traditional power stages mostly adapt monolithic solutions, suffering from performance inefficiencies due to the LDMOS process, while co-packaged solutions with combined VDMOS and LDMOS processes suffer from potential large current monitoring errors due to different operating temperatures. The current invention proposes a current monitoring circuit with temperature compensation to cancel the temperature coefficient mismatch between the external power MOSFET and the current monitoring circuit.

Abstract: Provided is an integrated fan-out (InFO) package structure including a first die, a second die, a third die, a protective layer, and an interconnect structure. The first die has a first surface and a second surface opposite to each other. The first die has a plurality of through substrate vias (TSVs) protruding from the second surface. The second die and the third die are bonded on the first surface of the first die. The protective layer laterally surrounds protrusions of the plurality of TSVs that protrude from the second surface. The interconnect structure are disposed on the protective layer and electrically connected to the plurality of TSVs. The interconnect structure includes a polymer layer covering the protective layer.

Abstract: Embodiments disclosed herein include a printed circuit board (PCB) with a non-uniform thickness and methods of fabricating such PCBs. In an embodiment, the PCB comprises a connector region with a top surface and a bottom surface, and a component region with a top surface and a bottom surface. In an embodiment, the bottom surface of the connector region is coplanar with the bottom surface of the component region. In an embodiment the top surface of the connector region is not coplanar with the top surface of the component region.

Abstract: An optical module includes a circuit board and a silicon optical chip. The circuit board includes a plurality of circuit board bonding pads. The silicon optical chip includes a plurality of chip bonding pads corresponding to the plurality of circuit board bonding pads. The plurality of chip bonding pads are electrically connected to the corresponding circuit board bonding pads, so that the silicon optical chip is electrically connected to the circuit board. A chip bonding pad is electrically connected to at least one corresponding circuit board bonding pad through a plurality of bonding wires, or a circuit board bonding pad is electrically connected to at least one corresponding chip bonding pad through a plurality of bonding wires. A connecting line of two or more of bonding positions of the plurality of bonding wires on the circuit board bonding pads is inclined with respect to a connecting line of centers of the circuit board bonding pads.

Abstract: An automotive power package includes a heat sink layer fabricated onto at least one surface of the automotive power package. The heat sink layer includes a material having a thermal conductivity higher than 130 W/m-K and a coefficient of thermal expansion between 5 and 15 ppm/° C.

Abstract: A tub of a semiconductor device includes a cool zone with a first projected operating temperature and a hot zone with a second projected operating temperature greater than the first projected operating temperature. A design parameter has a first value in the cool zone and a second value different from the first value in the hot zone. The difference configures the tub to dissipate less heat in the hot zone during operation of the semiconductor device than would be dissipated if the first and second values were equal. The design parameter may be, for example, a tub width, a source structure width, a JFET region width, a channel length, a channel width, a length of a gate, a displacement of a center of the gate relative to a center of a JFET region, a dopant concentration, or a combination thereof.

Abstract: A semiconductor device includes: a substrate main body having a first surface and a second surface; an electric component arranged in the substrate main body; a first terminal and a second terminal arranged on the first surface or the second surface, respectively; a first internal conductor pattern arranged in a first circuit layer arranged between the electric component and the first surface, and electrically connected to the first terminal and the electric component; and a second internal conductor pattern arranged in a second circuit layer arranged between the electric component and the second surface, and electrically connected to the second terminal and the electric component. The first internal conductor pattern and the second internal conductor pattern are at least partially opposed to each other inside the substrate main body.

Abstract: An electronic assembly includes a plurality of electronic die arranged into shingles, each shingle having a multiple offset stacked die coupled by cascading connections. Each shingle is arranged in a stack of shingles with alternate shingles having die stacked in opposite directions and offset in a zigzag manner to facilitate vertical electrical connections from a top of the electronic assembly to a bottom die of each shingle.

Abstract: The present disclosure relates to a radio frequency device that includes a transfer device die and a multilayer redistribution structure underneath the transfer device die. The transfer device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion and a transfer substrate. The FEOL portion includes isolation sections and an active layer surrounded by the isolation sections. A top surface of the device region is planarized. The transfer substrate resides over the top surface of the device region. Herein, silicon crystal does not exist within the transfer substrate or between the transfer substrate and the active layer. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the transfer device die.

Abstract: The present disclosure relates to a radio frequency (RF) device that includes a mold device die and a multilayer redistribution structure underneath the mold device die. The mold device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion, and a first mold compound. The FEOL portion includes an active layer formed from a strained silicon epitaxial layer, in which a lattice constant is greater than 5.461 at a temperature of 300K. The first mold compound resides over the active layer. Herein, silicon crystal does not exist between the first mold compound and the active layer. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the mold device die.

Abstract: The present disclosure relates to a radio frequency (RF) device including a device substrate, a thinned device die with a device region over the device substrate, a first mold compound, and a second mold compound. The device region includes an isolation portion, a back-end-of-line (BEOL) portion, and a front-end-of-line (FEOL) portion with a contact layer and an active section. The contact layer resides over the BEOL portion, the active section resides over the contact layer, and the isolation portion resides over the contact layer to encapsulate the active section. The first mold compound resides over the device substrate, surrounds the thinned device die, and extends vertically beyond the thinned device die to define an opening over the thinned device die and within the first mold compound. The second mold compound fills the opening and directly connects the isolation portion of the thinned device die.

Abstract: In examples, a semiconductor package comprises a ceramic substrate and a horizontal metal layer covered by the ceramic substrate. The metal layer is configured to carry signals in the 5 GHz to 38 GHz frequency range. The package also includes a vertical castellation on an outer surface of the ceramic substrate, the castellation coupled to the metal layer and having a height ranging from 0.10 mm to 0.65 mm.

Abstract: A memory die assembly, comprising a non-volatile memory structure, performs autonomous testing of the memory die assembly by repeatedly performing a group of tests for multiple cycles such that the group of tests includes programming, erasing and reading the non-volatile memory structure. Failure events from the tests are recorded by storing error data for each recorded failure event including a location in the non-volatile memory structure of the failure event, a type of test that failed and a cycle during which the failure event occurred.

Abstract: A method for producing a power semiconductor module arrangement includes: arranging at least one semiconductor substrate in a housing, each semiconductor substrate including a first metallization layer attached to a dielectric insulation layer, the housing including a through hole extending through a component of the housing; inserting a fastener into the through hole such that an upper portion of the fastener is not inserted into the through hole; arranging a printed circuit board on the housing; arranging the housing on a mounting surface, the mounting surface comprising a hole, wherein the housing is arranged on the mounting surface such that the through hole is aligned with the hole in the mounting surface; and exerting a force on the printed circuit board such that the force causes the fastener to be pressed into the hole in the mounting surface so as to secure the housing to the mounting surface.

Abstract: A method for testing a stacked integrated circuit device comprising a first die and a second die, the method comprising: sending from testing logic of the first die, first testing control signals to first testing apparatus on the first die; in response to the first testing control signals, the first testing apparatus running a first one or more tests for testing functional logic or memory of the first die; sending from the testing logic of the first die, second testing control signals to the second die via through silicon vias formed in a substrate of the first die; and in dependence upon the second testing control signals from the first die, running a second one or more tests for testing the stacked integrated circuit device.

Abstract: A power control switch assembly. The assembly may include a thyristor device, where the thyristor device includes a first device terminal, a second device terminal, and a gate terminal> The assembly may include a negative temperature coefficient (NTC) device, electrically coupled to the gate terminal of the thyristor device on a first end, and electrically coupled to the first device terminal of the thyristor device on a second end, wherein the NTC device is thermally coupled to the thyristor device.

Abstract: A semiconductor package is provided. The semiconductor package includes a semiconductor die, a stack of polymer layers, redistribution elements and a passive filter. The polymer layers cover a front surface of the semiconductor die. The redistribution elements and the passive filter are disposed in the stack of polymer layers. The passive filter includes a ground plane and conductive patches. The ground plane is overlapped with the conductive patches, and the conductive patches are laterally separated from one another. The ground plane is electrically coupled to a reference voltage. The conductive patches are electrically connected to the ground plane, electrically floated, or electrically coupled to a direct current (DC) voltage.

Abstract: The present disclosure relates to a radio frequency (RF) device including a device substrate, a thinned device die with a device region over the device substrate, a first mold compound, and a second mold compound. The device region includes an isolation portion, a back-end-of-line (BEOL) portion, and a front-end-of-line (FEOL) portion with a contact layer and an active section. The contact layer resides over the BEOL portion, the active section resides over the contact layer, and the isolation portion resides over the contact layer to encapsulate the active section. The first mold compound resides over the device substrate, surrounds the thinned device die, and extends vertically beyond the thinned device die to define an opening over the thinned device die and within the first mold compound. The second mold compound fills the opening and directly connects the isolation portion of the thinned device die.

Abstract: The present disclosure relates to a radio frequency (RF) device that includes a mold device die and a multilayer redistribution structure underneath the mold device die. The mold device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion, and a first mold compound. The FEOL portion includes an active layer formed from a strained silicon epitaxial layer, in which a lattice constant is greater than 5.461 at a temperature of 300K. The first mold compound resides over the active layer. Herein, silicon crystal does not exist between the first mold compound and the active layer. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the mold device die.

Abstract: Methods and systems for protecting a secure computing system. Aspects include connecting a pluggable security card to a motherboard of the secure computing system. Aspects also include activating a detection circuit to monitor a physical connection between the pluggable security card and the motherboard. Based on detecting that the physical connection between the pluggable security card and the motherboard has been interrupted, aspects include setting a tamper event flag, wherein the secure computing system is prevented from being operated when the tamper event flag is set.

Abstract: A modular switching cell of a high voltage direct current power converter has a modular switching cell that includes a base module, which has: a first switching unit; a second switching unit; a first capacitor; and a second capacitor. The first switching unit, the second switching unit, the first capacitor, and the second capacitor are mounted on a chassis. The base module is configured to receive at least three different busbar sets, each of the busbar sets having a plurality of busbars for interconnecting the first switching unit, the second switching unit, the first capacitor, and the second capacitor to form one of: two parallel half bridge circuits between a first cell terminal and a second cell terminal; two serial half bridge circuits between the first cell terminal and the second cell terminal; or a full bridge circuit between the first cell terminal and the second cell terminal.

Abstract: Embodiments described herein can include multi-layer circuits within a liquid crystal polymer (LCP) material to define a 3-D interconnect structure that connects the microelectronics features, devices, components and electrical interfaces. In addition, mechanical functions can be embedded in a fashion and proximity such that the embedded electronics can interface and interact with each other as well as introduced conditions relevant to the function of the device and the outside world or environment it is exposed to.

Abstract: Semiconductor devices including lids having liquid-cooled channels and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a first integrated circuit die; a lid coupled to the first integrated circuit die, the lid including a plurality of channels in a surface of the lid opposite the first integrated circuit die; a cooling cover coupled to the lid opposite the first integrated circuit die; and a heat transfer unit coupled to the cooling cover through a pipe fitting, the heat transfer unit being configured to supply a liquid coolant to the plurality of channels through the cooling cover.

Abstract: A multi-chip module (MCM includes a substrate and first and second integrated circuit chips disposed on the substrate. The second IC chip includes transceiver circuitry configured to communicate with the first IC chip. The transceiver circuitry includes transmit circuitry having an inverter circuit to generate a first signal for transmission to the first IC chip along a signaling link. The signaling link includes a line termination impedance. Receiver circuitry includes a receiver circuit to receive a second signal from the first IC chip along the signaling link concurrently with transmission of the first signal along the signaling link. Hybrid circuitry is coupled to the transmit circuitry and to the receiver circuitry. The hybrid circuitry is configured to cancel a received component of the first signal. The hybrid circuitry includes a replica termination impedance that is configured in an open state.

Abstract: A multiphase inverter apparatus includes: an insulating substrate; at least one low voltage bus and at least one high voltage bus on a first surface of the insulating substrate; a plurality of half-bridge circuits, each half-bridge circuit being electrically coupled between a respective one of the at least one low voltage bus and a respective one of the at least one high voltage bus; and a phase output lead for each half-bridge circuit. For each half bridge circuit, the phase output lead is arranged on and electrically coupled to at least one packaged low side switch and at least one packaged high side switch of the half bridge circuit such that each packaged low side switch and each packaged high side switch is arranged vertically between the phase output lead and the first surface of the insulating substrate.

Abstract: A power control switch assembly. The assembly may include a thyristor device, where the thyristor device includes a first device terminal, a second device terminal, and a gate terminal> The assembly may include a negative temperature coefficient (NTC) device, electrically coupled to the gate terminal of the thyristor device on a first end, and electrically coupled to the first device terminal of the thyristor device on a second end, wherein the NTC device is thermally coupled to the thyristor device.

Abstract: The present disclosure relates to a radio frequency (RF) device including a device substrate, a thinned device die with a device region over the device substrate, a first mold compound, and a second mold compound. The device region includes an isolation portion, a back-end-of-line (BEOL) portion, and a front-end-of-line (FEOL) portion with a contact layer and an active section. The contact layer resides over the BEOL portion, the active section resides over the contact layer, and the isolation portion resides over the contact layer to encapsulate the active section. The first mold compound resides over the device substrate, surrounds the thinned device die, and extends vertically beyond the thinned device die to define an opening over the thinned device die and within the first mold compound. The second mold compound fills the opening and directly connects the isolation portion of the thinned device die.

Abstract: A system of providing power to a chip on a mainboard includes: a first power supply, located on the mainboard, and being configured to receive a first voltage and to provide a second voltage; and a second power supply and a third power supply, located on the mainboard and disposed at different sides of the chip, each of the second power supply and the third power supply is electrically connected to the first power supply to receive the second voltage, the second power supply provides a third voltage to the chip, the third power supply provides a fourth voltage to the chip, and ZBUS_2?5*(ZPS2_2+ZPDN_2), ZBUS_2 is bus impedance between the first power supply and the third power supply, ZPS2_2 is equivalent output impedance of the third power supply, and ZPDN_2 is transmission impedance between the third power supply and the chip.

Abstract: The present disclosure relates to a radio frequency (RF) device that includes a mold device die and a multilayer redistribution structure underneath the mold device die. The mold device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion, and a first mold compound. The FEOL portion includes an active layer formed from a strained silicon epitaxial layer, in which a lattice constant is greater than 5.461 at a temperature of 300K. The first mold compound resides over the active layer. Herein, silicon crystal does not exist between the first mold compound and the active layer. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the mold device die.

Abstract: Representative techniques and devices including process steps may be employed to mitigate the potential for delamination of bonded microelectronic substrates due to metal expansion at a bonding interface. For example, a metal pad having a larger diameter or surface area (e.g., oversized for the application) may be used when a contact pad is positioned over a TSV in one or both substrates.

Abstract: An electronic package includes an electronic component and a heat dissipation structure, wherein the heat dissipation structure has a plurality of bonding pillars, and a metal layer is formed on the bonding pillars, so as to stably dispose the heat dissipation structure on the electronic component via the bonding pillars and the metal layer.

Abstract: A board main body part has a multilayer structure with even-numbered layers including a first layer formed on a surface part on one side and a second layer formed on a surface part on the other side. On both of the first layer and the second layer, a low voltage region in which a low voltage circuit is disposed, a high voltage region in which high voltage circuits are disposed, and an insulating region in which the low voltage region is electrically isolated from the high voltage region are formed. At least a part of a first high voltage circuit is disposed in a first-layer high voltage region formed on the first layer, and at least a part of a second high voltage circuit is disposed in a second-layer high voltage region formed on the second layer.

Abstract: Systems, methods, and devices for a ball grid array with non-linear conductive routing are described herein. Such a ball grid array may include a plurality of solder balls that are electrically coupled by a non-linear conductive routing. The non-linear conductive routing may include a plurality of routing sections where each of the plurality of routing sections is disposed at an angle to adjacent routing sections.

Abstract: The present disclosure relates to a radio frequency (RF) device including a device substrate, a thinned device die with a device region over the device substrate, a first mold compound, and a second mold compound. The device region includes an isolation portion, a back-end-of-line (BEOL) portion, and a front-end-of-line (FEOL) portion with a contact layer and an active section. The contact layer resides over the BEOL portion, the active section resides over the contact layer, and the isolation portion resides over the contact layer to encapsulate the active section. The first mold compound resides over the device substrate, surrounds the thinned device die, and extends vertically beyond the thinned device die to define an opening over the thinned device die and within the first mold compound. The second mold compound fills the opening and directly connects the isolation portion of the thinned device die.

Abstract: A power tool that includes a motor and a printed circuit board (“PCB”). The motor includes a rotor and a stator. The stator includes a plurality of stator terminals. The PCB is electrically connected to the stator. The PCB includes a switch and an embedded busbar. A first end of the embedded busbar is electrically connected to the switch. The embedded busbar extends away from the PCB. A second end of the embedded busbar electrically connects to a stator terminal of the plurality of stator terminals for providing power to the motor using the switch. The embedded bus bar is embedded between two layers of the printed circuit board.

Abstract: An example sensor interposer employing castellated through-vias formed in a PCB includes a planar substrate defining a plurality of castellated through-vias; a first electrical contact formed on the planar substrate and electrically coupled to a first castellated through-via; a second electrical contact formed on the planar substrate and electrically coupled to a second castellated through-via, the second castellated through-via electrically isolated from the first castellated through-via; and a guard trace formed on the planar substrate, the guard trace having a first portion formed on a first surface of the planar substrate and electrically coupling a third castellated through-via to a fourth castellated through-via, the guard trace having a second portion formed on a second surface of the planar substrate and electrically coupling the third castellated through-via to the fourth castellated through-via, the guard trace formed between the first and second electrical contacts to provide electrical isolation b

Abstract: A semiconductor device includes a first substrate and a second substrate. The semiconductor device includes a plurality of conductive pillars between the first and second substrates. The plurality of conductive pillars includes a first conductive pillar having a first width, wherein the first width is substantially uniform along an entire first height of the first conductive pillar, a second conductive pillar having a second width, wherein the second width is substantially uniform along an entire second height of the second conductive pillar, the first width is different from the second width, and the entire first height is equal to the entire second height, and a third conductive pillar having a third width, wherein the third width is substantially uniform along an entire third height of the third conductive pillar, and the third conductive pillar is between the first conductive pillar and the second conductive pillar in the first direction.

Abstract: Provided is a power converter that allows a reduction in EMC noise current flowing through a control circuit board. A power converter 1 includes a semiconductor module 52, a capacitor 51, a control circuit board 45a, positive and negative-side bus bars 41, 42 connecting the semiconductor module 52 and the capacitor 51, a base 33 electrically connected to a ground of the control circuit board 45a, the control circuit board 45a being placed on the base 33, and an electrical conductor 35 electrically connected to the base 33 and extending in a stacking direction in which the base 33 and the control circuit board 45a are stacked. The positive and negative-side bus bars 41, 42 extend around the electrical conductor 35 and are connected to the semiconductor module 52.

Abstract: Smartcards with metal layers manufactured according to various techniques disclosed herein. One or more metal layers of a smartcard stackup may be provided with slits overlapping at least a portion of a module antenna in an associated transponder chip module disposed in the smartcard so that the metal layer functions as a coupling frame. One or more metal layers may be pre-laminated with plastic layers to form a metal core or clad subassembly for a smartcard, and outer printed and/or overlay plastic layers may be laminated to the front and/or back of the metal core. Front and back overlays may be provided. Various constructions of and manufacturing techniques (including temperature, time, and pressure regimes for laminating) for smartcards are disclosed herein.

Abstract: A semiconductor package includes a mold substrate, at least one first semiconductor chip in the mold substrate and including chip pads, wiring bonding pads formed at a first surface of the mold substrate and connected to the chip pads by bonding wires, and a redistribution wiring layer covering the first surface of the mold substrate and including redistribution wirings connected to the wiring bonding wirings.

Abstract: A manufacturing method of a semiconductor package is provided as follows. A semiconductor die is provided, wherein the semiconductor die comprises a semiconductor substrate, an interconnection layer and a through semiconductor via, the interconnection layer is disposed on an active surface of the semiconductor substrate, the through semiconductor via penetrates the semiconductor substrate from a back surface of the semiconductor substrate to the active surface of the semiconductor substrate. An encapsulant is provided to laterally encapsulate the semiconductor die. A through encapsulant via penetrating through the encapsulant is formed.

Abstract: A package for power electronics includes a power substrate, a number of power semiconductor die, and a Kelvin connection contact. Each one of the power semiconductor die are on the power substrate and include a first power switching pad, a second power switching pad, a control pad, a semiconductor structure, and a Kelvin connection pad. The semiconductor structure is between the first power switching pad, the second power switching pad, and the control pad, and is configured such that a resistance of a power switching path between the first power switching pad and the second power switching pad is based on a control signal provided at the control pad. The Kelvin connection pad is coupled to the power switching path. The Kelvin connection contact is coupled to the Kelvin connection pad of each one of the power semiconductor die via a Kelvin conductive trace on the power substrate.

Abstract: A master integrated circuit (IC) chip includes transmit circuitry and receiver circuitry. The transmit circuitry includes a timing signal generation circuit to generate a first timing signal, and a driver to transmit first data in response to the first timing signal. A timing signal path routes the first timing signal in a source synchronous manner with the first data. The receiver circuitry includes a receiver to receive second data from a slave IC chip, and sampling circuitry to sample the second data in response to a second timing signal that is derived from the first timing signal.

Abstract: The present invention provides a semiconductor module, a semiconductor member, and a method for manufacturing the same that make it possible to improve heat dissipation efficiency. This semiconductor module 1 comprises: a power supply unit 40; a RAM unit 50, which is a RAM module having a facing surface disposed so as to face an exposed surface of a logic chip 20 and an exposed surface of the power supply unit 40, the RAM module being disposed across some of a plurality of logic chip signal terminals 22 and some of a plurality of power supply unit power supply terminals 41; and a support substrate 10 having a power feeding circuit capable of feeding electrical power to the logic chip and to the power supply unit 40, one main surface of the support substrate 10 being disposed adjacent to a heat dissipation surface of the RAM unit 50, which is the surface of the RAM unit 50 opposite the facing surface.

Abstract: An electrical transmitter (100) is provided that comprises an ethernet connection (118) and a power source. Electronics (112) are configured to receive the ethernet connection (118) and the power source. The electronics (112) comprise logic operable to detect the power source and accept power from either the ethernet connection (118) or a dedicated power connection (116). A remappable power connection terminal (114) with the electronics (112) is operable to accept power when the dedicated power connection (116) is detected, and operable to accept a non-power connection when power from the ethernet connection (118) is detected.