Having Power Distribution Means (e.g., Bus Structure) Patents (Class 257/691)
  • Patent number: 11403037
    Abstract: An apparatus includes a memory circuit and a memory controller circuit. The memory controller circuit may include a write request queue. The memory controller circuit may be configured to receive a memory request to access the memory circuit and determine if the memory request includes a read request or a write request. A received read request may be scheduled for execution, while a received write request may be stored in the write request queue. The memory controller circuit may reorder scheduled memory requests based on achieving a specified memory access efficiency and based on a number of write requests stored in the write request queue.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: August 2, 2022
    Assignee: Apple Inc.
    Inventors: Shane J. Keil, Gregory S. Mathews, Lakshmi Narasimha Murthy Nukala, Thejasvi Magudilu Vijayaraj, Kai Lun Hsiung, Yanzhe Liu, Sukalpa Biswas
  • Patent number: 11404358
    Abstract: A semiconductor package device includes a leadframe, a first die and a package body. The leadframe includes a first die paddle and a lead. The first die paddle has a first surface and a second surface opposite to the first surface. The first die is disposed on the first surface of the first die paddle. The package body covers the first die and at least a portion of the first surface of the first die paddle and exposing the lead. The package body has a first surface and a second surface opposite to the first surface. The second surface of the package body is substantially coplanar with the second surface of the first die paddle. The lead extends from the second surface of the package body toward the first surface of the package body. A length of the lead is greater than a thickness of the package body.
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: August 2, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING KOREA, INC.
    Inventors: Junyoung Yang, Sangbae Park
  • Patent number: 11387174
    Abstract: A semiconductor device includes: a first semiconductor integrated circuit including at least a first terminal and a second terminal; a first lead frame connected to the first terminal; a second lead frame connected to the second terminal; and a mold resin covering the first semiconductor integrated circuit. The mold resin further covers the first lead frame with a portion of the first lead frame being exposed. The mold resin further covers the second lead frame with a tip of the second lead frame opposite to the second terminal being exposed. The mold resin includes a recess, and the recess is opened to expose only the portion and the mold resin.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: July 12, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kazuhiro Kawahara, Toshitaka Sekine, Hiroyuki Nakamura
  • Patent number: 11387157
    Abstract: The present disclosure relates to a radio frequency device that includes a mold device die and a multilayer redistribution structure underneath the mold device die. The mold device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion, a barrier layer, and a first mold compound. The FEOL portion includes isolation sections and an active layer surrounded by the isolation sections. The barrier layer formed of silicon nitride resides over the active layer and top surfaces of the isolation sections. The first mold compound resides over the barrier layer. Herein, silicon crystal does not exist between the first mold compound and the active layer. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the mold device die.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: July 12, 2022
    Assignee: QORVO US, INC.
    Inventors: Julio C. Costa, Michael Carroll, Philip W. Mason, Merrill Albert Hatcher, Jr.
  • Patent number: 11387170
    Abstract: The present disclosure relates to a radio frequency device that includes a transfer device die and a multilayer redistribution structure underneath the transfer device die. The transfer device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion and a transfer substrate. The FEOL portion includes isolation sections and an active layer surrounded by the isolation sections. A top surface of the device region is planarized. The transfer substrate resides over the top surface of the device region. Herein, silicon crystal does not exist within the transfer substrate or between the transfer substrate and the active layer. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the transfer device die.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: July 12, 2022
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Michael Carroll
  • Patent number: 11387206
    Abstract: The present disclosure relates to a radio frequency (RF) device that includes a mold device die and a multilayer redistribution structure underneath the mold device die. The mold device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion, and a first mold compound. The FEOL portion includes an active layer formed from a strained silicon epitaxial layer, in which a lattice constant is greater than 5.461 at a temperature of 300K. The first mold compound resides over the active layer. Herein, silicon crystal does not exist between the first mold compound and the active layer. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the mold device die.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: July 12, 2022
    Assignee: QORVO US, INC.
    Inventors: Julio C. Costa, Michael Carroll
  • Patent number: 11380656
    Abstract: The semiconductor device includes a semiconductor element, a first conductive member, a second conductive member, an insulating member, a first main terminal, and a second main terminal. The first main terminal and the second main terminal, respectively, extend from the first conductive member and the second conductive member. The first main terminal and the second main terminal, respectively, have a first projecting portion and a second projecting portion projecting outside of the insulating member. The first projecting portion and the second projecting portion, respectively, have a first facing portion and a second facing portion at which plate surfaces of the first and second projecting portions face each other across a gap, and a first non-facing portion and a second non-facing portion at which the plate surfaces of the first and second projecting portions do not face each other.
    Type: Grant
    Filed: November 10, 2020
    Date of Patent: July 5, 2022
    Assignee: DENSO CORPORATION
    Inventor: Hiroshi Ishino
  • Patent number: 11373956
    Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a first semiconductor device, a first conductive layer and a second conductive layer. The first semiconductor device has a first conductive pad. The first conductive layer is disposed in direct contact with the first conductive pad. The first conductive layer extends along a direction substantially parallel to a surface of the first conductive pad. The second conductive layer is disposed in direct contact with the first conductive pad and spaced apart from the first conductive layer.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: June 28, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Min Lung Huang, Hung-Jung Tu, Hsin Hsiang Wang, Chih-Wei Huang, Shiuan-Yu Lin
  • Patent number: 11373966
    Abstract: A package including a package substrate; an interposer electrically coupled to the package substrate and including a metal layer; a die including an integrated voltage regulator and electrically coupled to the interposer by solder features; and an inductor formed by a magnetic material disposed between two of the solder features electrically coupled to each other by a portion of the metal layer of the interposer, the inductor electrically coupled to the integrated voltage regulator.
    Type: Grant
    Filed: September 2, 2020
    Date of Patent: June 28, 2022
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Tae Hong Kim, Jiangqi He, Guotao Wang
  • Patent number: 11367680
    Abstract: An electronic assembly (100) includes a mechanical carrier (102), a plurality of integrated circuits (104A, 104B) disposed on the mechanical carrier, a fan out package (108) disposed on the plurality of integrated circuits, a plurality of singulated substrates (112A, 112B) disposed on the fan out package, a plurality of electronic components (114A, 114B) disposed on the plurality of singulated substrates, and at least one stiffness ring (116A, 116B, 116C) disposed on the plurality of singulated substrates.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: June 21, 2022
    Assignee: Tesla, Inc.
    Inventors: Mengzhi Pang, Shishuang Sun, Ganesh Venkataramanan
  • Patent number: 11355422
    Abstract: The present disclosure relates to a radio frequency device that includes a transfer device die and a multilayer redistribution structure underneath the transfer device die. The transfer device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion and a transfer substrate. The FEOL portion includes isolation sections and an active layer surrounded by the isolation sections. A top surface of the device region is planarized. The transfer substrate resides over the top surface of the device region. Herein, silicon crystal does not exist within the transfer substrate or between the transfer substrate and the active layer. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the transfer device die.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: June 7, 2022
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Michael Carroll
  • Patent number: 11355405
    Abstract: The present disclosure relates to a radio frequency device that includes a mold device die and a multilayer redistribution structure underneath the mold device die. The mold device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion, a barrier layer, and a first mold compound. The FEOL portion includes isolation sections and an active layer surrounded by the isolation sections. The barrier layer formed of silicon nitride resides over the active layer and top surfaces of the isolation sections. The first mold compound resides over the barrier layer. Herein, silicon crystal does not exist between the first mold compound and the active layer. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the mold device die.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: June 7, 2022
    Assignee: QORVO US, INC.
    Inventors: Julio C. Costa, Michael Carroll, Philip W. Mason, Merrill Albert Hatcher, Jr.
  • Patent number: 11355466
    Abstract: A package structure including at least one semiconductor die and a redistribution structure is provided. The semiconductor die is laterally encapsulated by an encapsulant, and the redistribution structure is disposed on the semiconductor die and the encapsulant and electrically connected with the semiconductor die. The redistribution structure includes signal lines and a pair of repair lines. The signal lines include a pair of first signal lines located at a first level, and each first signal line of the pair of first signal lines has a break that split each first signal line into separate first and second fragments. The pair of repair lines is located above the pair of first signal lines and located right above the break. Opposite ending portions of each repair line are respectively connected with the first and second fragments with each repair line covering the break in each first signal line.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: June 7, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Yuan Teng, Hao-Yi Tsai, Kuo-Lung Pan, Sen-Kuei Hsu, Tin-Hao Kuo, Yi-Yang Lei, Ying-Cheng Tseng, Chi-Hui Lai
  • Patent number: 11355470
    Abstract: In one example, a semiconductor device comprises an electronic component comprising a component face side, a component base side, a component lateral side connecting the component face side to the component base side, and a component port adjacent to the component face side, wherein the component port comprises a component port face. A clip structure comprises a first clip pad, a second clip pad, a first clip leg connecting the first clip pad to the second clip pad, and a first clip face. An encapsulant covers portions of the electronic component and the clip structure. The encapsulant comprises an encapsulant face, the first clip pad is coupled to the electronic component, and the component port face and the first clip face are exposed from the encapsulant face. Other examples and related methods are also disclosed herein.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: June 7, 2022
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Ji Yeon Ryu, Jae Beom Shim, Tae Yong Lee, Byong Jin Kim
  • Patent number: 11328983
    Abstract: The present disclosure relates to a radio frequency device that includes a transfer device die and a multilayer redistribution structure underneath the transfer device die. The transfer device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion and a transfer substrate. The FEOL portion includes isolation sections and an active layer surrounded by the isolation sections. A top surface of the device region is planarized. The transfer substrate resides over the top surface of the device region. Herein, silicon crystal does not exist within the transfer substrate or between the transfer substrate and the active layer. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the transfer device die.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: May 10, 2022
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Michael Carroll
  • Patent number: 11328971
    Abstract: A device includes a substrate with a die over the substrate. A molding compound surrounds the die and includes a structural interface formed along a peripheral region of the molding compound.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: May 10, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu-Shen Yeh, Po-Yao Lin, Shyue-Ter Leu, Shin-Puu Jeng, Chih-Kung Huang, Tsung-Ming Yeh
  • Patent number: 11329020
    Abstract: The present disclosure relates to a radio frequency (RF) device that includes a mold device die and a multilayer redistribution structure underneath the mold device die. The mold device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion, and a first mold compound. The FEOL portion includes an active layer formed from a strained silicon epitaxial layer, in which a lattice constant is greater than 5.461 at a temperature of 300K. The first mold compound resides over the active layer. Herein, silicon crystal does not exist between the first mold compound and the active layer. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the mold device die.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: May 10, 2022
    Assignee: QORVO US, INC.
    Inventors: Julio C. Costa, Michael Carroll
  • Patent number: 11322435
    Abstract: A package substrate according to an aspect of the disclosure includes a substrate body, and a first power trace pattern and a first ground trace pattern disposed on a first surface of the substrate body. The first power trace pattern has a parent power line portion and at least one child power line portion branched from the parent power line portion, and the first ground trace pattern has a parent ground line portion and at least one child ground line portion branched from the parent ground line portion. At least a portion of the first power trace pattern is disposed to surround at least a portion of the first ground trace pattern, and at least a portion of the first ground trace pattern is disposed to surround at least a portion of the first power trace pattern.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: May 3, 2022
    Assignee: SK hynix Inc.
    Inventor: Jeong Hyun Park
  • Patent number: 11322420
    Abstract: The present disclosure relates to a radio frequency device that includes a mold device die and a multilayer redistribution structure underneath the mold device die. The mold device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion, a barrier layer, and a first mold compound. The FEOL portion includes isolation sections and an active layer surrounded by the isolation sections. The barrier layer formed of silicon nitride resides over the active layer and top surfaces of the isolation sections. The first mold compound resides over the barrier layer. Herein, silicon crystal does not exist between the first mold compound and the active layer. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the mold device die.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: May 3, 2022
    Assignee: QORVO US, INC.
    Inventors: Julio C. Costa, Michael Carroll, Philip W. Mason, Merrill Albert Hatcher, Jr.
  • Patent number: 11310355
    Abstract: A radio frequency module that simultaneously receives a first reception signal and a second reception signal includes: a module board including a first principal surface and a second principal surface on opposite sides of the module board; a first reception low noise amplifier that is disposed in a first semiconductor IC and amplifies the first reception signal; a second reception low noise amplifier that is disposed in a second semiconductor IC different from the first semiconductor IC and amplifies the second reception signal; and an external-connection terminal that is disposed on the second principal surface. At least one of the first semiconductor IC or the second semiconductor IC is disposed on the second principal surface.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: April 19, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Takayuki Shinozaki
  • Patent number: 11296046
    Abstract: The present disclosure relates to a radio frequency (RF) device that includes a mold device die and a multilayer redistribution structure underneath the mold device die. The mold device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion, and a first mold compound. The FEOL portion includes an active layer formed from a strained silicon epitaxial layer, in which a lattice constant is greater than 5.461 at a temperature of 300K. The first mold compound resides over the active layer. Herein, silicon crystal does not exist between the first mold compound and the active layer. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the mold device die.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: April 5, 2022
    Assignee: QORVO US, INC.
    Inventors: Julio C. Costa, Michael Carroll
  • Patent number: 11296006
    Abstract: A circuit board includes an upper circuit and a lower surface that are opposite to each other, a plurality of heat sink bonding pads, and a plurality of heat sink conductive pads. The heat sink bonding pads are disposed on the upper surface and electrically insulated from one another, and are used to electrically connect to a heat sink. The heat sink conductive pads are disposed on the lower surface, electrically insulated from one another, and electrically connected to the heat sink bonding pads, respectively.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: April 5, 2022
    Assignee: MEDIATEK INC.
    Inventor: You-Wei Lin
  • Patent number: 11296014
    Abstract: The present disclosure relates to a radio frequency device that includes a transfer device die and a multilayer redistribution structure underneath the transfer device die. The transfer device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion and a transfer substrate. The FEOL portion includes isolation sections and an active layer surrounded by the isolation sections. A top surface of the device region is planarized. The transfer substrate resides over the top surface of the device region. Herein, silicon crystal does not exist within the transfer substrate or between the transfer substrate and the active layer. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the transfer device die.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: April 5, 2022
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Michael Carroll
  • Patent number: 11289392
    Abstract: The present disclosure relates to a radio frequency device that includes a mold device die and a multilayer redistribution structure underneath the mold device die. The mold device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion, a barrier layer, and a first mold compound. The FEOL portion includes isolation sections and an active layer surrounded by the isolation sections. The barrier layer formed of silicon nitride resides over the active layer and top surfaces of the isolation sections. The first mold compound resides over the barrier layer. Herein, silicon crystal does not exist between the first mold compound and the active layer. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the mold device die.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: March 29, 2022
    Assignee: QORVO US, INC.
    Inventors: Julio C. Costa, Michael Carroll, Philip W. Mason, Merrill Albert Hatcher, Jr.
  • Patent number: 11269803
    Abstract: A system and method for providing efficient communication between a processor and a device. An interposer is provided to send signals from the processor to the device. The interposer includes a printed circuit board, a first interconnection port communicating with the processor, and a second interconnection port communicating with the device. A retimer/redriver circuit is coupled to the first interconnection port and the second interconnection port, and the retimer/redriver circuit routes signals from the first interconnection port to the second interconnection port.
    Type: Grant
    Filed: December 1, 2020
    Date of Patent: March 8, 2022
    Assignee: QUANTA COMPUTER INC.
    Inventors: Le-Sheng Chou, Sz-Chin Shih, Shuen-Hung Wang
  • Patent number: 11264347
    Abstract: The present disclosure relates to a radio frequency (RF) device that includes a mold device die and a multilayer redistribution structure underneath the mold device die. The mold device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion, and a first mold compound. The FEOL portion includes an active layer formed from a strained silicon epitaxial layer, in which a lattice constant is greater than 5.461 at a temperature of 300K. The first mold compound resides over the active layer. Herein, silicon crystal does not exist between the first mold compound and the active layer. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the mold device die.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: March 1, 2022
    Assignee: QORVO US, INC.
    Inventors: Julio C. Costa, Michael Carroll
  • Patent number: 11264308
    Abstract: The present disclosure relates to a radio frequency device that includes a transfer device die and a multilayer redistribution structure underneath the transfer device die. The transfer device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion and a transfer substrate. The FEOL portion includes isolation sections and an active layer surrounded by the isolation sections. A top surface of the device region is planarized. The transfer substrate resides over the top surface of the device region. Herein, silicon crystal does not exist within the transfer substrate or between the transfer substrate and the active layer. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the transfer device die.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: March 1, 2022
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Michael Carroll
  • Patent number: 11264324
    Abstract: An electronic chip disclosed herein includes a plurality of IP core circuits, with a shared strip that is at least partially conductive and is linked to a node for applying a fixed potential. A plurality of tracks electrically links the plurality of IP core circuits to the shared strip. Each individual track of the plurality of tracks solely links a single one of said IP core circuits to the shared strip.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: March 1, 2022
    Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Rousset) SAS
    Inventors: Samuel Boscher, Yann Rebours, Michel Cuenca
  • Patent number: 11257731
    Abstract: The present disclosure relates to a radio frequency device that includes a mold device die and a multilayer redistribution structure underneath the mold device die. The mold device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion, a barrier layer, and a first mold compound. The FEOL portion includes isolation sections and an active layer surrounded by the isolation sections. The barrier layer formed of silicon nitride resides over the active layer and top surfaces of the isolation sections. The first mold compound resides over the barrier layer. Herein, silicon crystal does not exist between the first mold compound and the active layer. The multilayer redistribution structure includes a number of bump structures, which are at a bottom of the multilayer redistribution structure and electrically coupled to the FEOL portion of the mold device die.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: February 22, 2022
    Assignee: QORVO US, INC.
    Inventors: Julio C. Costa, Michael Carroll, Philip W. Mason, Merrill Albert Hatcher, Jr.
  • Patent number: 11227807
    Abstract: Examples for a two-step insert molding process to encapsulate a pre-molded lead frame (104, 304, 504, 704) are described herein. In some examples, a first circuit component (106, 306, 506) and a first portion of a trace array (110, 310, 510) of the pre-molded lead frame for an integrated circuit (1C) assembly are encapsulated by a first insert molding component (112, 312, 512a, 512b, 712). The trace array connects the first circuit component to a second circuit component (108, 308, 508) of the pre-molded lead frame. A second portion of the trace array is encapsulated by a second insert molding component (114, 314, 514, 714).
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: January 18, 2022
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Michael W. Cumbie, Chien-Hua Chen
  • Patent number: 11227816
    Abstract: An electronic module has a sealing part 90; electronic elements 15, 25 provided in the sealing part 90; rear surface-exposed conductors 10, 20, 30 having rear surface-exposed parts whose rear surface are exposed from the sealing part 90, and having one-terminal parts 11, 21, 31, which extend from the rear surface-exposed parts 12, 22, 32 and protrude outwardly from a side of the sealing part 90; and rear surface-unexposed conductors 40, 50 having unexposed parts 42, 52, which are sealed in the sealing part 90, and having other-terminal parts 41, 51, which extend from the unexposed parts 42, 52 and protrude outwardly from a side of the sealing part 90. The electronic elements 15, 25 are placed on the rear surface-exposed parts 12, 22, 32. The other-terminal parts 41, 51 have a width narrower than a width of the one-terminal parts 11, 21, 31.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: January 18, 2022
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventor: Yoshihiro Kamiyama
  • Patent number: 11222834
    Abstract: A package with a laminate substrate is disclosed. The laminate substrate includes a first layer with a first terminal and a second terminal. The laminate substrate also includes a second layer with a conductive element. The laminate substrate further includes a first via and a second via that electrically connect the first terminal to the conductive element and the second terminal to the conductive element, respectively. The package can include a die mounted on and electrically connected to the laminate substrate.
    Type: Grant
    Filed: January 22, 2020
    Date of Patent: January 11, 2022
    Assignee: Analog Devices International Unlimited Company
    Inventors: Jonathan Kraft, David Aherne
  • Patent number: 11211312
    Abstract: A semiconductor device includes a first conductive plate, a second conductive plate, first switching elements, second switching elements, a first supply terminal and a second supply terminal. The first and second conductive plates are spaced apart from each other in a first direction. The first switching elements are bonded to the first conductive plate, and are electrically connected to the second conductive plate. The second switching elements are bonded to the second conductive plate. The first supply terminal is bonded to the first conductive plate. The second supply terminal has a region that overlaps with the first supply terminal as viewed in a plan view. The second supply terminal is spaced apart from the first conductive plate and the first supply terminal in a thickness direction perpendicular to the first direction. The second supply terminal is electrically connected to the second switching elements.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: December 28, 2021
    Assignee: ROHM CO., LTD.
    Inventors: Takumi Kanda, Masaaki Matsuo, Soichiro Takahashi, Yoshitoki Inami, Kaito Inoue
  • Patent number: 11191151
    Abstract: A device may include a substrate having a first surface and a second surface, a first conductive terminal disposed over the first surface, a second conductive terminal spaced apart from the first conductive terminal in a first direction and disposed over the first surface, a first conductive auxiliary pattern disposed below the first conductive terminal and overlapping with the first conductive terminal, the first conductive auxiliary pattern being coupled to the second conductive terminal, and a second conductive auxiliary pattern disposed below the second conductive terminal and overlapping with the second conducive terminal, the second conductive auxiliary pattern being coupled to the first conductive terminal.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: November 30, 2021
    Assignee: SK hynix Inc.
    Inventors: Kyu Yong Choi, Jin Ho Bae, Yu Jeong Choe
  • Patent number: 11183450
    Abstract: An electronic device (e.g., integrated circuit) and method of making the electronic device is provided that reduces a strength of an electric field generated outside a package of the electronic device proximate to the low voltage lead pins. The electronic device includes a low voltage side and a high voltage side. The low voltage side includes a low voltage die attached to a low voltage die attach pad. Similarly, the high voltage side includes a high voltage die attached to a high voltage die attach pad. Lead pins are attached to each of the low and high voltage attach pads and extend out from a package of the electronic device in an inverted direction.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: November 23, 2021
    Assignee: Texas Instruments Incorporated
    Inventors: Chang-Yen Ko, J K Ho
  • Patent number: 11178771
    Abstract: An aspect includes one or more board layers. A first chip cavity is formed within the one or more board layers, wherein a first Josephson amplifier or Josephson mixer is disposed within the first chip cavity. The first Josephson amplifier or Josephson mixer comprises at least one port, each port connected to at least one connector disposed on at least one of the one or more board layers, wherein at least one of the one or more board layers comprises a circuit trace formed on the at least one of the one or more board layers.
    Type: Grant
    Filed: July 28, 2020
    Date of Patent: November 16, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Baleegh Abdo, Nicholas T. Bronn, Oblesh Jinka, Salvatore B. Olivadese
  • Patent number: 11158587
    Abstract: A packaged semiconductor device includes a substrate and a contact pad disposed on the semiconductor substrate. The packaged semiconductor device also includes a dielectric layer disposed over the contact pad, the dielectric layer including a first opening over the contact pad, and an insulator layer disposed over the dielectric layer, the insulator layer including a second opening over the contact pad. The packaged semiconductor device also includes a molding material disposed around the substrate, the dielectric layer, and the insulator layer and a wiring over the insulator layer and extending through the second opening, the wiring being electrically coupled to the contact pad.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: October 26, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Po-Hao Tsai, Jui-Pin Hung, Jing-Cheng Lin
  • Patent number: 11127671
    Abstract: Power semiconductor module, including a base plate with at least one substrate located on the base plate, wherein an electronic circuit is provided on the at least one substrate, wherein located on the at least one substrate are electrical connectors comprising a DC+ power terminal, a DC? power terminal and an AC power terminal and further a control connector, wherein the power semiconductor module is designed as a half-bridge module including a first amount of switching power semiconductor devices and a second amount of switching power semiconductor devices, wherein the base plate includes a contact area, a first device area and a second device area, wherein the contact area is positioned in a center of the base plate such, that the first device area is positioned at a first side of the contact area and that the second device area is positioned at a second side of the contact area, the second side being arranged opposite to the first side, wherein the DC+ power terminal, the DC? power terminal, the AC power
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: September 21, 2021
    Assignee: ABB Power Grids Switzerland AG
    Inventors: Samuel Hartmann, Dominik Truessel
  • Patent number: 11101220
    Abstract: Certain aspects of the present disclosure generally relate to a chip package having through-package partial vias. An example chip package generally includes a first substrate, a second substrate, an integrated circuit die, and one or more conductive vias. The integrated circuit die is disposed between the first substrate and the second substrate. The one or more conductive vias are disposed on at least one edge of at least one of the first substrate or the second substrate and electrically coupled to at least one of the first substrate or the second substrate.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: August 24, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Hong Bok We, Aniket Patil, Jaehyun Yeon
  • Patent number: 11056415
    Abstract: To improve yield and reliability at the time when a plurality of semiconductor elements used for a semiconductor device is arranged in parallel.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: July 6, 2021
    Assignee: Hitachi Automotive Systems, Ltd.
    Inventors: Masami Oonishi, Takashi Hirao
  • Patent number: 11031373
    Abstract: A multi-die integrated circuit device and a method of fabricating the multi-die integrated circuit device involve a substrate. Two or more dice include components that implement functionality of the multi-die integrated circuit. The components include logic gates. The multi-die integrated circuit device also includes a spacer disposed between the substrate and each of the two or more dice. Each of the two or more dice makes direct electrical contact with the substrate without making direct electrical contact with the spacer through holes in the spacer.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: June 8, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Charles L. Arvin, Bhupender Singh, Richard Francis Indyk, Steve Ostrander, Thomas Weiss, Mark Kapfhammer
  • Patent number: 11018072
    Abstract: A semiconductor package includes an upper electrically conductive element having a lower carrier substrate having an upper electrically conductive layer, a lower electrically conductive layer having an outwardly exposed surface, and an electrical insulation layer arranged between the electrically conductive layers, a first electrically conductive spacer arranged between the upper electrically conductive element and the upper electrically conductive layer, a power semiconductor chip arranged between the upper electrically conductive element and the upper electrically conductive layer, and a second electrically conductive spacer arranged between the upper electrically conductive element and the chip. A first carrier region of the upper electrically conductive layer is configured to apply a positive supply voltage. A second carrier region alongside the first carrier region is configured as a phase.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: May 25, 2021
    Assignee: Infineon Technologies AG
    Inventors: Juergen Hoegerl, Ordwin Haase, Tobias Kist
  • Patent number: 11006527
    Abstract: An aspect includes one or more board layers. A first chip cavity is formed within the one or more board layers, wherein a first Josephson amplifier or Josephson mixer is disposed within the first chip cavity. The first Josephson amplifier or Josephson mixer comprises at least one port, each port connected to at least one connector disposed on at least one of the one or more board layers, wherein at least one of the one or more board layers comprises a circuit trace formed on the at least one of the one or more board layers.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: May 11, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Baleegh Abdo, Nicholas T. Bronn, Oblesh Jinka, Salvatore B. Olivadese
  • Patent number: 10997755
    Abstract: The computer-implemented tool generates radial organization charts by ingesting hierarchical structured data, with associated performance attributes, and populating a virtual reporting tree that stores tree structure and radial structure information. The graphing server populates the virtual reporting tree while adding ghost nodes to ensure symmetry. The graphing server calculates and assigns radial and angular positional information to each node and uses that positional information to generate the radial organizer chart, applying coloring information to selected nodes and graphically represented radial relationship lines based on the structure and associated performance attributes from the ingested data.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: May 4, 2021
    Assignee: AlixPartners, LLP
    Inventors: Francesco Barosi, Giuseppe Gasparro, Giacomo Cantu, Jeff Goldstein, Luca Ridolfi
  • Patent number: 10992022
    Abstract: A microwave antenna apparatus comprises a semiconductor element and an antenna element embedded into a mold layer, which is covered by a redistribution layer. The antenna element is preferably configured as SMD component so that it can be handled by a standard pick and place process. The coupling between semiconductor element and antenna element is provided either by a metal layer or aperture coupling within the redistribution layer. The microwave antenna apparatus may be coupled to a PCB arrangement thus forming an embedded wafer-level ball grid array (eWLB) or embedded micro-wafer-level-packaging (emWLP) package.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: April 27, 2021
    Assignee: SONY CORPORATION
    Inventors: Wasif Tanveer Khan, Ali Eray Topak, Arndt Thomas Ott
  • Patent number: 10985092
    Abstract: A semiconductor device includes: a seal portion; a first electronic element; a first lead terminal; a second lead terminal having one end that is disposed to be close to the one end of the first lead terminal within the seal portion, and another end that is exposed from another end of the seal portion, the other end of the seal portion being along the longitudinal direction; a first connecting element disposed within the seal portion, and having one end that is electrically connected to the first electrode disposed on the first electronic element, and another end that is electrically connected to the one end of the second lead terminal; and a conductive bonding agent.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: April 20, 2021
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventor: Yoshihiro Kamiyama
  • Patent number: 10980134
    Abstract: A BGA structure having larger solder balls in high stress regions of the array is disclosed. The larger solder balls have higher solder joint reliability (SJR) and as such may be designated critical to function (CTF), whereby the larger solder balls in high stress regions carry input/output signals between a circuit board and a package mounted thereon. The larger solder balls are accommodated by recessing each ball in the package substrate, the circuit board, or both the package substrate and the circuit board. Additionally, a ball attach method for mounting a plurality of solder balls having different average diameters is disclosed.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: April 13, 2021
    Assignee: Intel Corporation
    Inventors: MD Altaf Hossain, Scott A. Gilbert
  • Patent number: 10978364
    Abstract: A semiconductor module is obtained in which breakage of the semiconductor module can be detected in advance while suppressing increase in manufacturing cost. A semiconductor module includes a semiconductor element, a circuit board, a resistor, a first wiring member, and a detector. The circuit board includes a circuit pattern. The resistor is connected to a surface of the circuit pattern. The first wiring member directly connects the resistor to the semiconductor element. In the first wiring member, at least part of current flowing from the semiconductor element to the circuit pattern flows. The detector is configured to detect at least one of a change of a voltage drop value in the resistor and a change of a current value in the resistor.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: April 13, 2021
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Akihisa Fukumoto, Yasushi Nakayama, Hiroshi Kobayashi
  • Patent number: 10964622
    Abstract: A cooler (1) has a cooling plate (1a), a cooling fin (1b) provided on a center portion of a lower surface of the cooling plate (1a), and a lower projection (1c) provided on a peripheral portion of the lower surface of the cooling plate (1a). A semiconductor device (3) is provided on an upper surface of the cooling plate (1a). A bus bar (5) is connected to the semiconductor device (3). A cooling mechanism (8) encloses a lower surface and a lateral surface of the cooler (1). An O-ring (9) is provided between a lower surface of the lower projection (1c) and a bottom surface of the cooling mechanism (8). A bolt (10) penetrates a sidewall of the cooling mechanism (8) and screws the cooler (1) to the cooling mechanism (8).
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: March 30, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventors: Ryoji Murai, Natsuki Tsuji
  • Patent number: 10930617
    Abstract: The present disclosure provides a wafer-level system-in-package (WLSiP) packaging method and a WLSiP package structure. The WLSiP package structure includes a device substrate including a substrate and a plurality of first chips on the substrate, an encapsulation layer, covering the device substrate, a plurality of second chips embedded in the encapsulation; and an electrical connection structure, electrically connecting at least one of the plurality of second chips with at least one of the plurality of first chips. The plurality of first chips and the plurality of second chips are staggered from each other.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: February 23, 2021
    Assignee: Ningbo Semiconductor International Corporation
    Inventor: Mengbin Liu