Abstract: A package structure includes an insulating encapsulation, a semiconductor die, and a filter structure. The semiconductor die is encapsulated in the insulating encapsulation. The filter structure is electrically coupled to the semiconductor die, wherein the filter structure includes a patterned metallization layer with a pattern having a double-spiral having aligned centroids thereof.

Abstract: A buffer layer, an etching stop layer, and a channel layer are epitaxially grown in this order on a substrate. The substrate contains InP that has a high resistance by, for example, being doped with Fe. The buffer layer contains a compound semiconductor lattice-matched to InP. The etching stop layer includes InxAl1-xP (0?x?0.75). The channel layer contains InyGa1-y As (0<y?1).

Abstract: A semiconductor device includes an integrated circuit (IC) and an interlayer dielectric layer on the substrate, a contact through the interlayer dielectric layer and electrically connected to the IC, a wiring layer on the interlayer dielectric layer with a wiring line electrically connected to the contact, a first passivation layer on the wiring layer, first and second pads on the first passivation layer, and a through electrode through the substrate, the interlayer dielectric layer, the wiring layer, and the first passivation layer to connect to the first pad. The first pad includes a first head part on the first passivation layer, and a protruding part that extends into the first passivation layer from the first head part, the protruding part surrounding a lateral surface of the through electrode in the first passivation layer, and the second pad is connected to the IC through the wiring line and the contact.

Abstract: A die package and method is disclosed. In one example, the die package includes a die having a first die contact on a first side and a second die contact on a second side opposite the first side, and insulating material laterally adjacent to the die. A metal structure substantially directly contacts the surface of the second die contact, wherein the metal structure is made of the same material as the second die contact. A first pad contact on the first side of the die electrically contacts the first die contact, and a second pad contact on the first side of the die electrically contacts the second die contact via the metal structure. The insulating material electrically insulates the metal structure from the first die contact.

Abstract: A fan-out wafer level package includes a semiconductor die with a redistribution layer on a sidewall of the semiconductor die. A redistribution layer positioned over the die includes an extended portion that extends along the sidewall. The semiconductor die is encapsulated in a molding compound layer. The molding compound layer is positioned between the extended portion of the redistribution layer and the sidewall of the semiconductor die. Solder contacts, for electrically connecting the semiconductor device to an electronic circuit board, are positioned on the redistribution layer. The solder contacts and the sidewall of the redistribution layer can provide electrical contact on two different locations. Accordingly, the package can be used to improve interconnectivity by providing vertical and horizontal connections.

Abstract: A clip for connecting an electronic component with a carrier in a package is provided. The clip includes a clip body having a component connection portion configured to be connected with the electronic component to be mounted on the carrier, and a carrier connection portion configured to be connected with the carrier. The clip further includes at least one locking recess in a surface portion of the clip body, the surface portion being configured to face the carrier. The at least one locking recess is configured to accommodate material of an encapsulant of the package so as to lock the encapsulant and the clip. A corresponding method of manufacturing the package is also provided.

Abstract: The embodiments of the application provides an end cover assembly, a battery cell, a battery module and a device, the end cover assembly is used for the battery cell, the end cover assembly includes an end cover; an electrode terminal disposed on the end cover; an insulating member for insulating the electrode terminal and the end cover and disposed to surround the electrode terminal; wherein the insulating member abuts the electrode terminal, at least one of the insulating member and the electrode terminal is provided with a stress relief groove, the stress relief groove is configured to absorb stress generated by the electrode terminal's abutting the insulating member.

Abstract: According to one embodiment, a semiconductor device includes a wiring board that has a first surface and a second surface opposed to the first surface, a semiconductor chip provided on the first surface, external connection terminals provided on the second surface, a sealing resin layer provided on the first surface, and a conductive shield layer that covers at least a portion of a side surface of the wiring board and the sealing resin layer. The wiring board includes a first ground wire that is electrically connected to the conductive shield layer, and a second ground wire that is electrically connected to the conductive shield layer and is electrically insulated from the first ground wire.

Abstract: A semiconductor guide pin is disclosed. Specific implementations may include a heatsink, one or more substrates coupled together, one or more pressfit pins coupled to the one or more substrates, and two or more guide pins coupled to the one or more substrates, where the two or more guide pins may have a height greater than the one or more pressfit pins.

Abstract: A power module (10) for operating an electric vehicle drive includes a current input configured for supplying an input current. The current input includes multiple contact elements (182, 184). Multiple circuit-breakers (142, 144) are configured for generating an output current based on the supplied input current. A current output (192) is configured for outputting the output current at a consumer. A substrate (12) includes a metal layer (122-130) and an insulating layer (121) connected to the metal layer (122-130). The multiple circuit-breakers (142, 144) are arranged on the metal layer (122-130). The multiple contact elements (182, 184) are also arranged on the metal layer (122-130) such that the multiple contact elements (182, 184) extend perpendicular to a surface of the substrate (12).

Abstract: A semiconductor package includes a first substrate including a circuit pattern and a dummy pattern on an upper face of the first substrate, a solder ball, a second substrate on the first substrate, and an underfill material layer between the first and second substrates. The underfill material layer wraps around the solder ball. The dummy pattern is not electrically connected to the circuit pattern. The first substrate includes a solder resist layer on the circuit pattern and the dummy pattern. The solder resist layer includes a first opening for exposing at least a part of the circuit pattern. The solder ball is in the first opening and electrically insulated from the dummy pattern by the solder resist layer. The second substrate is electrically connected to the first substrate by the solder ball. The second substrate is electrically insulated from the dummy pattern by the solder resist layer.

Abstract: A semiconductor device, including a semiconductor chip having a first electrode on a rear surface thereof, a laminated substrate including a heat dissipation board laminated on a rear surface of an insulating board, and a case. The case includes a frame surrounding an opening penetrating the case from a front surface to a rear surface thereof, the frame being in contact with a periphery of the laminated substrate covering the opening from the rear surface of the case, and a first terminal penetrating the frame. The first terminal includes a first connection part penetrating the frame and extending out of the frame, and a first wiring part provided in the opening. The first wiring part has a wiring rear surface disposed on a front surface of the insulating board, and a wiring front surface mechanically and electrically connected to the first electrode of the semiconductor chip.

Abstract: Disclosed are support substrates, methods of fabricating semiconductor packages using the same, and methods of fabricating electronic devices using the same. The support substrate comprises a main body, and a plurality of first protrusions finely protruding from an upper surface of the main body. The main body and the first protrusions include the same material and are formed as a unitary structure. The first protrusions are spaced apart from each other in first and second directions intersecting each other, when viewed in plan.

Abstract: A packaged semiconductor device includes a lead frame including plurality of lead terminals each having a plated wettable flank dimple including 2 or more different widths including narrower lead terminals and wider lead terminals. A semiconductor die is attached to the lead frame. A mold material terminates at a saw line of the packaged semiconductor device providing encapsulation except for an exposed bottom contact and an exposed sidewall contact for the plurality of lead terminals. The wider lead terminals have a necked region with a reduced width extending inward a predetermined distance from the saw line, where a terminal region inward beyond the necked region which is wider as compared to the necked region.

Abstract: In a general aspect, a method for producing a semiconductor device assembly can include defining a cavity in a conductive spacer, and electrically and thermally coupling a semiconductor die with the conductive spacer, such that the semiconductor die is at least partially embedded in the cavity. The semiconductor die can have a first surface having active circuitry included therein, a second surface opposite the first surface, and a plurality of side surfaces each extending between the first surface of the semiconductor die and the second surface of the semiconductor die. The method can also include electrically coupling a direct bonded metal (DBM) substrate with the first surface of the semiconductor die.

Abstract: A semiconductor package includes a first semiconductor chip including a first surface and a second surface, and including a first active layer on a portion adjacent to the first surface; a first redistribution structure on the first surface of the first semiconductor chip, wherein the first redistribution structure includes a first area and a second area next to the first area; a second semiconductor chip mounted in the first area of the first redistribution structure, including a third surface, which faces the first surface, and a fourth surface, and including a second active layer on a portion adjacent to the third surface; a conductive post mounted in the second area of the first redistribution structure; a molding layer at least partially surrounding the second semiconductor chip and the conductive post on the first redistribution structure; and a second redistribution structure disposed on the molding layer and connected to the conductive post.

Abstract: Semiconductor devices having redistribution structures, and associated systems and methods, are disclosed herein. In some embodiments, a semiconductor assembly comprises a die stack including a plurality of semiconductor dies, and a routing substrate mounted on the die stack. The routing substrate includes an upper surface having a redistribution structure. The semiconductor assembly also includes a plurality of electrical connectors coupling the redistribution structure to at least some of the semiconductor dies. The semiconductor assembly further includes a controller die mounted on the routing substrate. The controller die includes an active surface that faces the upper surface of the routing substrate and is electrically coupled to the redistribution structure, such that the routing substrate and the semiconductor dies are electrically coupled to the controller die via the redistribution structure.

Abstract: A multi-chip device is provided. The multi-chip device includes a first chip, a second chip mounted on the first chip, and a hardened printed or sprayed electrically conductive material forming a sintered electrically conductive interface between the first chip and the second chip.

Abstract: A package substrate and method of manufacturing a package substrate and a semiconductor device package are provided. The package substrate includes a circuit layer, an optically-cured dielectric layer, a plurality of block layers and a sacrificial layer. The circuit layer includes a plurality of conductive pads. The optically-cured dielectric layer has an upper surface and a lower surface opposite to the upper surface. The optically-cured dielectric layer covers the circuit layer, and first surfaces of the conductive pads are at least partially exposed from the upper surface of the optically-cured dielectric layer. The block layers are respectively disposed on the first surfaces of the conductive pads exposed by the optically-cured dielectric layer. The sacrificial layer is disposed on the optically-cured dielectric layer and covering the block layers.

Abstract: A semiconductor device has a semiconductor die and an encapsulant deposited over the semiconductor die. A first conductive layer is formed with an antenna over a first surface of the encapsulant. A second conductive layer is formed with a ground plane over a second surface of the encapsulant with the antenna located within a footprint of the ground plane. A conductive bump is formed on the ground plane. A third conductive layer is formed over the first surface of the encapsulant. A fourth conductive layer is formed over the second surface of the encapsulant. A conductive via is disposed adjacent to the semiconductor die prior to depositing the encapsulant. The antenna is coupled to the semiconductor die through the conductive via. The antenna is formed with the conductive via between the antenna and semiconductor die. A PCB unit is disposed in the encapsulant.

Abstract: A power semiconductor module arrangement includes a semiconductor substrate arranged in a housing, at least one semiconductor body being arranged on the semiconductor substrate, and a mounting arrangement including a frame or body, a first terminal element, and a second terminal element. The mounting arrangement is inserted in and coupled to the housing. Each terminal element mechanically and electrically contacts the semiconductor substrate with a first end. A middle part of each terminal element extends through the frame or body. A second end of each terminal element extends outside the housing. The first terminal element is dielectrically insulated from the second terminal element by a portion of the frame or body. The first terminal element is injected into and inextricably coupled to the frame or body. The second terminal element is arranged within a hollow space inside the frame or body and is detachably coupled to the frame or body.

Abstract: Various heatsink arrangements, and methods for implementing and using such are discussed.

Abstract: A semiconductor package is provided. The semiconductor package may include a substrate, a chip stack disposed on the substrate, the chip stack including a plurality of semiconductor chips, a plurality of bonding wires electrically connecting the substrate to the plurality of semiconductor chips, a reinforcement layer disposed on the chip stack, and a molding layer surrounding side surfaces of the chip stack and the bonding wires and contacting side surfaces of the reinforcement layer. The reinforcement layer may include a lower layer including an adhesive, an intermediate layer disposed on the lower layer, and an upper layer disposed on the intermediate layer. The intermediate layer may have elongation in a range of 5% to 70%. The upper layer may have elongation less than 5%.

Abstract: A method for manufacturing a three-dimensional integrated circuit includes attaching a first side of a first die to a first carrier wafer. The method includes preparing a second side of the first die to generate a prepared second side of the first die. The method includes attaching the prepared second side of the first die to a second carrier wafer. The method includes removing the first carrier wafer from the first side of the first die to form a transitional three-dimensional integrated circuit. The method includes attaching a third carrier wafer to a first side of the transitional three-dimensional integrated circuit. The method includes attaching a first side of the second die to a second side of the transitional three-dimensional integrated circuit.

Abstract: Structures and formation methods of a package structure are provided. The method includes forming a conductive structure over a carrier substrate and disposing a semiconductor die over the carrier substrate. The method also includes pressing a protective substrate against the carrier substrate at an elevated temperature to bond the protective substrate to the conductive structure. The method further includes forming a protective layer to surround the semiconductor die.

Abstract: A lead for a surface mount package for a semiconductor device, and the surface mount package employing the same. In one example, the lead includes a central segment with a first side and a second side, a first extension from a portion of the first side, and a second extension from a portion of the second side. The lead also includes a recess extending through a portion of the central segment, the first extension and the second extension.

Abstract: A semiconductor device with redistribution layers on partial encapsulation is disclosed and may include providing a carrier with a non-photosensitive protection layer, forming a pattern in the non-photosensitive protection layer, providing a semiconductor die with a contact pad on a first surface, and bonding the semiconductor die to the non-photosensitive protection layer such that the contact pad aligns with the pattern formed in the non-photosensitive protection layer. A second surface opposite to the first surface of the semiconductor die, side surfaces between the first and second surfaces of the semiconductor die, and a portion of a first surface of the non-photosensitive protection layer may be encapsulated with an encapsulant. The carrier may be removed leaving the non-photosensitive protection layer bonded to the semiconductor die. A redistribution layer may be formed on the contact pad and a second surface of the non-photosensitive protection layer opposite to the first surface.

Abstract: A three-Dimensional Integrated Circuit (3DIC) Chip on Wafer on Substrate (CoWoS) packaging structure or system includes a silicon oxide interposer with no metal ingredients, and with electrically conductive TVs and RDLs. The silicon oxide interposer has a first surface and a second surface opposite to the first surface. The electrically conductive TVs penetrate through the silicon oxide interposer. The electrically interconnected RDLs are disposed over the first surface of the silicon oxide interposer, and are electrically coupled or connected to a number of the conductive TVs.

Abstract: A semiconductor memory device includes first and second memory chips, each including a region of a core circuit, a first area adjacent to a first side of the region in a first direction, a second area adjacent to a second side of the region in a second direction, a third area adjacent to the first area in the first direction and to the second area in the second direction, a first pad in the first area, a second pad in the second area, and third pad in the third area. In each memory chip, a first bonding wire connects the first and third pads. In addition, a second bonding wire connects the second pads of the first and second memory chips. The second memory chip is stacked on the first memory chip to expose the first, second, and third areas of the first memory chip in a third direction.

Abstract: Structures and formation methods of a chip package are provided. The chip package includes a substrate and a semiconductor die over the substrate. The chip package also includes a lid covering a top surface of the semiconductor die. The lid has a first support structure and a second support structure, and the first support structure and the second support structure are positioned at respective corner portions of the substrate. An opening penetrates through the lid to expose a space containing the semiconductor die, and the lid has a side edge extending from an edge of the first support structure to an edge of the second support structure.

Abstract: A component source wafer comprises printable components having adhesive disposed on a backside of the printable components. A wafer substrate comprises a sacrificial layer having recessed portions and anchors. A component is disposed entirely over each recessed portion. A tether physically connects each component to at least one of the anchors. A layer of adhesive is disposed on a side of the component adjacent to the recessed portion. Each component is suspended over the wafer substrate and the recessed portion defines a gap separating the component from the wafer substrate.

Abstract: A chip package including a lead frame, a first chip, a heat dissipation structure, and an insulating encapsulant is provided. The lead frame includes a chip pad having a first surface and a second surface opposite to the first surface and a lead connected to the chip pad. The first chip is disposed on the first surface of the chip pad and electrically connected to the lead of the lead frame and to the outside of the insulating encapsulant via the lead. The head dissipation structure is disposed on the second surface of the chip pad and includes a thermal interface material layer attached to the second surface. The insulating encapsulant encapsulates the first chip, the heat dissipation structure, and a portion of the lead frame.

Abstract: A method for preparing a bactericidal film on fiber cloth, comprising cleansing a reel of fiber cloth; placing the reel of fiber cloth into a vacuum chamber; supplying a DC power and a mid-frequency power; introducing argon gas to increase the chamber pressure to 0.3 Pa; position sputtering targets in the following order: silicon target, silicon carbide target, silver target, silicon carbide target, silver target, silicon carbide target and silver target, and then sputtering the targets simultaneously; wherein the silicon targets act as a bonding layer between the bactericidal film and the substrate; stopping the silicon targets, the silicon carbide targets and the silver targets first, and then turning off the argon gas; injecting air into the chamber until the pressure in the chamber and the atmospheric pressure are balanced.

Abstract: Reliable resin packages and semiconductor light-emitting devices using the resin package can include a printed circuit board including a resin layer, metallic layers formed on a top surface of the resin layer and underneath a bottom surface of the resin layer and a frame arranged from a top surface of the printed circuit board toward a bottom surface of the printed circuit board. The semiconductor light-emitting device using the resin package can prevent the printed circuit board from warping toward the frame when forming the frame incorporating the printed circuit board because a total of each thickness of the metallic layers formed on the top surface and underneath the bottom surface of the resin layer can be thicker than a thickness of the resin layer. Thus, the present invention can provide the semiconductor light-emitting devices having high reliability, which can be used as a light source for vehicle lamps, etc.

Abstract: A semiconductor package includes a lower package, an interposer on the lower package, and an under-fill layer between the interposer and the lower package. The interposer includes a through hole that vertically penetrates the interposer. The under-fill layer includes an extension that fills at least a portion of the through hole.

Abstract: Stacked semiconductor dies for semiconductor device assemblies and associated methods and systems are disclosed. In some embodiments, the semiconductor die assembly includes a substrate with a first opening in an inner portion and a second opening in an outer portion of the substrate. Further, the semiconductor die assembly can include a master die attached to a front side of the substrate, where the master die includes a first bond pad proximate to the first opening and a second bond pad proximate to the second opening. The first and second bond pads of the master die can be coupled with first and second substrate bond pads on a back side of the substrate, opposite to the front side, using first and second bonding wires extending through the first and second openings, respectively.

Abstract: A package structure and a method for connecting components are provided, in which the package includes a first substrate including a first wiring and at least one first contact connecting to the first wiring; a second substrate including a second wiring and at least one second contact connecting to the second wiring, the at least one first contact and the at least one second contact partially physically contacting with each other or partially chemically interface reactive contacting with each other; and at least one third contact surrounding the at least one first contact and the at least one second contact. The first substrate and the second substrate are electrically connected with each other at least through the at least one first contact and the at least one second contact.

Abstract: A semiconductor package includes a lower connection structure, a semiconductor chip on the lower connection structure, an upper connection structure including a first conductive pattern layer on the semiconductor chip, a first insulating layer on the first conductive pattern layer, a second conductive pattern layer on the first insulating layer, a first via penetrating the first insulating layer to extend between the first conductive pattern layer and the second conductive pattern layer, and a second insulating layer extending between a side surface of the first via and the first insulating layer, and an intermediate connection structure between the lower connection structure and the upper connection structure. A chemical composition of the first insulating layer may differ from a chemical composition of the second insulating layer.

Abstract: A circuit device capable of significantly improving heat dissipation performance of a printed circuit board without increasing the size includes a printed circuit board, a mounted component, a non-solid metal spacer, a cooler, and a resin layer. The mounted component is at least partially disposed on at least one main surface of printed circuit board. The non-solid metal spacer is disposed at least on one main surface of the printed circuit board. The cooler is disposed at the non-solid metal spacer on the opposite side to the printed circuit board. The resin layer is disposed between the non-solid metal spacer and the cooler. The non-solid metal spacer has a shape that allows at least one hollow portion to be formed between the printed circuit board and the cooler.

Abstract: Some embodiments include methods of forming integrated assemblies. First conductive structures are formed within an insulative support material and are spaced along a first pitch. Upper regions of the first conductive structures are removed to form first openings extending through the insulative support material and over lower regions of the first conductive structures. Outer lateral peripheries of the first openings are lined with spacer material. The spacer material is configured as tubes having second openings extending therethrough to the lower regions of the first conductive structures. Conductive interconnects are formed within the tubes. Second conductive structures are formed over the spacer material and the conductive interconnects. The second conductive structures are spaced along a second pitch, with the second pitch being less than the first pitch. Some embodiments include integrated assemblies.

Abstract: A semiconductor package includes a first substrate, a second substrate, a conductive component, an electronic component and a passive component. The conductive component is disposed between the first substrate and the second substrate, wherein the first substrate and the second substrate are separated from each other by an interval. The electronic component and the passive component are disposed within the interval.

Abstract: A semiconductor device includes a first semiconductor die, a first encapsulant surrounding the first semiconductor die, and a first redistribution structure formed on the first semiconductor die and the first encapsulant. The semiconductor device further includes a second semiconductor die, a second encapsulant surrounding the second semiconductor die, and a second redistribution structure formed on the second semiconductor die and the second encapsulant. The semiconductor device also include a conductive via electrically connecting the first redistribution structure to the second redistribution structure.

Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a first electronic component having an active surface and a backside surface opposite to the active surface and a first antenna layer disposed on the backside surface of the first electronic component. The semiconductor device package further includes a first dielectric layer covering the first antenna layer and a second antenna layer disposed over the first antenna layer. The second antenna layer is spaced apart from the first antenna layer by the first dielectric layer. A method of manufacturing a semiconductor device package is also disclosed.

Abstract: An implantable stimulator is provided having a conformable foil-like substrate, having a longitudinal axis extending from a pulse generator to a distal end of the substrate. The substrate comprising one or more adjacent polymeric substrate layers and an electrode array. The electrode array having a first and second electrode where one or more electrical interconnections are comprised in the substrate. The conformable foil-like substrate has a maximum thickness of 0.5 millimeter or less, proximate the electrodes. By providing a more easily patternable multilayer substrate, more complicated electrode array configurations may be supported, allowing a higher degree of flexibility to address transverse and/or longitudinal misalignment. By providing a relatively thin implantable electrode array user comfort may be increased through application of energy to tissue by the implantable stimulator.

Abstract: A semiconductor device package includes a substrate, a first molding compound and antenna layer. The substrate has a first surface and a second surface opposite to the first surface. The first molding compound is disposed on the first surface of the substrate. The antenna layer is disposed on the first molding compound. The substrate, the first molding compound and the antenna layer define a cavity.

Abstract: A method includes forming a composite material layer over a carrier, the composite material layer including particles of a filler material incorporated into a base material, forming a set of through vias over a first side of the composite material layer, attaching a die over the first side of the composite material layer, the die being spaced apart from the set of through vias, forming a molding material over the first side of the composite material layer, the molding material least laterally encapsulating the die and the through vias of the set of through vias, forming a redistribution structure over the die and the molding material, the redistribution structure electrically connected to the through vias, forming openings in a second side of the composite material layer opposite the first side, and forming conductive connectors in the openings, the conductive connectors electrically connected to the through vias.

Abstract: There are provided a semiconductor unit that prevents connection failure caused by a wiring substrate to improve reliability, a method of manufacturing the semiconductor unit, and an electronic apparatus including the semiconductor unit. The semiconductor unit includes: a device substrate including a functional device and an electrode; a first wiring substrate electrically connected to the functional device through the electrode; and a second wiring substrate electrically connected to the functional device through the first wiring substrate.

Abstract: A circuit interconnect for high bandwidth and high die-count memory stacks. The circuit interconnect may include a first ground trace, a first signal trace, a second ground trace, and a second signal trace. The first ground trace may reside in a first layer of a multilayer printed circuit board. The first signal trace may be positioned adjacent to the first ground trace within the first layer. The second ground trace may reside within a second layer of the multilayer printed circuit board. The second signal trace may be positioned adjacent to the second ground trace within the second layer.

Abstract: A package structure includes an insulating encapsulation, a semiconductor die, and a filter structure. The semiconductor die is encapsulated in the insulating encapsulation. The filter structure is electrically coupled to the semiconductor die, wherein the filter structure includes a patterned metallization layer with a pattern having a double-spiral having aligned centroids thereof.

Abstract: A semiconductor package may include a package substrate, a support structure on the package substrate and having a cavity therein, and at least one first semiconductor chip on the package substrate in the cavity. The support structure may have a first inner sidewall facing the cavity, a first top surface, and a first inclined surface connecting the first inner sidewall and the first top surface. The first inclined surface may be inclined with respect to a top surface of the at least one first semiconductor chip.