With Contact Or Lead Patents (Class 257/690)
  • Patent number: 10340198
    Abstract: The invention provides a semiconductor package and a method for fabricating the same. The semiconductor package includes a redistribution layer (RDL) structure, a semiconductor die, a molding compound and a supporter. The RDL structure has a first surface and a second surface opposite to the first surface. The semiconductor die is disposed on the first surface of the RDL structure and electrically coupled to the RDL structure. The molding compound is positioned overlying the semiconductor die and the first surface of the RDL structure. The supporter is positioned beside the semiconductor die and in contact with the first surface of the RDL structure.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: July 2, 2019
    Assignee: MEDIATEK INC.
    Inventors: Ta-Jen Yu, Wen-Sung Hsu
  • Patent number: 10332867
    Abstract: An illumination assembly includes a substrate, a wiring structure, a reflecting layer and a plurality of light-emitting diodes. The wiring structure is formed on a part of the substrate, and includes a catalyst layer covering the part of the substrate, and a conducting layer formed on the catalyst layer. The reflecting layer is formed on another part of the substrate that is exposed from the wiring structure. The light-emitting diodes are disposed on the wiring structure and are electrically connected to the wiring structure.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: June 25, 2019
    Assignee: Taiwan Green Point Enterprises Co., Ltd.
    Inventors: Yu-Chuan Lin, Pen-Yi Liao, Hui-Ching Chuang, Chih-Hao Chen, Ai-Ling Lin
  • Patent number: 10326052
    Abstract: Embodiments relate to a light emitting structure including a light emitting diode, a first contact, and a second contact. The light emitting diode includes a body of transparent semiconductor material with a top surface and a light emitting region below the top surface. The light emitting region emits light in response to current passing through the light emitting region; the emitted light passes through the body of the light emitting diode. The first contact is connected to the top surface of the body and has a spiral shape to induce an electromagnetic field. The electromagnetic field shapes the light emitted from the light emitting region and passes through the body of the light emitting diode. The second contact is connected to a surface of the light emitting structure. A voltage difference can be applied across the first contact and second contact to generate the current through the light emitting region.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: June 18, 2019
    Assignee: Facebook Technologies, LLC
    Inventor: Christopher Percival
  • Patent number: 10319661
    Abstract: In a semiconductor device, an outer peripheral case body has guiding portions formed therein as a plurality of recesses. The plurality of guiding portions each include an upper end opening. The outer peripheral case body has inner peripheral side openings formed in its inner peripheral surface, each of which is continuous with the upper end opening, extends from an upper end face toward a base body and is continuous with the guiding portion. The first insertion portion is inserted into a first guiding portion of the plurality of guiding portions. The first external terminal portion is continuous with the first insertion portion and extends through the upper end opening in the first guiding portion to outside of the outer peripheral case body. The first connection terminal portion is continuous with the first insertion portion and connected to a conductive pattern through the inner peripheral side opening.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: June 11, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hayato Nagamizu, Takuro Mori, Yoshitaka Otsubo
  • Patent number: 10319684
    Abstract: A semiconductor device has a first conductive layer and a second conductive layer. A first portion of the first conductive layer is aligned with a first portion of the second conductive layer. An insulating layer is deposited over the first conductive layer and second conductive layer. A third conductive layer includes a first portion of the third conductive layer vertically aligned with the first portion of the first conductive layer and the first portion of the second conductive layer. An electrical component is disposed over the first conductive layer and second conductive layer. An encapsulant is deposited over the first conductive layer, second conductive layer, and electrical component. A cut is made through the encapsulant, first conductive layer, and second conductive layer. A fourth conductive layer is deposited over side surfaces of the first conductive layer, second conductive layer, and encapsulant.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: June 11, 2019
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: InSang Yoon, SeungYong Chai, SoYeon Park
  • Patent number: 10319849
    Abstract: The semiconductor device has a first external electrode having an outer peripheral section, which has a circular shape in top plan view and which is to be attached to an alternator. On the first external electrode there mounted: a MOSFET chip; a control circuitry to which voltages at or a current flowing between a first main terminal and a second main terminal of the MOSFET chip is inputted and which generates, on the basis of the voltages or the current, a control signal applied to a gate of the MOSFET chip; and a capacitor for providing a power supply to the control circuitry. The semiconductor device further has a second external electrode disposed opposite to the first external electrode with respect to the MOSFET chip. An electrical connection is made between the first main terminal of the MOSFET chip and the first external electrode, and between the second main terminal of the MOSFET chip and the second external electrode.
    Type: Grant
    Filed: December 12, 2014
    Date of Patent: June 11, 2019
    Assignee: Hitachi Power Semiconductor Device, Ltd.
    Inventors: Tetsuya Ishimaru, Mutsuhiro Mori, Junichi Sakano, Kohhei Onda
  • Patent number: 10305411
    Abstract: A semiconductor module includes a die pad area between positions where a plurality of power terminals are arranged and positions where an HVIC and an LVIC are arranged. A plurality of RC-IGBTs are arranged in the die pad area at positions closer to the plurality of power terminals than to the HVIC and the LVIC.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: May 28, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Maki Hasegawa, Takuya Shiraishi
  • Patent number: 10304791
    Abstract: An electronic component package includes: a frame, including a through-hole and a through-wiring; an electronic component disposed in the through-hole of the frame; a metal plate disposed on a first side of the electronic component and the frame; and a redistribution layer disposed on a second side of the electronic component opposing the first side and electrically connected to the electronic component.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: May 28, 2019
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Yun Tae Lee, Moon Il Kim
  • Patent number: 10297552
    Abstract: A semiconductor device having an embedded semiconductor die and substrate-to-substrate interconnects is disclosed and may include a substrate with a top surface and a bottom surface, a semiconductor die bonded to the top surface of the substrate, a first mold material encapsulating the semiconductor die and at least a portion of the top surface of the substrate, and a first conductive bump that is on the top surface of the substrate and is at least partially encapsulated by the first mold material. An extended substrate may be coupled to the substrate utilizing the first conductive bump. A second conductive bump may be formed on the bottom surface of the substrate, and a second mold material may encapsulate at least a portion of the second conductive bump and at least a portion of the bottom surface of the substrate. A third mold material may be formed between the first mold material and the extended substrate.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: May 21, 2019
    Assignee: Amkor Technology, Inc.
    Inventors: Jin Seong Kim, Ye Sul Ahn, Cha Gyu Song
  • Patent number: 10299381
    Abstract: According to one embodiment, an electronic device includes a substrate including a first face, a plurality of first conductors on the first face, a plurality of second conductors on the first face, and a first electronic component mounted on the first face, and including a first terminal connected to the plurality of first conductors, and a second terminal connected to the plurality of second conductors.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: May 21, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Naoki Kimura, Tatsuro Hiruta
  • Patent number: 10297533
    Abstract: A semiconductor device is provided, including: a bottom portion having a pad formed of a conductive material; a lid portion covering at least a part of the bottom portion; and a first terminal portion and a second terminal portion which are provided in parallel with each other, are fixed to the lid portion, and each contact a corresponding pad, wherein: the first terminal portion is provided with a first plate-shaped portion; the second terminal portion is provided with a second plate-shaped portion; and each of the first plate-shaped portion and the second plate-shaped portion has a principal surface in a direction facing the pad and is flexible in a direction toward the pad.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: May 21, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Yoshihiro Kodaira
  • Patent number: 10290593
    Abstract: A method of assembling QFP devices includes providing a lead frame having leads that extend from a dam bar to a die flag, and performing a first molding process that fills spaces between the leads and between the dam bar and the die flag with a first mold compound. The first mold compound also forms a ring around the die flag, where the ring extends from both lateral sides of the lead frame. A first area around the die flag is removed to separate the leads from the die flag, and a second area near an inner corner of the dam bar is removed to form a mold gate. A die is attached to the die flag and electrically connected to the leads with bond wires, and then a second molding process is performed to encapsulate the die, bond wires and inner leads.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: May 14, 2019
    Assignee: NXP USA, INC.
    Inventors: Zhigang Bai, Zhijie Wang, Jinzhong Yao
  • Patent number: 10292257
    Abstract: A multilayered printed circuit board (PCB) may include a plurality of pads associated with facilitating a connection to a component. The component may include a first edge and a second edge. The plurality of pads may include a first pad, located between a second pad and the first edge. The PCB may include a plurality of vertically disposed vias electrically connected to the plurality of pads and a plurality of horizontally disposed signal layers, electrically connected by the plurality of vias, to route a set of signals toward the first edge. The set of signals may include a first signal that is routed by a first via, of the plurality of vias, and a first signal layer of the plurality of signal layers and a second signal that is routed by a second via, of the plurality of vias, and a second signal layer of the plurality of signal layers.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: May 14, 2019
    Assignee: Juniper Networks, Inc.
    Inventors: Raja C T Anand, Satish Kumar Brugumalla
  • Patent number: 10290612
    Abstract: A three-dimensional stacking technique performed in a wafer-to-wafer fashion reducing the machine movement in production. The Wafers are processed with metallic traces and stacked before dicing into separate die stacks. The traces of each layer of the stacks are interconnected via electroless plating.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: May 14, 2019
    Assignee: Invensas Corporation
    Inventors: Belgacem Haba, Ilyas Mohammed, Javier A. Delacruz
  • Patent number: 10283487
    Abstract: Embodiments of the present disclosure relate to an integrated circuit (IC) package, including a molding compound positioned on a first die and laterally adjacent to a stack of dies positioned on the first die. The stack of dies electrically couples the first die to an uppermost die, and a thermally conductive pillar extends through the molding compound from the first die to an upper surface of the molding compound. The thermally conductive pillar is electrically isolated from the stack of dies and the uppermost die. The thermally conductive pillar laterally abuts and contacts the molding compound.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: May 7, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Luke G. England, Kathryn C. Rivera
  • Patent number: 10283684
    Abstract: A light emitting device includes a first substrate, a second substrate and a plurality of micro epitaxial structures. The second substrate is disposed opposite to the first substrate. The micro epitaxial structures are periodically disposed on the substrate and located between the first substrate and the second substrate. A coefficient of thermal expansion of the first substrate is CTE1, a coefficient of thermal expansion of the second substrate is CTE2, a side length of each of the micro epitaxial structures is W, W is in the range between 1 micrometer and 100 micrometers, and a pitch of any two adjacent micro epitaxial structures is P, wherein W/P=0.1 to 0.95, and CTE2/CTE1=0.8 to 1.2.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: May 7, 2019
    Assignee: PlayNitride Inc.
    Inventors: Tzu-Yang Lin, Yu-Hung Lai, Yu-Yun Lo
  • Patent number: 10283459
    Abstract: A semiconductor device can include a first metal trace, a first via disposed on the first metal trace, a second metal trace disposed on the first via, and an insulator interposed between the first metal trace and the first via. The insulator can be configured to lower an energy barrier or redistribute structure defects or charge carriers, such that the first metal trace and the first via are electrically connected to each other when power is applied. The semiconductor device can further include a dummy via disposed on the first metal trace.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: May 7, 2019
    Assignee: University of Florida Research Foundation, Incorporated
    Inventors: Swarup Bhunia, Haoting Shen, Mark M. Tehranipoor, Domenic J. Forte, Navid Asadizanjani
  • Patent number: 10276517
    Abstract: A semiconductor device includes a mounting substrate including an interface, which is connectable with a host, and a first ground layer, a surface-mounted component mounted on the mounting substrate, and a plurality of solder balls between the mounting substrate and the surface-mounted component. The surface-mounted component includes a semiconductor chip, a package substrate that is positioned between the semiconductor chip and the solder balls and includes a second ground layer, a sealing portion that covers the semiconductor chip, and has an opening, a first conductive portion on a top surface of the sealing portion, and a second conductive portion on a side surface of the opening and electrically connected to the first conductive portion and the second ground layer. The second ground layer is electrically connected to the first ground layer through one of the solder balls.
    Type: Grant
    Filed: September 4, 2017
    Date of Patent: April 30, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Gen Watari, Masato Sugita
  • Patent number: 10276758
    Abstract: A two-stage singulation process is used in the fabrication of phosphor coated light emitting elements. Prior to the application of the phosphor coating, the individual light emitting elements are singulated using a laser dicing process (130); after application of the phosphor coating (150), the phosphor coated light emitting elements are singulated using a mechanical dicing process (180). Before laser dicing of the light emitting elements, the wafer is positioned on a piece of dicing- or die-attach-tape held by a frame; after laser dicing, the tape is stretched (140) to provide space between the individual light emitting elements that allows for the wider kerf width of the subsequent mechanical dicing (180) after application of the phosphor coating (150).
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: April 30, 2019
    Assignee: Lumileds LLC
    Inventor: Frank Lili Wei
  • Patent number: 10262918
    Abstract: A heat transfer cooling module is described. One embodiment of the module has a plate attached to a bracket. A tower is affixed the plate. One end of the tower can be in contact with the heat source. The opposite end of the tower has a radiator attached which dissipates the heat that travels from the first end of the tower to the opposite end of the tower. Both the tower and the radiator are made from efficient materials for the transfer of heat. Another embodiment of the heat transfer cooling module is shown where the device is in two pieces, the first a fin module affixed to a bracket. The heat source is in contact with a base of the fin module where the heat travels through the base, to the fins where it dissipates to ambient.
    Type: Grant
    Filed: December 23, 2015
    Date of Patent: April 16, 2019
    Inventor: Irfan Bhatti
  • Patent number: 10262962
    Abstract: A semiconductor device includes a terminal, a first semiconductor chip, a second semiconductor chip located on the first semiconductor chip, a first pad located on the first semiconductor chip and electrically disconnected from a semiconductor circuit of the first semiconductor chip, a second pad located on the second semiconductor chip and electrically connected to a semiconductor circuit of the second semiconductor chip, a first wire electrically connecting the first terminal to the first pad, and a second wire electrically connecting the first pad to the second pad.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: April 16, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Yoshihiro Monma
  • Patent number: 10244617
    Abstract: Provided is a power converter which is applied to a power converter equipped with a switching element provided on a line, and a radiator connected to a predetermined potential such as a ground potential. A noise eliminator in which a conductive member is covered with insulator is provided between the switching element (semiconductor switch) and the radiator (heatsink). A flexible connecting line connected to a conductive member of the noise eliminator is connected to an on-board line disposed on a circuit board.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: March 26, 2019
    Assignee: OMRON Corporation
    Inventors: Shingo Nagaoka, Hiroyuki Onishi, Takeo Nishikawa, Kentaro Hamana
  • Patent number: 10236228
    Abstract: An electronic component mounting board reduces shadows produced along its perimeter to improve the mountability of an electronic device and an electronic module. An electronic component mounting board (1) includes a substrate (2a) including a mount area (4) in which an electronic component (10) is mountable. The substrate (2a) includes electrode pads located at ends of the mount area (4) as viewed from above. The electronic component mounting board (1) includes a frame (2b) located outside the electrode pads (3) on the upper surface of the substrate (2a). The frame (2b) includes at least one side surface that slopes from an upper end to a lower end of the frame (2b), and flares from the upper end to the lower end as viewed from above.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: March 19, 2019
    Assignee: KYOCERA CORPORATION
    Inventor: Akihiko Funahashi
  • Patent number: 10229859
    Abstract: At least some embodiments of the present disclosure relate to a semiconductor device package. The semiconductor device package includes a first substrate, an electrical component disposed on the first substrate, a second substrate disposed over the electrical component, an adhesive layer, a spacer, and an encapsulation layer. The adhesive layer is disposed between the electrical component and the second substrate. The spacer directly contacts both the adhesive layer and the second substrate. The encapsulation layer is disposed between the first substrate and the second substrate.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: March 12, 2019
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventor: Wei-Jen Wang
  • Patent number: 10229779
    Abstract: In a method of manufacturing an embedded magnetic component, a cavity is formed in an insulating substrate. One or more drops of adhesive are applied to the cavity and a magnetic core is inserted in the cavity. The cavity and the magnetic core are then covered with a first insulating layer. Through holes are formed through the first insulating layer and the insulating substrate, and plated up to form conductive vias. Metallic traces are added to exterior surfaces of the first insulating layer and the insulating substrate to form upper and lower winding layers. The metallic traces and the conductive vias form the windings for an embedded magnetic component, such as a transformer or an inductor.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: March 12, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Jamie Harber
  • Patent number: 10224254
    Abstract: A package structure may include a one-piece metal carrier, a die, a mold layer and a redistribution layer. The one-piece metal carrier may include a bottom portion and a first supporting structure, and the one-piece metal carrier may have a recess defined by the bottom portion and the first supporting structure. The die may be disposed in the recess of the one-piece metal carrier, and the die may have a plurality of conductive bumps. The mold layer may be formed to encapsulate the die. The mold layer may expose a portion of each of the plurality of conductive bumps and a portion of the first supporting structure. The redistribution layer may be disposed on the mold layer and electrically connected to the plurality of conductive bumps.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: March 5, 2019
    Assignee: POWERTECH TECHNOLOGY INC.
    Inventors: Ming-Chih Chen, Hsien-Wen Hsu, Yuan-Fu Lan, Hung-Hsin Hsu
  • Patent number: 10211158
    Abstract: A power semiconductor module includes a direct copper bonded (DCB) substrate having a ceramic substrate, a first copper metallization bonded to a first main surface of the ceramic substrate and a second copper metallization bonded to a second main surface of the ceramic substrate opposite the first main surface. The power semiconductor module further includes a power semiconductor die attached the first copper metallization, a passive component attached the first copper metallization, a first isolation layer encapsulating the power semiconductor die and the passive component, a first structured metallization layer on the first isolation layer, and a first plurality of electrically conductive vias extending through the first isolation layer from the first structured metallization layer to the power semiconductor die and the passive component. An integrated power module and a method of manufacturing the integrated power module are also provided.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: February 19, 2019
    Assignee: Infineon Technologies AG
    Inventors: Olaf Hohlfeld, Juergen Hoegerl, Gottfried Beer, Magdalena Hoier, Georg Meyer-Berg
  • Patent number: 10211135
    Abstract: A semiconductor device includes a semiconductor element, a circuit board, metal wires, and an expanding member. The circuit board has an upper surface and a lower surface opposite the upper surface. The metal wires are formed on at least one of the upper surface and the lower surface. At least two connection terminals are formed in a terminal formation surface of the semiconductor element which is disposed so as to face the upper surface of the circuit board. The expanding member is fixed to the terminal formation surface of the semiconductor element, has a larger coefficient of linear thermal expansion than the semiconductor element, and has a size larger than the interval between adjacent two of the at least two connection terminals.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: February 19, 2019
    Assignee: JTEKT CORPORATION
    Inventor: Naoki Tani
  • Patent number: 10199311
    Abstract: A leadframe includes a frame, a die pad, a contact including a flank adjacent to the frame, a first tie bar between the frame and die pad, and a second tie bar between the die pad and contact. The leadframe is disposed over a carrier. A semiconductor die is disposed over the die pad. An encapsulant is deposited over the leadframe and semiconductor die including between the carrier and half-etched portions of the leadframe. A first trench is formed in the encapsulant to remove a portion of the frame and expose the flank of the contact. A conductive layer is formed over the flank by electroplating. A second trench is formed in the encapsulant through the second tie bar after forming the conductive layer.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: February 5, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Darrell D. Truhitte, Soon Wei Wang, Chee Hiong Chew
  • Patent number: 10192806
    Abstract: A semiconductor device includes an insulating substrate having a metal plate, an insulating resin plate, and a circuit plate laminated in order; a semiconductor element fixed to the circuit plate; a wiring member connected to an electrode disposed on a front surface of the semiconductor element or to the circuit plate of the insulating substrate; a housing accommodating the insulating substrate, the semiconductor element, and the wiring member; and a sealing material including a thermosetting resin, and sealing the insulating substrate, the semiconductor element, and the wiring member accommodated in the housing. The circuit plate of the insulating substrate is selectively formed on the insulating resin plate as a combination of a circuit pattern with a sealing material adhering pattern.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: January 29, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takahiro Nishijima, Takashi Katsuki, Toshio Denta
  • Patent number: 10186355
    Abstract: In a manufacturing method for a thermistor element (3) including: a thermistor portion (49) which is a sintered body formed from a thermistor material; and a pair of electrode wires (25) which are embedded in the thermistor portion (49) and at least one end portion of each of the electrode wires projects at an outer side of the thermistor portion (49), the resistance value of the thermistor element (3) is adjusted by performing a removal processing of removing a part of the thermistor portion (49).
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: January 22, 2019
    Assignee: NGK SPARK PLUG CO., LTD.
    Inventors: Tomoki Yamaguchi, Shinji Ban, Hiroshi Watanabe, Yasuyuki Okimura, Hiroaki Nakanishi, Seiji Oya, Seiya Matsuda
  • Patent number: 10177103
    Abstract: A fan-out semiconductor package includes: a support member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the support member and the semiconductor chip; and a connection member disposed on the support member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads. The support member includes a glass plate and an insulating layer connected to the glass plate.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: January 8, 2019
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Moon Hee Yi, Yong Ho Baek, Tae Seong Kim
  • Patent number: 10163746
    Abstract: A semiconductor package and manufacturing method thereof includes a chip member installed on an upper surface, a lower surface, or both of a substrate. The semiconductor package and manufacturing method thereof also include a mold part stacked embedding the chip member, a connection member disposed at a center portion of the mold part, and a solder part formed on a portion of the connection member.
    Type: Grant
    Filed: January 21, 2016
    Date of Patent: December 25, 2018
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jong In Ryu, Ki Joo Sim, Do Jae Yoo, Ki Ju Lee, Jin Su Kim
  • Patent number: 10163799
    Abstract: The present disclosure provides a semiconductor structure, including a first silicon layer having a through silicon via (TSV), a III-V structure over the first silicon layer, electrically coupling to the TSV, and a redistribution layer (RDL) under the first silicon layer, electrically coupling to the TSV. The present disclosure also provides a method of manufacturing a semiconductor device. The method includes providing a III-V-on-Si structure, comprising a III-V device over a silicon layer, forming a through silicon via (TSV) in the silicon layer, electrically coupling to the III-V device, and forming a redistribution layer (RDL) over a side of the silicon layer opposite to the III-V device.
    Type: Grant
    Filed: November 7, 2016
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ming-Fa Chen, Sung-Feng Yeh
  • Patent number: 10141279
    Abstract: A semiconductor device includes a semiconductor substrate, a conductor provided on a main surface of the semiconductor substrate, an insulating layer disposed to cover a surface of the conductor and having a recess from a surface thereof towards the conductor, the recess having an opening provided at a bottom portion of the recess and exposing a portion of the conductor, and an external connection terminal connected to the portion of the conductor exposed from the opening. In a plan view of the semiconductor device, the external connection terminal covers the entire opening, and the entire external connection terminal is within the recess.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: November 27, 2018
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventor: Masanori Shindo
  • Patent number: 10139456
    Abstract: A MEMS sensor according to the present invention includes a base substrate including a displaceably supported movable portion and a lid substrate covering the movable portion and functioning as a magnetic sensor that detects magnetism by making use of the Hall effect.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: November 27, 2018
    Assignee: ROHM CO., LTD.
    Inventors: Goro Nakatani, Yoshihiro Tada
  • Patent number: 10134701
    Abstract: A solder bump structure for a ball grid array (BGA) includes at least one under bump metal (UBM) layer and a solder bump formed over the at least one UBM layer. The solder bump has a bump width and a bump height and the ratio of the bump height over the bump width is less than 1.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: November 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jung-Hua Chang, Cheng-Lin Huang, Jing-Cheng Lin
  • Patent number: 10134935
    Abstract: In an embodiment, photoelectric conversion units (10) each include a package (12) accommodating a photoelectric conversion device (11). The package (12) has a front surface (12a) having a window (13); and a side surface (12c). The package (12) includes a first coupling portion (14) protruding from the side surface (12c) in a first direction X parallel to a light incident surface (11a) of the photoelectric conversion device (11), and a second coupling portion (15) recessed from the side surface (12c) in the first direction X. The first coupling portion (14) includes a first terminal (16) electrically connected with the photoelectric conversion device (11), and the second coupling portion (15) includes a second terminal (17) electrically connected with the photoelectric conversion device (11). The first coupling portion (14) and the second coupling portion (15) have shapes and sizes matching each other, and are coupled with each other by fitting.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: November 20, 2018
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Miyuki Nakai, Satoshi Shibata, Wataru Shinohara
  • Patent number: 10122237
    Abstract: An inverter circuit board to which a P-N terminal is attached such that stress applied to the circuit board can be distributed, making it possible to prevent detachment of the P-N terminal or damage to the circuit board or any components mounted thereon. Also provided is an inverter-containing electric compressor. A P-N terminal via which DC power is inputted is attached to this inverter circuit board, on which an inverter circuit is mounted. The P-N terminal is provided with the following: a pair of pins; a busbar of a prescribed length joined perpendicularly to one end of each pin; a resin molded member formed integrally with the pair of pins and the busbars; and surface-mounting terminals, soldered to the surface of the circuit board, and through-hole terminals, inserted into and soldered to through-holes in the circuit board, said terminals being provided on the pair of busbars.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: November 6, 2018
    Assignee: MITSUBISHI HEAVY INDUSTRIES THERMAL SYSTEMS, LTD.
    Inventors: Makoto Hattori, Masahiko Asai
  • Patent number: 10115704
    Abstract: A semiconductor device includes a first semiconductor chip having a first surface, a second surface on a side of the first semiconductor chip opposite to that of the first surface, a first electrode on the first surface, a second electrode on the second surface, and a first contact electrically connecting the first electrode and the second electrode, and a second semiconductor chip having a third surface facing the first surface, a fourth surface on a side of the second semiconductor chip opposite to that of the third surface and a third electrode on the fourth surface. The semiconductor device further includes a metal wire electrically connecting the first and third electrodes, a first insulating layer on the second surface, a first conductive layer that is on the first insulating layer and electrically connected to the second electrode, and a first external terminal electrically connected to the first conductive layer.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: October 30, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Jun Sagiya
  • Patent number: 10109565
    Abstract: Miniaturization of a semiconductor device is attained. An SOP1 includes: a semiconductor chip; another semiconductor chip; a die pad over which the former semiconductor chip is mounted; another die pad over which the latter semiconductor chip is mounted; a plurality of wires; and a sealing body. In plan view of the SOP1, the former semiconductor chip and the former die pad do not overlap the latter semiconductor chip and the latter die pad. Also, in a horizontal direction in cross sectional view, the former semiconductor chip and the former die pad do not overlap the latter semiconductor chip and the latter die pad.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: October 23, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Keita Takada, Tadatoshi Danno
  • Patent number: 10103303
    Abstract: A light emitting package includes a first lead frame; a second lead frame spaced apart from the first lead frame in a first direction; a body coupled to the first lead frame and the second lead frame; and a light emitting element on the first lead frame. The first lead frame includes first to fourth side parts, the first side part includes a first protrusion that protrudes outwards from one side surface of the body, and a first contact part disposed at the end of the first protrusion. The second lead frame includes fifth to eighth side parts, the fifth side part includes a second protrusion that protrudes outwards from a side surface of the body, which is symmetrical to the one side surface of the body, and a second contact part disposed at the end of the second protrusion. Each of the first contact part and the second contact part includes a second layer and first layer covers the second layer.
    Type: Grant
    Filed: November 25, 2016
    Date of Patent: October 16, 2018
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Dong Hyun Yu, Choong Youl Kim
  • Patent number: 10074581
    Abstract: A chip package includes a patterned conducting plate having a plurality of conducting sections electrically separated from each other, a plurality of conducting pads disposed on an upper surface of the patterned conducting plate, wherein a recess extending from a surface of one of the conducting pads towards an inner portion of the corresponding one of the conducting pads, a chip disposed on the conducting pads, a plurality of conducting bumps disposed on a lower surface of the patterned conducting plate, wherein each of the conducting bumps is electrically connected to a corresponding one of the conducting sections of the patterned conducting plate, and an insulating support layer partially surrounding the conducting bumps.
    Type: Grant
    Filed: August 2, 2016
    Date of Patent: September 11, 2018
    Assignee: MediaTek Inc.
    Inventors: Wen-Sung Hsu, Ming-Chieh Lin, Ta-Jen Yu
  • Patent number: 10059827
    Abstract: A conductive composition includes a mono-acid hybrid that includes an unprotected, single reactive group. The mono-acid hybrid may include substantially non-reactive groups elsewhere such that the mono-acid hybrid is functional as a chain terminator. Methods and devices using the compositions are also disclosed.
    Type: Grant
    Filed: May 6, 2016
    Date of Patent: August 28, 2018
    Inventors: Rajan Hariharan, James Hurley, Senthil Kanagavel, Jose Quinones, Martin Sobczak, Deborah Makita
  • Patent number: 10056308
    Abstract: Embodiments of the present disclosure are directed toward a molded composite enclosure for an integrated circuit (IC) assembly. In one embodiment, an enclosure for an integrated circuit (IC) assembly may include a molded lid structure having a body portion, and a side portion that extends from the body portion and forms a cavity configured to house the IC assembly, wherein the body portion and the side portion share a contiguous interior material comprising a polymer and share a contiguous exterior material comprising a metal, the contiguous interior material having an opening formed in the body portion such that the IC assembly can be thermally coupled with the contiguous exterior material through the opening. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: August 21, 2018
    Assignee: Intel Corporation
    Inventor: Paul J. Gwin
  • Patent number: 10057974
    Abstract: An electrical contactor assembly is provided including: an electrical contactor; an electrical bus bar; a panel; at least one post protruding through the panel and in contact with the electrical bus bar, the post being constructed from an electrically and thermally conductive material, wherein a first end of the at least one post is configured to electrically and thermally connect to the electrical contactor; and a liquid cooled heat sink thermally connected to a second end of the at least one post through the electrical bus bar, wherein the liquid cooled heat sink in operation circulates liquid coolant through the liquid cooled heat sink to absorb heat.
    Type: Grant
    Filed: November 4, 2016
    Date of Patent: August 21, 2018
    Assignee: HAMILTON SUNDSTRAND CORPORATION
    Inventor: Debabrata Pal
  • Patent number: 10049955
    Abstract: A fabrication method of a semiconductor package includes the steps of: forming a release layer on a carrier having concave portions; disposing chips on the release layer in the concave portions of the carrier; forming an encapsulant on the chips and the release layer; forming a bonding layer on the encapsulant; removing the release layer and the carrier so as to expose the active surfaces of the chips; and forming a circuit structure on the encapsulant and the chips. Since the release layer is only slightly adhesive to the chips and the encapsulant, the present invention avoids warpage of the overall structure during a thermal cycle caused by incompatible CTEs.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: August 14, 2018
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chiang-Cheng Chang, Meng-Tsung Lee, Jung-Pang Huang, Shih-Kuang Chiu
  • Patent number: 10043728
    Abstract: A semiconductor package structure and manufacturing method thereof are provided. Firstly, a first surface mounting unit, a first printed circuit board, and a second printed circuit board are provided. The first surface mounting unit includes a first chip and a first conductive frame, and the first conductive frame has a first carrier board and a first metal member connected to the first carrier board. A first side of the first chip is electrically connected to the first carrier board of the first conductive frame. A second side of the first chip and the first metal member are connected to the first circuit board by a first pad and a second pad respectively. The second circuit board is connected to the first carrier board and hence, the first surface mounting unit is located between the first circuit board and the second circuit board.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: August 7, 2018
    Assignee: NIKO SEMICONDUCTOR CO., LTD.
    Inventor: Chih-Cheng Hsieh
  • Patent number: 10037978
    Abstract: A semiconductor module and a stack arrangement of semiconductor modules is proposed. The semiconductor module comprises an insulated gate bipolar transistor, a wide band-gap switch, a base plate, and a press device. The insulated gate bipolar transistor and the wide band-gap switch are connected in parallel and are each mounted with a first planar terminal to a side of the base plate. Further, a second planar terminal of the insulated gate bipolar transistor and a second planar terminal of the wind band-gap switch are connected with an electrically conductive connection element, and the press device is arranged on the second planar terminal of the insulated gate bipolar transistor. Hence, when arranging the semiconductor modules in a stack arrangement, any press force is primarily applied to the insulated gate bipolar transistors of the semiconductor modules.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: July 31, 2018
    Assignee: ABB Schweiz AG
    Inventor: Munaf Rahimo
  • Patent number: 10026663
    Abstract: A semiconductor device manufacturing method is provided. In a semiconductor wafer prepared, the width of a dicing line is larger than a cut region to be diced with a dicing blade, a first chip forming region and a second chip forming region are adjacent and have the dicing line therebetween, some of the pads are formed on a first chip forming region side, and the remaining pads are formed on a second chip forming region side. The semiconductor wafer is diced with the dicing blade in such manner that, when the some of the pads are diced, a part of the dicing blade on the second chip forming region side does not abut the some of the pads, and, when the remaining pads are diced, a part of the dicing blade on the first one chip forming region side does not abut the remaining pads.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: July 17, 2018
    Assignee: DENSO CORPORATION
    Inventors: Kouji Eguchi, Takashi Nakano