With Contact Or Lead Patents (Class 257/690)
  • Patent number: 11456231
    Abstract: Various heatsink arrangements, and methods for implementing and using such are discussed.
    Type: Grant
    Filed: January 18, 2021
    Date of Patent: September 27, 2022
    Assignee: Fortinet, Inc.
    Inventors: Shen Sunny Zhong, Qian Yu, Han Hsu
  • Patent number: 11450644
    Abstract: A semiconductor package is provided. The semiconductor package may include a substrate, a chip stack disposed on the substrate, the chip stack including a plurality of semiconductor chips, a plurality of bonding wires electrically connecting the substrate to the plurality of semiconductor chips, a reinforcement layer disposed on the chip stack, and a molding layer surrounding side surfaces of the chip stack and the bonding wires and contacting side surfaces of the reinforcement layer. The reinforcement layer may include a lower layer including an adhesive, an intermediate layer disposed on the lower layer, and an upper layer disposed on the intermediate layer. The intermediate layer may have elongation in a range of 5% to 70%. The upper layer may have elongation less than 5%.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: September 20, 2022
    Assignee: SK hynix Inc.
    Inventors: Sung Su Kim, Byoung Jun Ahn
  • Patent number: 11437359
    Abstract: A method for manufacturing a three-dimensional integrated circuit includes attaching a first side of a first die to a first carrier wafer. The method includes preparing a second side of the first die to generate a prepared second side of the first die. The method includes attaching the prepared second side of the first die to a second carrier wafer. The method includes removing the first carrier wafer from the first side of the first die to form a transitional three-dimensional integrated circuit. The method includes attaching a third carrier wafer to a first side of the transitional three-dimensional integrated circuit. The method includes attaching a first side of the second die to a second side of the transitional three-dimensional integrated circuit.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: September 6, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Brett P. Wilkerson, Milind S. Bhagavat, Rahul Agarwal, Dmitri Yudanov
  • Patent number: 11430720
    Abstract: A lead for a surface mount package for a semiconductor device, and the surface mount package employing the same. In one example, the lead includes a central segment with a first side and a second side, a first extension from a portion of the first side, and a second extension from a portion of the second side. The lead also includes a recess extending through a portion of the central segment, the first extension and the second extension.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: August 30, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Naweed Anjum, Michael Gerald Amaro, Makarand Ramkrishna Kulkarni
  • Patent number: 11430739
    Abstract: Structures and formation methods of a package structure are provided. The method includes forming a conductive structure over a carrier substrate and disposing a semiconductor die over the carrier substrate. The method also includes pressing a protective substrate against the carrier substrate at an elevated temperature to bond the protective substrate to the conductive structure. The method further includes forming a protective layer to surround the semiconductor die.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: August 30, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Hao Tsai, Hsien-Wen Liu, Shin-Puu Jeng, Meng-Liang Lin, Shih-Yung Peng, Shih-Ting Hung
  • Patent number: 11424180
    Abstract: A semiconductor device with redistribution layers on partial encapsulation is disclosed and may include providing a carrier with a non-photosensitive protection layer, forming a pattern in the non-photosensitive protection layer, providing a semiconductor die with a contact pad on a first surface, and bonding the semiconductor die to the non-photosensitive protection layer such that the contact pad aligns with the pattern formed in the non-photosensitive protection layer. A second surface opposite to the first surface of the semiconductor die, side surfaces between the first and second surfaces of the semiconductor die, and a portion of a first surface of the non-photosensitive protection layer may be encapsulated with an encapsulant. The carrier may be removed leaving the non-photosensitive protection layer bonded to the semiconductor die. A redistribution layer may be formed on the contact pad and a second surface of the non-photosensitive protection layer opposite to the first surface.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: August 23, 2022
    Assignee: AMKOR TECHNOLOGY SINGAPORE HOLDING PTE. LTD.
    Inventors: Jong Sik Paek, Jin Young Kim, YoonJoo Kim, Jin Han Kim, SeungJae Lee, Se Woong Cha, SungKyu Kim, Jae Hun Bae, Dong Jin Kim, Doo Hyun Park
  • Patent number: 11417594
    Abstract: A three-Dimensional Integrated Circuit (3DIC) Chip on Wafer on Substrate (CoWoS) packaging structure or system includes a silicon oxide interposer with no metal ingredients, and with electrically conductive TVs and RDLs. The silicon oxide interposer has a first surface and a second surface opposite to the first surface. The electrically conductive TVs penetrate through the silicon oxide interposer. The electrically interconnected RDLs are disposed over the first surface of the silicon oxide interposer, and are electrically coupled or connected to a number of the conductive TVs.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: August 16, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Wen-Shiang Liao
  • Patent number: 11410974
    Abstract: A semiconductor memory device includes first and second memory chips, each including a region of a core circuit, a first area adjacent to a first side of the region in a first direction, a second area adjacent to a second side of the region in a second direction, a third area adjacent to the first area in the first direction and to the second area in the second direction, a first pad in the first area, a second pad in the second area, and third pad in the third area. In each memory chip, a first bonding wire connects the first and third pads. In addition, a second bonding wire connects the second pads of the first and second memory chips. The second memory chip is stacked on the first memory chip to expose the first, second, and third areas of the first memory chip in a third direction.
    Type: Grant
    Filed: September 3, 2020
    Date of Patent: August 9, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Masahiro Yoshihara, Toshikazu Watanabe, Nobuharu Miyata, Yasumitsu Nozawa, Tomohito Kawano, Sachie Fukuda, Akiyoshi Itou, Toshimitsu Iwasawa
  • Patent number: 11410939
    Abstract: Structures and formation methods of a chip package are provided. The chip package includes a substrate and a semiconductor die over the substrate. The chip package also includes a lid covering a top surface of the semiconductor die. The lid has a first support structure and a second support structure, and the first support structure and the second support structure are positioned at respective corner portions of the substrate. An opening penetrates through the lid to expose a space containing the semiconductor die, and the lid has a side edge extending from an edge of the first support structure to an edge of the second support structure.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: August 9, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shu-Shen Yeh, Chin-Hua Wang, Kuang-Chun Lee, Po-Yao Lin, Shyue-Ter Leu, Shin-Puu Jeng
  • Patent number: 11398399
    Abstract: A component source wafer comprises printable components having adhesive disposed on a backside of the printable components. A wafer substrate comprises a sacrificial layer having recessed portions and anchors. A component is disposed entirely over each recessed portion. A tether physically connects each component to at least one of the anchors. A layer of adhesive is disposed on a side of the component adjacent to the recessed portion. Each component is suspended over the wafer substrate and the recessed portion defines a gap separating the component from the wafer substrate.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: July 26, 2022
    Assignee: X Display Company Technology Limited
    Inventors: António José Marques Trindade, Raja Fazan Gul, Ronald S. Cok
  • Patent number: 11387159
    Abstract: A chip package including a lead frame, a first chip, a heat dissipation structure, and an insulating encapsulant is provided. The lead frame includes a chip pad having a first surface and a second surface opposite to the first surface and a lead connected to the chip pad. The first chip is disposed on the first surface of the chip pad and electrically connected to the lead of the lead frame and to the outside of the insulating encapsulant via the lead. The head dissipation structure is disposed on the second surface of the chip pad and includes a thermal interface material layer attached to the second surface. The insulating encapsulant encapsulates the first chip, the heat dissipation structure, and a portion of the lead frame.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: July 12, 2022
    Assignee: Industrial Technology Research Institute
    Inventors: Kuo-Shu Kao, Tao-Chih Chang, Wen-Chih Chen, Tai-Jyun Yu, Po-Kai Chiu, Yen-Ting Lin, Wei-Kuo Han
  • Patent number: 11377727
    Abstract: A method for preparing a bactericidal film on fiber cloth, comprising cleansing a reel of fiber cloth; placing the reel of fiber cloth into a vacuum chamber; supplying a DC power and a mid-frequency power; introducing argon gas to increase the chamber pressure to 0.3 Pa; position sputtering targets in the following order: silicon target, silicon carbide target, silver target, silicon carbide target, silver target, silicon carbide target and silver target, and then sputtering the targets simultaneously; wherein the silicon targets act as a bonding layer between the bactericidal film and the substrate; stopping the silicon targets, the silicon carbide targets and the silver targets first, and then turning off the argon gas; injecting air into the chamber until the pressure in the chamber and the atmospheric pressure are balanced.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: July 5, 2022
    Inventor: Fook Chi Mak
  • Patent number: 11367679
    Abstract: A semiconductor package includes a lower package, an interposer on the lower package, and an under-fill layer between the interposer and the lower package. The interposer includes a through hole that vertically penetrates the interposer. The under-fill layer includes an extension that fills at least a portion of the through hole.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: June 21, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ji Hwang Kim, Hyunkyu Kim, Jongbo Shim, Eunhee Jung, Kyoungsei Choi
  • Patent number: 11367813
    Abstract: Reliable resin packages and semiconductor light-emitting devices using the resin package can include a printed circuit board including a resin layer, metallic layers formed on a top surface of the resin layer and underneath a bottom surface of the resin layer and a frame arranged from a top surface of the printed circuit board toward a bottom surface of the printed circuit board. The semiconductor light-emitting device using the resin package can prevent the printed circuit board from warping toward the frame when forming the frame incorporating the printed circuit board because a total of each thickness of the metallic layers formed on the top surface and underneath the bottom surface of the resin layer can be thicker than a thickness of the resin layer. Thus, the present invention can provide the semiconductor light-emitting devices having high reliability, which can be used as a light source for vehicle lamps, etc.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: June 21, 2022
    Assignee: STANLEY ELECTRIC CO., LTD.
    Inventors: Seishi Watanabe, Daisuke Yoshimi, Kohei Tai
  • Patent number: 11362071
    Abstract: Stacked semiconductor dies for semiconductor device assemblies and associated methods and systems are disclosed. In some embodiments, the semiconductor die assembly includes a substrate with a first opening in an inner portion and a second opening in an outer portion of the substrate. Further, the semiconductor die assembly can include a master die attached to a front side of the substrate, where the master die includes a first bond pad proximate to the first opening and a second bond pad proximate to the second opening. The first and second bond pads of the master die can be coupled with first and second substrate bond pads on a back side of the substrate, opposite to the front side, using first and second bonding wires extending through the first and second openings, respectively.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: June 14, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Yeongbeom Ko, Youngik Kwon, Jong Sik Paek, Jungbae Lee
  • Patent number: 11355445
    Abstract: A semiconductor package includes a lower connection structure, a semiconductor chip on the lower connection structure, an upper connection structure including a first conductive pattern layer on the semiconductor chip, a first insulating layer on the first conductive pattern layer, a second conductive pattern layer on the first insulating layer, a first via penetrating the first insulating layer to extend between the first conductive pattern layer and the second conductive pattern layer, and a second insulating layer extending between a side surface of the first via and the first insulating layer, and an intermediate connection structure between the lower connection structure and the upper connection structure. A chemical composition of the first insulating layer may differ from a chemical composition of the second insulating layer.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: June 7, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joonsung Kim, Doohwan Lee, Taeho Ko, Bongsoo Kim, Seokbong Park
  • Patent number: 11355472
    Abstract: A package structure and a method for connecting components are provided, in which the package includes a first substrate including a first wiring and at least one first contact connecting to the first wiring; a second substrate including a second wiring and at least one second contact connecting to the second wiring, the at least one first contact and the at least one second contact partially physically contacting with each other or partially chemically interface reactive contacting with each other; and at least one third contact surrounding the at least one first contact and the at least one second contact. The first substrate and the second substrate are electrically connected with each other at least through the at least one first contact and the at least one second contact.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: June 7, 2022
    Assignee: Industrial Technology Research Institute
    Inventors: Yu-Min Lin, Tao-Chih Chang, Wei-Chung Lo
  • Patent number: 11350517
    Abstract: A circuit device capable of significantly improving heat dissipation performance of a printed circuit board without increasing the size includes a printed circuit board, a mounted component, a non-solid metal spacer, a cooler, and a resin layer. The mounted component is at least partially disposed on at least one main surface of printed circuit board. The non-solid metal spacer is disposed at least on one main surface of the printed circuit board. The cooler is disposed at the non-solid metal spacer on the opposite side to the printed circuit board. The resin layer is disposed between the non-solid metal spacer and the cooler. The non-solid metal spacer has a shape that allows at least one hollow portion to be formed between the printed circuit board and the cooler.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: May 31, 2022
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Hiroyuki Yahara, Kenta Fujii, Yuji Shirakata, Tomohito Fukuda, Takashi Kumagai, Koji Nakajima
  • Patent number: 11348871
    Abstract: Some embodiments include methods of forming integrated assemblies. First conductive structures are formed within an insulative support material and are spaced along a first pitch. Upper regions of the first conductive structures are removed to form first openings extending through the insulative support material and over lower regions of the first conductive structures. Outer lateral peripheries of the first openings are lined with spacer material. The spacer material is configured as tubes having second openings extending therethrough to the lower regions of the first conductive structures. Conductive interconnects are formed within the tubes. Second conductive structures are formed over the spacer material and the conductive interconnects. The second conductive structures are spaced along a second pitch, with the second pitch being less than the first pitch. Some embodiments include integrated assemblies.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: May 31, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Werner Juengling
  • Patent number: 11342316
    Abstract: A semiconductor package includes a first substrate, a second substrate, a conductive component, an electronic component and a passive component. The conductive component is disposed between the first substrate and the second substrate, wherein the first substrate and the second substrate are separated from each other by an interval. The electronic component and the passive component are disposed within the interval.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: May 24, 2022
    Assignee: MEDIATEK INC.
    Inventors: Tien-Yu Lu, Chu-Wei Hu, Hsin-Hsin Hsiao
  • Patent number: 11328969
    Abstract: A semiconductor device includes a first semiconductor die, a first encapsulant surrounding the first semiconductor die, and a first redistribution structure formed on the first semiconductor die and the first encapsulant. The semiconductor device further includes a second semiconductor die, a second encapsulant surrounding the second semiconductor die, and a second redistribution structure formed on the second semiconductor die and the second encapsulant. The semiconductor device also include a conductive via electrically connecting the first redistribution structure to the second redistribution structure.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: May 10, 2022
    Assignee: AMKOR TECHNOLOGY SINGAPORE HOLDING PTE. LTD.
    Inventors: Do Hyun Na, Sung Soon Park, Dae Gon Kim
  • Patent number: 11329017
    Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a first electronic component having an active surface and a backside surface opposite to the active surface and a first antenna layer disposed on the backside surface of the first electronic component. The semiconductor device package further includes a first dielectric layer covering the first antenna layer and a second antenna layer disposed over the first antenna layer. The second antenna layer is spaced apart from the first antenna layer by the first dielectric layer. A method of manufacturing a semiconductor device package is also disclosed.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: May 10, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wei-Tung Chang, Cheng-Nan Lin
  • Patent number: 11318319
    Abstract: An implantable stimulator is provided having a conformable foil-like substrate, having a longitudinal axis extending from a pulse generator to a distal end of the substrate. The substrate comprising one or more adjacent polymeric substrate layers and an electrode array. The electrode array having a first and second electrode where one or more electrical interconnections are comprised in the substrate. The conformable foil-like substrate has a maximum thickness of 0.5 millimeter or less, proximate the electrodes. By providing a more easily patternable multilayer substrate, more complicated electrode array configurations may be supported, allowing a higher degree of flexibility to address transverse and/or longitudinal misalignment. By providing a relatively thin implantable electrode array user comfort may be increased through application of energy to tissue by the implantable stimulator.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: May 3, 2022
    Assignee: Salvia BioElectronics B.V.
    Inventors: Daniel Willem Elisabeth Schobben, Hubert Cecile Francois Martens
  • Patent number: 11316274
    Abstract: A semiconductor device package includes a substrate, a first molding compound and antenna layer. The substrate has a first surface and a second surface opposite to the first surface. The first molding compound is disposed on the first surface of the substrate. The antenna layer is disposed on the first molding compound. The substrate, the first molding compound and the antenna layer define a cavity.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: April 26, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Cheng-Nan Lin, Hsu-Nan Fang
  • Patent number: 11309294
    Abstract: A method includes forming a composite material layer over a carrier, the composite material layer including particles of a filler material incorporated into a base material, forming a set of through vias over a first side of the composite material layer, attaching a die over the first side of the composite material layer, the die being spaced apart from the set of through vias, forming a molding material over the first side of the composite material layer, the molding material least laterally encapsulating the die and the through vias of the set of through vias, forming a redistribution structure over the die and the molding material, the redistribution structure electrically connected to the through vias, forming openings in a second side of the composite material layer opposite the first side, and forming conductive connectors in the openings, the conductive connectors electrically connected to the through vias.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: April 19, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Kuo Lung Pan, Tin-Hao Kuo, Hao-Yi Tsai, Hsiu-Jen Lin, Hao-Jan Pei, Ching-Hua Hsieh
  • Patent number: 11302645
    Abstract: A circuit interconnect for high bandwidth and high die-count memory stacks. The circuit interconnect may include a first ground trace, a first signal trace, a second ground trace, and a second signal trace. The first ground trace may reside in a first layer of a multilayer printed circuit board. The first signal trace may be positioned adjacent to the first ground trace within the first layer. The second ground trace may reside within a second layer of the multilayer printed circuit board. The second signal trace may be positioned adjacent to the second ground trace within the second layer.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: April 12, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: John Thomas Contreras, Sayed Mobin, Daniel Oh, Rehan Ahmed Zakai
  • Patent number: 11302766
    Abstract: There are provided a semiconductor unit that prevents connection failure caused by a wiring substrate to improve reliability, a method of manufacturing the semiconductor unit, and an electronic apparatus including the semiconductor unit. The semiconductor unit includes: a device substrate including a functional device and an electrode; a first wiring substrate electrically connected to the functional device through the electrode; and a second wiring substrate electrically connected to the functional device through the first wiring substrate.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: April 12, 2022
    Assignee: SONY CORPORATION
    Inventor: Hironobu Abe
  • Patent number: 11296067
    Abstract: A package structure includes an insulating encapsulation, a semiconductor die, and a filter structure. The semiconductor die is encapsulated in the insulating encapsulation. The filter structure is electrically coupled to the semiconductor die, wherein the filter structure includes a patterned metallization layer with a pattern having a double-spiral having aligned centroids thereof.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: April 5, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sen-Kuei Hsu, Hsin-Yu Pan, Ming-Hsien Tsai
  • Patent number: 11289408
    Abstract: A semiconductor device according to one embodiment includes a first leadframe, a second leadframe, a semiconductor chip, and a conductive member. The second leadframe has a first face provided with a recess and is separated from the first leadframe. The semiconductor chip is mounted on the first leadframe. The conductive member has a second face connected to the first face with a conductive adhesive, the second face provided with a protrusion housed in the recess at least partially, and the conductive member electrically connected the semiconductor chip and the second leadframe to each other. The recess and the protrusion are longer in a first direction in which the first face extends than in a second direction along the first face and orthogonal to the first direction.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: March 29, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Kakeru Yamaguchi, Jun Karasawa
  • Patent number: 11289430
    Abstract: A semiconductor package may include a package substrate, a support structure on the package substrate and having a cavity therein, and at least one first semiconductor chip on the package substrate in the cavity. The support structure may have a first inner sidewall facing the cavity, a first top surface, and a first inclined surface connecting the first inner sidewall and the first top surface. The first inclined surface may be inclined with respect to a top surface of the at least one first semiconductor chip.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: March 29, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-Gi Chang, Bok Sik Myung
  • Patent number: 11276656
    Abstract: Semiconductor devices and methods of forming are provided. A molding compound extends along sidewalls of a first die and a second die. A redistribution layer is formed over the first die, the second die, and the molding compound. The redistribution layer includes a conductor overlying a gap between the first die and the second die. The conductor is routed at a first angle over an edge of the first die. The first angle is measured with respect to a straight line that extends along a shortest between the first die and the second die, and the first angle is greater than 0.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: March 15, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, An-Jhih Su, Tsung-Shu Lin
  • Patent number: 11276629
    Abstract: A semiconductor device according to embodiments includes a first base material having a first side surface, a first semiconductor chip provided above the first base material, a first insulating plate provided between the first base material and the first semiconductor chip, a first metal plate provided between the first insulating plate and the first semiconductor chip, a first bonding material provided between the first metal plate and the first semiconductor chip, the first bonding material bonding the first metal plate and the first semiconductor chip, a second bonding material provided between the first base material and the first insulating material, the second bonding material bonding the first base material and the first insulating plate, a second base material having a second side surface, a second semiconductor chip provided above the second base material, a second insulating plate provided between the second base material and the second semiconductor chip, a second metal plate provided between the s
    Type: Grant
    Filed: January 30, 2020
    Date of Patent: March 15, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Fumiyoshi Kawashiro
  • Patent number: 11270970
    Abstract: A semiconductor device, including a semiconductor chip having a first main electrode on a front surface thereof, the first main electrode having a plurality of bonded regions, and a plurality of wires that are bonded respectively to the plurality of bonded regions of the first main electrode. In a top view of the semiconductor device, the plurality of bonded regions do not overlap in either a predetermined first direction, or a second direction perpendicular to the predetermined first direction.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: March 8, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Masaki Takahashi
  • Patent number: 11257726
    Abstract: A device is provided. The device may include one or more of a package base, a substrate, a die secured to the substrate, a plurality of bond connections, and a package lid. The package base includes a plurality of package leads and a package base body. The package base body includes an open cavity disposed through the entire package base body, a plurality of package bond pads, disposed within a periphery of the open cavity, and a mounting shelf, disposed within the open cavity. The substrate is secured to the mounting shelf, and includes a plurality of substrate bond pads. The plurality of bond connections are configured to provide electrical connections between one or more of the die, the substrate bond pads, and the package bond pads. The package lid is secured over the open cavity to the package base body.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: February 22, 2022
    Assignee: Global Circuit Innovations Incorporated
    Inventor: Timothy Mark Barry
  • Patent number: 11244906
    Abstract: A package structure including a first semiconductor die, a second semiconductor die, first conductive pillars and a first insulating encapsulation is provided. The first semiconductor die includes a semiconductor substrate, an interconnect structure and a first redistribution circuit structure. The semiconductor substrate includes a first portion and a second portion disposed on the first portion. The interconnect structure is disposed on the second portion, the first redistribution circuit structure is disposed on the interconnect structure, and the lateral dimension of the first portion is greater than the lateral dimension of the second portion. The second semiconductor die is disposed on the first semiconductor die. The first conductive pillars are disposed on the first redistribution circuit structure of the first semiconductor die. The first insulating encapsulation is disposed on the first portion.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: February 8, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Sung Huang, Cheng-Chieh Hsieh, Hsiu-Jen Lin, Hui-Jung Tsai, Hung-Yi Kuo, Hao-Yi Tsai, Ming-Hung Tseng, Yen-Liang Lin, Chun-Ti Lu, Chung-Ming Weng
  • Patent number: 11233003
    Abstract: This disclosure relates to a semiconductor device and method of manufacture, including: a semiconductor die having a first major surface and a first contact terminal arranged thereon and an opposing second major having a second contact terminal arranged thereon and a first lead frame having first and second opposing major surfaces. The first major surface is fixedly attached to the first contact terminal of the semiconductor die. A second lead frame has first and second opposing major surfaces and the first major surface is fixedly attached to the second contact terminal of the semiconductor die. The first lead frame includes an integrally formed external contact portion extending from the first major surface thereof to a plane substantially co-planar with the second major surface of the second leadframe.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: January 25, 2022
    Assignee: Nexperia B.V.
    Inventors: Christine Ting, Vegneswary Ramalingam, Melvin Hung
  • Patent number: 11227813
    Abstract: An electronic apparatus includes: a first metal layer; an electronic component that is provided on the first metal layer; a second metal layer that is provided on the first metal layer and on the electronic component; and an insulating resin that fills a space between the first metal layer and the second metal layer so as to cover the electronic component. The second metal layer includes: a sheet-like electrode pad portion; and a connection portion that is disposed along a peripheral edge of the electrode pad portion, and that protrudes from the electrode pad portion toward the first metal layer so as to electrically connect the second metal layer to the first metal layer.
    Type: Grant
    Filed: July 7, 2020
    Date of Patent: January 18, 2022
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Takayuki Matsumoto, Tsukasa Nakanishi, Tadaaki Katsuyama
  • Patent number: 11211299
    Abstract: A wiring structure includes a first unit, a second unit, a first insulation wall, a first redistribution layer and a third unit. The first unit is disposed at a first elevation and having a first circuit layer and a first dielectric layer surrounding the first circuit layer. The second unit is disposed at the first elevation and having a second circuit layer and a second dielectric layer surrounding the second circuit layer. The first insulation wall is disposed between the first unit and the second unit. The first redistribution layer is disposed on the first unit and the second unit, and electrically connected between the first unit and the second unit. The third unit is disposed on the first redistribution layer and having a third circuit layer and a third dielectric layer surrounding the third circuit layer.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: December 28, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen Hung Huang
  • Patent number: 11211261
    Abstract: A packaging structure and a method of forming a packaging structure are provided. The packaging structure, such as an interposer, is formed by optionally bonding two carrier substrates together and simultaneously processing two carrier substrates. The processing includes forming a sacrificial layer over the carrier substrates. Openings are formed in the sacrificial layers and pillars are formed in the openings. Substrates are attached to the sacrificial layer. Redistribution lines may be formed on an opposing side of the substrates and vias may be formed to provide electrical contacts to the pillars. A debond process may be performed to separate the carrier substrates. Integrated circuit dies may be attached to one side of the redistribution lines and the sacrificial layer is removed.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: December 28, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Liang Meng, Wei-Hung Lin, Yu-min Liang, Ming-Che Ho, Hung-Jui Kuo, Chung-Shi Liu, Mirng-Ji Lii
  • Patent number: 11195773
    Abstract: In an embodiment, a quantum device includes an interposer layer comprising a set of vias. In an embodiment, the quantum device includes a dielectric layer formed on a first side of the interposer, the dielectric layer including a set of transmission lines communicatively coupled to the set of vias. In an embodiment, the quantum device includes a plurality of qubit chips coupled to an opposite side of the interposer layer, each qubit chip of the plurality of qubit chips including: a plurality of qubits on a first side of the qubit chip and a plurality of protrusions on a second side of the qubit chip. In an embodiment, the quantum device includes a heat sink thermally coupled with the plurality of qubit chips, the heat sink comprising a plurality of recesses aligned with the plurality of protrusions of the plurality of qubit chips.
    Type: Grant
    Filed: April 3, 2020
    Date of Patent: December 7, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jae-Woong Nah, Hanhee Paik, Jerry M. Chow
  • Patent number: 11195727
    Abstract: Generally discussed herein are systems, devices, and methods that include an organic high density interconnect structure and techniques for making the same. According to an example a method can include forming one or more low density buildup layers on a core, conductive interconnect material of the one or more low density buildup layers electrically and mechanically connected to conductive interconnect material of the core, forming one or more high density buildup layers on an exposed low density buildup layer of the one or more low density buildup layers, conductive interconnect material of the high density buildup layers electrically and mechanically connected to the conductive interconnect material of the one or more low density buildup layers, and forming another low density buildup layer on and around an exposed high density buildup layer of the one or more high density buildup layers.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: December 7, 2021
    Assignee: Intel Corporation
    Inventors: Sri Chaitra Jyotsna Chavali, Siddharth K. Alur, Lilia May, Amanda E. Schuckman
  • Patent number: 11183441
    Abstract: The disclosed principles provide a stress buffer layer between an IC die and heat spreader used to dissipate heat from the die. The stress buffer layer comprises distributed pairs of conductive pads and a corresponding set of conductive posts formed on the conductive pads. In one embodiment, the stress buffer layer may comprise conductive pads laterally distributed over non-electrically conducting surfaces of an embedded IC die to thermally conduct heat from the IC die. In addition, such a stress buffer layer may comprise conductive posts laterally distributed and formed directly on each of the conductive pads. Each of the conductive posts thermally conduct heat from respective conductive pads. In addition, each conductive post may have a lateral width less than a lateral width of its corresponding conductive pad. A heat spreader is then formed over the conductive posts which thermally conducts heat from the conductive posts through the heat spreader.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: November 23, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Woochan Kim, Masamitsu Matsuura, Mutsumi Masumoto, Kengo Aoya, Hau Thanh Nguyen, Vivek Kishorechand Arora, Anindya Poddar
  • Patent number: 11177309
    Abstract: The present disclosure relates to an image sensor with a pad structure formed during a front-end-of-line process. The pad structure can be formed prior to formation of back side deep trench isolation structures and metal grid structures. An opening is formed on a back side of the image sensor device to expose the embedded pad structure and to form electrical connections.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: November 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yun-Wei Cheng, Chun-Hao Chou, Kuo-Cheng Lee, Hsun-Ying Huang, Yin-Chieh Huang
  • Patent number: 11177188
    Abstract: A chip packaging structure includes a heat dissipation substrate, a pre-molded chipset, an interconnection and a second encapsulant. The pre-molded chipset is located on the heat dissipation substrate. The interconnection is located in the packaging structure and electrically connects the heat dissipation substrate and the pre-molded chipset. The second encapsulant covers part of the heat dissipation substrate, part or all of the interconnection, and part or all of the pre-molded chipset. The pre-molded chipset includes a thermally conductive substrate, at least two chips, a patterned circuit, and a first encapsulant. The patterned circuit is located in the pre-molded chipset. At least two chips are electrically connected by the patterned circuit. The first encapsulant covers at least two chips and part or all of the patterned circuit. A manufacturing method of a chip packaging structure is also provided.
    Type: Grant
    Filed: September 13, 2020
    Date of Patent: November 16, 2021
    Assignee: ACTRON TECHNOLOGY CORPORATION
    Inventors: Hsin-Chang Tsai, Ching-Wen Liu
  • Patent number: 11166642
    Abstract: A measurement sensor package and a measurement sensor reduce susceptibility to noise and enable highly accurate measurement. A measurement sensor package (1) includes a substrate (2), a lid (3), and a ground conductor layer (4). The substrate (2) contains a light emitter and a light receiver, and includes a substrate body (20), a plurality of ground via conductors (21), an frame-shaped ground conductor layer (22), signal wiring conductors (23), and an external connection terminal (24). The ground via conductors (21) are connectable to a ground potential, and are located outward from a first recess (20a) and a second recess (20b) included in the substrate body (20) in a plan view.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: November 9, 2021
    Assignee: KYOCERA CORPORATION
    Inventors: Yasushi Oode, Hiroki Ito, Yoshimasa Sugimoto, Noritaka Niino, Shogo Matsunaga, Takuya Hayashi
  • Patent number: 11159071
    Abstract: A busbar unit for an electric motor may include a busbar holder at least a portion of which is made of an electrically insulating material, and at least one busbar mounted on the busbar holder. The busbar may include a base portion extending along a mounting surface of the busbar holder, at least one coil connection terminal portion to be electrically connected to a coil of the electric motor, and a power source connection terminal portion to be electrically connected to a power source. The power source connection terminal portion may extend from the base portion and at least a portion of the base portion may include a resilient member allowing displacement of the power source connection terminal portion towards the busbar holder.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: October 26, 2021
    Assignee: NIDEC CORPORATION
    Inventors: Matthias Fischer, Keisuke Fukunaga, Thomas Kuebler, Juergen Schmid
  • Patent number: 11150273
    Abstract: A current sensor integrated circuit (IC) includes a unitary lead frame having at least one first lead having a terminal end, at least one second lead having a terminal end, and a paddle having a first surface and a second opposing surface. A semiconductor die is supported by the first surface of the paddle, wherein the at least one first lead is electrically coupled to the semiconductor die and the at least one second lead is electrically isolated from the semiconductor die. The current sensor IC further includes a first mold material configured to enclose the semiconductor die and the paddle and a second mold material configured to enclose at least a portion of the first mold material, wherein the terminal end of the at least one first lead and the terminal end of the at least one second lead are external to the second mold material.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: October 19, 2021
    Assignee: Allegro MicroSystems, LLC
    Inventors: Shixi Louis Liu, Paul A. David, Shaun D. Milano, Rishikesh Nikam, Alexander Latham, Wade Bussing, Natasha Healey, Georges El Bacha
  • Patent number: 11129986
    Abstract: An implantable stimulator is provided having a conformable foil-like substrate, having a longitudinal axis extending from a pulse generator to a distal end of the substrate. The substrate comprising one or more adjacent polymeric substrate layers and an electrode array. The electrode array having a first and second electrode where one or more electrical interconnections are comprised in the substrate. The conformable foil-like substrate has a maximum thickness of 0.5 millimeter or less, proximate the electrodes. By providing a more easily patternable multilayer substrate, more complicated electrode array configurations may be supported, allowing a higher degree of flexibility to address transverse and/or longitudinal misalignment. By providing a relatively thin implantable electrode array user comfort may be increased through application of energy to tissue by the implantable stimulator.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: September 28, 2021
    Inventors: Daniel Willem Elisabeth Schobben, Hubert Cecile Francois Martens, Maartje van der Zalm
  • Patent number: 11114401
    Abstract: A bonding structure and a method for manufacturing the bonding structure are provided. Multiple chips arranged in an array are formed on a surface of a wafer. Each of the chips includes a device structure, an interconnect structure electrically connected to the device structure, and a first package pad layer electrically connected to the interconnect structure. The first package pad layer is arranged at an edge region of the chip. A chip stack is obtained after bonding and cutting the multiple wafers, and the first package pad layer at the edge region of the chip is exposed.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: September 7, 2021
    Assignee: Wuhan Xinxin Semiconductor Manufacturing Co., Ltd.
    Inventors: Fei Liang, Jing Cao, Sheng Hu
  • Patent number: 11107795
    Abstract: Semiconductor devices with duplicated die bond pads and associated device packages and methods of manufacture are disclosed herein. In one embodiment, a semiconductor device package includes a plurality of package contacts and a semiconductor die having a plurality of first die bond pads, a plurality of second die bond pads, and a plurality of duplicate die bond pads having the same pin assignments as the first die bond pads. The semiconductor die further includes an integrated circuit operably coupled to the package contacts via the plurality of first die bond pads and either the second die bond pads or the duplicate die bond pads, but not both. The integrated circuit is configured to be programmed into one of (1) a first pad state in which the first and second die bond pads are enabled for use with the package contacts and (2) a second pad state in which the first and duplicate die bond pads are enabled for use with the package contacts.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: August 31, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Nathan J. Sirocka, Trismardawi Tanadi, Andrew D. Proescholdt