With Contact Or Lead Patents (Class 257/690)
  • Patent number: 11114401
    Abstract: A bonding structure and a method for manufacturing the bonding structure are provided. Multiple chips arranged in an array are formed on a surface of a wafer. Each of the chips includes a device structure, an interconnect structure electrically connected to the device structure, and a first package pad layer electrically connected to the interconnect structure. The first package pad layer is arranged at an edge region of the chip. A chip stack is obtained after bonding and cutting the multiple wafers, and the first package pad layer at the edge region of the chip is exposed.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: September 7, 2021
    Assignee: Wuhan Xinxin Semiconductor Manufacturing Co., Ltd.
    Inventors: Fei Liang, Jing Cao, Sheng Hu
  • Patent number: 11107795
    Abstract: Semiconductor devices with duplicated die bond pads and associated device packages and methods of manufacture are disclosed herein. In one embodiment, a semiconductor device package includes a plurality of package contacts and a semiconductor die having a plurality of first die bond pads, a plurality of second die bond pads, and a plurality of duplicate die bond pads having the same pin assignments as the first die bond pads. The semiconductor die further includes an integrated circuit operably coupled to the package contacts via the plurality of first die bond pads and either the second die bond pads or the duplicate die bond pads, but not both. The integrated circuit is configured to be programmed into one of (1) a first pad state in which the first and second die bond pads are enabled for use with the package contacts and (2) a second pad state in which the first and duplicate die bond pads are enabled for use with the package contacts.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: August 31, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Nathan J. Sirocka, Trismardawi Tanadi, Andrew D. Proescholdt
  • Patent number: 11081927
    Abstract: A busbar assembly for an electric motor may include a busbar holder at least a portion of which is made of an electrically insulating material, and at least one busbar mounted on the busbar holder. The busbar may include a base portion extending along a mounting surface of the busbar holder, at least one coil connection terminal portion to be electrically connected to a coil of the electric motor, and a power source connection terminal portion to be electrically connected to a power source. The power source connection terminal portion may extend from the base portion and at least a portion of the base portion may include a resilient member allowing displacement of the power source connection terminal portion towards the busbar holder.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: August 3, 2021
    Assignee: NIDEC CORPORATION
    Inventors: Matthias Fischer, Keisuke Fukunaga, Thomas Kuebler, Juergen Schmid
  • Patent number: 11081371
    Abstract: A chip package process includes the following steps. A supporting structure and a carrier plate are provided. The supporting structure has a plurality of openings. The supporting structure is disposed on the carrier plate. A plurality of chips is disposed on the carrier plate. The chips are respectively located in the openings of the supporting structure. An encapsulated material is formed to cover the supporting structure and the chips. The supporting structure and the chips are located between the encapsulated material and the carrier plate. The encapsulated material is filled between the openings and the chips. The carrier plate is removed. A redistribution structure is disposed on the supporting structure, wherein the redistribution structure is connected to the chips.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: August 3, 2021
    Assignee: VIA Alliance Semiconductor Co., Ltd.
    Inventors: Wen-Yuan Chang, Wei-Cheng Chen, Hsueh-Chung Shelton Lu
  • Patent number: 11075190
    Abstract: A semiconductor device includes a printed circuit board in a peripheral portion of a housing portion of a case in which a laminated substrate is housed. A terminal block holding control terminals from which control signals are outputted to the printed circuit board is disposed over the printed circuit board. A gate electrode of a semiconductor chip and the printed circuit board are electrically connected by a wire.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: July 27, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Shin Soyano
  • Patent number: 11075150
    Abstract: A redistribution structure includes a first dielectric layer and a first redistribution circuit layer. The first dielectric layer includes a first via opening. The first redistribution circuit layer is disposed on the first dielectric layer and includes a via portion filling the first via opening and a circuit portion connecting the via portion and extending over the first dielectric layer. A maximum vertical distance between an upper surface of the via portion and an upper surface of the circuit portion is substantially equal to or smaller than 0.5 ?m.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: July 27, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Hsien Huang, An-Jhih Su, Der-Chyang Yeh, Hua-Wei Tseng, Chiang Lin, Ming-Shih Yeh
  • Patent number: 11069600
    Abstract: A semiconductor package includes a die pad having a die attach surface, a rear surface opposite the die attach surface, and an outer edge side extending between the die attach surface and the rear surface, the outer edge side having a step-shaped profile, wherein an upper section of the die pad laterally overhangs past a lower section of the die pad, a semiconductor die mounted on the die attach surface and having a first electrical terminal on an upper surface of the semiconductor die, and a first conductive clip that directly electrically contacts the first electrical terminal and wraps around the outer edge side of the die pad such that a section of the first conductive clip is at least partially within an area that is directly below the upper section of the die pad and directly laterally adjacent to the lower section.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: July 20, 2021
    Assignee: Infineon Technologies AG
    Inventors: Ke Yan Tean, Thomas Bemmerl, Thai Kee Gan, Azlina Kassim
  • Patent number: 11056486
    Abstract: A semiconductor device includes a first vertical device having a first threshold and second vertical device having a second threshold. The first vertical device includes a first source; a first channel over the first source; a first drain over the first channel; a first conductive layer adjacent to the first channel; and a first gate adjacent to the first conductive layer. The second vertical device includes a second source; a second channel over the second source; a second drain over the second channel; a second conductive layer adjacent to the second channel; and a second gate adjacent to the second conductive layer.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: July 6, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Li-Ting Wang, Teng-Chun Tsai, Cheng-Tung Lin, De-Fang Chen, Hui-Cheng Chang
  • Patent number: 11043471
    Abstract: A mixed-orientation multi-die (“MOMD”) integrated circuit package includes dies mounted in different physical orientations. An MOMD package includes both (a) one or more dies horizontally-mounted dies (HMDs) mounted horizontally to a horizontally-extending die mount base and (b) one or more vertically-mounted dies (VMDs) mounted vertically to the horizontally-extending die mount base. HMDs may include FPGAs or other high performance chips, while VMDs may include low performance chips and other physical structures such as heat dissipators, memory, high voltage/analog devices, sensors, or MEMS, for example. The die mount base of an MOMD package may include structures for aligning and mounting VMD(s), for example, VMD slots for receiving each mounted VMD, and VMD alignment structures that facilitate aligning and/or guiding a vertical mounting of each VMD to the die mount base.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: June 22, 2021
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Justin Sato, Bomy Chen
  • Patent number: 11037898
    Abstract: A semiconductor device package includes a first electronic device and a second electronic device. The first electronic device includes a first redistribution layer (RDL) including a circuit layer. The second electronic device is disposed on the first RDL of the first electronic device. The second electronic device includes an encapsulant and a patterned conductive layer. The encapsulant has a first surface facing the first RDL of the first electronic device, and a second surface opposite to the first surface. The patterned conductive layer is disposed at the second surface of the encapsulant, and is configured to be electrically coupled to the circuit layer of the first RDL of the first electronic device.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: June 15, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Ming Hsien Chu, Chi-Yu Wang
  • Patent number: 11037853
    Abstract: A semiconductor heat dissipation structure includes a first semiconductor device including a first active surface and a first back surface opposite to the first active surface, a second semiconductor device including a second active surface and a second back surface opposite to the second active surface, a first heat conductive layer embedded in the first back surface of the first semiconductor device, a second heat conductive layer embedded in the second back surface of the second semiconductor device, and a third heat conductive layer disposed adjoining the first heat conductive layer and extending to the first active surface of the first semiconductor device. The first back surface of the first semiconductor device and the second back surface of the second semiconductor device are in contact with each other. At least a portion of the first heat conductive layer are in contact with the second heat conductive layer.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: June 15, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Ya Fang Chan, Yuan-Feng Chiang, Po-Wei Lu
  • Patent number: 11024567
    Abstract: A surface mount (SMD) diode taking a runner as the body and a manufacturing method thereof are described. An elongated runner groove is adopted to cure and package groups of diode chips arranged side by side and corresponding copper pins thereon, with the utilization rate of epoxy resin up to 90% or more. The use cost of epoxy resin is thus reduced, and environmental pollution is also reduced.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: June 1, 2021
    Assignee: SIYANG GRANDE ELECTRONICS CO., LTD.
    Inventor: Yunhui Zhong
  • Patent number: 11018078
    Abstract: A method of producing electronic components including at least one circuit having coupled therewith electrical connections including metallic wire bondable surfaces encased in a packaging, the method including bonding stud bumps, in particular copper stud bumps, at determined areas of said wire bondable surfaces.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: May 25, 2021
    Assignee: STMICROELECTRONICS S.r.l.
    Inventor: Fabio Marchisi
  • Patent number: 11018026
    Abstract: A semiconductor package includes: a plurality of unit redistribution layers vertically stacked, each including: a first polymer layer having a first via hole pattern; a second polymer layer formed on the first polymer layer, and having a redistribution pattern on the first polymer layer and a second via hole pattern in the first via hole pattern; a seed layer covering sidewalls and bottom surfaces of the redistribution pattern and the second via hole pattern; a conductive via plug formed in the second via hole pattern; and a conductive redistribution line formed in the redistribution pattern; a connection terminal disposed on a bottom surface of a lowermost unit redistribution layer and electrically connected to the conductive via plug; a semiconductor device mounted on the unit redistribution layers with a conductive terminal interposed therebetween. Upper surfaces of the second polymer layer, the conductive redistribution line and the conductive via plug are substantially coplanar.
    Type: Grant
    Filed: November 29, 2019
    Date of Patent: May 25, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Un-Byoung Kang, Tae-Je Cho, Hyuek-Jae Lee, Cha-Jea Jo
  • Patent number: 11019723
    Abstract: The present application discloses a stretchable electrode, an electronic device and a manufacturing method thereof. The stretchable electrode includes a substrate, an electric conductive area and an electronic device integration area; the substrate has a first elastic layer and a second elastic layer with different elastic moduli. The electronic device produced by using the afore-mentioned stretchable electrode can be stretched entirely, and when it is stretched, the electronic device would not be damaged and the variation of its impedance is small. Tests have shown that the electric conductive layer can be stretched by more than 20%, with the variation ratio of its impedance being less than 1.5%, and no damage is caused to the electronic device.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: May 25, 2021
    Assignees: KUNSHAN NEW FLAT PANEL DISPLAY TECHNOLOGY CENTER CO., LTD., KUNSHAN GO-VISIONOX OPTO-ELECTRONICS CO., LTD.
    Inventors: Tao Wang, Xuna Li, Feng Zhai, Songlin Jia, Weigao Cheng, Yalei Ren
  • Patent number: 11004775
    Abstract: One or more embodiments are directed to quad flat no-lead (QFN) semiconductor packages, devices, and methods in which one or more electrical components are positioned between a die pad of a QFN leadframe and a semiconductor die. In one embodiment, a device includes a die pad, a lead that is spaced apart from the die pad, and at least one electrical component that has a first contact on the die pad and a second contact on the lead. A semiconductor die is positioned on the at least one electrical component and is spaced apart from the die pad by the at least one electrical component. The device further includes at least one conductive wire, or wire bond, that electrically couples the at least one lead to the semiconductor die.
    Type: Grant
    Filed: February 5, 2020
    Date of Patent: May 11, 2021
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Cristina Somma, Fulvio Vittorio Fontana
  • Patent number: 10991673
    Abstract: According to one embodiment, the interconnect layer includes a fourth conductive member and a fifth conductive member. The fourth conductive member is provided between the first region of the first chip and the third region of the second chip. The fourth conductive member connects the first conductive member of the first chip and the second conductive member of the second chip. The fifth conductive member is provided between the second region of the first chip and the fifth region of the third chip. The fifth conductive member connects the first conductive member of the first chip and the third conductive member of the third chip. The first chip is provided between the first terminal and the second terminal.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: April 27, 2021
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoichiro Kurita
  • Patent number: 10988647
    Abstract: The purpose of the present invention is to provide a semiconductor substrate manufacturing method, which prevents detachment of a semiconductor wafer being ground, and which prevents cracking or chipping in a semiconductor substrate obtained. In order to solve the problem, the semiconductor substrate manufacturing method comprises: a polyimide layer forming step of forming a polyimide layer on a support material; a wafer attaching step of affixing the support material and a semiconductor wafer to each other with the polyimide layer disposed therebetween; a wafer grinding step of grinding the semiconductor wafer; a support material peeling step of peeling the support material from the polyimide layer; and a polyimide layer peeling step of peeling the polyimide layer from the semiconductor wafer. The polyimide layer includes polyimide which includes a benzophenone skeleton and an aliphatic structure, wherein an amine equivalent weight is 4000 to 20000.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: April 27, 2021
    Assignee: MITSUI CHEMICALS, INC.
    Inventors: Jun Kamada, Kaichiro Haruta, Takashi Unezaki, Kiyomi Imagawa, Kenichi Fujii, Yasuhisa Kayaba, Kazuo Kohmura
  • Patent number: 10978433
    Abstract: A package for a use in a package-on-package (PoP) device and a method of forming is provided. The package includes a substrate, a polymer layer formed on the substrate, a first via formed in the polymer layer, and a material disposed in the first via to form a first passive device. The material may be a high dielectric constant dielectric material in order to form a capacitor or a resistive material to form a resistor.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: April 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Ching-Wen Hsiao, Chen-Shien Chen
  • Patent number: 10976994
    Abstract: An audio apparatus includes a network interface, a receiver, at least one storage, and at least one processor. The processor is configured to determine that the audio apparatus is in a state capable of communicating with the other audio apparatus via the network interface. The processor is also configured to receive audio data via the receiver transmitted from an external apparatus different from the other audio apparatus. The processor is also configured to output a sound based on the received audio data. The processor is also configured to transmit the sound emission control information stored in the at least one storage to the other audio apparatus. The sound emission control information includes one or more of a sound volume, and a frequency band.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: April 13, 2021
    Assignee: Yamaha Corporation
    Inventor: Daigo Sugiura
  • Patent number: 10971436
    Abstract: An example multi-branch terminal for an integrated circuit (IC) package is described herein. An example multi-branch terminal of an integrated circuit (IC), may include a first branch that may include an active bonding with a chip of the IC, wherein the active bonding may include a wire bonded to the chip of the IC; and a second branch that may include a passive bonding with the chip of the IC, wherein the passive bonding may include a capacitor bonded to the second branch and a first terminal of the IC.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: April 6, 2021
    Assignee: Infineon Technologies AG
    Inventors: Thomas Stoek, Chii Shang Hong, Chiew Li Tai, Edmund Sales Cabatbat
  • Patent number: 10964669
    Abstract: A semiconductor package includes a chip stack having a plurality of semiconductor chips vertically stacked on a package substrate. A stress-equalizing chip is disposed on the chip stack, the stress-equalizing chip providing means to reduce the variation in the electrical characteristics of the plurality of semiconductor chips. An encapsulant is disposed on the package substrate and is configured to cover at least a portion of the chip stack. Each of the plurality of semiconductor chips is electrically connected to the package substrate. The stress-equalizing chip is not electrically connected to the substrate or to the plurality of semiconductor chips.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: March 30, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Il Ho Kim
  • Patent number: 10964666
    Abstract: A system and method for packaging semiconductor device is provided. An embodiment comprises forming vias over a carrier wafer and attaching a first die over the carrier wafer and between a first two of the vias. A second die is attached over the carrier wafer and between a second two of the vias. The first die and the second die are encapsulated to form a first package, and at least one third die is connected to the first die or the second die. A second package is connected to the first package over the at least one third die.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: March 30, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Der-Chyang Yeh, Kuo-Chung Yee, Jui-Pin Hung
  • Patent number: 10957636
    Abstract: A semiconductor device includes leads, a switching element, a control element that controls the switching element, and a resin member covering the switching element, the control element and parts of the respective leads. The leads include a drain lead connected to a drain electrode of the switching element, a source lead connected to a source electrode of the switching element, and at least one control lead connected to the control element. The resin member includes a drain exposed portion at which the drain lead is exposed, a source exposed portion at which the source lead is exposed, and a control exposed portion at which the control lead is exposed. The distance in a first direction between the drain exposed portion and the source exposed portion is larger than the distance in the first direction between the control exposed portion and the source exposed portion.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: March 23, 2021
    Assignee: ROHM CO., LTD.
    Inventors: Makoto Hirata, Shingo Matsumaru, Satoru Nate
  • Patent number: 10950580
    Abstract: A semiconductor device package is provided. The semiconductor device package includes a stack of semiconductor dies over a substrate, the substrate including a plurality of electrical contacts, and an annular lower lid disposed over the substrate and surrounding the stack of semiconductor dies. The annular lower lid includes a lower surface coupled to the substrate, an upper surface coupled to an upper lid, and an outer surface in which is formed an opening. The semiconductor device assembly further includes a circuit element disposed in the opening and electrically coupled to at least a first one of the plurality of electrical contacts. The semiconductor device assembly further includes the upper lid disposed over the annular lower lid and the stack of semiconductor dies.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: March 16, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Thomas H. Kinsley
  • Patent number: 10950566
    Abstract: Provided is a technique for improving the durability of a semiconductor device. A semiconductor device includes a semiconductor substrate, an electrode on the semiconductor substrate, a solder-joining metal Him on the electrode, an oxidation-inhibiting metal film on the solder-joining metal film, and a solder layer on the oxidation-inhibiting metal film. The solder-joining metal film includes a first portion that does not overlap the oxidation-inhibiting metal film in plan view when the solder-joining metal film and the oxidation-inhibiting metal film are viewed from the oxidation-inhibiting metal film.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: March 16, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kenji Harada, Shinya Soneda
  • Patent number: 10930620
    Abstract: The present invention relates to a multi-chip detector apparatus composed of multiple single detectors. An embodiment of the invention provides a multi-chip detector apparatus having a multiple number of single chips arranged in inter-chip connection on a substrate, where the multi-chip detector apparatus includes: a first single chip that has a multiple number of single detectors formed in m rows and n columns; a second single chip that is positioned at either a left side or a right side of the first single chip and is connected row-wise with the first single chip; and a third single chip that is positioned at either an upper side or a lower side of the first single chip and is connected column-wise with the first single chip, and where the second single chip and the third single chip also have multiple numbers of single detectors formed in m rows and n columns.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: February 23, 2021
    Assignee: Korea University Research and Business Foundation
    Inventors: Jae-Sung Rieh, Ki Ryong Song, Jai Heon Cho, DoYoon Kim
  • Patent number: 10930574
    Abstract: A semiconductor device includes a semiconductor element, a first substrate, a first electrode, a second electrode and a sealing resin. The first substrate has a first front surface and a first back surface that are spaced apart from each other in a thickness direction. The semiconductor element is mounted on the first main surface. The first electrode includes a first conductive portion and a second conductive portion. The first conductive portion is formed on a portion of the first front surface. The second conductive portion is connected to the first conductive portion and overlaps with the first substrate as viewed in a first direction perpendicular to the thickness direction. The sealing resin covers the semiconductor element. The second electrode is exposed from the sealing resin and electrically connected to the first electrode. The second electrode is in contact with the second conductive portion.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: February 23, 2021
    Assignee: ROHM CO., LTD.
    Inventor: Isamu Nishimura
  • Patent number: 10910292
    Abstract: An electronic device has a sealing part 90, an electronic element 95 provided in the sealing part 90 and a connection body 50 having a head part 40 connected to a front surface of the electronic element 95 via a conductive adhesive 75. The head part 40 has a second projection protruding 42 toward the electronic element 95 and a first projection 41 protruding from the second projection 42 toward the electronic element 95.
    Type: Grant
    Filed: February 20, 2017
    Date of Patent: February 2, 2021
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Soichiro Umeda, Yuji Morinaga
  • Patent number: 10910303
    Abstract: A package structure and a manufacturing method thereof are provided. The package structure includes an insulation layer, an electronic component and a lead frame unit. The electronic component is embedded within the insulation layer and includes plural conducting terminals. The lead frame unit is embedded within the insulation layer and includes a lead frame and a metallization layer. The metallization layer having a thickness more than 10 ?m is disposed on at least a part of the lead frame and electrically connected with at least one of the plural conducting terminals of the electronic component.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: February 2, 2021
    Assignee: DELTA ELECTRONICS INT'L (SINGAPORE) PTE LTD
    Inventors: Xiaofeng Xu, Beng Beng Lim
  • Patent number: 10896867
    Abstract: Provided is a terminal plate according to an embodiment including: a first plate portion for being connected to a first semiconductor element; a second plate portion for being connected to a second semiconductor element; a third plate portion provided above the first plate portion and the second plate portion; a first connecting portion provided between the first plate portion and the third plate portion and connecting the first plate portion and the third plate portion; a second connecting portion provided between the second plate portion and the third plate portion and connecting the second plate portion and the third plate portion; a fourth plate portion provided above the first plate portion and the second plate portion and provided on the opposite side of the third plate portion with interposing the first and second plate portions; a third connecting portion provided between the first plate portion and the fourth plate portion and connecting the first plate portion and the fourth plate portion; a fourth
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: January 19, 2021
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Eitaro Miyake, Kazuya Kodani, Hiroshi Matsuyama, Tatsuya Hirakawa
  • Patent number: 10892249
    Abstract: An integrated circuit (IC) chip carrier includes one or more memory devices therein. The memory is integrated into the carrier prior to the IC chip being connected to the carrier. Therefore, the IC chip may be connected to the memory at the same time as the IC chip is connected to the carrier. Because the memory is integrated into the IC chip carrier, prior to the IC chip being attached thereto, reliability concerns that result from attaching the memory to the IC chip carrier affect the IC chip carrier and do not affect the yield of the relatively more expensive IC chip.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: January 12, 2021
    Assignee: International Business Machines Corporation
    Inventors: Charles L. Arvin, Brian M. Erwin, Mark W. Kapfhammer, Brian W. Quinlan, Charles L. Reynolds, Thomas Weiss
  • Patent number: 10886253
    Abstract: A semiconductor package is provided. The semiconductor package includes: a mounting substrate including at least one bonding pad; a first semiconductor chip disposed on the mounting substrate, and including a first protrusion on one side of the first semiconductor chip; a first spacer ball electrically connected to the first semiconductor chip; a first bump ball electrically connected to the first spacer ball; and a first wire which electrically connects the first bump ball and the bonding pad without contacting the first protrusion, wherein the first wire includes a first portion extending in a direction away from the bonding pad, and a second portion extending in a direction approaching the bonding pad.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: January 5, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Saet Byeol Lee, You Kyung Son, Seung Lo Lee, Won Gil Han, Ho Soo Han
  • Patent number: 10867949
    Abstract: A device includes a first die, a second die, one or more redistribution layers (RDLs) electrically connected to the first die, a plurality of connectors on a surface of the one or more RDLs and a package substrate electrically connected to the first die and the second die. The package substrate is electrically connected to the first die through the one or more RDLs and the plurality of connectors. The package substrate comprises a cavity, and the second die is at least partially disposed in the cavity.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jung Wei Cheng, Tsung-Ding Wang, Mirng-Ji Lii, Chien-Hsun Lee, Chen-Hua Yu
  • Patent number: 10867925
    Abstract: A method for forming a chip package structure is provided. The method includes forming a first redistribution structure over a first carrier substrate. The method includes bonding a chip structure to the first surface through a first conductive bump. The method includes forming a first molding layer over the first redistribution structure. The method includes removing the first carrier substrate. The method includes forming a second conductive bump over the second surface. The method includes forming a second redistribution structure over a second carrier substrate. The method includes bonding the first redistribution structure to the third surface. The method includes forming a second molding layer over the second redistribution structure. The method includes removing the second carrier substrate. The method includes removing a portion of the second redistribution structure from the fourth surface. The method includes forming a third conductive bump over the fourth surface.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shin-Puu Jeng, Shuo-Mao Chen, Feng-Cheng Hsu, Po-Yao Lin
  • Patent number: 10861713
    Abstract: A semiconductor device may include first and second conductor plates opposed to each other via first and second semiconductor chips, a first conductor spacer interposed between the first semiconductor chip and the second conductor plate, a second conductor spacer interposed between the second semiconductor chip and the second conductor plate, and an encapsulant provided between the first and second conductor plates. A lower surface of the second conductor plate may include a first joint area where the first conductor spacer is joined, a second joint area where the second conductor spacer is joined, an adhesion area to which the encapsulant adheres, and a separation area from which the encapsulant is separated. The adhesion area may surround the first joint area, the second joint area, and the separation area. The separation area may be located between the first and the second joint areas.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: December 8, 2020
    Assignee: DENSO CORPORATION
    Inventor: Takanori Kawashima
  • Patent number: 10854529
    Abstract: A high resistivity wafer with a heat dissipation structure includes a high resistivity wafer and a metal structure. The high resistivity wafer includes a heat dissipation region and a device support region. The high resistivity wafer consists of an insulating material. The metal structure is only embedded within the heat dissipation region of the high resistivity wafer. The metal structure surrounds the device support region.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: December 1, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Purakh Raj Verma, Kuo-Yuh Yang, Chia-Huei Lin
  • Patent number: 10852165
    Abstract: An orientation-determining device to determine orientation of a vehicle includes a housing, a circuit board, and an orientation-identifying electronic device that includes an integrated accelerometer, an integrated gyroscope, and an integrated magnetometer. The orientation-identifying electronic device is coupled to the circuit board. The orientation-determining device includes a gyroscope that is coupled to the circuit board, an accelerometer that is coupled to the circuit board, and a dampening structure connected between the housing and the circuit board to isolate the circuit board, the orientation-identifying electronic device, the gyroscope, and the accelerometer from vibrations of the housing.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: December 1, 2020
    Assignee: Davis Intellectual Properties LLC
    Inventors: Shannon R. Davis, Charles Leo
  • Patent number: 10840205
    Abstract: Methods for hybrid bonding include depositing and patterning a dielectric layer on a substrate to form openings in the dielectric layer, depositing a barrier layer over the dielectric layer and within a first portion of the openings, and depositing a conductive structure over the barrier layer and within a second portion of the openings not occupied by the barrier layer, at least a portion of the conductive structure in the second portion of the openings coupled or contacting electrical circuitry within the substrate. The conductive structure is polished to reveal portions of the barrier layer deposited over the dielectric layer and not in the second portion of the openings. Further, the barrier layer is polished with a selective polish to reveal a bonding surface on or at the dielectric layer.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: November 17, 2020
    Assignee: INVENSAS BONDING TECHNOLOGIES, INC.
    Inventors: Gaius Gillman Fountain, Jr., Chandrasekhar Mandalapu, Cyprian Emeka Uzoh, Jeremy Alfred Theil
  • Patent number: 10833118
    Abstract: A manufacturing method of a chip package includes the following steps. A light transmissive substrate is bonded to a first surface of a wafer, such that a dam element between the light transmissive substrate and the wafer covers a conductive pad of the wafer. A second surface of the wafer facing away from the first surface is etched, such that a hollow region and a trench selectively communicated with the hollow region are synchronously formed in the wafer. A first isolation layer on the conductive pad is etched to expose the conductive pad through the hollow region.
    Type: Grant
    Filed: January 19, 2016
    Date of Patent: November 10, 2020
    Assignee: XINTEC INC.
    Inventors: Tsang-Yu Liu, Chia-Ming Cheng
  • Patent number: 10825760
    Abstract: A semiconductor chip having a core region and an I/O region which surrounds the core region is provided with a plurality of external connection pads connected to I/O cells. The plurality of external connection pads include a first pad group comprised of the external connection pads connected to the same node, and a second pad group comprised of the external connection pads connected to respective different nodes. In first and second pad groups, the external connection pads are arranged in an X direction along an external side of the semiconductor chip, and a pad arrangement pitch in the first pad group is smaller than that in the second pad group.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: November 3, 2020
    Assignee: SOCIONEXT INC.
    Inventors: Toshihiro Nakamura, Isao Motegi, Noriyuki Shimazu, Masanobu Hirose, Taro Fukunaga
  • Patent number: 10818630
    Abstract: An object of the present invention is to provide a highly reliable semiconductor device that allows voids remaining in a bonding material to be reduced. The semiconductor device includes a semiconductor chip, an insulation substrate, a metal base plate, a resin section, and a bump. The semiconductor chip is warped into a concave shape. On the insulation substrate, the semiconductor chip is mounted by bonding. The metal base plate has the insulation substrate mounted thereon and has a heat dissipation property. The resin section seals the insulation substrate and the semiconductor chip. The bump is disposed in a joint between the semiconductor chip and the insulation substrate. A warp amount of the semiconductor chip warped into a concave shape is equal to or greater than 1 ?m and less than a height of the bump.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: October 27, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yuki Yoshioka, Taishi Sasaki, Hiroyuki Harada
  • Patent number: 10818603
    Abstract: A semiconductor package includes a silicon substrate including a cavity and a plurality of through holes spaced apart from the cavity, a first semiconductor chip in the cavity, a plurality of conductive vias in the plurality of through holes, a first redistribution layer on the silicon substrate and connected to the first semiconductor chip and the conductive vias, and a second redistribution layer below the silicon substrate and connected to the first semiconductor chip and the plurality of conductive vias.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: October 27, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young Kun Jee, Ii Hwan Kim, Un Byoung Kang
  • Patent number: 10811342
    Abstract: A semiconductor package includes a semiconductor die having a semiconductor device, and first and second contact pads arranged on opposite surfaces of the die. The semiconductor die is embedded in a dielectric layer. The semiconductor package also includes one or more first package contact pads and one or more second package contact pads arranged on a first major surface of the semiconductor package. The first contact pad of the die is coupled to the one or more first package contact pads, and the second contact pad of the die is coupled to the one or more second package contact pads. In operation, the semiconductor device causes a current path between the first contact pad and the second contact pad. The package contact pads are arranged on the first major surface of the semiconductor package to provide multiple non-parallel current paths.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: October 20, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Sergey Yuferev, Robert Fehler, Petteri Palm
  • Patent number: 10811281
    Abstract: A manufacturing method of a semiconductor device, includes: (a) preparing a lead frame having: a first tie bar extending in a first direction in plan view so as to couple a plurality of first leads to one another; a second tie bar extending in the first direction in plan view so as to couple a plurality of second leads to one another; a coupling portion coupled to the first tie bar and the second tie bar; a first chip mounting portion arranged between the first tie bar and the second tie bar in plan view; and a second chip mounting portion arranged between the first chip mounting portion and the second tie bar in plan view; and (b) after the (a), mounting a first semiconductor chip on the first chip mounting portion and mounting a second semiconductor chip on the second chip mounting portion.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: October 20, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shoji Hashizume, Keita Takada
  • Patent number: 10804183
    Abstract: The method for producing a preform integrating at least one electronic chip included between insulating and/or conductive laminated internal layers; mechanically securing metal bus-bar segments at given spaced-apart positions on opposing upper and lower faces of the preform, using dielectric portions of a resin prepreg; and for each of the upper and lower opposing faces, electrodepositing a metal layer in order to interconnect bus-bar segments secured to the face in question and an electrode of the electronic chip, thereby forming an electronic power circuit comprising bus-bars forming heat sinks.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: October 13, 2020
    Assignee: INSTITUT VEDECOM
    Inventor: Friedbald Kiel
  • Patent number: 10790207
    Abstract: The invention relates to a power semiconductor device comprising a pin element which passes through a housing opening, comprising a support device, further comprising an elastic sealing device which is arranged on the support device, comprising a pressure device which is arranged on the sealing device, and comprising an electrically conductive sleeve. A first pressure element of the pressure device presses a first sealing element of the sealing device against a first support element of the support device in the axial direction of the pin element causes deformation of the first sealing element so that the first sealing element presses against the housing opening wall and against the sleeve in a perpendicular direction in relation to the axial direction of the pin element.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: September 29, 2020
    Assignee: SEMIKRON ELEKTRONIK GmbH & CO. KG
    Inventors: Jörg Ammon, Harald Kobolla, Stefan Weiss
  • Patent number: 10763242
    Abstract: A semiconductor package includes a first layer of one or more first semiconductor chips each having a first surface at which one or more first pads are exposed, a second layer of one or more second semiconductor chips disposed over the first layer and each having a second surface at which one or more second pads are exposed, and a first redistribution layer between the first layer and the second layer and electrically connected to the one or more first pads. The first layer may include one or more first TPVs extending through a substrate (panel) of the first layer and electrically connected to the first redistribution layer.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: September 1, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Hoon Son, Jung-Hwan Choi, Seok-Hun Hyun
  • Patent number: 10763182
    Abstract: The invention relates to a power semiconductor device having a pin element which passes through a housing opening, an elastic sealing device which is arranged between a housing opening wall of the housing, where the housing opening wall delimits the housing opening and encircles the pin element. The pin element runs through the sleeve and through a sealing device opening of the sealing element. The sealing device is not connected in a materially bonded manner to the sleeve, to the housing opening wall and to the pin element and the sealing device seals off the housing opening wall from the sleeve and seals off the sleeve from the pin element. A crosslinked potting compound is arranged on the sealing device. The crosslinked potting compound is connected in a materially bonded manner to the sleeve, to the housing opening wall and to the pin element and the potting compound seals off the housing opening wall from the sleeve and seals off the sleeve from the pin element.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: September 1, 2020
    Assignee: SEMIKRON ELECTRONIK GMBH & CO. KG
    Inventors: Thomas Hunka, Stefan Weiss, Rainer Popp
  • Patent number: 10756019
    Abstract: A die-to-die interconnect structure includes an interconnect network including a plurality of metal interconnect layers. The interconnect network is configured to electrically couple a first die and a second die mounted on a top surface of the die-to-die interconnect structure. A first metal interconnect layer of the plurality of metal interconnect layers includes a plurality of ground lines and a plurality of signal lines distributed across the first metal interconnect layer according to a GSSG pattern. In some examples, adjacent signal lines within the first metal interconnect layer are separated by a dielectric region. In some embodiments, a second metal interconnect layer of the plurality of metal interconnect layers is disposed above the first metal interconnect layer and includes a plurality of configurable signal/ground lines. By way of example, each of the plurality of configurable signal/ground lines is disposed over the dielectric region and within the second metal interconnect layer.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: August 25, 2020
    Assignee: Xilinx, Inc.
    Inventors: Shuxian Wu, Xiaobao Wang, Xuemei Xi