With Contact Or Lead Patents (Class 257/690)
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Patent number: 12119320Abstract: A chip package structure is provided. The chip package structure includes a redistribution structure and a first chip structure over the redistribution structure. The chip package structure also includes a first solder bump between the redistribution structure and the first chip structure and a first molding layer surrounding the first chip structure. The chip package structure further includes a second chip structure over the first chip structure and a second molding layer surrounding the second chip structure. In addition, the chip package structure includes a third molding layer surrounding the first molding layer, the second molding layer, and the first solder bump. A portion of the third molding layer is between the first molding layer and the redistribution structure.Type: GrantFiled: July 20, 2022Date of Patent: October 15, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wei-Yu Chen, Li-Hsien Huang, An-Jhih Su, Hsien-Wei Chen
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Patent number: 12070800Abstract: One aspect of the present invention is a method for manufacturing an electronic component, the method including: a first step of applying a metal paste containing metal particles onto a polymer compact in a prescribed pattern to form a metal paste layer; a second step of sintering the metal particles to form metal wiring; a third step of applying a solder paste containing solder particles and a resin component onto the metal wiring to form a solder paste layer; a fourth step of disposing an electronic element on the solder paste layer; and a fifth step of heating the solder paste layer so as to form a solder layer bonding the metal wiring and the electronic element, and so as to form a resin layer covering at least a portion of the solder layer.Type: GrantFiled: September 5, 2019Date of Patent: August 27, 2024Assignee: RESONAC CORPORATIONInventors: Yoshinori Ejiri, Shinichirou Sukata, Masaya Toba, Hideo Nakako, Yuki Kawana, Kosuke Urashima, Motoki Yonekura, Takaaki Nohdoh, Yoshiaki Kurihara, Hiroshi Masuda, Keita Sone
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Patent number: 12068230Abstract: A semiconductor module includes a conductive substrate, a semiconductor element, a control terminal, and a sealing resin. The conductive substrate has an obverse surface and a reverse surface that are spaced apart from each other in a thickness direction. The semiconductor element is electrically bonded to the obverse surface and has a switching function. The control terminal is configured to control the semiconductor element. The sealing resin has a resin obverse surface and a resin reverse surface, and covers the conductive substrate, the semiconductor element, and a part of the control terminal. The control terminal protrudes from the resin obverse surface, and extends along the thickness direction.Type: GrantFiled: February 1, 2024Date of Patent: August 20, 2024Assignee: ROHM CO., LTD.Inventors: Kohei Tanikawa, Kenji Hayashi, Ryosuke Fukuda
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Patent number: 12057425Abstract: A semiconductor package including a base chip; a semiconductor chip having a lower surface on which connection pads are disposed, the semiconductor chip being mounted on an upper surface of the base chip; a plurality of bumps on the connection pads and electrically connecting the base chip to the semiconductor chip; an adhesive film between the base chip and the semiconductor chip and fixing the semiconductor chip to the base chip; and an encapsulant on the base chip and encapsulating the semiconductor chip, wherein the semiconductor chip includes a central portion spaced apart from the upper surface of the base chip by a first distance, and an edge portion spaced apart from the upper surface of the base chip by a second distance, the edge portion being outside of the central portion, and a ratio of the second distance to the first distance is about 0.8 to about 1.0.Type: GrantFiled: December 2, 2021Date of Patent: August 6, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Eunyeong Kim, Yeongseok Kim, Jihwan Hwang
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Patent number: 12046530Abstract: Disclosed are apparatuses and techniques for fabricating an apparatus including a semiconductor device. The semiconductor device may include: a die, a thermally conductive interface that includes a thermal bridge interposer (THBI) structure, and a substrate. The die is coupled to the substrate by the thermally conductive interface and at least a portion of the die is coupled to the substrate by the THBI structure.Type: GrantFiled: December 21, 2021Date of Patent: July 23, 2024Assignee: QUALCOMM INCORPORATEDInventors: Je-Hsiung Lan, Jonghae Kim, Ranadeep Dutta
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Patent number: 11990411Abstract: In one example, a semiconductor device comprises a redistribution layer (RDL) substrate having a top surface and a bottom surface, wherein the RDL substrate comprises a filler-free dielectric material, an electronic device on the top surface of the RDL substrate, an electrical interconnect on the bottom surface of the RDL substrate and electrically coupled to the electronic device, a first protective material contacting a side surface of the electronic device and the top surface of the RDL substrate, and a second protective material contacting a side surface of the electrical interconnect and the bottom surface of the RDL substrate. Other examples and related methods are also disclosed herein.Type: GrantFiled: April 13, 2022Date of Patent: May 21, 2024Assignee: Amkor Technology Singapore Holding Pte. Ltd.Inventors: Tae Ki Kim, Jae Beom Shim, Seung Nam Son, Won Chul Do
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Patent number: 11978689Abstract: Embodiments disclosed herein include semiconductor dies and methods of forming such dies. In an embodiment, the semiconductor die comprises a semiconductor substrate, an active device layer in the semiconductor substrate, where the active device layer comprises one or more transistors, an interconnect layer over a first surface of the active device layer, a first bonding layer over a surface of the semiconductor substrate, a second bonding layer secured to the first bonding layer, and a heat spreader attached to the second bonding layer.Type: GrantFiled: December 27, 2022Date of Patent: May 7, 2024Assignee: Intel CorporationInventors: Shrenik Kothari, Chandra Mohan Jha, Weihua Tang, Robert Sankman, Xavier Brun, Pooya Tadayon
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Patent number: 11961779Abstract: A package includes a substrate having a conductive layer, and the conductive layer comprises an exposed portion. A die stack is disposed over the substrate and electrically connected to the conductive layer. A high thermal conductivity material is disposed over the substrate and contacting the exposed portion of the conductive layer. The package further includes a contour ring over and contacting the high thermal conductivity material.Type: GrantFiled: May 27, 2021Date of Patent: April 16, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC).Inventors: Wensen Hung, Szu-Po Huang, Hsiang-Fan Lee, Kim Hong Chen, Chi-Hsi Wu, Shin-Puu Jeng
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Patent number: 11955413Abstract: A semiconductor module includes a conductive substrate, a semiconductor element, a control terminal, and a sealing resin. The conductive substrate has an obverse surface and a reverse surface that are spaced apart from each other in a thickness direction. The semiconductor element is electrically bonded to the obverse surface and has a switching function. The control terminal is configured to control the semiconductor element. The sealing resin has a resin obverse surface and a resin reverse surface, and covers the conductive substrate, the semiconductor element, and a part of the control terminal. The control terminal protrudes from the resin obverse surface, and extends along the thickness direction.Type: GrantFiled: August 24, 2023Date of Patent: April 9, 2024Assignee: ROHM CO., LTD.Inventors: Kohei Tanikawa, Kenji Hayashi, Ryosuke Fukuda
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Patent number: 11955414Abstract: A semiconductor module includes a conductive substrate, a semiconductor element, a control terminal, and a sealing resin. The conductive substrate has an obverse surface and a reverse surface that are spaced apart from each other in a thickness direction. The semiconductor element is electrically bonded to the obverse surface and has a switching function. The control terminal is configured to control the semiconductor element. The sealing resin has a resin obverse surface and a resin reverse surface, and covers the conductive substrate, the semiconductor element, and a part of the control terminal. The control terminal protrudes from the resin obverse surface, and extends along the thickness direction.Type: GrantFiled: August 24, 2023Date of Patent: April 9, 2024Assignee: ROHM CO., LTD.Inventors: Kohei Tanikawa, Kenji Hayashi, Ryosuke Fukuda
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Patent number: 11942430Abstract: Stacked die modules for semiconductor device assemblies and methods of manufacturing the modules are disclosed. In some embodiments, the module includes a shingled stack of semiconductor dies, each die having an uncovered porch with bond pads. Further, a dielectric structure partially encapsulates the shingled stack of semiconductor dies. The dielectric structure includes openings corresponding to the bond pads. The module also includes conductive structures disposed on the dielectric structure, where each of the conductive structures extends over at least one porch of the semiconductor dies to connect to at least one bond pad through a corresponding opening. The semiconductor device assembly may include a controller die attached to a package substrate, the controller die carrying one or more stacked die modules, and bonding wires connecting terminals of the modules to package bond pads.Type: GrantFiled: July 12, 2021Date of Patent: March 26, 2024Assignee: Micron Technology, Inc.Inventor: Jong Sik Paek
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Patent number: 11929430Abstract: A method includes providing a semiconductor body including a plurality of two-dimensional charge carrier gas channels, forming a gate fin by forming a pair of gate trenches in an upper surface of the semiconductor body, the pair of gate trenches exposing each one of two-dimensional charge carrier gas channels, providing source and drain contacts that are electrically connected to each one of the plurality of two-dimensional charge carrier gas channels, providing a gate structure that is configured to control a conductive connection between the source and drain contacts, wherein providing the gate structure includes forming a layer of doped type III-nitride semiconductor material that covers the gate fin and extends into the gate trenches, and forming a conductive gate electrode on top of the layer of doped type III-nitride semiconductor material.Type: GrantFiled: December 28, 2021Date of Patent: March 12, 2024Assignee: Infineon Technologies Austria AGInventors: Thomas Detzel, Gerhard Prechtl, Oliver Haeberlen
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Patent number: 11908766Abstract: The present invention relates to a cooling system where a semiconductor component including a semiconductor chip and a cooling apparatus are joined, wherein a coolant is supplied to a substrate, on which a semiconductor chip is installed, through an opening member of the cooling apparatus so that a surface of the substrate may be directly cooled by the coolant so as to improve cooling efficiency, and a cooling post structure, which enables the coolant to smoothly flow, is used to further improve cooling efficiency.Type: GrantFiled: September 28, 2021Date of Patent: February 20, 2024Assignee: JMJ Korea Co., Ltd.Inventor: Yun Hwa Choi
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Patent number: 11901319Abstract: A first protective layer is formed on a first die and a second die, and openings are formed within the first protective layer. The first die and the second die are encapsulated such that the encapsulant is thicker than the first die and the second die, and vias are formed within the openings. A redistribution layer can also be formed to extend over the encapsulant, and the first die may be separated from the second die.Type: GrantFiled: April 19, 2021Date of Patent: February 13, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hui-Min Huang, Chih-Wei Lin, Tsai-Tsung Tsai, Ming-Da Cheng, Chung-Shi Liu, Chen-Hua Yu
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Patent number: 11892503Abstract: A semiconductor device includes first and second chips in a package. A first pad is on the first chip and electrically connected to a node between a power supply pad and a ground pad on the first chip. Second and third pads are on the second chip. An internal wiring connects the first pad to the second pad within the package. A power circuit on the semiconductor chip configured to supply a current to the second pad. A switch is on the second chip between the second pad and the power supply circuit to connect or disconnect the second pad from the power circuit. A control circuit is on the second chip and configured to output a first signal for the switch in response to a test signal supplied to the third pad and a second signal to the power circuit to cause the power circuit to output current.Type: GrantFiled: August 29, 2022Date of Patent: February 6, 2024Assignee: Toshiba Tec Kabushiki KaishaInventors: Takuya Kusaka, Hirosuke Narai, Kazunori Masuda, Makoto Iwai
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Patent number: 11894333Abstract: A semiconductor package includes: a redistribution substrate including a connection via and a redistribution layer electrically connected to each other, and a redistribution pad electrically connected to the redistribution layer by the connection via, a space pattern separating at least some of the redistribution pads from each other, a dummy metal pattern at least partially surrounded by the space pattern, and a degassing opening passing through at least one of the redistribution pad and the dummy metal pattern; a connection bump electrically connected to the redistribution pad; and a semiconductor chip on the redistribution substrate and including a connection pad electrically connected to the redistribution layer, the redistribution pad including a plurality of protrusions protruding from the same plane in directions different from each other and having a corner having a rounded shape, and the dummy metal pattern includes branch patterns each extending in directions different from one another.Type: GrantFiled: August 13, 2021Date of Patent: February 6, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dahee Kim, Jeongrim Seo, Gookmi Song
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Patent number: 11870130Abstract: A semiconductor device includes a semiconductor die comprising a radio frequency (RF) circuit, a first dielectric layer disposed over a first surface of the semiconductor die, an antenna layer disposed over a surface of the first dielectric layer, and an antenna feeding structure coupling the antenna layer to the RF circuit of the semiconductor die, wherein the semiconductor die comprises a via, and the antenna feeding structure comprises a first portion arranged within the opening of the semiconductor die and extending to the first surface of the semiconductor die, and a second portion arranged through the first dielectric layer.Type: GrantFiled: July 27, 2020Date of Patent: January 9, 2024Assignee: Infineon Technologies AGInventors: Eung San Cho, Ashutosh Baheti, Saverio Trotta
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Patent number: 11854958Abstract: A method includes obtaining an active feature layer having a first surface bearing one or more active feature areas. A first capacitor plate of a first capacitor is formed on an interior surface of a cap. A second capacitor plate of the first capacitor is formed on an exterior surface of the cap. The first capacitor plate of the first capacitor overlays and is spaced apart from the second capacitor plate of the first capacitor along a direction that is orthogonal to the exterior surface of the cap to form the first capacitor. The cap is coupled with the first surface of the active feature layer such that the second capacitor plate of the first capacitor is in electrical communication with at least a first active feature of the active feature layer. The cap is bonded with the passive layer substrate.Type: GrantFiled: July 27, 2022Date of Patent: December 26, 2023Assignee: General Electric CompanyInventors: Marco Francesco Aimi, Joseph Alfred Iannotti, Joleyn Eileen Brewer
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Patent number: 11837523Abstract: A transistor package comprising: a substrate; a first transistor in thermal contact with the substrate, wherein the transistor comprises a gate; the substrate sintered to a heat sink through a sintered layer; an encapsulant that at least partially encapsulates the first transistor; and a Kelvin connection to the transistor gate.Type: GrantFiled: October 14, 2022Date of Patent: December 5, 2023Assignee: Tesla, Inc.Inventors: Wenjun Liu, Robert James Ramm, Alan David Tepe, Colin Kenneth Campbell, Dino Sasaridis
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Patent number: 11824054Abstract: A package structure includes an insulating encapsulation, a semiconductor die, and a filter structure. The semiconductor die is encapsulated in the insulating encapsulation. The filter structure is electrically coupled to the semiconductor die, wherein the filter structure includes a patterned metallization layer with a pattern having a double-spiral having aligned centroids thereof.Type: GrantFiled: March 28, 2022Date of Patent: November 21, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sen-Kuei Hsu, Hsin-Yu Pan, Ming-Hsien Tsai
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Patent number: 11824110Abstract: A buffer layer, an etching stop layer, and a channel layer are epitaxially grown in this order on a substrate. The substrate contains InP that has a high resistance by, for example, being doped with Fe. The buffer layer contains a compound semiconductor lattice-matched to InP. The etching stop layer includes InxAl1-xP (0?x?0.75). The channel layer contains InyGa1-y As (0<y?1).Type: GrantFiled: November 19, 2019Date of Patent: November 21, 2023Assignee: Nippon Telegraph and Telephone CorporationInventor: Hiroki Sugiyama
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Patent number: 11798883Abstract: A semiconductor device includes an integrated circuit (IC) and an interlayer dielectric layer on the substrate, a contact through the interlayer dielectric layer and electrically connected to the IC, a wiring layer on the interlayer dielectric layer with a wiring line electrically connected to the contact, a first passivation layer on the wiring layer, first and second pads on the first passivation layer, and a through electrode through the substrate, the interlayer dielectric layer, the wiring layer, and the first passivation layer to connect to the first pad. The first pad includes a first head part on the first passivation layer, and a protruding part that extends into the first passivation layer from the first head part, the protruding part surrounding a lateral surface of the through electrode in the first passivation layer, and the second pad is connected to the IC through the wiring line and the contact.Type: GrantFiled: November 16, 2021Date of Patent: October 24, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Shaofeng Ding, Jeong Hoon Ahn, Yun Ki Choi
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Patent number: 11791255Abstract: A die package and method is disclosed. In one example, the die package includes a die having a first die contact on a first side and a second die contact on a second side opposite the first side, and insulating material laterally adjacent to the die. A metal structure substantially directly contacts the surface of the second die contact, wherein the metal structure is made of the same material as the second die contact. A first pad contact on the first side of the die electrically contacts the first die contact, and a second pad contact on the first side of the die electrically contacts the second die contact via the metal structure. The insulating material electrically insulates the metal structure from the first die contact.Type: GrantFiled: June 27, 2022Date of Patent: October 17, 2023Assignee: Infineon Technologies AGInventor: Petteri Palm
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Patent number: 11749627Abstract: A fan-out wafer level package includes a semiconductor die with a redistribution layer on a sidewall of the semiconductor die. A redistribution layer positioned over the die includes an extended portion that extends along the sidewall. The semiconductor die is encapsulated in a molding compound layer. The molding compound layer is positioned between the extended portion of the redistribution layer and the sidewall of the semiconductor die. Solder contacts, for electrically connecting the semiconductor device to an electronic circuit board, are positioned on the redistribution layer. The solder contacts and the sidewall of the redistribution layer can provide electrical contact on two different locations. Accordingly, the package can be used to improve interconnectivity by providing vertical and horizontal connections.Type: GrantFiled: October 28, 2021Date of Patent: September 5, 2023Assignee: STMICROELECTRONICS LTDInventors: Endruw Jahja, Cheng-Yang Su
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Patent number: 11728309Abstract: A clip for connecting an electronic component with a carrier in a package is provided. The clip includes a clip body having a component connection portion configured to be connected with the electronic component to be mounted on the carrier, and a carrier connection portion configured to be connected with the carrier. The clip further includes at least one locking recess in a surface portion of the clip body, the surface portion being configured to face the carrier. The at least one locking recess is configured to accommodate material of an encapsulant of the package so as to lock the encapsulant and the clip. A corresponding method of manufacturing the package is also provided.Type: GrantFiled: May 15, 2020Date of Patent: August 15, 2023Assignee: Infineon Technologies AGInventors: Melvin Levardo, Ryan Ross Agbay Alinea, Markus Dinkel
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Patent number: 11715867Abstract: The embodiments of the application provides an end cover assembly, a battery cell, a battery module and a device, the end cover assembly is used for the battery cell, the end cover assembly includes an end cover; an electrode terminal disposed on the end cover; an insulating member for insulating the electrode terminal and the end cover and disposed to surround the electrode terminal; wherein the insulating member abuts the electrode terminal, at least one of the insulating member and the electrode terminal is provided with a stress relief groove, the stress relief groove is configured to absorb stress generated by the electrode terminal's abutting the insulating member.Type: GrantFiled: December 7, 2020Date of Patent: August 1, 2023Assignee: Contemporary Amperex Technology Co., LimitedInventors: Ningsheng Wu, Chengyou Xing, Yuanbao Chen, Peng Wang, Quankun Li
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Patent number: 11715701Abstract: According to one embodiment, a semiconductor device includes a wiring board that has a first surface and a second surface opposed to the first surface, a semiconductor chip provided on the first surface, external connection terminals provided on the second surface, a sealing resin layer provided on the first surface, and a conductive shield layer that covers at least a portion of a side surface of the wiring board and the sealing resin layer. The wiring board includes a first ground wire that is electrically connected to the conductive shield layer, and a second ground wire that is electrically connected to the conductive shield layer and is electrically insulated from the first ground wire.Type: GrantFiled: April 17, 2019Date of Patent: August 1, 2023Assignee: Kioxia CorporationInventors: Yuusuke Takano, Yoshiaki Goto, Takeshi Watanabe, Takashi Imoto
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Patent number: 11710687Abstract: A semiconductor guide pin is disclosed. Specific implementations may include a heatsink, one or more substrates coupled together, one or more pressfit pins coupled to the one or more substrates, and two or more guide pins coupled to the one or more substrates, where the two or more guide pins may have a height greater than the one or more pressfit pins.Type: GrantFiled: July 3, 2019Date of Patent: July 25, 2023Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Chee Hiong Chew, Yushuang Yao, Atapol Prajuckamol, Chuncao Niu
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Patent number: 11679680Abstract: A power module (10) for operating an electric vehicle drive includes a current input configured for supplying an input current. The current input includes multiple contact elements (182, 184). Multiple circuit-breakers (142, 144) are configured for generating an output current based on the supplied input current. A current output (192) is configured for outputting the output current at a consumer. A substrate (12) includes a metal layer (122-130) and an insulating layer (121) connected to the metal layer (122-130). The multiple circuit-breakers (142, 144) are arranged on the metal layer (122-130). The multiple contact elements (182, 184) are also arranged on the metal layer (122-130) such that the multiple contact elements (182, 184) extend perpendicular to a surface of the substrate (12).Type: GrantFiled: October 7, 2021Date of Patent: June 20, 2023Assignee: ZF FRIEDRICHSHAFEN AGInventor: Wei Liu
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Patent number: 11658131Abstract: A semiconductor package includes a first substrate including a circuit pattern and a dummy pattern on an upper face of the first substrate, a solder ball, a second substrate on the first substrate, and an underfill material layer between the first and second substrates. The underfill material layer wraps around the solder ball. The dummy pattern is not electrically connected to the circuit pattern. The first substrate includes a solder resist layer on the circuit pattern and the dummy pattern. The solder resist layer includes a first opening for exposing at least a part of the circuit pattern. The solder ball is in the first opening and electrically insulated from the dummy pattern by the solder resist layer. The second substrate is electrically connected to the first substrate by the solder ball. The second substrate is electrically insulated from the dummy pattern by the solder resist layer.Type: GrantFiled: February 5, 2021Date of Patent: May 23, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jin-Woo Park, Un-Byoung Kang, Jong Ho Lee
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Patent number: 11637049Abstract: A semiconductor device, including a semiconductor chip having a first electrode on a rear surface thereof, a laminated substrate including a heat dissipation board laminated on a rear surface of an insulating board, and a case. The case includes a frame surrounding an opening penetrating the case from a front surface to a rear surface thereof, the frame being in contact with a periphery of the laminated substrate covering the opening from the rear surface of the case, and a first terminal penetrating the frame. The first terminal includes a first connection part penetrating the frame and extending out of the frame, and a first wiring part provided in the opening. The first wiring part has a wiring rear surface disposed on a front surface of the insulating board, and a wiring front surface mechanically and electrically connected to the first electrode of the semiconductor chip.Type: GrantFiled: June 23, 2021Date of Patent: April 25, 2023Assignee: FUJI ELECTRIC CO., LTD.Inventor: Tomoyuki Wakiyama
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Patent number: 11631608Abstract: Disclosed are support substrates, methods of fabricating semiconductor packages using the same, and methods of fabricating electronic devices using the same. The support substrate comprises a main body, and a plurality of first protrusions finely protruding from an upper surface of the main body. The main body and the first protrusions include the same material and are formed as a unitary structure. The first protrusions are spaced apart from each other in first and second directions intersecting each other, when viewed in plan.Type: GrantFiled: October 1, 2020Date of Patent: April 18, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kunsil Lee, Seung Hwan Lee
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Patent number: 11600557Abstract: A packaged semiconductor device includes a lead frame including plurality of lead terminals each having a plated wettable flank dimple including 2 or more different widths including narrower lead terminals and wider lead terminals. A semiconductor die is attached to the lead frame. A mold material terminates at a saw line of the packaged semiconductor device providing encapsulation except for an exposed bottom contact and an exposed sidewall contact for the plurality of lead terminals. The wider lead terminals have a necked region with a reduced width extending inward a predetermined distance from the saw line, where a terminal region inward beyond the necked region which is wider as compared to the necked region.Type: GrantFiled: May 6, 2019Date of Patent: March 7, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Robert F. Mortan
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Patent number: 11594510Abstract: In a general aspect, a method for producing a semiconductor device assembly can include defining a cavity in a conductive spacer, and electrically and thermally coupling a semiconductor die with the conductive spacer, such that the semiconductor die is at least partially embedded in the cavity. The semiconductor die can have a first surface having active circuitry included therein, a second surface opposite the first surface, and a plurality of side surfaces each extending between the first surface of the semiconductor die and the second surface of the semiconductor die. The method can also include electrically coupling a direct bonded metal (DBM) substrate with the first surface of the semiconductor die.Type: GrantFiled: April 1, 2021Date of Patent: February 28, 2023Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Yong Liu, Yusheng Lin, Huibin Chen
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Patent number: 11557543Abstract: A semiconductor package includes a first semiconductor chip including a first surface and a second surface, and including a first active layer on a portion adjacent to the first surface; a first redistribution structure on the first surface of the first semiconductor chip, wherein the first redistribution structure includes a first area and a second area next to the first area; a second semiconductor chip mounted in the first area of the first redistribution structure, including a third surface, which faces the first surface, and a fourth surface, and including a second active layer on a portion adjacent to the third surface; a conductive post mounted in the second area of the first redistribution structure; a molding layer at least partially surrounding the second semiconductor chip and the conductive post on the first redistribution structure; and a second redistribution structure disposed on the molding layer and connected to the conductive post.Type: GrantFiled: March 22, 2021Date of Patent: January 17, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Eunkyoung Choi
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Patent number: 11552045Abstract: Semiconductor devices having redistribution structures, and associated systems and methods, are disclosed herein. In some embodiments, a semiconductor assembly comprises a die stack including a plurality of semiconductor dies, and a routing substrate mounted on the die stack. The routing substrate includes an upper surface having a redistribution structure. The semiconductor assembly also includes a plurality of electrical connectors coupling the redistribution structure to at least some of the semiconductor dies. The semiconductor assembly further includes a controller die mounted on the routing substrate. The controller die includes an active surface that faces the upper surface of the routing substrate and is electrically coupled to the redistribution structure, such that the routing substrate and the semiconductor dies are electrically coupled to the controller die via the redistribution structure.Type: GrantFiled: November 20, 2020Date of Patent: January 10, 2023Assignee: Micron Technology, Inc.Inventors: Owen R. Fay, Madison E. Wale, James L. Voelz, Dylan W. Southern, Dustin L. Holloway
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Patent number: 11488921Abstract: A multi-chip device is provided. The multi-chip device includes a first chip, a second chip mounted on the first chip, and a hardened printed or sprayed electrically conductive material forming a sintered electrically conductive interface between the first chip and the second chip.Type: GrantFiled: October 1, 2020Date of Patent: November 1, 2022Assignee: Infineon Technologies AGInventors: Ali Roshanghias, Alfred Binder, Barbara Eichinger, Stefan Karner, Martin Mischitz, Rainer Pelzer
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Patent number: 11482480Abstract: A package substrate and method of manufacturing a package substrate and a semiconductor device package are provided. The package substrate includes a circuit layer, an optically-cured dielectric layer, a plurality of block layers and a sacrificial layer. The circuit layer includes a plurality of conductive pads. The optically-cured dielectric layer has an upper surface and a lower surface opposite to the upper surface. The optically-cured dielectric layer covers the circuit layer, and first surfaces of the conductive pads are at least partially exposed from the upper surface of the optically-cured dielectric layer. The block layers are respectively disposed on the first surfaces of the conductive pads exposed by the optically-cured dielectric layer. The sacrificial layer is disposed on the optically-cured dielectric layer and covering the block layers.Type: GrantFiled: March 19, 2020Date of Patent: October 25, 2022Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventor: You-Lung Yen
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Patent number: 11469191Abstract: A semiconductor device has a semiconductor die and an encapsulant deposited over the semiconductor die. A first conductive layer is formed with an antenna over a first surface of the encapsulant. A second conductive layer is formed with a ground plane over a second surface of the encapsulant with the antenna located within a footprint of the ground plane. A conductive bump is formed on the ground plane. A third conductive layer is formed over the first surface of the encapsulant. A fourth conductive layer is formed over the second surface of the encapsulant. A conductive via is disposed adjacent to the semiconductor die prior to depositing the encapsulant. The antenna is coupled to the semiconductor die through the conductive via. The antenna is formed with the conductive via between the antenna and semiconductor die. A PCB unit is disposed in the encapsulant.Type: GrantFiled: March 21, 2020Date of Patent: October 11, 2022Assignee: STATS ChipPAC Pte. Ltd.Inventors: Pandi Chelvam Marimuthu, Andy Chang Bum Yong, Aung Kyaw Oo, Yaojian Lin
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Patent number: 11462446Abstract: A power semiconductor module arrangement includes a semiconductor substrate arranged in a housing, at least one semiconductor body being arranged on the semiconductor substrate, and a mounting arrangement including a frame or body, a first terminal element, and a second terminal element. The mounting arrangement is inserted in and coupled to the housing. Each terminal element mechanically and electrically contacts the semiconductor substrate with a first end. A middle part of each terminal element extends through the frame or body. A second end of each terminal element extends outside the housing. The first terminal element is dielectrically insulated from the second terminal element by a portion of the frame or body. The first terminal element is injected into and inextricably coupled to the frame or body. The second terminal element is arranged within a hollow space inside the frame or body and is detachably coupled to the frame or body.Type: GrantFiled: May 5, 2020Date of Patent: October 4, 2022Assignee: Infineon Technologies AGInventor: Alexander Hoehn
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Patent number: 11456231Abstract: Various heatsink arrangements, and methods for implementing and using such are discussed.Type: GrantFiled: January 18, 2021Date of Patent: September 27, 2022Assignee: Fortinet, Inc.Inventors: Shen Sunny Zhong, Qian Yu, Han Hsu
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Patent number: 11450644Abstract: A semiconductor package is provided. The semiconductor package may include a substrate, a chip stack disposed on the substrate, the chip stack including a plurality of semiconductor chips, a plurality of bonding wires electrically connecting the substrate to the plurality of semiconductor chips, a reinforcement layer disposed on the chip stack, and a molding layer surrounding side surfaces of the chip stack and the bonding wires and contacting side surfaces of the reinforcement layer. The reinforcement layer may include a lower layer including an adhesive, an intermediate layer disposed on the lower layer, and an upper layer disposed on the intermediate layer. The intermediate layer may have elongation in a range of 5% to 70%. The upper layer may have elongation less than 5%.Type: GrantFiled: September 15, 2020Date of Patent: September 20, 2022Assignee: SK hynix Inc.Inventors: Sung Su Kim, Byoung Jun Ahn
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Patent number: 11437359Abstract: A method for manufacturing a three-dimensional integrated circuit includes attaching a first side of a first die to a first carrier wafer. The method includes preparing a second side of the first die to generate a prepared second side of the first die. The method includes attaching the prepared second side of the first die to a second carrier wafer. The method includes removing the first carrier wafer from the first side of the first die to form a transitional three-dimensional integrated circuit. The method includes attaching a third carrier wafer to a first side of the transitional three-dimensional integrated circuit. The method includes attaching a first side of the second die to a second side of the transitional three-dimensional integrated circuit.Type: GrantFiled: February 24, 2020Date of Patent: September 6, 2022Assignee: Advanced Micro Devices, Inc.Inventors: Brett P. Wilkerson, Milind S. Bhagavat, Rahul Agarwal, Dmitri Yudanov
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Patent number: 11430739Abstract: Structures and formation methods of a package structure are provided. The method includes forming a conductive structure over a carrier substrate and disposing a semiconductor die over the carrier substrate. The method also includes pressing a protective substrate against the carrier substrate at an elevated temperature to bond the protective substrate to the conductive structure. The method further includes forming a protective layer to surround the semiconductor die.Type: GrantFiled: June 11, 2019Date of Patent: August 30, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Po-Hao Tsai, Hsien-Wen Liu, Shin-Puu Jeng, Meng-Liang Lin, Shih-Yung Peng, Shih-Ting Hung
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Patent number: 11430720Abstract: A lead for a surface mount package for a semiconductor device, and the surface mount package employing the same. In one example, the lead includes a central segment with a first side and a second side, a first extension from a portion of the first side, and a second extension from a portion of the second side. The lead also includes a recess extending through a portion of the central segment, the first extension and the second extension.Type: GrantFiled: July 27, 2020Date of Patent: August 30, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Naweed Anjum, Michael Gerald Amaro, Makarand Ramkrishna Kulkarni
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Patent number: 11424180Abstract: A semiconductor device with redistribution layers on partial encapsulation is disclosed and may include providing a carrier with a non-photosensitive protection layer, forming a pattern in the non-photosensitive protection layer, providing a semiconductor die with a contact pad on a first surface, and bonding the semiconductor die to the non-photosensitive protection layer such that the contact pad aligns with the pattern formed in the non-photosensitive protection layer. A second surface opposite to the first surface of the semiconductor die, side surfaces between the first and second surfaces of the semiconductor die, and a portion of a first surface of the non-photosensitive protection layer may be encapsulated with an encapsulant. The carrier may be removed leaving the non-photosensitive protection layer bonded to the semiconductor die. A redistribution layer may be formed on the contact pad and a second surface of the non-photosensitive protection layer opposite to the first surface.Type: GrantFiled: June 2, 2020Date of Patent: August 23, 2022Assignee: AMKOR TECHNOLOGY SINGAPORE HOLDING PTE. LTD.Inventors: Jong Sik Paek, Jin Young Kim, YoonJoo Kim, Jin Han Kim, SeungJae Lee, Se Woong Cha, SungKyu Kim, Jae Hun Bae, Dong Jin Kim, Doo Hyun Park
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Patent number: 11417594Abstract: A three-Dimensional Integrated Circuit (3DIC) Chip on Wafer on Substrate (CoWoS) packaging structure or system includes a silicon oxide interposer with no metal ingredients, and with electrically conductive TVs and RDLs. The silicon oxide interposer has a first surface and a second surface opposite to the first surface. The electrically conductive TVs penetrate through the silicon oxide interposer. The electrically interconnected RDLs are disposed over the first surface of the silicon oxide interposer, and are electrically coupled or connected to a number of the conductive TVs.Type: GrantFiled: November 26, 2018Date of Patent: August 16, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventor: Wen-Shiang Liao
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Patent number: 11410974Abstract: A semiconductor memory device includes first and second memory chips, each including a region of a core circuit, a first area adjacent to a first side of the region in a first direction, a second area adjacent to a second side of the region in a second direction, a third area adjacent to the first area in the first direction and to the second area in the second direction, a first pad in the first area, a second pad in the second area, and third pad in the third area. In each memory chip, a first bonding wire connects the first and third pads. In addition, a second bonding wire connects the second pads of the first and second memory chips. The second memory chip is stacked on the first memory chip to expose the first, second, and third areas of the first memory chip in a third direction.Type: GrantFiled: September 3, 2020Date of Patent: August 9, 2022Assignee: KIOXIA CORPORATIONInventors: Masahiro Yoshihara, Toshikazu Watanabe, Nobuharu Miyata, Yasumitsu Nozawa, Tomohito Kawano, Sachie Fukuda, Akiyoshi Itou, Toshimitsu Iwasawa
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Patent number: 11410939Abstract: Structures and formation methods of a chip package are provided. The chip package includes a substrate and a semiconductor die over the substrate. The chip package also includes a lid covering a top surface of the semiconductor die. The lid has a first support structure and a second support structure, and the first support structure and the second support structure are positioned at respective corner portions of the substrate. An opening penetrates through the lid to expose a space containing the semiconductor die, and the lid has a side edge extending from an edge of the first support structure to an edge of the second support structure.Type: GrantFiled: September 28, 2020Date of Patent: August 9, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shu-Shen Yeh, Chin-Hua Wang, Kuang-Chun Lee, Po-Yao Lin, Shyue-Ter Leu, Shin-Puu Jeng
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Patent number: 11398399Abstract: A component source wafer comprises printable components having adhesive disposed on a backside of the printable components. A wafer substrate comprises a sacrificial layer having recessed portions and anchors. A component is disposed entirely over each recessed portion. A tether physically connects each component to at least one of the anchors. A layer of adhesive is disposed on a side of the component adjacent to the recessed portion. Each component is suspended over the wafer substrate and the recessed portion defines a gap separating the component from the wafer substrate.Type: GrantFiled: March 3, 2020Date of Patent: July 26, 2022Assignee: X Display Company Technology LimitedInventors: António José Marques Trindade, Raja Fazan Gul, Ronald S. Cok