With Contact Or Lead Patents (Class 257/690)
  • Patent number: 12278190
    Abstract: The present application provides a semiconductor package structure having interconnections between dies, and a manufacturing method of the semiconductor package structure. The semiconductor package structure includes a first interposer including a first substrate and a first interconnect layer over the first substrate; a second interposer disposed over the first interposer, wherein the second interposer includes a second substrate and a second interconnect layer over the second substrate; a first die disposed over the first interposer and adjacent to the second interposer; a second die disposed over the second interposer; a first molding disposed over the second interposer and surrounding the second die; and a second molding disposed over the first interposer and surrounding the first die and the first molding, wherein the first interconnect layer includes a first communication member electrically connecting the first die to the second interposer and the second die.
    Type: Grant
    Filed: May 12, 2023
    Date of Patent: April 15, 2025
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Shing-Yih Shih
  • Patent number: 12272862
    Abstract: A semiconductor device includes a semiconductor die comprising a radio frequency (RF) circuit, a first dielectric layer disposed over a first surface of the semiconductor die, an antenna layer disposed over a surface of the first dielectric layer, and an antenna feeding structure coupling the antenna layer to the RF circuit of the semiconductor die, wherein the semiconductor die comprises a via, and the antenna feeding structure comprises a first portion arranged within the opening of the semiconductor die and extending to the first surface of the semiconductor die, and a second portion arranged through the first dielectric layer.
    Type: Grant
    Filed: November 27, 2023
    Date of Patent: April 8, 2025
    Assignee: Infineon Technologies AG
    Inventors: Eung San Cho, Ashutosh Baheti, Saverio Trotta
  • Patent number: 12266628
    Abstract: A semiconductor package includes: a semiconductor die attached to a lead frame and having a first bond pad at a side of the semiconductor die facing away from the lead frame; a metal clip having a first bonding region attached to the first bond pad by a solder joint, the metal clip providing an electrical pathway to the first bond pad; and an additional electrical pathway to the first bond pad. A first end of the additional electrical pathway is attached to the first bond pad. At one or more locations between the first end and a second end of the additional electrical pathway, the additional electrical pathway is attached to a surface of the first bonding region of the metal clip that faces away from the first bond pad. Methods of producing the semiconductor package are also described.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: April 1, 2025
    Assignee: Infineon Technologies AG
    Inventors: Engku Izyan Munirah E Afandi, Wee Peng Chong, Joel Feliciano Del Rosario
  • Patent number: 12266648
    Abstract: A package structure includes an insulating encapsulation, a semiconductor die, and a filter structure. The semiconductor die is encapsulated in the insulating encapsulation. The filter structure is electrically coupled to the semiconductor die, wherein the filter structure includes a patterned metallization layer with a pattern having a double-spiral having aligned centroids thereof.
    Type: Grant
    Filed: August 2, 2023
    Date of Patent: April 1, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sen-Kuei Hsu, Hsin-Yu Pan, Ming-Hsien Tsai
  • Patent number: 12264390
    Abstract: This pure copper material includes Cu in an amount of 99.96 mass % or more, either one or both of one or more A-group elements selected from Ca, Ba, Sr, Zr, Hf, Y, Sc, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu, and one or more B-group elements selected from O, S, Se, and Te are included in a total amount of 10 mass ppm or more and 300 mass ppm or less, an average crystal grain size in a rolled surface is 15 ?m or more, and a high-temperature Vickers hardness at 850° C. is 4.0 HV or more and 10.0 HV or less.
    Type: Grant
    Filed: July 27, 2023
    Date of Patent: April 1, 2025
    Assignee: MITSUBISHI MATERIALS CORPORATION
    Inventors: Yuki Ito, Takumi Odaira, Kenichiro Kawasaki, Kazunari Maki
  • Patent number: 12255155
    Abstract: A package structure is provided. The package structure includes a lower semiconductor die and a first protective layer surrounding the lower semiconductor die. The package structure also includes a dielectric layer partially covering the first protective layer and the lower semiconductor die and an upper semiconductor die over the lower semiconductor die and the first protective layer. The upper semiconductor die is bonded with the lower semiconductor die through a connector. The package structure further includes an insulating film surrounding the connector and a second protective layer surrounding the upper semiconductor die. A portion of the second protective layer is between the insulating film and the dielectric layer.
    Type: Grant
    Filed: January 28, 2022
    Date of Patent: March 18, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Chao Mao, Chin-Chuan Chang, Szu-Wei Lu
  • Patent number: 12243853
    Abstract: A stack package includes a core die disposed over a package substrate, and a controller die disposed between the core die and the package substrate to control the core die. The core die includes banks each including memory cell arrays, an interbank region in which row decoders and column decoders are arranged, and a pad region in which first connection pads electrically connected to the row decoders and column decoders through first wirings are disposed. The controller die includes a through via region in which controller die through vias penetrating the controller die to be connected to the first connection pads are disposed, and a circuit region in which controlling circuitry electrically connected to the controller die through vias through second wirings is disposed.
    Type: Grant
    Filed: October 2, 2023
    Date of Patent: March 4, 2025
    Assignee: SK hynix Inc.
    Inventor: Bok Kyu Choi
  • Patent number: 12243772
    Abstract: A method includes bonding a first wafer to a second wafer. The first wafer includes a plurality of dielectric layers, a metal pipe penetrating through the plurality of dielectric layers, and a dielectric region encircled by the metal pipe. The dielectric region has a plurality of steps formed of sidewalls and top surfaces of portions of the plurality of dielectric layers that are encircled by the metal pipe. The method further includes etching the first wafer to remove the dielectric region and to leave an opening encircled by the metal pipe, extending the opening into the second wafer to reveal a metal pad in the second wafer, and filling the opening with a conductive material to form a conductive plug in the opening.
    Type: Grant
    Filed: July 21, 2023
    Date of Patent: March 4, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ssu-Chiang Weng, Ping-Hao Lin, Fu-Cheng Chang
  • Patent number: 12243850
    Abstract: A package includes a first chip stack. The first chip stack includes a first chip including first bonding structures, a second chip including second bonding structures facing the first bonding structures and bonded to the first bonding structures, and a first electrical contact on the second chip. At least a portion of the first electrical contact does not overlap with the first chip in a plan view.
    Type: Grant
    Filed: August 3, 2021
    Date of Patent: March 4, 2025
    Assignee: Flex Ltd.
    Inventors: Cheng Yang, Dongkai Shangguan
  • Patent number: 12237253
    Abstract: A semiconductor package includes an interposer having a pad insulating film, a first lower pad exposed from a lower surface of the pad insulating film, the first lower pad including a first extension and a second extension spaced apart from each other and extending side by side in a first direction, and a first connection extending in a second direction intersecting the first direction and connecting the first extension and the second extension, and a redistribution structure that covers an upper surface of the pad insulating film, first interposer bumps on a lower surface of the interposer and spaced apart from each other, at least a part of each of the first and second extensions being connected to one of the first interposer bumps, and a first semiconductor chip on an upper surface of the interposer and electrically connected to the redistribution structure.
    Type: Grant
    Filed: February 22, 2022
    Date of Patent: February 25, 2025
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jun Hyeong Park, Jin Young Kim, Young Kwan Seo
  • Patent number: 12211840
    Abstract: A metal oxide semiconductor, MOS, device (405) is described that includes a gate terminal, at least one source terminal and at least one drain terminal, wherein at least one source terminal and at least one drain terminal are formed of metal and are connected to a number of respective contact vias.
    Type: Grant
    Filed: December 14, 2021
    Date of Patent: January 28, 2025
    Assignee: NXP B.V.
    Inventors: Jozef Reinerus Maria Bergervoet, Xin Yang, Mark Pieter van der Heijden, Lukas Frederik Tiemeijer, Alessandro Baiano
  • Patent number: 12199077
    Abstract: A light emitting apparatus including a substrate, a plurality of light emitting diode devices disposed on the substrate, a light non-transmitting layer disposed on the substrate and having at least one of open regions, and a first conductive bonding layer disposed between the plurality of lighting emitting diode devices and the substrate and electrically contacting the plurality of light emitting diode devices, in which an upper surface of the first conductive bonding layer is placed above the light non-transmitting layer.
    Type: Grant
    Filed: March 20, 2022
    Date of Patent: January 14, 2025
    Assignee: Seoul Semiconductor Co., Ltd.
    Inventors: Motonobu Takeya, Sung Su Son, Jong Ik Lee, Seung Sik Hong
  • Patent number: 12199080
    Abstract: A method includes bonding a first package to a second package to form a third package. The first package is an Integrated Fan-Out (InFO) package including a plurality of package components, and an encapsulating material encapsulating the plurality of package components therein. The plurality of package components include device dies. The method further includes placing at least a portion of the third package into a recess in a Printed Circuit Board (PCB). The recess extends from a top surface of the PCB to an intermediate level between the top surface and a bottom surface of the PCB. Wire bonding is performed to electrically connect the third package to the PCB.
    Type: Grant
    Filed: April 18, 2023
    Date of Patent: January 14, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hua Yu, Chien-Hsun Lee, Jiun Yi Wu
  • Patent number: 12199602
    Abstract: According to one embodiment, a semiconductor device includes a substrate; a first transistor, a second transistor, a third transistor, and a fourth transistor; a first light emitting element and a second light emitting element; a first light receiving element configured to switch the first transistor and the second transistor to an ON state or to an OFF state; and a second light receiving element configured to switch the third transistor and the fourth transistor to the ON state or to the OFF state, wherein the first light emitting element and the second light emitting element are configured such that, when either one of the first light emitting element or the second light emitting element is turned to a lit state, the other one is turned to an unlit state.
    Type: Grant
    Filed: August 29, 2023
    Date of Patent: January 14, 2025
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Yuichiro Niikura, Hitoshi Imai
  • Patent number: 12191251
    Abstract: A method includes forming a redistribution structure on a carrier, attaching an integrated passive device on a first side of the redistribution structure, attaching an interconnect structure to the first side of the redistribution structure, the integrated passive device interposed between the redistribution structure and the interconnect structure, depositing an underfill material between the interconnect structure and the redistribution structure, and attaching a semiconductor device on a second side of the redistribution structure that is opposite the first side of the redistribution structure.
    Type: Grant
    Filed: June 14, 2023
    Date of Patent: January 7, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jiun Yi Wu, Chen-Hua Yu, Chien-Hsun Chen
  • Patent number: 12166009
    Abstract: A semiconductor device package includes a first conductive layer, a second conductive layer and a third conductive layer. The first conductive layer has a first pitch. The second conductive layer has a second pitch and is arranged at two different sides of the first conductive layer. The third conductive layer has a third pitch and is disposed above the first conductive layer and the second conductive layer. The third conductive layer is electrically connected to the first conductive layer. The first pitch is smaller than the third pitch, and the third pitch is smaller than the second pitch.
    Type: Grant
    Filed: August 29, 2023
    Date of Patent: December 10, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Tang-Yuan Chen, Meng-Kai Shih, Teck-Chong Lee, Shin-Luh Tarng, Chih-Pin Hung
  • Patent number: 12142545
    Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a base substrate. The base substrate may have a plurality of through substrate vias. In an embodiment, a first die is over the base substrate. In an embodiment a first cavity is disposed into the base substrate. In an embodiment, the first cavity is at least partially within a footprint of the first die. In an embodiment, a first component is in the first cavity.
    Type: Grant
    Filed: August 28, 2023
    Date of Patent: November 12, 2024
    Assignee: Intel Corporation
    Inventors: Ravindranath Mahajan, Debendra Mallik, Sujit Sharan, Digvijay Raorane
  • Patent number: 12125760
    Abstract: A method of manufacturing an electronic package structure is disclosed. A solder mask layer is formed on an upper surface of a substrate. A recessed area is formed in the solder mask layer. An electronic component is mounted on the substrate. Pads are disposed on the upper surface of the substrate. The pads respectively correspond to the bumps on a first surface of the electronic component. The pads are electrically connected to the bumps. A heat treatment is performed to make the first surface close to the substrate and form a cavity in the recessed area. The cavity is between the first surface of the electronic component, the solder mask layer and the upper surface of the substrate.
    Type: Grant
    Filed: February 23, 2023
    Date of Patent: October 22, 2024
    Assignee: RichWave Technology Corp.
    Inventor: Yu-Lung Wen
  • Patent number: 12119320
    Abstract: A chip package structure is provided. The chip package structure includes a redistribution structure and a first chip structure over the redistribution structure. The chip package structure also includes a first solder bump between the redistribution structure and the first chip structure and a first molding layer surrounding the first chip structure. The chip package structure further includes a second chip structure over the first chip structure and a second molding layer surrounding the second chip structure. In addition, the chip package structure includes a third molding layer surrounding the first molding layer, the second molding layer, and the first solder bump. A portion of the third molding layer is between the first molding layer and the redistribution structure.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: October 15, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Yu Chen, Li-Hsien Huang, An-Jhih Su, Hsien-Wei Chen
  • Patent number: 12070800
    Abstract: One aspect of the present invention is a method for manufacturing an electronic component, the method including: a first step of applying a metal paste containing metal particles onto a polymer compact in a prescribed pattern to form a metal paste layer; a second step of sintering the metal particles to form metal wiring; a third step of applying a solder paste containing solder particles and a resin component onto the metal wiring to form a solder paste layer; a fourth step of disposing an electronic element on the solder paste layer; and a fifth step of heating the solder paste layer so as to form a solder layer bonding the metal wiring and the electronic element, and so as to form a resin layer covering at least a portion of the solder layer.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: August 27, 2024
    Assignee: RESONAC CORPORATION
    Inventors: Yoshinori Ejiri, Shinichirou Sukata, Masaya Toba, Hideo Nakako, Yuki Kawana, Kosuke Urashima, Motoki Yonekura, Takaaki Nohdoh, Yoshiaki Kurihara, Hiroshi Masuda, Keita Sone
  • Patent number: 12068230
    Abstract: A semiconductor module includes a conductive substrate, a semiconductor element, a control terminal, and a sealing resin. The conductive substrate has an obverse surface and a reverse surface that are spaced apart from each other in a thickness direction. The semiconductor element is electrically bonded to the obverse surface and has a switching function. The control terminal is configured to control the semiconductor element. The sealing resin has a resin obverse surface and a resin reverse surface, and covers the conductive substrate, the semiconductor element, and a part of the control terminal. The control terminal protrudes from the resin obverse surface, and extends along the thickness direction.
    Type: Grant
    Filed: February 1, 2024
    Date of Patent: August 20, 2024
    Assignee: ROHM CO., LTD.
    Inventors: Kohei Tanikawa, Kenji Hayashi, Ryosuke Fukuda
  • Patent number: 12057425
    Abstract: A semiconductor package including a base chip; a semiconductor chip having a lower surface on which connection pads are disposed, the semiconductor chip being mounted on an upper surface of the base chip; a plurality of bumps on the connection pads and electrically connecting the base chip to the semiconductor chip; an adhesive film between the base chip and the semiconductor chip and fixing the semiconductor chip to the base chip; and an encapsulant on the base chip and encapsulating the semiconductor chip, wherein the semiconductor chip includes a central portion spaced apart from the upper surface of the base chip by a first distance, and an edge portion spaced apart from the upper surface of the base chip by a second distance, the edge portion being outside of the central portion, and a ratio of the second distance to the first distance is about 0.8 to about 1.0.
    Type: Grant
    Filed: December 2, 2021
    Date of Patent: August 6, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eunyeong Kim, Yeongseok Kim, Jihwan Hwang
  • Patent number: 12046530
    Abstract: Disclosed are apparatuses and techniques for fabricating an apparatus including a semiconductor device. The semiconductor device may include: a die, a thermally conductive interface that includes a thermal bridge interposer (THBI) structure, and a substrate. The die is coupled to the substrate by the thermally conductive interface and at least a portion of the die is coupled to the substrate by the THBI structure.
    Type: Grant
    Filed: December 21, 2021
    Date of Patent: July 23, 2024
    Assignee: QUALCOMM INCORPORATED
    Inventors: Je-Hsiung Lan, Jonghae Kim, Ranadeep Dutta
  • Patent number: 11990411
    Abstract: In one example, a semiconductor device comprises a redistribution layer (RDL) substrate having a top surface and a bottom surface, wherein the RDL substrate comprises a filler-free dielectric material, an electronic device on the top surface of the RDL substrate, an electrical interconnect on the bottom surface of the RDL substrate and electrically coupled to the electronic device, a first protective material contacting a side surface of the electronic device and the top surface of the RDL substrate, and a second protective material contacting a side surface of the electrical interconnect and the bottom surface of the RDL substrate. Other examples and related methods are also disclosed herein.
    Type: Grant
    Filed: April 13, 2022
    Date of Patent: May 21, 2024
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Tae Ki Kim, Jae Beom Shim, Seung Nam Son, Won Chul Do
  • Patent number: 11978689
    Abstract: Embodiments disclosed herein include semiconductor dies and methods of forming such dies. In an embodiment, the semiconductor die comprises a semiconductor substrate, an active device layer in the semiconductor substrate, where the active device layer comprises one or more transistors, an interconnect layer over a first surface of the active device layer, a first bonding layer over a surface of the semiconductor substrate, a second bonding layer secured to the first bonding layer, and a heat spreader attached to the second bonding layer.
    Type: Grant
    Filed: December 27, 2022
    Date of Patent: May 7, 2024
    Assignee: Intel Corporation
    Inventors: Shrenik Kothari, Chandra Mohan Jha, Weihua Tang, Robert Sankman, Xavier Brun, Pooya Tadayon
  • Patent number: 11961779
    Abstract: A package includes a substrate having a conductive layer, and the conductive layer comprises an exposed portion. A die stack is disposed over the substrate and electrically connected to the conductive layer. A high thermal conductivity material is disposed over the substrate and contacting the exposed portion of the conductive layer. The package further includes a contour ring over and contacting the high thermal conductivity material.
    Type: Grant
    Filed: May 27, 2021
    Date of Patent: April 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC).
    Inventors: Wensen Hung, Szu-Po Huang, Hsiang-Fan Lee, Kim Hong Chen, Chi-Hsi Wu, Shin-Puu Jeng
  • Patent number: 11955414
    Abstract: A semiconductor module includes a conductive substrate, a semiconductor element, a control terminal, and a sealing resin. The conductive substrate has an obverse surface and a reverse surface that are spaced apart from each other in a thickness direction. The semiconductor element is electrically bonded to the obverse surface and has a switching function. The control terminal is configured to control the semiconductor element. The sealing resin has a resin obverse surface and a resin reverse surface, and covers the conductive substrate, the semiconductor element, and a part of the control terminal. The control terminal protrudes from the resin obverse surface, and extends along the thickness direction.
    Type: Grant
    Filed: August 24, 2023
    Date of Patent: April 9, 2024
    Assignee: ROHM CO., LTD.
    Inventors: Kohei Tanikawa, Kenji Hayashi, Ryosuke Fukuda
  • Patent number: 11955413
    Abstract: A semiconductor module includes a conductive substrate, a semiconductor element, a control terminal, and a sealing resin. The conductive substrate has an obverse surface and a reverse surface that are spaced apart from each other in a thickness direction. The semiconductor element is electrically bonded to the obverse surface and has a switching function. The control terminal is configured to control the semiconductor element. The sealing resin has a resin obverse surface and a resin reverse surface, and covers the conductive substrate, the semiconductor element, and a part of the control terminal. The control terminal protrudes from the resin obverse surface, and extends along the thickness direction.
    Type: Grant
    Filed: August 24, 2023
    Date of Patent: April 9, 2024
    Assignee: ROHM CO., LTD.
    Inventors: Kohei Tanikawa, Kenji Hayashi, Ryosuke Fukuda
  • Patent number: 11942430
    Abstract: Stacked die modules for semiconductor device assemblies and methods of manufacturing the modules are disclosed. In some embodiments, the module includes a shingled stack of semiconductor dies, each die having an uncovered porch with bond pads. Further, a dielectric structure partially encapsulates the shingled stack of semiconductor dies. The dielectric structure includes openings corresponding to the bond pads. The module also includes conductive structures disposed on the dielectric structure, where each of the conductive structures extends over at least one porch of the semiconductor dies to connect to at least one bond pad through a corresponding opening. The semiconductor device assembly may include a controller die attached to a package substrate, the controller die carrying one or more stacked die modules, and bonding wires connecting terminals of the modules to package bond pads.
    Type: Grant
    Filed: July 12, 2021
    Date of Patent: March 26, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Jong Sik Paek
  • Patent number: 11929430
    Abstract: A method includes providing a semiconductor body including a plurality of two-dimensional charge carrier gas channels, forming a gate fin by forming a pair of gate trenches in an upper surface of the semiconductor body, the pair of gate trenches exposing each one of two-dimensional charge carrier gas channels, providing source and drain contacts that are electrically connected to each one of the plurality of two-dimensional charge carrier gas channels, providing a gate structure that is configured to control a conductive connection between the source and drain contacts, wherein providing the gate structure includes forming a layer of doped type III-nitride semiconductor material that covers the gate fin and extends into the gate trenches, and forming a conductive gate electrode on top of the layer of doped type III-nitride semiconductor material.
    Type: Grant
    Filed: December 28, 2021
    Date of Patent: March 12, 2024
    Assignee: Infineon Technologies Austria AG
    Inventors: Thomas Detzel, Gerhard Prechtl, Oliver Haeberlen
  • Patent number: 11908766
    Abstract: The present invention relates to a cooling system where a semiconductor component including a semiconductor chip and a cooling apparatus are joined, wherein a coolant is supplied to a substrate, on which a semiconductor chip is installed, through an opening member of the cooling apparatus so that a surface of the substrate may be directly cooled by the coolant so as to improve cooling efficiency, and a cooling post structure, which enables the coolant to smoothly flow, is used to further improve cooling efficiency.
    Type: Grant
    Filed: September 28, 2021
    Date of Patent: February 20, 2024
    Assignee: JMJ Korea Co., Ltd.
    Inventor: Yun Hwa Choi
  • Patent number: 11901319
    Abstract: A first protective layer is formed on a first die and a second die, and openings are formed within the first protective layer. The first die and the second die are encapsulated such that the encapsulant is thicker than the first die and the second die, and vias are formed within the openings. A redistribution layer can also be formed to extend over the encapsulant, and the first die may be separated from the second die.
    Type: Grant
    Filed: April 19, 2021
    Date of Patent: February 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hui-Min Huang, Chih-Wei Lin, Tsai-Tsung Tsai, Ming-Da Cheng, Chung-Shi Liu, Chen-Hua Yu
  • Patent number: 11892503
    Abstract: A semiconductor device includes first and second chips in a package. A first pad is on the first chip and electrically connected to a node between a power supply pad and a ground pad on the first chip. Second and third pads are on the second chip. An internal wiring connects the first pad to the second pad within the package. A power circuit on the semiconductor chip configured to supply a current to the second pad. A switch is on the second chip between the second pad and the power supply circuit to connect or disconnect the second pad from the power circuit. A control circuit is on the second chip and configured to output a first signal for the switch in response to a test signal supplied to the third pad and a second signal to the power circuit to cause the power circuit to output current.
    Type: Grant
    Filed: August 29, 2022
    Date of Patent: February 6, 2024
    Assignee: Toshiba Tec Kabushiki Kaisha
    Inventors: Takuya Kusaka, Hirosuke Narai, Kazunori Masuda, Makoto Iwai
  • Patent number: 11894333
    Abstract: A semiconductor package includes: a redistribution substrate including a connection via and a redistribution layer electrically connected to each other, and a redistribution pad electrically connected to the redistribution layer by the connection via, a space pattern separating at least some of the redistribution pads from each other, a dummy metal pattern at least partially surrounded by the space pattern, and a degassing opening passing through at least one of the redistribution pad and the dummy metal pattern; a connection bump electrically connected to the redistribution pad; and a semiconductor chip on the redistribution substrate and including a connection pad electrically connected to the redistribution layer, the redistribution pad including a plurality of protrusions protruding from the same plane in directions different from each other and having a corner having a rounded shape, and the dummy metal pattern includes branch patterns each extending in directions different from one another.
    Type: Grant
    Filed: August 13, 2021
    Date of Patent: February 6, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dahee Kim, Jeongrim Seo, Gookmi Song
  • Patent number: 11870130
    Abstract: A semiconductor device includes a semiconductor die comprising a radio frequency (RF) circuit, a first dielectric layer disposed over a first surface of the semiconductor die, an antenna layer disposed over a surface of the first dielectric layer, and an antenna feeding structure coupling the antenna layer to the RF circuit of the semiconductor die, wherein the semiconductor die comprises a via, and the antenna feeding structure comprises a first portion arranged within the opening of the semiconductor die and extending to the first surface of the semiconductor die, and a second portion arranged through the first dielectric layer.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: January 9, 2024
    Assignee: Infineon Technologies AG
    Inventors: Eung San Cho, Ashutosh Baheti, Saverio Trotta
  • Patent number: 11854958
    Abstract: A method includes obtaining an active feature layer having a first surface bearing one or more active feature areas. A first capacitor plate of a first capacitor is formed on an interior surface of a cap. A second capacitor plate of the first capacitor is formed on an exterior surface of the cap. The first capacitor plate of the first capacitor overlays and is spaced apart from the second capacitor plate of the first capacitor along a direction that is orthogonal to the exterior surface of the cap to form the first capacitor. The cap is coupled with the first surface of the active feature layer such that the second capacitor plate of the first capacitor is in electrical communication with at least a first active feature of the active feature layer. The cap is bonded with the passive layer substrate.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: December 26, 2023
    Assignee: General Electric Company
    Inventors: Marco Francesco Aimi, Joseph Alfred Iannotti, Joleyn Eileen Brewer
  • Patent number: 11837523
    Abstract: A transistor package comprising: a substrate; a first transistor in thermal contact with the substrate, wherein the transistor comprises a gate; the substrate sintered to a heat sink through a sintered layer; an encapsulant that at least partially encapsulates the first transistor; and a Kelvin connection to the transistor gate.
    Type: Grant
    Filed: October 14, 2022
    Date of Patent: December 5, 2023
    Assignee: Tesla, Inc.
    Inventors: Wenjun Liu, Robert James Ramm, Alan David Tepe, Colin Kenneth Campbell, Dino Sasaridis
  • Patent number: 11824110
    Abstract: A buffer layer, an etching stop layer, and a channel layer are epitaxially grown in this order on a substrate. The substrate contains InP that has a high resistance by, for example, being doped with Fe. The buffer layer contains a compound semiconductor lattice-matched to InP. The etching stop layer includes InxAl1-xP (0?x?0.75). The channel layer contains InyGa1-y As (0<y?1).
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: November 21, 2023
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventor: Hiroki Sugiyama
  • Patent number: 11824054
    Abstract: A package structure includes an insulating encapsulation, a semiconductor die, and a filter structure. The semiconductor die is encapsulated in the insulating encapsulation. The filter structure is electrically coupled to the semiconductor die, wherein the filter structure includes a patterned metallization layer with a pattern having a double-spiral having aligned centroids thereof.
    Type: Grant
    Filed: March 28, 2022
    Date of Patent: November 21, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sen-Kuei Hsu, Hsin-Yu Pan, Ming-Hsien Tsai
  • Patent number: 11798883
    Abstract: A semiconductor device includes an integrated circuit (IC) and an interlayer dielectric layer on the substrate, a contact through the interlayer dielectric layer and electrically connected to the IC, a wiring layer on the interlayer dielectric layer with a wiring line electrically connected to the contact, a first passivation layer on the wiring layer, first and second pads on the first passivation layer, and a through electrode through the substrate, the interlayer dielectric layer, the wiring layer, and the first passivation layer to connect to the first pad. The first pad includes a first head part on the first passivation layer, and a protruding part that extends into the first passivation layer from the first head part, the protruding part surrounding a lateral surface of the through electrode in the first passivation layer, and the second pad is connected to the IC through the wiring line and the contact.
    Type: Grant
    Filed: November 16, 2021
    Date of Patent: October 24, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Shaofeng Ding, Jeong Hoon Ahn, Yun Ki Choi
  • Patent number: 11791255
    Abstract: A die package and method is disclosed. In one example, the die package includes a die having a first die contact on a first side and a second die contact on a second side opposite the first side, and insulating material laterally adjacent to the die. A metal structure substantially directly contacts the surface of the second die contact, wherein the metal structure is made of the same material as the second die contact. A first pad contact on the first side of the die electrically contacts the first die contact, and a second pad contact on the first side of the die electrically contacts the second die contact via the metal structure. The insulating material electrically insulates the metal structure from the first die contact.
    Type: Grant
    Filed: June 27, 2022
    Date of Patent: October 17, 2023
    Assignee: Infineon Technologies AG
    Inventor: Petteri Palm
  • Patent number: 11749627
    Abstract: A fan-out wafer level package includes a semiconductor die with a redistribution layer on a sidewall of the semiconductor die. A redistribution layer positioned over the die includes an extended portion that extends along the sidewall. The semiconductor die is encapsulated in a molding compound layer. The molding compound layer is positioned between the extended portion of the redistribution layer and the sidewall of the semiconductor die. Solder contacts, for electrically connecting the semiconductor device to an electronic circuit board, are positioned on the redistribution layer. The solder contacts and the sidewall of the redistribution layer can provide electrical contact on two different locations. Accordingly, the package can be used to improve interconnectivity by providing vertical and horizontal connections.
    Type: Grant
    Filed: October 28, 2021
    Date of Patent: September 5, 2023
    Assignee: STMICROELECTRONICS LTD
    Inventors: Endruw Jahja, Cheng-Yang Su
  • Patent number: 11728309
    Abstract: A clip for connecting an electronic component with a carrier in a package is provided. The clip includes a clip body having a component connection portion configured to be connected with the electronic component to be mounted on the carrier, and a carrier connection portion configured to be connected with the carrier. The clip further includes at least one locking recess in a surface portion of the clip body, the surface portion being configured to face the carrier. The at least one locking recess is configured to accommodate material of an encapsulant of the package so as to lock the encapsulant and the clip. A corresponding method of manufacturing the package is also provided.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: August 15, 2023
    Assignee: Infineon Technologies AG
    Inventors: Melvin Levardo, Ryan Ross Agbay Alinea, Markus Dinkel
  • Patent number: 11715701
    Abstract: According to one embodiment, a semiconductor device includes a wiring board that has a first surface and a second surface opposed to the first surface, a semiconductor chip provided on the first surface, external connection terminals provided on the second surface, a sealing resin layer provided on the first surface, and a conductive shield layer that covers at least a portion of a side surface of the wiring board and the sealing resin layer. The wiring board includes a first ground wire that is electrically connected to the conductive shield layer, and a second ground wire that is electrically connected to the conductive shield layer and is electrically insulated from the first ground wire.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: August 1, 2023
    Assignee: Kioxia Corporation
    Inventors: Yuusuke Takano, Yoshiaki Goto, Takeshi Watanabe, Takashi Imoto
  • Patent number: 11715867
    Abstract: The embodiments of the application provides an end cover assembly, a battery cell, a battery module and a device, the end cover assembly is used for the battery cell, the end cover assembly includes an end cover; an electrode terminal disposed on the end cover; an insulating member for insulating the electrode terminal and the end cover and disposed to surround the electrode terminal; wherein the insulating member abuts the electrode terminal, at least one of the insulating member and the electrode terminal is provided with a stress relief groove, the stress relief groove is configured to absorb stress generated by the electrode terminal's abutting the insulating member.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: August 1, 2023
    Assignee: Contemporary Amperex Technology Co., Limited
    Inventors: Ningsheng Wu, Chengyou Xing, Yuanbao Chen, Peng Wang, Quankun Li
  • Patent number: 11710687
    Abstract: A semiconductor guide pin is disclosed. Specific implementations may include a heatsink, one or more substrates coupled together, one or more pressfit pins coupled to the one or more substrates, and two or more guide pins coupled to the one or more substrates, where the two or more guide pins may have a height greater than the one or more pressfit pins.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: July 25, 2023
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Chee Hiong Chew, Yushuang Yao, Atapol Prajuckamol, Chuncao Niu
  • Patent number: 11679680
    Abstract: A power module (10) for operating an electric vehicle drive includes a current input configured for supplying an input current. The current input includes multiple contact elements (182, 184). Multiple circuit-breakers (142, 144) are configured for generating an output current based on the supplied input current. A current output (192) is configured for outputting the output current at a consumer. A substrate (12) includes a metal layer (122-130) and an insulating layer (121) connected to the metal layer (122-130). The multiple circuit-breakers (142, 144) are arranged on the metal layer (122-130). The multiple contact elements (182, 184) are also arranged on the metal layer (122-130) such that the multiple contact elements (182, 184) extend perpendicular to a surface of the substrate (12).
    Type: Grant
    Filed: October 7, 2021
    Date of Patent: June 20, 2023
    Assignee: ZF FRIEDRICHSHAFEN AG
    Inventor: Wei Liu
  • Patent number: 11658131
    Abstract: A semiconductor package includes a first substrate including a circuit pattern and a dummy pattern on an upper face of the first substrate, a solder ball, a second substrate on the first substrate, and an underfill material layer between the first and second substrates. The underfill material layer wraps around the solder ball. The dummy pattern is not electrically connected to the circuit pattern. The first substrate includes a solder resist layer on the circuit pattern and the dummy pattern. The solder resist layer includes a first opening for exposing at least a part of the circuit pattern. The solder ball is in the first opening and electrically insulated from the dummy pattern by the solder resist layer. The second substrate is electrically connected to the first substrate by the solder ball. The second substrate is electrically insulated from the dummy pattern by the solder resist layer.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: May 23, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin-Woo Park, Un-Byoung Kang, Jong Ho Lee
  • Patent number: 11637049
    Abstract: A semiconductor device, including a semiconductor chip having a first electrode on a rear surface thereof, a laminated substrate including a heat dissipation board laminated on a rear surface of an insulating board, and a case. The case includes a frame surrounding an opening penetrating the case from a front surface to a rear surface thereof, the frame being in contact with a periphery of the laminated substrate covering the opening from the rear surface of the case, and a first terminal penetrating the frame. The first terminal includes a first connection part penetrating the frame and extending out of the frame, and a first wiring part provided in the opening. The first wiring part has a wiring rear surface disposed on a front surface of the insulating board, and a wiring front surface mechanically and electrically connected to the first electrode of the semiconductor chip.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: April 25, 2023
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Tomoyuki Wakiyama
  • Patent number: 11631608
    Abstract: Disclosed are support substrates, methods of fabricating semiconductor packages using the same, and methods of fabricating electronic devices using the same. The support substrate comprises a main body, and a plurality of first protrusions finely protruding from an upper surface of the main body. The main body and the first protrusions include the same material and are formed as a unitary structure. The first protrusions are spaced apart from each other in first and second directions intersecting each other, when viewed in plan.
    Type: Grant
    Filed: October 1, 2020
    Date of Patent: April 18, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kunsil Lee, Seung Hwan Lee