With Contact Or Lead Patents (Class 257/690)
  • Patent number: 10763242
    Abstract: A semiconductor package includes a first layer of one or more first semiconductor chips each having a first surface at which one or more first pads are exposed, a second layer of one or more second semiconductor chips disposed over the first layer and each having a second surface at which one or more second pads are exposed, and a first redistribution layer between the first layer and the second layer and electrically connected to the one or more first pads. The first layer may include one or more first TPVs extending through a substrate (panel) of the first layer and electrically connected to the first redistribution layer.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: September 1, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Hoon Son, Jung-Hwan Choi, Seok-Hun Hyun
  • Patent number: 10763182
    Abstract: The invention relates to a power semiconductor device having a pin element which passes through a housing opening, an elastic sealing device which is arranged between a housing opening wall of the housing, where the housing opening wall delimits the housing opening and encircles the pin element. The pin element runs through the sleeve and through a sealing device opening of the sealing element. The sealing device is not connected in a materially bonded manner to the sleeve, to the housing opening wall and to the pin element and the sealing device seals off the housing opening wall from the sleeve and seals off the sleeve from the pin element. A crosslinked potting compound is arranged on the sealing device. The crosslinked potting compound is connected in a materially bonded manner to the sleeve, to the housing opening wall and to the pin element and the potting compound seals off the housing opening wall from the sleeve and seals off the sleeve from the pin element.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: September 1, 2020
    Assignee: SEMIKRON ELECTRONIK GMBH & CO. KG
    Inventors: Thomas Hunka, Stefan Weiss, Rainer Popp
  • Patent number: 10756019
    Abstract: A die-to-die interconnect structure includes an interconnect network including a plurality of metal interconnect layers. The interconnect network is configured to electrically couple a first die and a second die mounted on a top surface of the die-to-die interconnect structure. A first metal interconnect layer of the plurality of metal interconnect layers includes a plurality of ground lines and a plurality of signal lines distributed across the first metal interconnect layer according to a GSSG pattern. In some examples, adjacent signal lines within the first metal interconnect layer are separated by a dielectric region. In some embodiments, a second metal interconnect layer of the plurality of metal interconnect layers is disposed above the first metal interconnect layer and includes a plurality of configurable signal/ground lines. By way of example, each of the plurality of configurable signal/ground lines is disposed over the dielectric region and within the second metal interconnect layer.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: August 25, 2020
    Assignee: Xilinx, Inc.
    Inventors: Shuxian Wu, Xiaobao Wang, Xuemei Xi
  • Patent number: 10748826
    Abstract: The power module includes: a first metallic pattern; a plurality of power devices bonded on the first metallic pattern, each of the plurality of the power devices has a thickness thinner than a thickness of the metallic pattern; a frame member disposed so as to collectively enclose a predetermined number of the power devices on the first metallic pattern; a second metallic pattern disposed outside the frame member; and a resin layer configured to seal the plurality of the power devices and the first and second metallic patterns so as to include the frame member, wherein the frame member suppresses a stress according to a difference between a coefficient of thermal expansion of the metallic pattern and a coefficient of thermal expansion of the power devices. There is provided the power module easy to be fabricated, capable of suppressing the degradation of the bonded portion and improving reliability.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: August 18, 2020
    Assignee: ROHM CO., LTD.
    Inventor: Seita Iwahashi
  • Patent number: 10745818
    Abstract: This disclosure provides a package substrate fabrication method including: providing a carrier; forming a first dielectric layer on the carrier while enabling the first dielectric layer to be patterned including an opening; forming a first conducting unit on the carrier while enabling the first conducting unit to fill up the opening, a height of the first conducting unit at the opening larger than a thickness of the first dielectric layer, and a width of the first conducting unit larger than a width of the opening; forming a second dielectric layer on the first conducting unit; forming a second conducting unit on the second dielectric layer; forming a third dielectric layer on the second conducting unit; removing the carrier and the first dielectric layer while enabling the part of the first conducting unit in the opening to be removed; and forming a fourth dielectric layer to cover the first conducting unit.
    Type: Grant
    Filed: December 8, 2016
    Date of Patent: August 18, 2020
    Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.
    Inventors: Chun-Hsien Yu, Shih-Ping Hsu, Pao-Hung Chou
  • Patent number: 10741439
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to merged mandrel lines and methods of manufacture. The structure includes: at least one metal line having a first dimension in a self-aligned double patterning (SADP) line array; and at least one metal line having a second dimension inserted into the SADP line array, the second dimension being different than the first dimension.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: August 11, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hsueh-Chung Chen, Martin J. O'Toole, Terry A. Spooner, Jason E. Stephens
  • Patent number: 10734355
    Abstract: An electronic circuit board includes: electronic components; a silicon board that is plate shaped, includes a wiring pattern provided on at least one of a surface and a reverse surface thereof, and includes recessed portions where the electronic components are individually mounted; and a supporting board that is layered over the reverse surface of the silicon board, and includes a wiring pattern provided on at least one of a surface and a reverse surface thereof. Side faces of the recessed portions are perpendicular to the surface of the silicon board, the wiring pattern is connected to at least one of the electronic components mounted in the recessed portions, via at least one of a via and a bottom surface electrode provided in of the at least one of the recessed portions, and the recessed portions penetrate through the silicon board.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: August 4, 2020
    Assignee: OLYMPUS CORPORATION
    Inventor: Takuro Suyama
  • Patent number: 10727213
    Abstract: Gates of semiconductor switching elements are connected to a gate control wiring pattern. The gate control wiring pattern is further connected to a gate control terminal and a filter terminal which are connected by an element for forming a filter outside a housing. The filter terminal and the gate control terminal are connected to the gate control wiring pattern in such a manner that a section electrically connecting the filter terminal and the gate control terminal overlaps with at least a part of a section electrically connecting the gates of the semiconductor switching elements on the gate control wiring pattern.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: July 28, 2020
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Junichi Nakashima, Yoshiko Tamada, Yasushi Nakayama
  • Patent number: 10714402
    Abstract: This semiconductor chip package has opposed first surface and second surface, and includes a semiconductor chip having a circuit part and an electrode for supplying a voltage to the circuit part, a resin layer formed in a periphery of the semiconductor chip, a substrate that is disposed to face the first surface of the semiconductor chip and the resin layer, and a plurality of external terminals that are provided on the second surface of the semiconductor chip, each of the plurality of external terminals being electrically coupled to any of the plurality of electrodes.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: July 14, 2020
    Assignee: SONY CORPORATION
    Inventors: Hiroyuki Shigeta, Yuuji Nishitani
  • Patent number: 10712497
    Abstract: Photonic integrated circuit packages having improved integration, and methods of manufacturing such photonic integrated circuit packages, are provided. As an example, a photonic integrated circuit package may include a substrate, a first insulating layer on the substrate, a photonic core layer on the first insulating layer, and a second insulating layer on the photonic core layer. A photonic coupling device may be in the photonic core layer, and may be, as examples, at least one of a grating coupler or a photodetector. A concave mirror may extend into at least the second insulating layer. In some embodiments, the concave mirror may extend through the second insulating layer and into the first insulating layer.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: July 14, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho Chul Ji, Kwan Sik Cho, Keun Yeong Cho
  • Patent number: 10716202
    Abstract: The subject disclosure relates generally to a method of implementing magnetic shielding walls with specific respective dimensions to reduce crosstalk between transmission lines in wire-bonds for supercomputing chipsets. In one embodiment, the device comprises: a chip-set comprised of superconducting materials; at least one superconducting data line attached to chip-set dies by a set of wire bonds; and magnetic shielding walls that respectively isolate the set of wire bonds.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: July 14, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Salvatore Bernardo Olivadese
  • Patent number: 10692795
    Abstract: In an embodiment, a quantum device includes an interposer layer comprising a set of vias. In an embodiment, the quantum device includes a dielectric layer formed on a first side of the interposer, the dielectric layer including a set of transmission lines communicatively coupled to the set of vias. In an embodiment, the quantum device includes a plurality of qubit chips coupled to an opposite side of the interposer layer, each qubit chip of the plurality of qubit chips including: a plurality of qubits on a first side of the qubit chip and a plurality of protrusions on a second side of the qubit chip. In an embodiment, the quantum device includes a heat sink thermally coupled with the plurality of qubit chips, the heat sink comprising a plurality of recesses aligned with the plurality of protrusions of the plurality of qubit chips.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: June 23, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jae-Woong Nah, Hanhee Paik, Jerry M. Chow
  • Patent number: 10692842
    Abstract: A microelectronic assembly (300) or system (1500) includes at least one microelectronic package (100) having a microelectronic element (130) mounted face up above a first surface (108) of a substrate (102), one or more columns (138, 140) of contacts (132) extending in a first direction (142) along the microelectronic element front face. Columns (104A, 105B, 107A, 107B) of terminals (105 107) exposed at a second surface (110) of the substrate extend in the first direction. First terminals (105) exposed at surface (110) in a central region (112) thereof having width (152) not more than three and one-half times a minimum pitch (150) of the columns of terminals can be configured to carry address information usable to determine an addressable memory location. An axial plane of the microelectronic element can intersect the central region.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: June 23, 2020
    Assignee: Invensas Corporation
    Inventors: Richard Dewitt Crisp, Wael Zohni, Belgacem Haba, Frank Lambrecht
  • Patent number: 10685850
    Abstract: Generally discussed herein are systems, devices, and methods that include an organic high density interconnect structure and techniques for making the same. According to an example a method can include forming one or more low density buildup layers on a core, conductive interconnect material of the one or more low density buildup layers electrically and mechanically connected to conductive interconnect material of the core, forming one or more high density buildup layers on an exposed low density buildup layer of the one or more low density buildup layers, conductive interconnect material of the high density buildup layers electrically and mechanically connected to the conductive interconnect material of the one or more low density buildup layers, and forming another low density buildup layer on and around an exposed high density buildup layer of the one or more high density buildup layers.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: June 16, 2020
    Assignee: Intel Corporation
    Inventors: Sri Chaitra Jyotsna Chavali, Siddharth K. Alur, Lilia May, Amanda E. Schuckman
  • Patent number: 10679953
    Abstract: Semiconductor devices and methods of forming are provided. A molding compound extends along sidewalls of a first die and a second die. A redistribution layer is formed over the first die, the second die, and the molding compound. The redistribution layer includes a conductor overlying a gap between the first die and the second die. The conductor is routed at a first angle over an edge of the first die. The first angle is measured with respect to a straight line that extends along a shortest between the first die and the second die, and the first angle is greater than 0.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: June 9, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, An-Jhih Su, Tsung-Shu Lin
  • Patent number: 10660207
    Abstract: A circuit module includes a substrate on which a first electrode and a second electrode are provided, a first electronic component, and a first resin layer. The first electrode includes a first electrode base body and a first plating film. The second electrode and the first electronic component are covered with the first resin layer. The second electrode includes a second electrode base body, a metal column, whose one end is directly connected to the second electrode base body and another end is positioned in an inner side relative to an outer surface of the first resin layer, a second plating film with a cylindrical shape covering a side surface of a connection body of the second electrode base body and the metal column, and a covering portion connected to the other end of the metal column.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: May 19, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Takafumi Kusuyama
  • Patent number: 10651052
    Abstract: A semiconductor package structure includes a first insulating layer, a first conductive layer, a multi-layered circuit structure, a protection layer, and a semiconductor chip electrically connected to the multi-layered circuit structure. The first insulating layer defines a first through hole extending through the first insulating layer. The first conductive layer includes a conductive pad disposed in the first through hole and a trace disposed on an upper surface of the first insulating layer. The multi-layered circuit structure is disposed on an upper surface of the first conductive layer. The multi-layered circuit structure includes a bonding region disposed on the conductive pad of the first conductive layer and an extending region disposed on the trace of the first conductive layer. The protection layer covers the upper surface of the first insulating layer and the extending region of the multi-layered circuit structure, and exposes the bonding region of the multi-layered circuit structure.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: May 12, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wen Hung Huang, Yan Wen Chung
  • Patent number: 10652998
    Abstract: An electronic package can include modulated mesh planes for reducing crosstalk between adjacent signal wires within the electronic package. Modulated mesh planes above and below a wiring plane can include sets of adjacent wires arranged in an orientation parallel to signal wires within the wiring plane, and sets of adjacent wires arranged in an orientation perpendicular to the signal wires. The sets of wires in each of the mesh planes are each electrically interconnected and insulated by a dielectric layer from the signal wires. The electronic package also includes a region of the mesh planes having the adjacent wires that are arranged in an orientation perpendicular to the signal wires separated by a first distance, and another region of the mesh planes having adjacent wires perpendicular to the signal wires separated by a distance greater than the first distance.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: May 12, 2020
    Assignee: International Business Machines Corporation
    Inventors: Jinwoo Choi, Daniel M. Dreps, Yanyan Zhang
  • Patent number: 10629520
    Abstract: A semiconductor device provided according to an aspect of the present disclosure includes a semiconductor element, a bonding target, a first wire, a wire strip and a second wire. The bonding target is electrically connected to the semiconductor element. The first wire is made of a first metal. The first wire includes a first bonding portion bonded to the bonding target and a first line portion extending from the first bonding portion. The wire strip is made of the first metal. The wire strip is bonded to the bonding target. The second wire is made of a second metal different from the first metal. The second wire includes a second bonding portion bonded to the bonding target via the wire strip and a second line portion extending from the second bonding portion.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: April 21, 2020
    Assignee: ROHM CO., LTD.
    Inventor: Motoharu Haga
  • Patent number: 10599967
    Abstract: An RFID label with protection of the RFID function includes an RFID transponder chip and a carrier substrate, on which the RFID transponder chip is disposed. Furthermore, at least one structure element in vertical projection is disposed laterally offset from the RFID transponder chip. The at least one structure element acts as a spacer and, in case of an external mechanical stress, prevents a direct force action on the transponder chip and a junction to an attached antenna structure.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: March 24, 2020
    Assignee: Schreiner Group GmbH & Co. KG
    Inventors: Maximilian Jaeger, Sabine Krueger, Christian Kuczera, Dirk Probian, Arne Rehm, Gerhard Ross
  • Patent number: 10593633
    Abstract: It is an object of the present invention to provide a semiconductor module which suppresses a break in a current path and occurrence of arc discharge when a semiconductor chip is short-circuited. A semiconductor module 100 according to the present invention includes at least one semiconductor chip 2, a housing 5 in which the semiconductor chip 2 is stored, and at least one pressurizing member which is placed between an upper electrode 2a of the semiconductor chip 2 and an upper-side electrode 3 provided in the housing 5 and electrically connects the upper electrode 2a and the upper-side electrode 3, the pressurizing member 10 is elastic, and the pressurizing member 10 includes a conductive block 12 and a plate spring member 11 including current paths 11a and 11b which are opposed to each other with at least a part of the conductive block 12 located between the current paths 11a and 11b.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: March 17, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Shigeto Fujita, Tetsuya Matsuda
  • Patent number: 10580731
    Abstract: A combined electrode comprises a negative electrode, a first intermediate electrode, a positive electrode and a second intermediate electrode, wherein a main body portion of the negative electrode and a main body portion of the first intermediate electrode, a connection portion of the negative electrode and a connection portion of the first intermediate electrode, main body portions of the positive electrode and main body portions of the second intermediate electrode, and a connection portion of the positive electrode and a connection portion of the second intermediate electrode are arranged in parallel to and directly facing each other, thereby increasing a facing area between the negative electrode and the first intermediate electrode and between the positive electrode and the second intermediate electrode, reducing a current loop area between the negative electrode and the first intermediate electrode and between the positive electrode and the second intermediate electrode.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: March 3, 2020
    Assignee: YANGZHOU GUOYANG ELECTRONIC CO., LTD.
    Inventors: Wenhui Xu, Yulin Wang, Hesong Teng
  • Patent number: 10573630
    Abstract: A three-dimensional integrated circuit includes a first die having a first geometry. The first die includes a first region that operates with a first power density and a second region that operates with a second power density. The first power density is less than the second power density. The first die includes first electrical contacts disposed in the first region on a first side of the first die along a periphery of the first die. The three-dimensional integrated circuit includes a second die having a second geometry. The second die includes second electrical contacts disposed on a first side of the second die. A stacked portion of the second die is stacked within the periphery of the first die and an overhang portion of the second die extends beyond the periphery of the first die. The second electrical contacts are aligned with and coupled to the first electrical contacts.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: February 25, 2020
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Brett P. Wilkerson, Milind Bhagavat, Rahul Agarwal, Dmitri Yudanov
  • Patent number: 10573619
    Abstract: A printed wiring board according to an embodiment includes a metal plate and a wiring member. The meal plate includes a current path part, which is a main current path of an electronic part mounted on or above a front surface of the metal plate, and a heat radiation part, which radiates heat generated from the electronic part. The wiring member is arranged on or above a back surface of the metal plate. The current path part and the heat radiation part are in the same layer to be integrally formed with the wiring member.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: February 25, 2020
    Assignees: FUJITSU TEN LIMITED, FUJITSU LIMITED
    Inventors: Takashi Akaguma, Takafumi Yasuhara, Naohito Motooka, Satoru Hasegawa, Satoshi Yamagishi, Shinya Muroga, Kazumasa Yasuta
  • Patent number: 10555420
    Abstract: A method of manufacturing a circuit board includes: a single-sided copper-clad base is provided; a plurality of grooves are defined in the base facing away from the copper-clad side for receiving electronic elements, a depth of each of the grooves is equal to a thickness of the corresponding electronic element; the electronic elements are fixed into their respective grooves; a plurality of holes are defined in the laminating member to expose the electrodes of the electronic elements; an electroplated layer is formed on the surface of the embedded body, the electroplated layer is electrically connected with the electrodes of the electronic elements. A circuit board made by the method is also provided.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: February 4, 2020
    Assignees: HongQiSheng Precision Electronics (QinHuangDao) Co., Ltd., Avary Holding (Shenzhen) Co., Limited.
    Inventors: Han-Pei Huang, Yong-Quan Yang
  • Patent number: 10546837
    Abstract: A semiconductor device package is provided. The semiconductor device package includes a stack of semiconductor dies over a substrate, the substrate including a plurality of electrical contacts, and an annular lower lid disposed over the substrate and surrounding the stack of semiconductor dies. The annular lower lid includes a lower surface coupled to the substrate, an upper surface coupled to an upper lid, and an outer surface in which is formed an opening. The semiconductor device assembly further includes a circuit element disposed in the opening and electrically coupled to at least a first one of the plurality of electrical contacts. The semiconductor device assembly further includes the upper lid disposed over the annular lower lid and the stack of semiconductor dies.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: January 28, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Thomas H. Kinsley
  • Patent number: 10535635
    Abstract: An integrated circuit includes a first semiconductor wafer, a second semiconductor wafer, a first interconnect structure, an inductor, a second interconnect structure and a through substrate via. The first semiconductor wafer has a first device in a front side of the first semiconductor wafer. The second semiconductor wafer is bonded to the first semiconductor wafer. The first interconnect structure is below a backside of the first semiconductor wafer. The inductor is below the first semiconductor wafer, and at least a portion of the inductor is within the first interconnect structure. The second interconnect structure is on the front side of the first semiconductor wafer. The through substrate via extends through the first semiconductor wafer. The inductor is coupled to at least the first device by the second interconnect structure and the through substrate via.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: January 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Lin Chen, Chin-Chou Liu, Fong-Yuan Chang, Hui-Yu Lee, Po-Hsiang Huang
  • Patent number: 10535537
    Abstract: Packaged semiconductor devices and methods of packaging semiconductor devices are disclosed. In some embodiments, a packaged semiconductor device includes an integrated circuit die and a first interconnect structure coupled to the integrated circuit die. Through-vias are also coupled to the first interconnect structure. A molding material is disposed around the integrated circuit die and the through-vias over the first interconnect structure. The molding material has a pit disposed therein. A recovery material is disposed within the pit in the molding material. A second interconnect structure is disposed over the molding material, the recovery material, the integrated circuit die, and the through-vias.
    Type: Grant
    Filed: October 6, 2017
    Date of Patent: January 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Hsien-Wei Chen
  • Patent number: 10529668
    Abstract: Forming a groove in a dicing region so as to expose a conductive pattern material on a side surface, closer to a first side of each of mounting regions, of a substrate; when forming a first sealing portion enclosing a wireless region and a second sealing portion enclosing an antenna region adjacent to the wireless region on a side of a second side of each of the mounting regions, reducing a thickness in a height direction such that a thickness of the second sealing portion becomes smaller in thickness than a thickness of the first sealing portion; forming a shielding film such that a scattered matter made of a conductive material is allowed to pass through an upper surface of the second sealing portion, to be deposited onto the conductive pattern material exposed on a side surface of the substrate; and separating the substrate into the mounting regions individually.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: January 7, 2020
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Kenzo Kitazaki, Takehiko Kai, Masaya Shimamura, Mikio Aoki, Jin Mikata, Taiji Ito
  • Patent number: 10522435
    Abstract: On a conductive plate of an insulated substrate, one open end of a main body part of a cylindrical contact member is bonded by solder. In a hollow part of a hollow cylinder shaped external electrode terminal, a part of the other open end side of the main body part of the cylindrical contact member is inserted from an open end of the external electrode terminal. The other end of the external electrode terminal is separated into branches by cuts inserted in a through-hole insertion part. A column surface of the outside of the branches of the external electrode terminal has an arc shape. Pressure in a direction from inside the external electrode terminal toward the outside is applied to the branches of the through-hole insertion part by an auxiliary wedge. With such a configuration, assembly defects accompanying connection of the external electrode terminal and other members may be eliminated.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: December 31, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Kazuya Adachi
  • Patent number: 10522615
    Abstract: A semiconductor package with an embedded capacitor and corresponding manufacturing methods are described. The semiconductor package with the embedded capacitor includes a semiconductor die having a first metal layer extending across at least a portion of a first side of the semiconductor die and a package structure formed on the first side of the semiconductor die. A first electrical conductor of the embedded capacitor is formed in the first metal layer of the semiconductor die. The package structure includes a second metal layer that has formed therein a second electrical conductor of the embedded capacitor. A dielectric of the embedded capacitor is positioned within either the semiconductor die or the package structure of the semiconductor package to isolate the first electrical conductor from the second electrical conductor of the embedded capacitor.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: December 31, 2019
    Assignee: NXP USA, INC.
    Inventors: Sergio A. Ajuria, Phuc M. Nguyen, Douglas M. Reber
  • Patent number: 10522476
    Abstract: A package structure including an integrated fan-out package and plurality of conductive terminals is provided. The integrated fan-out package includes an integrated circuit component, a plurality of conductive through vias, an insulating encapsulation having a first surface and a second surface opposite to the first surface, and a redistribution circuit structure. The insulating encapsulation laterally encapsulates the conductive through vias and the integrated circuit component. Each of conductive through vias includes a protruding portion accessibly revealed by the insulating encapsulation. The redistribution circuit structure is electrically connected to the integrated circuit component and covers the first surface of the insulating encapsulation and the integrated circuit component.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: December 31, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Li-Hui Cheng, Jing-Cheng Lin, Po-Hao Tsai
  • Patent number: 10522458
    Abstract: A method of tuning inductive and/or capacitive components within an integrated circuit device. The method comprises measuring bare-die mounted performance of such a component formed within a semiconductor die, determining a package distribution layer pattern for the at least one component for achieving a desired performance for the at least one component based at least partly on the measured bare-die mounted performance, and packaging the semiconductor die with the determined package distribution layer pattern for the at least one component.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: December 31, 2019
    Assignee: NXP USA, Inc.
    Inventors: Yi Yin, Ziqiang Tong
  • Patent number: 10510690
    Abstract: A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and a conductive pad formed on the substrate. The semiconductor device structure includes a protection layer formed over the conductive pad and a post-passivation interconnect (PPI) structure formed at least in the protection layer. The PPI structure is electrically connected to the conductive pad. The semiconductor device structure also includes a first moisture-resistant layer formed over the protection layer, and the protection layer and the first moisture-resistant layer are made of different materials. The semiconductor device structure further includes an under bump metallurgy (UBM) layer formed over the first moisture-resistant layer and connected to the PPI structure.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shin-Puu Jeng, Hsien-Wen Liu
  • Patent number: 10510683
    Abstract: The present disclosure proposes a packaging structure for a metallic bonding based opto-electronic device and a manufacturing method thereof. According to the embodiments, the packaging structure for an opto-electronic device may comprise an opto-electronic chip and a packaging base. The opto-electronic chip comprises: a substrate having a first substrate surface and a second substrate surface opposite to each other; an opto-electronic device formed on the substrate; and electrodes for the opto-electronic device which are formed on the first substrate surface. The packaging base has a first base surface and a second base surface opposite to each other, and comprises conductive channels extending from the first base surface to the second base surface.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: December 17, 2019
    Assignees: Tsinghua University, NUCTECH COMPANY LIMITED
    Inventors: Wenjian Zhang, Qingjun Zhang, Yuanjing Li, Zhiqiang Chen, Ziran Zhao, Yinong Liu, Yaohong Liu, Xiang Zou, Huishao He, Shuwei Li, Nan Bai
  • Patent number: 10510633
    Abstract: Generally, the present disclosure provides example embodiments relating to a package that may be attached to a printed circuit board (PCB). In an embodiment, a structure includes a package. The package includes one or more dies and metal pads on an exterior surface of the package. At least some of the metal pads are first solder ball pads. The structure further includes pins, and each of the pins is attached to a respective one of the metal pads.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Pei-Haw Tsao, Tsung-Hsing Lu, Li-Huan Chu
  • Patent number: 10506702
    Abstract: Provided is a mounting structure that can bond a first heat dissipation element to a second substrate through a hole in a first substrate without using a binder such as solder, an adhesive, or the like. A mounting structure of the present disclosure includes a first substrate (10) in which a penetrating hole (11) is formed, a second substrate (20) and a first heat dissipation element (30) overlapped with both surfaces of the first substrate (10), respectively, so as to cover the penetrating hole (11), and a second heat dissipation element (40) sandwiched and attached between the second substrate (20) and the first heat dissipation element (30) inside the penetrating hole (11).
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: December 10, 2019
    Assignee: NEC CORPORATION
    Inventor: Makoto Hayakawa
  • Patent number: 10483234
    Abstract: Chip packages and method of manufacturing the same are disclosed. In an embodiment, a chip package may include: a redistribution layer (RDL); a first chip including a plurality of first contact pads, the plurality of first contact pads facing the RDL; a second chip disposed between the first chip and the redistribution layer (RDL) wherein a portion of the first chip is disposed outside a lateral extent of the second chip; and a conductive via laterally separated from the second chip, the conductive via extending between the RDL and a first contact pad of the plurality of first contact pads, the first contact pad located in the portion of the first chip disposed outside the lateral extent of the second chip.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: November 19, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Wei Wu, Jing-Cheng Lin, Szu-Wei Lu, Ying-Ching Shih
  • Patent number: 10475767
    Abstract: According to one embodiment, the interconnect layer includes a fourth conductive member and a fifth conductive member. The fourth conductive member is provided between the first region of the first chip and the third region of the second chip. The fourth conductive member connects the first conductive member of the first chip and the second conductive member of the second chip. The fifth conductive member is provided between the second region of the first chip and the fifth region of the third chip. The fifth conductive member connects the first conductive member of the first chip and the third conductive member of the third chip. The first chip is provided between the first terminal and the second terminal.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: November 12, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoichiro Kurita
  • Patent number: 10468378
    Abstract: The present disclosure provides a method for preparing a semiconductor package having a standard size from a die having a size smaller than the standard size. The method includes: providing a wafer; forming a die on the wafer, wherein the die has a size smaller than one-half of a standard size 0201; dicing the die from the wafer; encapsulating the die to form an encapsulated die; and singulating the encapsulated die to form a semiconductor package having a size equal to or larger than the standard size 0201.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: November 5, 2019
    Assignee: INPAQ TECHNOLOGY CO., LTD.
    Inventors: Yu-Ming Peng, Chu-Chun Hsu, Hung-Shung Ko, Hsiu-Lun Yeh
  • Patent number: 10453784
    Abstract: A semiconductor device has a first semiconductor die with a base material. A covering layer is formed over a surface of the base material. The covering layer can be made of an insulating material or metal. A trench is formed in the surface of the base material. The covering layer extends into the trench to provide the cantilevered protrusion of the covering layer. A portion of the base material is removed by plasma etching to form a cantilevered protrusion extending beyond an edge of the base material. The cantilevered protrusion can be formed by removing the base material to the covering layer, or the cantilevered protrusion can be formed within the base material under the covering layer. A second semiconductor die is disposed partially under the cantilevered protrusion. An interconnect structure is formed between the cantilevered protrusion and second semiconductor die.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: October 22, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Francis J. Carney, Michael J. Seddon
  • Patent number: 10438907
    Abstract: The present invention discloses a wireless package with a resilient connector for connecting a substrate to an antenna. The antenna is disposed directly on a top surface of a molding compound of the wireless package. The resilient connector has a lower terminal bonded to the substrate, a horizontal contact portion, and an oblique support portion integrally extending between the horizontal contact portion and the lower terminal. The horizontal contact portion has a flat top surface that is coplanar with the top surface of the molding compound and is in direct contact with the antenna such that the contact resistance distribution is concentrated and the production yield of the wireless package is improved.
    Type: Grant
    Filed: December 11, 2016
    Date of Patent: October 8, 2019
    Assignee: CYNTEC CO., LTD.
    Inventors: Chun-Fu Hu, Chih-Yu Hu, Shu-Wei Chang
  • Patent number: 10418295
    Abstract: A power module includes an insulated circuit board, a semiconductor element, a first buffer plate, and first and second joining materials. The semiconductor element is disposed on a side of one main surface of the insulated circuit board. The first buffer plate is disposed between the insulated circuit board and the semiconductor element. The first joining material is divided into a plurality of portions in a plan view. The first buffer plate is higher in coefficient of linear expansion than the semiconductor element and lower in coefficient of linear expansion than the insulated circuit board. The first buffer plate is lower in Young's modulus than the semiconductor element.
    Type: Grant
    Filed: November 4, 2016
    Date of Patent: September 17, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yoshinori Yokoyama, Shinnosuke Soda, Narihito Ota, Kazuyasu Nishikawa, Akihisa Fukumoto
  • Patent number: 10403602
    Abstract: A semiconductive device stack, includes a baseband processor die with an active surface and a backside surface, and a recess in the backside surface. A recess-seated device is disposed in the recess, and a through-silicon via in the baseband processor die couples the baseband processor die at the active surface to the recess-seated die at the recess. A processor die is disposed on the baseband processor die backside surface, and a memory die is disposed on the processor die. The several dice are coupled by through-silicon via groups.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: September 3, 2019
    Assignee: Intel IP Corporation
    Inventors: Bernd Waidhas, Georg Seidemann, Andreas Augustin, Laurent Millou, Andreas Wolter, Reinhard Mahnkopf, Stephan Stoeckl, Thomas Wagner
  • Patent number: 10388614
    Abstract: The present disclosure relates to a fan-out semiconductor package including a frame having a through hole, a semiconductor chip disposed in the through hole, a first encapsulant disposed in a space between the frame and the semiconductor chip, a second encapsulant disposed on one sides of the frame and the semiconductor chip, and a redistribution layer disposed on the other sides of the frame and the semiconductor chip, and a method of manufacturing the same. The first encapsulant and the second encapsulant may include different materials.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: August 20, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ji Hyun Lee, Kyoung Moo Harr, Seung Yeop Kook, Ji Hoon Kim, Young Gwan Ko
  • Patent number: 10381268
    Abstract: A fan-out wafer level chip package structure and the manufacturing method thereof are provided. The method includes the steps of providing a supporting plate having a removable tape formed on the supporting plate, placing a plurality of chips on the removable tape, applying an adhesive layer on a back surface of each of the chips, providing a conductive cover for covering all chips and isolating the chips from each other by a plurality of partitions, injecting a molding compound into an inside of the conductive cover and curing the molding compound for forming an encapsulation, separating the encapsulation from the supporting plate, forming a connection layer on an active surface of each of the chips to establish electrical connections, and performing a cutting process to divide the encapsulation into a plurality of the package structures.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: August 13, 2019
    Assignees: NIKO SEMICONDUCTOR CO., LTD., SUPER GROUP SEMICONDUCTOR CO., LTD.
    Inventors: Chih-Cheng Hsieh, Hsiu-Wen Hsu
  • Patent number: 10381283
    Abstract: The present invention discloses a power semiconductor module, comprising: a substrate; a semiconductor provided on a top side of the substrate; and a package formed on the semiconductor and the substrate, wherein the package has openings at a top side thereof, through which terminal contacts of the semiconductor and the substrate are exposed outside and accessible from outside.
    Type: Grant
    Filed: July 4, 2016
    Date of Patent: August 13, 2019
    Assignee: DANFOSS SILICON POWER GMBH
    Inventors: Frank Osterwald, Ronald Eisele, Holger Ulrich
  • Patent number: 10381309
    Abstract: A package structure includes a first redistribution layer, a second redistribution layer, at least one semiconductor chip, an insulating encapsulation, a protection layer, and at least one connecting module. The at least one semiconductor chip is located between and electrically connected to the first redistribution layer and the second redistribution layer. The insulating encapsulation encapsulates the at least one semiconductor chip. The protection layer is disposed on and partially covers the first redistribution layer, wherein the first redistribution layer is located between the at least one semiconductor chip and the protection layer.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: August 13, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chuei-Tang Wang, Chung-Hao Tsai, Chen-Hua Yu, Chun-Lin Lu, Chao-Wen Shih, Han-Ping Pu, Kai-Chiang Wu, Albert Wan
  • Patent number: 10366959
    Abstract: Semiconductor devices and methods of forming are provided. A molding compound extends along sidewalls of a first die and a second die. A redistribution layer is formed over the first die, the second die, and the molding compound. The redistribution layer includes a conductor overlying a gap between the first die and the second die. The conductor is routed at a first angle over an edge of the first die. The first angle is measured with respect to a straight line that extends along a shortest between the first die and the second die, and the first angle is greater than 0.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: July 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, An-Jhih Su, Tsung-Shu Lin
  • Patent number: 10340198
    Abstract: The invention provides a semiconductor package and a method for fabricating the same. The semiconductor package includes a redistribution layer (RDL) structure, a semiconductor die, a molding compound and a supporter. The RDL structure has a first surface and a second surface opposite to the first surface. The semiconductor die is disposed on the first surface of the RDL structure and electrically coupled to the RDL structure. The molding compound is positioned overlying the semiconductor die and the first surface of the RDL structure. The supporter is positioned beside the semiconductor die and in contact with the first surface of the RDL structure.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: July 2, 2019
    Assignee: MEDIATEK INC.
    Inventors: Ta-Jen Yu, Wen-Sung Hsu