With Discrete Components Patents (Class 257/724)
  • Patent number: 10386590
    Abstract: One example of a multi-chip module includes a substrate, a semiconductor chip, and an optical transceiver. The substrate has a first side and a second side opposite the first side. The semiconductor chip is electrically coupled to the first side of the substrate. The optical transceiver is electrically coupled to the second side of the substrate.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: August 20, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Kevin Leigh, George Megason, John Norton
  • Patent number: 10347567
    Abstract: In a resin sealing type semiconductor device, a semiconductor chip CP2 is mounted over a die pad DP having conductivity via a bonding member BD2 having insulation property, and a semiconductor chip CP1 is mounted over the die pad DP via a bonding member BD1 having conductivity. A first length of a portion, in a first side formed by an intersection of a first side surface and a second side surface of the semiconductor chip CP2, covered with the bonding member BD2 is larger than a second length of a portion, in a second side formed by an intersection of a third side surface and a fourth side surface of the semiconductor chip CP1, covered with the bonding member BD1.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: July 9, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Atsushi Nishikizawa, Yuichi Yato, Hiroi Oka, Tadatoshi Danno, Hiroyuki Nakamura
  • Patent number: 10325865
    Abstract: A semiconductor structure includes a die, a molding surrounding the die, an interconnect structure disposed over the die and the molding, and a first seal ring. The interconnect structure includes a dielectric layer and a conductive member disposed within the dielectric layer. The first seal ring is disposed within the dielectric layer and disposed over the molding.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: June 18, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ying-Ju Chen, Hsien-Wei Chen, Ming-Fa Chen
  • Patent number: 10314203
    Abstract: The disclosed apparatus may include a fluid-cooled plate that may be thermally coupled to a first electronic component for cooling the first electronic component by way of a cooling fluid, and a gas-cooled plate physically coupled to the fluid-cooled plate. The gas-cooled plate may be thermally coupled to a second electronic component for cooling the second electronic component by way of a gas. The gas-cooled plate may be separated from the fluid-cooled plate by a gap. Various other apparatuses, systems, and methods are also disclosed.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: June 4, 2019
    Assignee: Juniper Networks, Inc
    Inventor: Alexander I. Yatskov
  • Patent number: 10306761
    Abstract: Provided is a printed wiring board including: a plurality of inner layers including a ground layer and a power supply layer; and a plurality of ground vias and a plurality of power supply vias each provided to penetrate at least the ground layer and the power supply layer in a thickness direction of the printed wiring board, a ground potential being applied to the plurality of ground vias at the ground layer, and a power supply potential being applied to the plurality of power supply vias at the power supply layer. In a top view from a direction perpendicular to the printed wiring board, a distance between vias to which the same potential is applied is shorter than a distance between vias to which different potentials are applied.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: May 28, 2019
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Takashi Numagi, Youhei Tazawa, Shoji Matsumoto
  • Patent number: 10290602
    Abstract: Inexpensive production is achieved while avoiding the degradation of electrical performance caused by the lowering of heat dissipation. The base plate 11 used here has a linear expansion coefficient of 2 to 10 ppm/K, which differs from the linear expansion coefficient of the semiconductor chip 13 by an absolute value of 7 ppm/K or smaller. The bonding layer 12 is formed such that the thickness b thereof is 50 micrometers or smaller, which is thinner than the thickness c of the semiconductor chip 13. Since the thickness b of the bonding layer 12 is thinner than the thickness c of the semiconductor chip 13, the bonding layer 12 upon the heating of the semiconductor chip 13 exhibits thermal expansion that is of relatively small significance, and thus follows the expansion and contraction of the base plate 11.
    Type: Grant
    Filed: July 4, 2016
    Date of Patent: May 14, 2019
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Hisato Michikoshi, Hiroshi Notsu
  • Patent number: 10283214
    Abstract: A semiconductor device is provided where it is possible to access and test a memory chip by a simple method. The semiconductor device that mounts a plurality of chips in a common package includes a logic chip having a predetermined function and a memory chip that is coupled with the logic chip and stores data. The memory chip includes a memory chip testing circuit that performs an operation test of the memory chip and a serial bus interface circuit for transmitting and receiving data between the memory chip testing circuit and a serial bus provided outside the package.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: May 7, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Hajime Sato
  • Patent number: 10177130
    Abstract: A semiconductor assembly includes an anti-warping controller, a semiconductor device, a balance layer and a first routing circuitry positioned within a through opening of a stiffener and a second routing circuitry positioned outside of the through opening of the stiffener and electrically connected to the first routing circuitry and a vertical connecting element of the stiffener. The mechanical robustness of the stiffener and the anti-warping controller can prevent the assembly from warping, whereas the vertical connecting element of the stiffener provides electrical connection between two opposite sides of the stiffener. The first routing circuitry can enlarge the pad size and pitch of the semiconductor device, whereas the second routing circuitry not only provides further fan-out wiring structure, but also mechanically binds the first routing circuitry with the stiffener.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: January 8, 2019
    Assignee: BRIDGE SEMICONDUCTOR CORPORATION
    Inventors: Charles W. C. Lin, Chia-Chung Wang
  • Patent number: 10163804
    Abstract: A method in which microelectronic devices are attached to a substrate surface, wherein spaces interpose neighboring ones of the microelectronic devices. Each microelectronic device has an outermost surface that is substantially parallel to the substrate surface. The substrate is closed in a transfer molding cavity of a transfer molding apparatus such that an internal surface of the transfer molding cavity contacts a substantial portion of each of the outermost surfaces of the microelectronic devices. A molding compound is subsequently injected into the transfer molding cavity, including into the spaces between ones of the plurality of microelectronic devices.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chen-Hua Yu, Chung-Shi Liu, Chih-Fan Huang, Hui-Min Huang, Wei-Hung Lin, Ming-Da Cheng
  • Patent number: 10153364
    Abstract: A power module is disclosed that includes a housing with an interior chamber wherein multiple switch modules are mounted within the interior chamber. The switch modules comprise multiple transistors and diodes that are interconnected to facilitate switching power to a load. In one embodiment, at least one of the switch modules supports a current density of at least 10 amperes per cm2.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: December 11, 2018
    Assignee: Cree, Inc.
    Inventors: Jason Patrick Henning, Qingchun Zhang, Sei-Hyung Ryu, Anant Kumar Agarwal, John Williams Palmour, Scott Allen
  • Patent number: 10141302
    Abstract: A power module includes a housing with an interior chamber and multiple switch modules mounted within the interior chamber of the housing. The switch modules are interconnected and configured to facilitate switching power to a load. Each one of the switch modules includes at least one transistor and at least one diode. The at least one transistor and the at least one diode may be formed from a wide band-gap material system, such as silicon carbide (SiC), thereby allowing the power module to operate at high frequencies with lower switching losses when compared to conventional power modules.
    Type: Grant
    Filed: March 22, 2016
    Date of Patent: November 27, 2018
    Assignee: Cree, Inc.
    Inventors: Mrinal K. Das, Henry Lin, Marcelo Schupbach, John Williams Palmour
  • Patent number: 10141289
    Abstract: A semiconductor package includes a lower package with a lower semiconductor chip on a lower package substrate, and an upper package with an upper semiconductor chip on an upper package substrate. The upper semiconductor chip has a plurality of chip pads and the upper package substrate has a plurality of substrate pads. The upper package is stacked on the lower package. The chip pads have a first pitch and the substrate pads have a second pitch greater than the first pitch. The upper package substrate has a plurality of connection lines that electrically connect the substrate pads to the chip pads.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: November 27, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Taejoo Hwang
  • Patent number: 10134598
    Abstract: As a first grinding step, a peripheral portion of a back surface of a wafer (1) is ground with a first grindstone (17) to form a fractured layer (19) in the peripheral portion. Subsequently, as a second grinding step, a central portion of the back surface of the wafer (1) is ground with the first grindstone (17) to form a recess (21) while the peripheral portion in which the fractured layer (19) is formed is left as a rib (20). Subsequently, as a third grinding step, a bottom surface of the recess (21) is ground with a second grindstone (22) of an abrasive grain size smaller than that of the first grindstone (17) to reduce a thickness of the wafer (1).
    Type: Grant
    Filed: October 10, 2014
    Date of Patent: November 20, 2018
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kazunari Nakata, Tamio Matsumura, Yoshiaki Terasaki
  • Patent number: 10121766
    Abstract: Semiconductor device packages for incorporation into semiconductor device assemblies may include a substrate including an array of electrically conductive elements located on a lower surface of the substrate. A window may extend through the substrate from the lower surface to an upper surface of the substrate. The array of electrically conductive elements may at least partially laterally surround a periphery of the window, and the substrate may extend laterally beyond the array of electrically conductive elements. Semiconductor devices may be supported on the upper surface of the substrate around a periphery of the array of electrically conductive elements. The semiconductor devices may be electrically connected to at least some of the electrically conductive elements of the array by routing elements extending from the semiconductor devices toward the window.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: November 6, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Matthew Monroe
  • Patent number: 10099574
    Abstract: A vehicle power stage assembly is disclosed which may include a power stage housing, a power stage supported by the housing, and a pair of stacked DC leadframes. The pair of stacked DC leadframes are of opposite polarity and spaced apart from one another. Each of the DC leadframes may extend from the power stage and each has distal and proximal ends. The spacing between the leadframes may be such that parasitic inductances associated with current flowing through each of the leadframes at least partially cancel one another. Each of the leadframes may define a first and second side surface opposite one another. The first side surfaces may be coplanar and the second side surfaces may be coplanar. A distance between the spaced apart pair of DC leadframes may be based on a preselected amount of current and a material of the DC leadframes.
    Type: Grant
    Filed: April 15, 2015
    Date of Patent: October 16, 2018
    Assignee: Ford Global Technologies, LLC
    Inventors: Guangyin Lei, Chingchi Chen, Ke Zou, Michael W. Degner
  • Patent number: 10090274
    Abstract: A method and system for electrically connect a semiconductor device with a flip-chip form factor to a printed circuit board. An exemplary embodiment of the method comprises: aligning solder contacts on the device with a first copper contact and a second copper contact of the external circuitry, and, applying a supply current only directly to a buried layer of the first copper and not directly to the layer which is nearest the device, such that no current is sourced to the device through the layer nearest the device.
    Type: Grant
    Filed: March 24, 2015
    Date of Patent: October 2, 2018
    Assignee: Efficient Power Conversion Corporation
    Inventors: Robert Strittmatter, Seshadri Kolluri, Robert Beach, Jianjun Cao, Alana Nakata
  • Patent number: 10084389
    Abstract: A power module includes a substrate, a first sub-module and a second sub-module. Each of the first sub-module and the second sub-module includes a semiconductor switch and a diode. The first sub-module is formed as the high-voltage-side switching element. The second sub-module is formed as the low-voltage-side switching element. The plural electrodes of the high-voltage-side switching element and the plural electrodes of the low-voltage-side switching element are electrically connected with the conducting terminals of the corresponding semiconductor switches and the corresponding diodes. The high-voltage-side switching element is disposed on the substrate and electrically connected with the corresponding conducting parts of the substrate. The low-voltage-side switching element is disposed on the high-voltage-side switching element and electrically connected with the corresponding conducting parts of the substrate through the high-voltage-side switching element.
    Type: Grant
    Filed: May 26, 2016
    Date of Patent: September 25, 2018
    Assignee: DELTA ELECTRONICS INT'L (SINGAPORE) PTE LTD
    Inventors: Yiu-Wai Lai, Da-Jung Chen
  • Patent number: 10079441
    Abstract: A fixing structure of electronic components has a first substrate, at least one second substrate, at least one electronic component, and at least one fixing mechanism. Each second substrate has at least two first pins to electrically connect to the first substrate. Multiple second pins formed on a side surface of the electronic component are electrically connected to the second substrate. The at least one fixing mechanism covers the at least one electronic component and the at least one second substrate. A first mounting part and a second mounting part respectively extend downward from opposite sides of the at least one fixing mechanism for clamping the electronic component and the second substrate so that the at least one electronic component and the at least one second substrate are erectly mounted on the first substrate. Thus, more electronic components are allowed to be erectly mounted on the first substrate.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: September 18, 2018
    Assignee: JIANGYIN SINBON ELECTRONICS CO., LTD.
    Inventors: Jen-Shing Chen, Xue Feng Zhang, Jian Zhou
  • Patent number: 10074646
    Abstract: A protective circuit includes a non-linear element, which further includes a gate electrode, a gate insulating layer covering the gate electrode, a pair of first and second wiring layers whose end portions overlap with the gate electrode over the gate insulating layer and in which a conductive layer and a second oxide semiconductor layer are stacked, and a first oxide semiconductor layer which overlaps with at least the gate electrode and which is in contact with side face portions of the gate insulating layer and the conductive layer of the first wiring layer and the second wiring layer and a side face portion and a top face portion of the second oxide semiconductor layer. Over the gate insulating layer, oxide semiconductor layers with different properties are bonded to each other, whereby stable operation can be performed as compared with Schottky junction. Thus, the junction leakage can be decreased and the characteristics of the non-linear element can be improved.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: September 11, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kengo Akimoto, Shigeki Komori, Hideki Uochi, Tomoya Futamura, Takahiro Kasahara
  • Patent number: 10045440
    Abstract: Apparatus and methods for magnetically enhanced electrical signal conduction are disclosed. An embodiment electrical connector comprises a connector body, a first active signal contact mechanically attached to and at least partially disposed within the connector body, a ground contact mechanically attached to the connector body, an insulator mechanically separating and electrically isolating the first active signal contact and the ground contact, and a first permanent magnet electrically connected to the first active signal contact. An embodiment electrical cable comprises an elongated insulating sheath, a first active signal electrical conductor disposed within the sheath, a first connector body mechanically attached to a first end of the sheath, a first active signal contact mechanically attached to the first connector body, and electrically connected to the first active signal electrical conductor, and a first permanent magnet electrically connected to the first active signal electrical conductor.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: August 7, 2018
    Assignee: MAGNETIC INNOVATIONS LLC
    Inventor: Ricky David Schultz
  • Patent number: 10032705
    Abstract: A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and method of manufacturing thereof, that comprises a substrate having a first surface and a second surface opposite to the first surface, and comprising at least one first recess portion formed in a direction ranging from the first surface toward the second surface, a plurality of first recess conductive patterns formed in the first recess portion, and a first passive element inserted into the first recess portion of the substrate and having a first electrode and a second electrode electrically connected to the plurality of first recess conductive patterns.
    Type: Grant
    Filed: May 8, 2016
    Date of Patent: July 24, 2018
    Assignee: Amkor Technology, Inc.
    Inventors: Jae Ung Lee, Yung Woo Lee, EunNaRa Cho, Dong Hyun Bang, Wook Choi, KooWoong Jeong, Byong Jin Kim, Min Chul Shin, Ho Jeong Lim, Ji Hyun Kim, Chang Hun Kim
  • Patent number: 10028380
    Abstract: A semiconductor package such as a multi-chip package is disclosed. The semiconductor package may be configured for dual second level interconnection onto a printed circuit board of a host device. Thus, a single semiconductor package may be used on host printed circuit boards having different configurations.
    Type: Grant
    Filed: October 22, 2014
    Date of Patent: July 17, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Abhishek Ramesh Tambat, Naveen Kini, Elad Baram, Pradip Ghimire
  • Patent number: 10014280
    Abstract: A power electronic package includes a first substrate, a second substrate oppositely disposed from the first substrate, one or more chips disposed between the substrates, and at least three spacers. The spacers control a height variation of the power electronic package and protect the chips and other electronics from experiencing excessive stress. The height of the spacers is determined based on a height of the chips, on a height of solder blocks that connect the chips to the top substrate, and on a height of solder blocks that connect the chips to the bottom substrate.
    Type: Grant
    Filed: June 11, 2017
    Date of Patent: July 3, 2018
    Assignee: HONG KONG APPLIED SCIENCE AND TECHNOLOGY RESEARCH INSTITUTE CO. LTD.
    Inventors: Ziyang Gao, Xunqing Shi, Shi Wo Chow
  • Patent number: 10004161
    Abstract: An electronic module is provided in which a chip is disposed over a substrate and electrically connected to the substrate by a plurality of electrical connect structures disposed between the chip and the substrate. A heat distributor, fabricated of a thermally conductive material, is disposed between the chip and the substrate and sized to extend beyond an edge of the chip to facilitate conduction of heat laterally out from between the chip and substrate. The heat distributor includes openings sized and positioned to allow the electrical connect structures to pass through the heat distributor without electrically contacting the heat distributor. The heat distributor is electrically isolated from the electrical connect structures, the chip and the substrate. In one implementation, the heat distributor physically contacts a thermally conductive enclosure of the electronic module to facilitate conduction of heat from between the chip and substrate to the enclosure.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: June 19, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Arvind K. Sinha, Kory W. Weckman
  • Patent number: 9997444
    Abstract: A microelectronic package including a passive microelectronic device disposed within a package body, wherein the package body is the portion of the microelectronic package which provides support and/or rigidity to the microelectronic package. In a flip-chip type microelectronic package, the package body may comprise a microelectronic substrate to which an active microelectronic device is electrically attached. In an embedded device type microelectronic package, the package body may comprise the material in which the active microelectronic device is embedded.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: June 12, 2018
    Assignee: Intel Corporation
    Inventors: Thorsten Meyer, Gerald Ofner, Andreas Wolter, Georg Seidemann, Sven Albers, Christian Geissler
  • Patent number: 9967975
    Abstract: A multi-layer circuit board includes a first circuit board, multiple conducting blocks, a second circuit board, and multiple conducting recesses. The first circuit board has a first conductor layer formed thereon. The conducting blocks are mounted on the first circuit board and electrically connected to the first conductor layer. The second circuit board has a second conductor layer mounted thereon and facing the first circuit board. The conducting recesses are formed in the surface of the second circuit board. Each conducting recess has a conducting layer electrically connected to the second conductor layer. When the conducting blocks are mounted in the conducting recesses, the first conductor layer and the second conductor layer are electrically connected through the conducting blocks and the conducting recesses. As can be separated from the first circuit board for test of the two conductor layers, the yield of the second circuit board is enhanced.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: May 8, 2018
    Assignee: KINSUS INTERCONNECT TECHNOLOGY CORP.
    Inventors: Ting-Hao Lin, Chiao-Cheng Chang, Yi-Nong Lin
  • Patent number: 9934829
    Abstract: A memory device including a plurality of pins and a plurality of memory dies is provided. Each of the memory dies is coupled to the pins, and each of the memory dies includes a matching circuit and a core circuit. During a course of power-on, according to voltage levels of data pins or control pins, the matching circuit may be selected automatically an enabled one of memory dies. When the core enabling signal is enabled, the core circuit starts operating, and when the core enabling signal is disabled, the core circuit stops operating. When the core circuit of one of the memory dies is operating, the core circuits of the rest of the memory dies stop operating.
    Type: Grant
    Filed: January 17, 2017
    Date of Patent: April 3, 2018
    Assignee: Winbond Electronics Corp.
    Inventor: Chi-Cheng Lin
  • Patent number: 9899316
    Abstract: For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: February 20, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Katsuhiko Hotta, Kyoko Sasahara
  • Patent number: 9875970
    Abstract: A fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole of the first connection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first connection member and the inactive surface of the semiconductor chip; a pattern layer disposed on the encapsulant and covering at least portions of the encapsulant adjacent to the inactive surface of the semiconductor chip; vias penetrating through the encapsulant and connecting the pattern layer and the inactive surface of the semiconductor chip to each other; and a second connection member disposed on the first connection member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads of the semiconductor chip.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: January 23, 2018
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Moon Hee Yi, Joo Hwan Jung, Yul Kyo Chung
  • Patent number: 9859059
    Abstract: A multilayer ceramic capacitor includes a multilayer unit, thickness-direction first and second outer layer sections, length-direction first and second outer layer sections, and width-direction first and second outer layer sections. A dimension of the thickness-direction second outer layer section is greater than a dimension of the thickness-direction first outer layer section. The thickness-direction second outer layer section includes an inner portion and an outer portion. A composition ratio of Si to Ti in a ceramic dielectric layer included in the outer portion is higher than that in the inner portion. A boundary portion between the outer portion and the inner portion has a larger Si content than the outer portion. The inner portion has a higher composition ratio of Mn to Ti than the outer portion.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: January 2, 2018
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Shota Kitano, Takanobu Katsuyama, Hiroaki Sugita
  • Patent number: 9839132
    Abstract: In a component-embedded substrate, a component and wiring block units are embedded in a component-embedded layer; conductive layers are located on all surfaces of the wiring block units; the component and the wiring block units are arranged such that lower surface side conductive layers of the wiring block units and electrodes of the component contact lower surface side wiring layers; via-hole conductors are located in respective upper positions relative to upper surface side conductive layers of the wiring block units and the electrodes of the component; and upper surface side wiring layers of the component-embedded layer are thus electrically connected to upper surface side conductive layers of the wiring block units, and the electrodes of the component by the via-hole conductors.
    Type: Grant
    Filed: August 15, 2012
    Date of Patent: December 5, 2017
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Masanori Fujidai, Isamu Fujimoto
  • Patent number: 9832885
    Abstract: Disclosed is a circuit board having a contact pad for connection with an external device, which protrudes from an upper surface of an outermost insulating layer. A device can be mounted on the circuit board, and a connection terminal of the device can be connected to the contact pad of the circuit board by a wire etc.
    Type: Grant
    Filed: May 26, 2015
    Date of Patent: November 28, 2017
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Myung Sam Kang, Ki Jung Sung, Seung Yeop Kook, Seung Eun Lee
  • Patent number: 9824988
    Abstract: A fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface disposed to oppose the active surface; a dummy chip disposed in the through-hole and spaced apart from the semiconductor chip; a second connection member disposed on the first connection member, the dummy chip, and the active surface of the semiconductor chip; and an encapsulant encapsulating at least portions of the first connection member, the dummy chip, and the inactive surface of the semiconductor chip. The first connection member and the second connection member include, respectively, redistribution layers electrically connected to the connection pads.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: November 21, 2017
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Yun Tae Lee, Sung Han Kim, Han Kim
  • Patent number: 9807882
    Abstract: An integrated circuit (IC) device may include a first substrate having an inductor ground plane in a conductive layer of the first substrate. The integrated circuit may also include a first inductor in a passive device layer of a second substrate that is supported by the first substrate. A shape of the inductor ground plane may substantially correspond to a silhouette of the first inductor.
    Type: Grant
    Filed: August 17, 2016
    Date of Patent: October 31, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: David Francis Berdy, Changhan Hobie Yun, Niranjan Sunil Mudakatte, Mario Francisco Velez, Chengjie Zuo, Jonghae Kim
  • Patent number: 9806051
    Abstract: A package structure includes a first dielectric layer, semiconductor device(s) attached to the first dielectric layer, and an embedding material applied to the first dielectric layer so as to embed the semiconductor device therein, the embedding material comprising one or more additional dielectric layers. Vias are formed through the first dielectric layer to the at least one semiconductor device, with metal interconnects formed in the vias to form electrical interconnections to the semiconductor device. Input/output (I/O) connections are located on one end of the package structure on one or more outward facing surfaces thereof to provide a second level connection to an external circuit. The package structure interfits with a connector on the external circuit to mount the package perpendicular to the external circuit, with the I/O connections being electrically connected to the connector to form the second level connection to the external circuit.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: October 31, 2017
    Assignee: General Electric Company
    Inventors: Arun Virupaksha Gowda, Paul Alan McConnelee, Shakti Singh Chauhan
  • Patent number: 9780470
    Abstract: A contact device system having a plate-shaped carrier and at least five accommodating areas are disposed on a bottom side of the pressing unit, at least five accommodating areas and at least five contact area pairs are disposed on a top side of the carrier. The contact area pairs each have a first and second electrically conductive contact area, and in each case the first contact area is spaced apart from the second contact area and insulated electrically therefrom. The first and second contact areas have a functional electrical connection to an evaluation circuit via a trace section. The carrier has a plurality of accommodating areas for a packaged electronic component, that each have one of the at least five contact area pairs. The electronic components have at least two terminal contacts, whereby after accommodation of the packaged electronic components, the terminal contacts of the particular component are pressed down.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: October 3, 2017
    Assignee: TDK-Micronas GmbH
    Inventors: Johannes Gutmann, Timo Kaufmann, Klaus Heberle, Mike Kunze, Till Feger, Georg Sammel
  • Patent number: 9741689
    Abstract: A package includes an interposer, which includes a first substrate free from through-vias therein, redistribution lines over the first substrate, and a first plurality of connectors over and electrically coupled to the redistribution lines. A first die is over and bonded to the first plurality of connectors. The first die includes a second substrate, and through-vias in the second substrate. A second die is over and bonded to the plurality of connectors. The first die and the second die are electrically coupled to each other through the redistribution lines. A second plurality of connectors is over the first die and the second die. The second plurality of connectors is electrically coupled to the first plurality of connectors through the through-vias in the second substrate.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: August 22, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Chuan Chang, Jing-Cheng Lin, Chen-Hua Yu
  • Patent number: 9736943
    Abstract: A power module includes: a plurality of partition wall plates that are provided in a case and form a trench; a plurality of relay terminals whose electric potentials are different, that are formed so that the plurality of partition wall plates are positioned therebetween and that are formed to be opposed with each other; a printed circuit board to which the plurality of relay terminals is connected and which is provided with a slit at a position opposing the trench; and a shielding plate that is placed so that one end portion of the shielding plate is positioned in the trench, and so that an amount by which the other end portion thereof protrudes from the slit is larger than amounts by which the relay terminals protrude from the printed circuit board. The power module ensures insulation inside the power module.
    Type: Grant
    Filed: May 19, 2014
    Date of Patent: August 15, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventor: Masaki Taya
  • Patent number: 9726927
    Abstract: A user terminal and a display device thereof are provided. The display device includes a display panel including a glass plate for displaying an image by outputting light, and a polarizing plate attached to both a top surface and a bottom surface of the glass plate for exposing an edge portion of the glass plate, a cover window mounted on the display panel for transmitting the light, an adhesive sheet interposed between the display panel and the cover window and for adhering the cover window at the edge portion of the glass plate. The user terminal can be formed to have a small thickness and size, and light is shielded from being leaked to the outside of the user terminal via an edge portion of the display panel in the user terminal.
    Type: Grant
    Filed: August 7, 2012
    Date of Patent: August 8, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Sil Kyu Lim
  • Patent number: 9712769
    Abstract: An image sensor having a pixel part generating a signal in accordance with a light, a signal processing part performing signal processing on the signal read from the pixel part, and a power supply part connected to the signal processing part via a first wiring, and supplying a power supply to the signal processing part, and a storage package storing the image sensor, and having a second wiring configuring a parallel circuit by being connected to the first wiring. Accordingly, it is possible to solve a problem such that a wiring resistance is increased when a power supply circuit is configured inside of a solid state image sensor.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: July 18, 2017
    Assignee: NIKON CORPORATION
    Inventor: Takafumi Komaba
  • Patent number: 9702527
    Abstract: A light emitting device comprises a housing and a LED module. The housing comprises a first part and a second part connecting the first part, wherein the first part comprises a first side, a second side and a middle portion connecting the first side and the second side, and a thickness of the first side and a thickness of the second side are thinner than that of the middle portion. The LED module is disposed on the housing for emitting light.
    Type: Grant
    Filed: December 5, 2012
    Date of Patent: July 11, 2017
    Assignee: Lite-On Electronics (Guangzhou) Limited
    Inventors: Shih-Chang Wang, Po-Chang Li, Pin-Hao Hsu, Kun-Tsai Wu
  • Patent number: 9698131
    Abstract: Methods of forming 3-D ICs with integrated passive devices (IPDs) include stacking separately prefabricated substrates coupled by through-substrates-vias (TSVs). An active device (AD) substrate has contacts on its upper portion. An isolator substrate is bonded to the AD substrate so the TSVs in the isolator substrate are coupled to the contacts on the AD substrate. An IPD substrate is bonded to the isolator substrate so that TVs therein are coupled to an interconnect zone on the isolator substrate and/or TSVs therein. The IPDs of the IPD substrate are coupled by TSVs in the IPD and isolator substrates to devices in the AD substrate. The isolator substrate provides superior IPD to AD cross-talk attenuation while permitting each substrate to have small high aspect ratio TSVs, thus facilitating high circuit packing density and efficient manufacturing.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: July 4, 2017
    Assignee: Invensas Corporation
    Inventors: Paul W. Sanders, Robert E. Jones, Michael F. Petras, Chandrasekaram Ramiah
  • Patent number: 9698125
    Abstract: Reduction in reliability of a semiconductor device is suppressed. A semiconductor device includes a plurality of metal patterns formed on a ceramic substrate, and a plurality of semiconductor chips mounted on the plurality of metal patterns. Also, the plurality of metal patterns include metal patterns MPH and MPU which face each other. In addition, a region which is provided between these metal patterns MPH and MPU and which is exposed from the plurality of metal patterns extends so as to zigzag along an extending direction of the metal pattern MPH.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: July 4, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yukihiro Sato, Katsuhiko Funatsu, Takamitsu Kanazawa, Masahiro Koido, Hiroyoshi Taya
  • Patent number: 9679839
    Abstract: A system and method for packaging semiconductor device is provided. An embodiment comprises forming vias over a carrier wafer and attaching a first die over the carrier wafer and between a first two of the vias. A second die is attached over the carrier wafer and between a second two of the vias. The first die and the second die are encapsulated to form a first package, and at least one third die is connected to the first die or the second die. A second package is connected to the first package over the at least one third die. Alternatively, instead of forming vias over the carrier wafer, through silicon vias may be formed within a semiconductor substrate and the semiconductor substrate may be attached to the carrier wafer.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: June 13, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: An-Jhih Su, Der-Chyang Yeh, Hsien-Wei Chen
  • Patent number: 9668350
    Abstract: A semiconductor module includes a printed circuit board, and first and second embedded semiconductor chips. The first and second semiconductor chips each have a first load connection and a second load connection. The printed circuit board further includes a structured first metalization layer, which has a first section and a second section, and a structured second metalization layer, which has a first section, a second section and a third section. The first section of the second metalization layer and the second section of the first metalization layer have comb shaped structures having first and second protrusions. These first and second sections are electrically conductively connected to one another by a number of first plated-through holes each of which is permanently electrically conductively connected both at first protrusions to the first section of the second metalization layer and at second protrusions to the second section of the first metalization layer.
    Type: Grant
    Filed: May 12, 2015
    Date of Patent: May 30, 2017
    Assignee: Infineon Technologies AG
    Inventor: Andre Arens
  • Patent number: 9653421
    Abstract: A semiconductor device is provided with: a semiconductor chip die-bonding mounted face up on a support; an intermediate substrate connecting the semiconductor chip to a plurality of external connection portions; and a plurality of connection bumps connecting the semiconductor chip and the intermediate substrate. The plurality of connection bumps includes a plurality of power supply bumps connected to a plurality of electrode pads on the semiconductor chip for supplying power to the semiconductor chip. The intermediate substrate includes: a plurality of power supply pads connected to the plurality of electrode pads through the plurality of power supply bumps; a bump surface facing the semiconductor chip and having a plurality of power supply pads formed thereon; an external connection surface having a plurality of external connection pads formed thereon connected to the external connection portions; and a capacitor connected to the plurality of power supply bumps.
    Type: Grant
    Filed: April 7, 2015
    Date of Patent: May 16, 2017
    Assignee: NODA SCREEN CO., LTD.
    Inventor: Atsunori Hattori
  • Patent number: 9601423
    Abstract: A laminate includes a buildup layer having a top and a bottom and a solder mask contacting the top. The laminate also includes a circuit element disposed on the top of the buildup layer and at least partially covered by the solder mask, the circuit element including a first via formed therein that allows for a power signal provided to an underside of the circuit element to be provided to a first connection on a top of the circuit element.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: March 21, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Charles L. Arvin, Jon A. Casey, Brian M. Erwin, Steven P. Ostrander, Brian W. Quinlan
  • Patent number: 9596756
    Abstract: An electronic device may be provided with integrated circuits and electrical components such as capacitors that are soldered to printed circuit boards. Liquid polymer adhesive such as encapsulant and underfill materials may be deposited on the printed circuit. Electrical components such as capacitors may be coated with the encapsulant. The underfill may be deposited adjacent to an integrated circuit, so that the underfill wicks into a gap between the integrated circuit and the printed circuit board. The encapsulant may be more viscous than the underfill and may therefore prevent the flowing underfill from reaching the electrical components. Some of the encapsulant may be located between the electrical components and the printed circuit board. The encapsulant can be cured to form an elastomeric material covering the electrical components that helps damp vibrations. The elastomeric material may be less stiff than the underfill.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: March 14, 2017
    Assignee: Apple Inc.
    Inventors: Amanda R. Rainer, Connor R. Duke, James W. Bilanski, Jeffrey M. Thoma, Michael Eng, Mingzhe Li, Sung Woo Yoo, Miguel Alejandro Lara-Pena, Weng Choy Foo, Kieran Poulain
  • Patent number: 9589941
    Abstract: In an embodiment, a semiconductor structure includes a multi-chip package system (MCPS). The MCPS includes one or more dies, a molding compound extending along sidewalls of the one or more dies, and a redistribution layer (RDL) over the one or more dies and the molding compound. The semiconductor structure also includes at least one sensor coupled to the RDL, with the RDL interposed between the at least one sensor and the one or more dies. The semiconductor structure further includes a substrate having conductive features on a first side of the substrate. The conductive features are coupled to the RDL. The substrate has a cavity extending from the first side of the substrate to a second side of the substrate opposite the first side, and the at least one sensor is disposed in the cavity.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: March 7, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hua Chen, Yu-Feng Chen, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
  • Patent number: 9543233
    Abstract: A chip package includes a chip, a laser stopper, an isolation layer, a redistribution layer, an insulating layer, and a conductive structure. The chip has a conductive pad, a first surface, and a second surface opposite to the first surface. The conductive pad is located on the first surface. The second surface has a first though hole to expose the conductive pad. The laser stopper is located on the conductive pad. The isolation layer is located on the second surface and in the first though hole. The isolation layer has a third surface opposite to the second surface. The isolation layer and the conductive pad have a second though hole together, such that the laser stopper is exposed through the second though hole. The redistribution layer is located on the third surface, the sidewall of the second though hole, and the laser stopper.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: January 10, 2017
    Assignee: XINTEC INC.
    Inventors: Chien-Hung Liu, Ying-Nan Wen, Shih-Yi Lee, Ho-Yin Yiu