Abstract: A fluid circulator including a pump body with an impeller; an electric motor having a rotor connected to the impeller for rotatably driving the impeller; an end portion associated with the motor body for housing at least one electronic board for controlling the circulator. The end portion is monolithically cup-shaped lid fitted onto the motor body in substantial continuity therewith enclosing a housing compartment for said electronic board; an electronic power device mounted onto the electronic board so as to face the end wall of the cup-shaped lid; at least one portion of said end wall being recessed towards the electronic board and being externally provided with at least one cooling fin extending in parallel to the axis of the motor to constitute a heat sink; and a layer of a heat-conductive paste material in contact with the electronic power devices and recessed surface.

Abstract: An electronic device includes a carrier substrate with an electronic IC chip mounted on top of the carrier substrate. An encapsulation block on top of the front face of the carrier substrate embeds the IC chip. The encapsulation block has a through-void for positioning and confinement that extends through the encapsulation block to the top of the carrier substrate. At least one electronic component is positioned within the through-void and mounted to the top of the carrier substrate. Solder bumps or pads are located within the through-void to electrically connect the at least one electronic component to the carrier substrate.

Abstract: The present disclosure discloses a time synchronous hybrid analog and digital sensor data acquisition system and method, comprising analog sensors, digital modules, digital sensors, hubs for networking a plurality of heterogeneous sensors, a local-area network device and a data processing terminal. The present disclosure solves the problem that data cannot be compared due to time difference in acquisition for the reason that the sampling time of different sensors cannot be synchronized precisely in the existing experiments and practical engineering, and also solves the problems of single function, low integration level and manpower consumption when different sensor instruments work separately. The data acquisition system of the present disclosure can be directly connected to various heterogeneous sensors to realize synchronous acquisition, synchronous transmission and simple and fast operation.

Abstract: A package includes a first device die, and a first encapsulating material encapsulating the first device die therein. A bottom surface of the first device die is coplanar with a bottom surface of the first encapsulating material. First dielectric layers are underlying the first device die. First redistribution lines are in the first dielectric layers and electrically coupling to the first device die. Second dielectric layers are overlying the first device die. Second redistribution lines are in the second dielectric layers and electrically coupling to the first redistribution lines. A second device die is overlying and electrically coupling to the second redistribution lines. No solder region connects the second device die to the second redistribution lines. A second encapsulating material encapsulates the second device die therein. A third device die is electrically coupled to the second redistribution lines. A third encapsulating material encapsulates the third device die therein.

Abstract: A package structure includes a circuit substrate, a semiconductor package, a lid structure, a passive device and a barrier structure. The semiconductor package is disposed on and electrically connected to the circuit substrate. The lid structure is disposed on the circuit substrate covering the semiconductor package. The lid structure is attached to the circuit substrate through an adhesive material. The passive device is disposed on the circuit substrate in between the semiconductor package and the lid structure. The barrier structure is separating the passive device from the lid structure and the adhesive material, and the barrier structure is in contact with the adhesive material.

Abstract: A semiconductor device, including a substrate having an insulating layer and a plurality of circuit patterns formed on the insulating layer, the substrate having a principal surface on which an element region is set. The semiconductor device further includes a plurality of semiconductor elements provided on the plurality of circuit patterns in the element region, a plurality of main terminals that each have a first end joined to one of the plurality of circuit patterns in the element region and a second end extending out of the substrate from a first side of the substrate, a plurality of control terminals disposed in a control region that is adjacent to a second side of the substrate opposite the first side, and a sealing member that seals the principal surface and the control region.

Abstract: A method for producing a PUF-film includes printing a layer of dielectric material on a film substrate, such that a variable thickness of the layer is obtained by the printing. The method includes arranging a structured electrode layer on the dielectric material such that the structured electrode layer is influenced with respect to an electric measurement value due to the variable thickness.

Abstract: An interconnect interface is provided to enable communication with an off-package device over a link including a plurality of lanes. Logic of the interconnect interface includes receiver logic to receive a valid signal from the off-package device on a dedicated valid lane of the link indicating that data is to arrive on a plurality of dedicated data lanes in the plurality of lanes, receive the data on the data lanes from the off-package device sampled based on arrival of the valid signal, and receive a stream signal from the off-package device on a dedicated stream lane in the plurality of lanes. The stream signal corresponds to the data and indicates a particular data type of the data. The particular data type can be one of a plurality of different data types capable of being received on the plurality of data lanes of the link.

Abstract: Various embodiments include a capacitor structure comprising: a plurality of capacitors disposed in a support structure, wherein each of the plurality of capacitors includes a first capacitor electrode and a second capacitor electrode. The support structure includes a first electrode and a second electrode. Each of the plurality of capacitors makes electrical contact with the first electrode via the respective first capacitor electrode and with the second electrode via the respective second capacitor electrode. The support structure includes a mounting side for surface mounting, the mounting side comprising a first contact area of the first electrode and a second contact area of the second electrode. The support structure defines a cuboid interior and the capacitors are disposed in the cuboid interior. An outer side of the support structure defines an additional structural framework outside the mounting side.

Abstract: An opto-electronic package is described. The opto-electronic package is manufactured using a fan out wafer level packaging to produce dies/frames which include connection features. Additional structures such as heat exchanged structures are joined to a connection component and affixed to packages, using the connection features, to provide structural support and heat exchange to heat generating components in the package, among other functions.

Abstract: A power module is disclosed. The power module includes a carrier board, two switches, at least one metal block, a clamping component and a metal conductive component. The carrier board includes an upper surface and a lower surface. The two switches are disposed on the upper surface and connected in series to form a bridge arm electrically connected between a positive terminal and a negative terminal. The metal block is electrically connected to the two switches. The clamping component is disposed on the upper surface and electrically connected in parallel with the bridge arm through the carrier board. The metal conductive component is connected from a common node of the two switches to an output terminal. The metal conductive component is located at a side of the two switches facing away from the upper surface.

Abstract: Disclosed herein are capacitor-wirebond pad structures for integrated circuit (IC) packages, as well as related methods and devices. For example, in some embodiments, an IC package may include a die and an IC package support. The IC package support may include a capacitor, and the capacitor may include a first capacitor plate, a second capacitor plate, and a capacitor dielectric between the first capacitor plate and the second capacitor plate. The die may be wirebonded to the first capacitor plate.

Abstract: Certain aspects of the present disclosure generally relate to a modular capacitor array, such as for an integrated circuit package, and methods for fabricating the same. One example integrated circuit package generally includes a package substrate, a semiconductor die disposed above the package substrate, and at least one modular capacitor array disposed below the package substrate. The modular capacitor array may be a pre-packaged array of capacitive elements, such as multi-layer ceramic capacitors (MLCCs).

Abstract: A semiconductor device includes: an oscillator including external terminals disposed on a first face with a specific distance along a first direction; an integrated circuit including a first region formed with first electrode pads along one side, and a second region formed with second electrode pads on two opposing sides of the first region; a lead frame that includes terminals at a peripheral portion, and on which the oscillator and the integrated circuit are mounted such that the external terminals, the first and second electrode pads face in a substantially same direction and such that one side of the integrated circuit is substantially parallel to the first direction; a first bonding wire that connects one external terminal to one first electrode pad; a second bonding wire that connects one terminal of one lead frame to one second electrode pad; and a sealing member that seals all of the components.

Abstract: A method of manufacturing a semiconductor package may include forming a first substrate including a redistribution layer, providing a second substrate including a semiconductor chip and an interconnection layer on the first substrate to connect the semiconductor chip to the redistribution layer, forming a first encapsulation layer covering the second substrate, and forming a via structure penetrating the first encapsulation layer. The forming the via structure may include forming a first via hole in the first encapsulation layer, forming a photosensitive material layer in the first via hole, exposing and developing the photosensitive material layer in the first via hole to form a second encapsulation layer having a second via hole, and filling the second via hole with a conductive material. A surface roughness of a sidewall of the first encapsulation layer may be greater than a surface roughness of a sidewall of the second encapsulation layer.

Abstract: A semiconductor device package includes a first substrate, a second substrate, a first electronic component, a second electronic component and a shielding layer. The second substrate is disposed over the first substrate. The first electronic component is disposed between the first substrate and the second substrate. The second electronic component is disposed between the first substrate and the second substrate and adjacent to the second substrate than the first electronic component. The shielding element electrically connects the second electronic component to the second substrate. The second electronic component and the shielding element define a space accommodating the first electronic component.

Abstract: A semiconductor element includes a semiconductor substrate, first and second amplifiers provided on the semiconductor substrate and adjacently provided in a first direction, a first reference potential bump provided on a main surface of the semiconductor substrate, and connecting the first amplifier and a reference potential, a second reference potential bump provided on the main surface, being adjacent to the first reference potential bump in the first direction, and connecting the second amplifier and a reference potential, and a rectangular bump provided on the main surface, provided between the first and second reference potential bumps in a plan view, and formed such that a second width in a second direction orthogonal to the first direction is larger than a first width in the first direction. The second width is larger than a width of at least one of the first and second reference potential bumps in the second direction.

Abstract: A semiconductor device includes a first chip package, a heat dissipation structure and an adapter. The first chip package includes a semiconductor die laterally encapsulated by an insulating encapsulant, the semiconductor die has an active surface and a back surface opposite to the active surface. The heat dissipation structure is connected to the chip package. The adapter is disposed over the first chip package and electrically connected to the semiconductor die.

Abstract: Provided is a semiconductor device free from chipping of a thin semiconductor element during transportation. The semiconductor device includes: a thin semiconductor element including a front-side electrode on the front side of the semiconductor element, and including a back-side electrode on the back side of the semiconductor element; a metallic member formed on at least one of the front-side electrode and the back-side electrode, the metallic member having a thickness equal to or greater than the thickness of the semiconductor element; and a resin member in contact with the lateral side of the metallic member and surrounding the periphery of the metallic member, with a part of the front side of the semiconductor element being exposed.

Abstract: Disclosed are a chip package capable of improving the strength of a package and simplifying a manufacturing process and a manufacturing method therefor. This invention may improve the durability of the package by further forming a reinforcing layer on a chip by using an adhesive layer and molding the chip and the reinforcing layer so as to be integrated by using a molding layer. Also, the strength of the package may be improved by having a structure in which solder balls are formed between a base substrate and a re-wiring layer and integrated with the molding layer, and a wiring layer may be formed directly on the molding layer by using polyimide (PI) as the molding layer without using a separate insulating layer formed on the molding layer as in the conventional art.

Abstract: A package apparatus comprises a first wiring layer, a first dielectric material layer, a first conductive pillar layer, a first buffer layer, a second wiring layer, and a protection layer. The first wiring layer has a first surface and a second surface opposite to the first surface. The first dielectric material layer is disposed within partial zone of the first wiring layer. The first conductive pillar layer is disposed on the second surface of the first wiring layer. The first buffer layer is disposed within partial zone of the first conductive pillar layer. The second wiring layer is disposed on the first buffer layer and one end of the first conductive pillar layer. The protection layer is disposed on the first buffer layer and the second wiring layer.

Abstract: A display panel, a manufacturing method thereof, and a display device are provided. The display panel has a display area and a peripheral area surrounding the display area, the display panel includes a first substrate, a second substrate disposed opposite to the first substrate, and a sealing member. The sealing member is disposed between the first substrate, and the second substrate and located in the peripheral area, and configured to hermetically connect the first substrate and the second substrate, the sealing member includes a first sealant and a first retaining wall, an orthographic projection of the first retaining wall on the second substrate is at least partially overlapped with an orthographic projection of the first sealant on the second substrate, and elastic modulus of a material of the first sealant is greater than elastic modulus of a material of the first retaining wall.

Abstract: A semiconductor device may include a substrate constituted of an insulator; a first conductor film provided on a part of the substrate; a semiconductor chip located on the first conductor film; and an external connection terminal joined to the substrate via a joining layer at a position separated from the first conductor film. The semiconductor chip may be a power semiconductor chip including a main electrode and a signal electrode. The main electrode may be electrically connected to the first conductor film and the signal electrode may be electrically connected to the external connection terminal.

Abstract: The integrated circuit assembly can include: a semiconductor and a substrate (e.g., PCB). The integrated circuit assembly can optionally include: a compliant connector, a thermal management, and a securing element. The semiconductor 210 can include a first alignment feature. (e.g., orifice). The substrate can include a second alignment feature (e.g., alignment target) and conductive pads. The substrate can optionally include a cavity.

Abstract: A power semiconductor device includes a Si chip providing a Si switch and a wide bandgap material chip providing a wide bandgap material switch, wherein the Si switch and the wide bandgap material switch are electrically connected in parallel. A method for controlling a power semiconductor device includes: during a normal operation mode, controlling at least the wide bandgap material switch for switching a current through the power semiconductor device by applying corresponding gate signals to at least the wide bandgap material switch; sensing a failure in the power semiconductor device; and, in the case of a sensed failure, controlling the Si switch by applying a gate signal, such that a current is generated in the Si chip heating the Si chip to a temperature forming a permanent conducting path through the Si chip.

Abstract: Electrical current flow in a ball grid array (BGA) package can be measured by an apparatus including an integrated circuit (IC) electrically connected to the BGA package. Solder balls connect the BGA package to a printed circuit board (PCB). A current sense mesh can be placed between adjacent solder balls and is attached to the upper surface of the PCB. The solder balls are electrically connected to supply current from the PCB through the BGA package to the IC. A MUX/Sequencer can sequentially connect wires of the current sense mesh to an amplifier. The amplifier can amplify a voltage induced on the current sense mesh by current flow into the BGA package. A sensing analog-to-digital converter (ADC) is electrically connected to convert a voltage at the output of the amplifier into digital output signals.

Abstract: A field effect transistor according to the present invention includes a semiconductor substrate, a plurality of drain electrodes provided on a first surface of the semiconductor substrate and extending in a first direction, an input terminal, an output terminal, and a plurality of metal layers provided in the semiconductor substrate apart from the first surface and extending in a second direction crossing the first direction, in which the plurality of metal layers include a first metal layer and a second metal layer which is longer than the first metal layer and which crosses more drain electrodes than the first metal layer when seen from a direction perpendicular to the first surface, and among the plurality of drain electrodes, those having a smaller length of line from the input terminal to the output terminal are provided with more metal layers directly thereunder.

Abstract: Systems and methods for placing capacitors between IC bumps and BGA balls are described. In one embodiment, the method may include placing a ball grid array (BGA) package or integrated circuit (IC) package on a printed circuit board (PCB) of an electronic device, and placing a capacitor between a first BGA ball and a second BGA ball of the BGA package and/or placing a capacitor between a first IC bump and a second IC bump of the IC package to maintain impedance of a power delivery network (PDN) of the BGA package or IC package below a target impedance.

Abstract: A device and method of forming the device that includes a first substrate having a cavity on a bottom surface of the first substrate and MEMS components formed on the first substrate and in the cavity; a second substrate having an upper surface; a first metal bond that extends around a perimeter of the cavity and forming a first connection between the bottom surface of first substrate and the upper surface of the second substrate; a second metal bond that extends around a perimeter of the first metal bond and spaced from the first metal bond, the second metal bond forming a second connection between the bottom surface of the first substrate and the upper surface of the second substrate; where the MEMS components are hermetically sealed between the first and second substrates. A getter agent can be between the first and second metal bonds.

Abstract: In a semiconductor device using a wide bandgap semiconductor material having a bandgap larger than that of silicon, reliability of the semiconductor device is improved by achieving a structure in which electric field strength in the vicinity of an outer end portion of a semiconductor chip is relaxed. A side surface of the semiconductor chip CHP1a is formed of a region R1 including a first corner, a region R2 including a second corner, and a region R3 interposed between the region R1 and the region R2. At this point, in a case of defining a minimum film thickness of a high electric field-resistant sealing member MR in the region R3 as t1 and defining a maximum film thickness of the high electric field-resistant sealing member MR in the region R1 as t2, a relation of t2?1.5×t1 is satisfied.

Abstract: Provided is a semiconductor module enabling to effectively reduce, with a relatively simple structure, a thermal strain occurring in a bonding section between a semiconductor chip and other conductor members. The semiconductor module is characterized by being provided with: a first wiring layer; a semiconductor element bonded on the first wiring layer via a first bonding layer; a first electrode bonded on the semiconductor element via a second bonding layer; a second electrode connected on the first electrode; and a second wiring layer connected on the second electrode. The semiconductor module is also characterized in that: the width of the second electrode, said width being in the short-side direction, is more than the thickness of the first electrode; and the second electrode is disposed at a position off the center position of the semiconductor element.

Abstract: In a general aspect, an apparatus can include a metal layer, a first semiconductor die, a second semiconductor die, a molding compound, a first electrical contact and a second electrical contact. The first semiconductor die can have a first side disposed on the metal layer. The second semiconductor die can have a first side disposed on the metal layer. The metal layer can electrically couple the first side of the first semiconductor die with the first side of the second semiconductor die. The molding compound can at least partially encapsulate the metal layer, the first semiconductor die and the second semiconductor die. The first electrical contact can be to a second side of the first semiconductor die and disposed on a surface of the apparatus. The second electrical contact can be to a second side of the second semiconductor die and disposed on the surface of the apparatus.

Abstract: An electronics package includes a support substrate, an electrical component having a first surface coupled to a first surface of the support substrate, and an insulating structure coupled to the first surface of the support substrate and sidewalls of the electrical component. The insulating structure has a sloped outer surface. A conductive layer encapsulates the electrical component and the sloped outer surface of the insulating structure. A first wiring layer is formed on a second surface of the support substrate. The first wiring layer is coupled to the conductive layer through at least one via in the support substrate.

Abstract: The present disclosure is directed to a flat no-lead semiconductor package with a surfaced mounted structure. An end portion of the surface mounted structure includes a recessed member so that the surface mounted structure is coupled to leads of the flat no-lead semiconductor package through, among others, the sidewalls of the recessed members.

Abstract: In an embodiment, a package includes: a first redistribution structure; a first integrated circuit die connected to the first redistribution structure; a ring-shaped substrate surrounding the first integrated circuit die, the ring-shaped substrate connected to the first redistribution structure, the ring-shaped substrate including a core and conductive vias extending through the core; a encapsulant surrounding the ring-shaped substrate and the first integrated circuit die, the encapsulant extending through the ring-shaped substrate; and a second redistribution structure on the encapsulant, the second redistribution structure connected to the first redistribution structure through the conductive vias of the ring-shaped substrate.

Abstract: An embodiment provides a printed circuit board and an electronic component package including the same, the printed circuit board comprising: a data line layer; a ground layer disposed on the data line layer; a power line layer disposed on the ground layer; and insulation layers disposed between the data line layer and the ground layer and between the ground layer and the power line layer, respectively, wherein the ground layer comprises a common ground and a chassis ground electrically insulated from the common ground.

Abstract: In various embodiments, a memory module houses memory devices and, in some embodiments, a memory controller. Each of the devices has a near-field interface coupled to loop antennas to communicate over-the-air data. A coil is formed on, for example, a memory device substrate or molded into a plastic mold to create near-field magnetic coupling between the stacked memory devices and, in certain embodiments, the memory controller. Other embodiments are disclosed.

Abstract: A circuit board is provided and the circuit board is used for being attached to a matching board. The circuit board includes a first circuit pattern and an attaching state inspection area, and the attaching state inspection area further includes a third circuit pattern. A liquid crystal display device is further provided, including the circuit board and the matching board, the matching board includes a second circuit pattern matching the circuit board. It is more accurate to judge the attaching state between the circuit board and the matching board by detecting the deformation state of the conductive particles in vacant areas at different locations after the circuit board is attached to the matching board.

Abstract: An electronics package includes a support substrate, an electrical component having a first surface coupled to a first surface of the support substrate, and an insulating structure coupled to the first surface of the support substrate and sidewalls of the electrical component. The insulating structure has a sloped outer surface. A conductive layer encapsulates the electrical component and the sloped outer surface of the insulating structure. A first wiring layer is formed on a second surface of the support substrate. The first wiring layer is coupled to the conductive layer through at least one via in the support substrate.

Abstract: An electronic package is provided, which includes: a first substrate; a first electronic component disposed on the first substrate; a second substrate stacked on the first substrate through a plurality of first conductive elements and a plurality of second conductive elements and bonded to the first electronic component through a bonding layer; and a first encapsulant formed between the first substrate and the second substrate. The first conductive elements are different in structure from the second conductive elements so as to prevent a mold flow of the first encapsulant from generating an upward pushing force during a molding process and hence avoid cracking of the second substrate. The present disclosure further provides a method for fabricating the electronic package.

Abstract: A housing for receiving a circuit board with an overvoltage protection unit and overvoltage protection module. The housing includes a support frame and a film. The support frame is formed of a thermoplastic material and has a main leg, two side legs adjoining the main leg at one end in each case, and at least one lateral flat brace. The film is formed of a thermoplastic material and is formed U-shaped. An end face of the film at least partially covers an end face of the main leg, each side surface of the film at least partially covering the two side legs and the brace. The film is materially connected to the side legs such that the housing made up of the support frame and film is at least partially open on a side opposite the end face of the film.

Abstract: An electronic device has a first bus bar (conductor plate) connected to a first semiconductor device (semiconductor part) having a first power transistor; and a second bus bar (conductor plate) connected to a second semiconductor device (semiconductor part) having a second power transistor. The first and second bus bars have first portions facing each other with an insulating plate interposed therebetween and extending in a Z direction intersecting with an upper surface (main surface) of a board. The first bus bar has a second portion located between the first portion and a terminal (exposed portion) and extending in an X direction away from the second bus bar and a third portion located between the second portion and the terminal and extending in the X direction. An extension distance of the third portion in the Z direction is shorter than an extension distance of the second portion in the X direction.

Abstract: A preformed lead frame device includes a molding layer and a plurality of spaced-apart lead frame units. The molding layer is made of a polymer material, and includes a plurality of framed portions, and a plurality of longitudinal and transverse frame sections intersecting each other to frame the framed portions. The lead frame units are arranged in an array and made of metal. Each of the lead frame units is embedded in a respective one of the framed portions and includes a plurality of spaced-apart leads.

Abstract: The disclosure provides an interposer substrate and a method for manufacturing the same. The method includes forming an insulating protection layer having a phosphorus compound on a substrate body, thereby providing toughness and strength as required when the thickness of the interposer substrate becomes too thin, and preventing substrate warpage when the substrate has a shrinkage stress or structural asymmetries.

Abstract: In accordance with some embodiments of the present disclosure, an integrated fan-out (INFO) package includes a substrate, a molding compound, a buffer layer, a first chip, a second chip, and a redistribution circuit structure layer. The molding compound is disposed on the substrate. The buffer layer is disposed on the substrate and includes a first buffer pattern and a second pattern separated from the first buffer pattern by a distance. A thickness of the first buffer pattern is greater than a thickness of the second buffer pattern. The first chip is attached to the substrate through the first buffer pattern and surrounded by the molding compound. The second chip is attached to the substrate through the second buffer pattern and surrounded by the molding compound. The redistribution circuit structure layer is disposed on the molding compound and electrically connected to the first chip and the second chip.

Abstract: A multi-chip semiconductor device with multi-level structure including a substrate with a top substrate surface, a cavity with a depth in the substrate, a first chip having a top first chip surface with a first chip height, optionally including a second chip having a top second chip surface with a second chip height, and a connecting passive chip bridging the first chip, the second chip and the substrate by solder bumps wherein the solder bumps enable the connecting passive chip to be level.

Abstract: Disclosed herein is a configuration for ensuring ESD protection capability for a core power supply of a semiconductor integrated circuit device, without causing an increase in the circuit area. A first pad row in a core region includes a first pad for core power supply. The first pad is connected to a core power supply interconnect, and supplied with a power supply potential or a ground potential. A second pad row provided outwardly from the first pad row includes a second pad for core power supply. The second pad is supplied with the same power supply or ground potential as the first pad for core power supply, and connected to an I/O cell for core power supply.

Abstract: A semiconductor package assembly is provided. The semiconductor package assembly includes a semiconductor package. The semiconductor package includes a semiconductor die. A redistribution layer (RDL) structure is disposed on the semiconductor die and is electrically connected to the semiconductor die. An active or passive element is disposed between the semiconductor die and the RDL structure. A molding compound surrounds the semiconductor die and the active or passive element.

Abstract: Implementations of semiconductor packages may include: an image sensor; an optically transmissive transparent coating directly coupled to the image sensor; and a glass lid coupled directly coupled to the optically transmissive coating. An entire surface of the glass may be directly coupled to an entire surface of the optically transmissive adhesive coating.

Abstract: Techniques for using a single thru-chip signal path to auto-identify and address each integrated circuit within a stack of integrated circuits upon power-up of stack. In an example, each integrated circuit of the stack can include a single auto-identify input terminal, a single auto-identify output terminal, and control logic configured to receive a logic state on the single auto-identify input terminal, to set an internal indicator to one of three states, and to control a state of the single auto-identify output terminal in response to a power up condition or to a change in the logic state of the single auto-identify input terminal.