Devices Held In Place By Clamping Patents (Class 257/726)
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Patent number: 11289839Abstract: A memory slot adapted to dispose on a circuit board is provided. The memory slot includes a slot body and a plurality of pins. The slot body includes N connecting parts for configuring to M memory cards. The plurality of pins are disposed in the slot body for electrically connecting the M memory cards to the circuit board. Each pin includes O branches extending to the connecting parts respectively for electrically connecting corresponding golden fingers of the memory cards. Where the N, M and O are greater than or equal to 2. The disclosure further provides a main board with the memory slot.Type: GrantFiled: February 19, 2020Date of Patent: March 29, 2022Assignee: ASUSTEK COMPUTER INC.Inventors: Ping-Han Tsou, Li-Chien Wan
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Patent number: 10736206Abstract: A power electronics assembly for an electric motor controller. The power electronics assembly comprises an insulated metal substrate, a composite material substrate, and a bolt having a bolt head and a bolt shaft for mechanically coupling the composite material substrate to the insulated metal substrate. The power electronics assembly also includes an electrically conductive sleeve configured to be held between a first electrical contact carried by the insulated metal substrate and a second electrical contact carried by the composite material substrate and the bolt is configured to clamp the composite material substrate to the insulated metal substrate to force the electrically conductive sleeve against the first electrical contact and the second electrical contact.Type: GrantFiled: July 27, 2016Date of Patent: August 4, 2020Assignee: Sevcon LimitedInventors: Peter Barrass, Matt Jackson
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Patent number: 10242941Abstract: The disclosed apparatus may include (1) a stiffening brace that (A) is coupled to a top surface of a lidless integrated circuit and (B) includes at least one joint and (2) a removable lid that (A) interfaces with the stiffening brace at the joint, (B) temporarily sits atop the stiffening brace during a reflow process in which a bottom surface of the lidless integrated circuit is soldered to a circuit board, and (C) provides structural support to the lidless integrated circuit to impede the lidless integrated circuit from warping during the reflow process. Various other apparatuses, systems, and methods are also disclosed.Type: GrantFiled: August 7, 2017Date of Patent: March 26, 2019Assignee: Juniper Networks, IncInventors: Peng Su, Helen L. Turner, Marc D. Hartranft, Gautam Ganguly, Guhan Subbarayan
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Patent number: 10164519Abstract: A semiconductor stack for a converter comprises two series-connected semiconductor switches; two terminals for connecting a cell capacitor, which are connected to one another by the two semiconductor switches; at least one cooling element arranged between the semiconductor switches; a frame, by which the semiconductor switches and the cooling element are fixed to one another and which provides the terminals; and at least two snubber capacitors which are mechanically fixed to the frame and which are connected in parallel, are connected to the terminals and which in each case form a commutation loop with the semiconductor switches.Type: GrantFiled: April 1, 2016Date of Patent: December 25, 2018Assignee: ABB Schweiz AGInventors: Osman Senturk, Peter Steimer
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Patent number: 9956643Abstract: Provided is a pressure applying unit used in baking a metal particle paste of an assembled body formed by arranging an electronic part on a substrate with the metal particle paste interposed therebetween by heating the assembled body while applying pressure to the assembled body using a pair of heating parts. The pressure applying unit includes: a pair of transferring members which transfers pressure and heat to the assembled body by sandwiching the assembled body therebetween; guide members which movably connect the pair of transferring members to each other; and a distance adjusting mechanism being configured to make the second transferring member separated from the assembled body during a pressure non-applying time and brings both the first transferring member and the second transferring member into contact with the assembled body during a pressure applying time.Type: GrantFiled: March 31, 2015Date of Patent: May 1, 2018Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.Inventor: Ryo Matsubayashi
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Patent number: 9659804Abstract: An orientating and installing jig for orientating a heat-dissipating unit (or a workpiece) to fix on a heat-generating device (or a target device) above a circuit board (or a supporting baseplate), which includes a carrying board formed with at least one assembling opening, a plurality of fixing posts and a pair of arrest-orientating modules oppositely arranged at two sides of the assembling opening. The assembling opening is shaped correspondingly to the shape of the heat-dissipating unit. The fixing posts are disposed at a bottom surface of the carrying board for fixing the carrying board above the circuit board. Each arrest-orientating module includes an arresting barrier. The arresting barrier is rotatably disposed at a suspending position of suspending the workpiece on the carrying board, and a releasing position of allowing the workpiece to pass through the assembling opening, so that the workpiece is put on the target device.Type: GrantFiled: May 3, 2014Date of Patent: May 23, 2017Assignee: WISTRON CORP.Inventors: Xiao-Hua Ke, Wan-Rong Zhu
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Patent number: 9634554Abstract: A short-circuit switch for use with a first electrical conductor and a second electrical conductor includes a controllable semiconductor switch that is configured to short-circuit a voltage present between the first conductor and the second conductor responsive to receipt of a trigger, and a mechanical press-pack structure. The controllable semiconductor switch is a press-pack-type thyristor having a first planar electrode and a second planar electrode on contact sides situated opposite one another. The thyristor is disposed in the mechanical press-pack structure. The mechanical press-pack structure includes: a first terminal electrode that is configured to connect the first planar electrode to the first conductor, wherein the first terminal electrode is resiliently supported by a spring assembly; and a second terminal electrode that is configured to connect the second planar electrode to the second conductor. The press-pack structure forms a protective cover enveloping the thyristor.Type: GrantFiled: August 13, 2015Date of Patent: April 25, 2017Assignee: Raycap, S.A.Inventors: Andreas Falk, Alexander Krug, Max Rothenburger, Gerold Schulze
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Patent number: 9147666Abstract: Disclosed is a semiconductor device having a structure capable of reducing the self-inductance of internal wiring. The semiconductor device includes: a lower board having a lower conductor layer formed on the surface thereof; a switching element bonded to the lower conductor layer in an element bonding area; a terminal bonded to the lower conductor layer in a terminal bonding area; an upper board stacked on the lower board in a board bonding area between the element bonding area and the terminal bonding area, and having an upper conductor layer on the surface thereof; and a switching element connecting member which connects the switching element with the upper conductor layer.Type: GrantFiled: May 12, 2010Date of Patent: September 29, 2015Assignee: ROHM CO., LTD.Inventors: Katsuhiko Yoshihara, Kouichi Kitaguro
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Patent number: 9030006Abstract: An integrated circuit package system includes: providing an integrated circuit substrate; forming an internal stacking module coupled to the integrated circuit substrate including: forming a flexible substrate, coupling a stacking module integrated circuit to the flexible substrate, and bending a flexible extension over the stacking module integrated circuit; and molding a package body on the integrated circuit substrate and the internal stacking module.Type: GrantFiled: July 31, 2012Date of Patent: May 12, 2015Assignee: STATS ChipPAC Ltd.Inventors: Seng Guan Chow, Heap Hoe Kuan, Reza Argenty Pagaila
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Patent number: 8970030Abstract: The invention relates to an electronic module and to a method for producing same, comprising a mold body (2), a first circuit carrier (3; 13) having a first inner face (3a; 13a), on which electronic components (5) are arranged, and a first outer face (3b; 13b), a second circuit carrier (4; 14) having a second inner face (4a; 14a), on which electronic components (5) are arranged, and a second outer face (4b; 14b), and at least one spring device (6, 7; 16) which connects the inner faces (3a, 14a; 13a, 14a), or surfaces of electronic components (5) arranged thereon, of the first and second circuit carriers (3, 4; 13, 14), wherein the first and second outer faces (3a, 4a; 13a, 14a) are exposed towards the outside of the electronic module in order to emit heat directly to the outside, and wherein the first and second outer faces (3a, 4a; 13a, 14a) are parallel to each other.Type: GrantFiled: September 23, 2011Date of Patent: March 3, 2015Assignee: Robert Bosch GmbHInventor: Matthias Keil
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Patent number: 8963324Abstract: In a semiconductor device, a semiconductor module is pressed against a cooler by a spring member. The spring member is compressed by a beam member that is connected with a strut fixed to the cooler. The cooler has a pressed part in which the semiconductor module is pressed, and a strut fixing part to which the strut is fixed. The strut fixing part has higher rigidity than the pressed part.Type: GrantFiled: March 26, 2014Date of Patent: February 24, 2015Assignee: Toyota Jidosha Kabushiki KaishaInventors: Takato Sato, Yukio Onishi, Hiroyuki Kono, Hiroaki Yoshizawa, Toshio Watari, Hiromi Yamasaki
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Patent number: 8879256Abstract: An electric power conversion apparatus includes a plurality of semiconductor modules, a frame, a control circuit board, and a reinforcing and fixing member. Each of the semiconductor modules has a plurality of control terminals. The frame receives the semiconductor modules therein. The frame has, at least, a pair of side walls that face each other with the semiconductor modules interposed therebetween. The control circuit board is located outside of the frame and has the control terminals of the semiconductor modules connected thereto. The reinforcing and fixing member extends to connect the side walls of the frame, thereby reinforcing the frame. The reinforcing and fixing member also has the control circuit board fixed thereto so that the reinforcing and fixing member is positioned between the control circuit board and the semiconductor modules.Type: GrantFiled: March 27, 2012Date of Patent: November 4, 2014Assignee: Denso CorporationInventors: Hiromi Ichijyo, Takahisa Kaneko, Takeshi Fujihara, Kenshiro Hida
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Patent number: 8860198Abstract: According to an exemplary embodiment, a dual compartment semiconductor package includes a conductive clip having first and second compartments. The first compartment is electrically and mechanically connected to a top surface of the first die. The second compartment electrically and mechanically connected to a top surface of a second die. The dual compartment semiconductor package also includes a groove formed between the first and second compartments, the groove preventing contact between the first and second dies. The dual compartment package electrically connects the top surface of the first die to the top surface of the second die. The first die can include an insulated-gate bipolar transistor (IGBT) and the second die can include a diode. A temperature sensor can be situated adjacent to, over, or within the groove for measuring a temperature of the dual compartment semiconductor package.Type: GrantFiled: January 23, 2014Date of Patent: October 14, 2014Assignee: International Rectifier CorporationInventor: Henning M. Hauenstein
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Patent number: 8796826Abstract: A device and method for minimizing the forces that may compromise a lead frame mount to a support structure in an integrated circuit die package during various packaging method steps. When a window clamp is used to provide pressure during a lead frame bonding step or during a wire bonding step during packaging, the vertical force applied by the window clamp may be transferred in lateral direction by the physical contour of the top plate of the support structure. By changing the physical contour of the top plate of the support structure, such as by disposing a specific kind of contoured protrusion, one may minimize or eliminate the lateral forces that act against achieving a solid bond of the lead frame to the support structure. Further, during wire bonding, the same minimization or elimination of lateral forces lead to improved wire bonding.Type: GrantFiled: December 22, 2011Date of Patent: August 5, 2014Assignee: STMicroelectronics Pte LtdInventors: Xueren Zhang, Kim-Yong Goh, Wingshenq Wong
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Patent number: 8797743Abstract: An electronic device mounted on a circuit board and accommodated in a housing includes a heat source element accommodated in the housing and mounted on the circuit board, and a heat conducting member accommodated in the housing. The heat conducting member is movably mounted on the circuit board. An elastic member fixes the heat source element and the heat conducting member in abutment with each other. The elasticity of the elastic member permits variations in the relative positions of the heat source element and the heat conducting member while maintaining the abutment of the heat source element and the heat conducting member.Type: GrantFiled: November 17, 2011Date of Patent: August 5, 2014Assignee: Aisin Aw Co., Ltd.Inventors: Yoichiro Taka, Masashi Takano, Tarou Aikawa
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Patent number: 8786077Abstract: Certain embodiments provide a semiconductor device including a first substrate, a circuit element, a second substrate, a metal layer, and a radiation plate. The circuit element is formed on a front surface of the first substrate and has an electrode. The second substrate has a first face, and is laminated on the first substrate so that the first face of the second substrate faces a front surface of the first substrate. The second substrate has a via hole arranged on the electrode. The metal layer is formed inside of the via hole. The radiation plate is formed on a second face of the second substrate, and is connected to the metal layer.Type: GrantFiled: December 21, 2011Date of Patent: July 22, 2014Assignee: Kabushiki Kaisha ToshibaInventor: Jeoungchill Shim
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Patent number: 8709870Abstract: A method of forming an integrated circuit (IC) package is disclosed comprising: (a) removing oxides from side surfaces of terminals of the IC package; (b) substantially covering an underside of the terminals of the IC package; and (c) forming a solder coating on the side surfaces of terminals of the IC packages while covering the underside of the terminals of the IC package. The solder coating on the side surfaces of the terminals protects the terminals from oxidation due to aging and subsequent processes. Additionally, the solder coating on the side surfaces of the terminals substantially improves the solderability of the IC package to printed circuit boards (PCBs) or other mountings. This further facilitates the inspection of the solder attachment using less expensive and complicated methods.Type: GrantFiled: January 15, 2010Date of Patent: April 29, 2014Assignee: Maxim Integrated Products, Inc.Inventor: Kenneth J. Huening
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Patent number: 8710644Abstract: A semiconductor unit of certain aspects of the invention includes electrically conductive plates in the shape of the letter L, each consisting of a horizontally disposed leg portion and a vertically disposed flat body portion that is perpendicular to a cooling plate adhered to the bottom of the semiconductor unit. A pair of the vertically disposed flat body portions sandwiches a semiconductor chip. Owing to this construction, the heat generated in the semiconductor chip can be conducted away through the both surfaces of the chip, thus improving cooling performance. Since the heat is conducted away through the leg portions of the L-shaped electrically conductive plates a projected planar area occupied by the cooling plate required for cooling the semiconductor unit is reduced. Therefore, the size of the semiconductor unit can be reduced.Type: GrantFiled: May 16, 2011Date of Patent: April 29, 2014Assignee: Fuji Electric Co., Ltd.Inventor: Kenichiro Sato
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Patent number: 8659130Abstract: A power module includes: a sealing body including a semiconductor element having a plurality of electrode surfaces, a first conductor plate connected to one electrode surface of the semiconductor element via solder, and a sealing material for sealing the semiconductor element and the first conductor plate, the sealing body having at least a first surface and a second surface on the opposite side of the first surface; and a case for housing the sealing body. The case is configured by a first heat radiation plate opposed to the first surface of the sealing body, a second heat radiation plate opposed to the second surface of the sealing body, and an intermediate member that connects the first heat radiation plate and the second heat radiation plate. The intermediate member has a first thin section having thickness smaller than the thickness of the first heat radiation plate, more easily elastically deformed than the first heat radiation plate, and formed to surround the first heat radiation plate.Type: GrantFiled: April 26, 2011Date of Patent: February 25, 2014Assignee: Hitachi Automotive Systems, Ltd.Inventors: Yusuke Takagi, Kaoru Uchiyama, Tokihito Suwa, Kinya Nakatsu, Takeshi Tokuyama, Shinji Hiramitsu
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Patent number: 8637981Abstract: According to an exemplary embodiment, a dual compartment semiconductor package includes a conductive clip having first and second compartments. The first compartment is electrically and mechanically connected to a top surface of the first die. The second compartment electrically and mechanically connected to a top surface of a second die. The dual compartment semiconductor package also includes a groove formed between the first and second compartments, the groove preventing contact between the first and second dies. The dual compartment package electrically connects the top surface of the first die to the top surface of the second die. The first die can include an insulated-gate bipolar transistor (IGBT) and the second die can include a diode. A temperature sensor can be situated adjacent to, over, or within the groove for measuring a temperature of the dual compartment semiconductor package.Type: GrantFiled: March 30, 2011Date of Patent: January 28, 2014Assignee: International Rectifier CorporationInventor: Henning M. Hauenstein
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Patent number: 8629555Abstract: A pressing portion of a fixture is put on a lid of a semiconductor package, and anchor portions on the opposite sides of the pressing portion are opposed to a baseplate. Two screw members are passed individually through opening parts formed spanning the pressing portion and anchor portions and threadedly engage with a heat sink through the baseplate. If the screw members are tightened in this state, the anchor portions are pressed by the baseplate, and the pressing portion presses the lid of the semiconductor package, whereby the baseplate is fixed to the heat sink in pressure contact with it.Type: GrantFiled: July 31, 2009Date of Patent: January 14, 2014Assignee: Kabushiki Kaisha ToshibaInventor: Tsuyoshi Hasegawa
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Patent number: 8531027Abstract: Systems and methods for utilizing power overlay (POL) technology and semiconductor press-pack technology to produce semiconductor packages with higher reliability and power density are provided. A POL structure may interconnect semiconductor devices within a semiconductor package, and certain embodiments may be implemented to reduce the probability of damaging the semiconductor devices during the pressing of the conductive plates. In one embodiment, springs and/or spacers may be used to reduce or control the force applied by an emitter plate onto the semiconductor devices in the package. In another embodiment, the emitter plate may be recessed to exert force on the POL structure, rather than directly against the semiconductor devices. Further, in some embodiments, the conductive layer of the POL structure may be grown to function as an emitter plate, and regions of the conductive layer may be made porous to provide compliance.Type: GrantFiled: April 30, 2010Date of Patent: September 10, 2013Assignee: General Electric CompanyInventors: Arun Virupaksha Gowda, Ahmed Elasser, Satish Sivarama Gunturi
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Patent number: 8519512Abstract: A semiconductor wafer structure includes a plurality of dies, a first scribe line extending along a first direction, a second scribe line extending along a second direction and intersecting the first scribe line, wherein the first and the second scribe lines have an intersection region. A test line is formed in the scribe line, wherein the test line crosses the intersection region. Test pads are formed in the test line and only outside a free region defined substantially in the intersection region.Type: GrantFiled: September 22, 2006Date of Patent: August 27, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hao-Yi Tsai, Chia-Lun Tsai, Shang-Yun Hou, Shin-Puu Jeng, Shih-Hsun Hsu, Wei-Ti Hsu, Lin-Ko Feng, Chun-Jen Chen
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Patent number: 8436429Abstract: A stacked power semiconductor device includes vertical metal oxide semiconductor field-effect transistors and dual lead frames packaged with flip-chip technology. In the method of manufacturing the stacked power semiconductor device, a first semiconductor chip is flip chip mounted on the first lead frame. A mounting clips is connected to the electrode at back side of the first semiconductor chip. A second semiconductor chip is mounted on the second lead frame, which is then flipped and stacked on the mounting clip.Type: GrantFiled: May 29, 2011Date of Patent: May 7, 2013Assignee: Alpha & Omega Semiconductor, Inc.Inventors: Yan Xun Xue, Yueh-Se Ho, Lei Shi, Jun Lu, Liang Zhao
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Patent number: 8415789Abstract: A wiring substrate has, on each of opposite faces thereof, connection pad portions to which various circuit elements are connected, and wiring traces for connecting the connection pad portions. The wiring substrate also has a through wiring portion for establishing mutual connection between the connection pad portions and the wiring traces on the front face and those on the back face. A post electrode component is formed such that it includes a plurality of post electrodes supported by a support portion. A semiconductor chip is attached to the back face of the wiring substrate, and is connected to the connection pad portions on the back face. After the post electrode component is fixed to and electrically connected to the wiring traces at predetermined positions, and resin sealing is performed, the support portion is separated so as to expose end surfaces of the post electrodes or back face wiring traces connected thereto.Type: GrantFiled: May 7, 2009Date of Patent: April 9, 2013Assignee: Kyushu Institute of TechnologyInventor: Masamichi Ishihara
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Patent number: 8381393Abstract: Methods of forming a microelectronic structure are described. Embodiments of those methods include attaching a patch to an interposer, forming at least one interconnect structure above and on a top surface of the interposer; and attaching a flex connector to the at least one interconnect structure.Type: GrantFiled: December 30, 2009Date of Patent: February 26, 2013Assignee: Intel CorporationInventors: Brent M. Roberts, Mihir K. Roy, Sriram Srinivasan, Sridhar Narasimhan
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Patent number: 8379390Abstract: A package substrate includes a circuit board, an electronic component, an electromagnetic shield cover, and a heat conducting member. The electronic component is disposed on the circuit board. The electromagnetic shield cover is fixedly coupled to the circuit board. The electromagnetic shield cover houses the electronic component within an inside space defined between the electromagnetic shield cover and the circuit board. The heat conducting member is disposed between the electronic component and the electromagnetic shield cover within the inside space. The heat conducting member contacts both of the electronic component and the electromagnetic shield cover such that the heat conducting member establishes a thermal connection between the electronic component and the electromagnetic shield cover.Type: GrantFiled: August 27, 2010Date of Patent: February 19, 2013Assignee: Funai Electric Co., Ltd.Inventor: Yoshihiko Inoue
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Patent number: 8379403Abstract: A spacer-connector and connection arrangements between daughter boards and motherboards are disclosed. Assemblies may include a daughter board one or more spacer-connectors spacing the daughter board above a motherboard and conductive elastomers providing electrical connections between the daughter board and spacer-connector and between the spacer-connector and the motherboard. The spacer-connector may include ground, power, digital and/or controlled impedance RF pathways to conduct signals between the daughter board to the mother board.Type: GrantFiled: March 30, 2010Date of Patent: February 19, 2013Assignee: QUALCOMM, IncorporatedInventors: David W. Waite, James L. Blair, Ashish Lohiya, Arvid G. Sammuli, Jeffrey T. Smith, Saritha Narra
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Patent number: 8373269Abstract: A device includes a lower jig and an upper jig, wherein the lower jig and the upper jig are configured to secure a package substrate. The lower jig includes a first base material and a first plurality of features attached to the first base material. The first plurality of features is disposed adjacent to a peripheral of the lower jig. The upper jig includes a second base material and a second plurality of features attached to the second base material. The second plurality of features is disposed adjacent to a peripheral of the upper jig. The first plurality of features is configured to be attracted to the second plurality of features by a magnetic force.Type: GrantFiled: September 8, 2011Date of Patent: February 12, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Li Hsiao, Chen-Hua Yu, Chung-Shi Liu, Chien Ling Hwang
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Patent number: 8368207Abstract: A pressure-contact power semiconductor module is arranged on a heat sink. The power semiconductor module is used with at least one substrate provided with conductor tracks and power semiconductor components. The module has a mounting body, on the underside of which the at least one substrate is arranged, and which is formed with cutouts. The module also includes a load connection element which is provided with contact feet that project away from strip sections and make pressure contact with the conductor tracks. The power semiconductor module additionally has a dimensionally stable cover, which covers the mounting body on all sides and is connected to the mounting body by means of snap-action latching connections. At least one pad element is restrained between the cover and the strip sections of the load connection elements.Type: GrantFiled: April 4, 2008Date of Patent: February 5, 2013Assignee: Semikron Elektronik GmbH & Co., KGInventors: Jürgen Steger, Frank Ebersberger
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Patent number: 8357942Abstract: In a semiconductor device by which peripheral circuit sections, such as a semiconductor element, a matching circuit section, a bias circuit section, a capacitor element, are placed on and connected to a substrate, the semiconductor element can be grounded, and the semiconductor device which can make heat radiation characteristics of the semiconductor element satisfactory is provided, without providing a via hole into a semiconductor substrate. It includes: a semiconductor element (2) placed on a substrate (1); peripheral circuit sections (30) and (40) placed on the substrate (1) and connected with the semiconductor element (2); an electrode (30e) provided in the peripheral circuit section (30) and grounded; an electrode (30s) for grounding connected to a metal layer (30m), a metal layer (30m) and a source electrode (2s) of the semiconductor element (2); and an electrode (30d) connected to a gate electrode (2g) of the semiconductor element (2).Type: GrantFiled: October 1, 2007Date of Patent: January 22, 2013Assignee: Kabushiki Kaisha ToshibaInventor: Kazutaka Takagi
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Patent number: 8344515Abstract: A semiconductor device includes a plurality of through vias extending through a substrate. The plurality of through vias are arranged dividedly in three or more via groups. Each of the via groups includes three or more of the through vias that are arranged in two dimensions.Type: GrantFiled: May 18, 2010Date of Patent: January 1, 2013Assignee: Panasonic CorporationInventors: Taichi Nishio, Hiroshige Hirano, Yukitoshi Ota
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Patent number: 8294263Abstract: A light-emitting diode packaging structure comprises a light-emitting diode and first and second metal plates on which the light-emitting diode is mounted. The light-emitting diodes includes first and second electrode leads, the second electrode lead having first and second contact surfaces on an outer edge of the second electrode lead. The first metal plate includes at least one clamping portion that clamps and fixes the first electrode lead on the first metal plate. The second metal plate includes at least first and second clamping portions. The first contact surface of the second electrode lead contacts the first clamping portion, and the second contact surface of the second electrode lead contacts the second clamping portion, such that the light-emitting diode is fixed on the second metal plate in at least two dimensions parallel to a primary surface of the second metal plate on which the light-emitting diodes is mounted.Type: GrantFiled: May 31, 2011Date of Patent: October 23, 2012Assignee: Everlight Electronics Co., Ltd.Inventors: Sheng-Jia Sheu, Chien-Chang Pei
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Patent number: 8283777Abstract: Flip chip packages having warpage control and methods for fabricating such packages are described. In one embodiment, the flip chip package comprises a package substrate; a chip coupled to the package substrate; and a ring structure coupled to the package substrate and positioned laterally around the periphery of the chip so that a surface of the chip is exposed, wherein the ring structure comprises one or more compressive members, each of the one or more compressive members compressively opposed to a surface of the package substrate to counter or absorb stresses in the package substrate.Type: GrantFiled: March 5, 2010Date of Patent: October 9, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Yao Lin, Wen-Yi Lin
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Patent number: 8278752Abstract: A microelectronic package includes first substrate (120) having first surface area (125) and second substrate (130) having second surface area (135). The first substrate includes first set of interconnects (126) having first pitch (127) at first surface (121) and second set of interconnects (128) having second pitch (129) at second surface (222). The second substrate is coupled to the first substrate using the second set of interconnects and includes third set of interconnects (236) having third pitch (237) and internal electrically conductive layers (233, 234) connected to each other with microvia (240). The first pitch is smaller than the second pitch, the second pitch is smaller than the third pitch, and the first surface area is smaller than the second surface area.Type: GrantFiled: December 23, 2009Date of Patent: October 2, 2012Assignee: Intel CorporationInventors: Brent M. Roberts, Mihir K. Roy, Sriram Srinivasan, Sridhar Narasimhan
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Patent number: 8269343Abstract: A semiconductor device in accordance with one embodiment of the invention can include a substrate onto which a wiring pattern is formed. In addition, the semiconductor device can include a plurality of semiconductor packages. Each semiconductor package can include a lead frame that is coupled to an electrode of a semiconductor chip. Each lead frame can be located on a side surface and a bottom surface of the semiconductor package. In addition, the semiconductor device can include a pressure-contact section for receiving the plurality of semiconductor packages and for causing the plurality of semiconductor packages to come into contact with the wiring pattern.Type: GrantFiled: September 19, 2008Date of Patent: September 18, 2012Assignee: Spansion LLCInventor: Kouichi Meguro
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Patent number: 8258622Abstract: Provided are a power device package coupled to a heat sink using a bolt and a semiconductor package mold for fabricating the same. The power device package includes: a substrate; at least one power device mounted on the substrate; a mold member sealing the substrate and the power device; and at least one bushing member fixed to the mold member to provide a through hole for a bolt member for coupling a heat sink to the mold member.Type: GrantFiled: January 29, 2008Date of Patent: September 4, 2012Assignee: Fairchild Korea Semiconductor, Ltd.Inventors: Keun-hyuk Lee, Seung-won Lim, Sung-min Park
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Patent number: 8233268Abstract: A housing comprising at least one electrical connection through a housing wall that is particularly inexpensive to produce and allows the electronic components located on the internal face and the external face of the housing to be attached in a particularly variable manner. The electrical connection is directly surrounded by housing material while being additionally sealed by means of sealing material. The inventive housing seal is provided with a profiled seal encompassing at least two sealing lips. The sealing material is additionally used for sealing the cover and/or the bottom relative to the housing wall. The arrangement is also particularly well protected against oil and other aggressive media as a combination of housing material and sealing material is used for surrounding the electrical connection.Type: GrantFiled: December 8, 2006Date of Patent: July 31, 2012Assignees: ZF Friedrichshanfen AG, Continental Automotive GmbH, Walter Soehner GmbH & Co. KGInventors: Robert Ingenbleek, Michael Schwab, Marc Abele, Thomas Betz, Rolf Zoeller, Andreas Rekofsky
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Patent number: 8208266Abstract: Shaped integrated passive devices and corresponding methodologies relate to construction and mounting of shaped passive devices on substrates so as to provide both mechanical and electrical connection. Certain components and component assemblies are associated with the implementation of surface mountable devices. Specially shaped integrated passive device are capable of providing simplified mounting on and simultaneous connection to selected electrical pathways on a printed circuit board or other mounting substrate. Shaped, plated side filter devices have plated sides which provide both mounting and grounding/power coupling functions. Thin film filters may be constructed on silicon wafers, which are then diced from the top surface with an angular dicing saw to produce a shaped groove in the top surface. The groove may be v-shaped or other shape, and is then plated with a conductive material. Individual pieces are separated by grinding the back surface of the wafer down to where the grooves are intercepted.Type: GrantFiled: May 13, 2008Date of Patent: June 26, 2012Assignee: AVX CorporationInventor: Gheorghe Korony
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Patent number: 8193618Abstract: A semiconductor die package. The semiconductor die package includes a leadframe structure comprising a first lead structure comprising a die attach pad, a second lead structure, and a third lead structure. It also includes a semiconductor die comprising a first surface and a second surface. The semiconductor die is on the die attach pad of the leadframe structure. The first surface is proximate the die attach pad. The semiconductor die package further includes a clip structure comprising a first interconnect structure and a second interconnect structure, the first interconnect structure comprising a planar portion and a protruding portion, the protruding portion including an exterior surface and side surfaces defining the exterior surface. The protruding portion extends from the planar portion of the first interconnect structure.Type: GrantFiled: December 12, 2008Date of Patent: June 5, 2012Assignee: Fairchild Semiconductor CorporationInventor: Ruben P. Madrid
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Patent number: 8188597Abstract: A fixture assembly and method of forming a chip assembly is provided. The fixture assembly includes a first plate having an opening sized to accommodate a chip mounted on a laminate. The fixture assembly further includes a second plate mated to the first plate by at least one mechanical fastening mechanism. The fixture assembly further includes a space defined by facing surfaces of the first plate and the second plate and confined by a raised stepped portion of at least one of the first plate and the second plate. The space is coincident with the opening. The space is sized and shaped such that the laminate is confined within the space and directly abuts the stepped portion and the facing surfaces of the first plate and the second plate to be confined in X, Y and Z directions.Type: GrantFiled: September 22, 2010Date of Patent: May 29, 2012Assignee: International Business Machines CorporationInventors: Thomas E. Lombardi, Donald Merte, Gregg B. Monjeau, David L. Questad, Son K. Tran
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Patent number: 8189324Abstract: A power electronic assembly includes a pair of thermally and electrically conductive plates, and semiconductor switching elements positioned between contact surfaces of the pair of conductive plates. A first of the semiconductor switching elements is positioned at a first region of the conductive plates, and a second of the semiconductor switching elements positioned at a second region of the conductive plates. At least one of the conductive plates includes an aperture positioned between the first region and the second region of the conductive plates, such that in a compressed state, a contact surface of the conductive plate associated with the first region is substantially parallel to and offset from that of the second region in a direction parallel to the direction of compression.Type: GrantFiled: December 7, 2009Date of Patent: May 29, 2012Assignee: American Superconductor CorporationInventor: Douglas C. Folts
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Patent number: 8149589Abstract: A holder for mounting multiple capacitors onto a circuit board includes a main structure and a plurality of latching member. The main structure has a top plate and a plurality of side plates. The top plate includes a plurality of holding slots, with the latching members off the side plates. Each latching member has an extension portion and an engaging member. The engaging member is located at the end of the extension under the bottom edge of the side plate. The capacitor includes a main body and a pair of electric leads at one end of the main body. At the opposite end of the electric leads, the main body is bounded on top by the top plate of the main structure, where the main body of each capacitor emerges partially above the upper surface of the top plate.Type: GrantFiled: August 19, 2010Date of Patent: April 3, 2012Assignee: Lien Chang Electronic Enterprise Co., Ltd.Inventors: Chun-Kong Chan, Chi-Ching Chen
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Patent number: 8125059Abstract: A highly flexible semiconductor device of a stacked-type semiconductor device which transfers information by inductive coupling between inductors, in which LSI chips can be stacked even when a transmitter circuit and a receiver circuit are arranged at different positions from each other when viewed in a stacking direction. The semiconductor device has an interposer including a first inductor which is inductively coupled with a transmitter circuit of a first LSI chip to be stacked, and a second inductor which is inductively coupled with a receiver circuit of a second LSI chip to be stacked, the first inductor and the second inductor being electrically connected. An interchip communication is made from the first LSI chip to the second LSI chip.Type: GrantFiled: October 29, 2009Date of Patent: February 28, 2012Assignee: Hitachi, Ltd.Inventors: Kiyoto Ito, Koji Hosogi, Takanobu Tsunoda
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Patent number: 8106507Abstract: Disclosed is a semiconductor package 3 including a socket 1 which is formed on the top surface 3a for enabling electrical conductivity and a connecting terminal 2 which is formed on the bottom surface 3b for enabling electrical conductivity. The socket 1a has a depressed shape, and a spiral contact 1 is formed in the depression 1c. An electronic circuit module is constructed by mounting and electrically connecting a semiconductor module wherein a plurality of semiconductor packages 3 is stacked on a circuit board. A circuit board with sockets is constructed by mounting a socket board on a circuit board.Type: GrantFiled: April 19, 2006Date of Patent: January 31, 2012Assignee: Advanced Systems Japan Inc.Inventor: Yukihiro Hirai
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Patent number: 8053663Abstract: A solar battery module as a panel-shaped semiconductor module comprises multiple spherical or nearly spherical, granular electric power generation semiconductor elements arranged in multiple rows and columns, a conductive connection mechanism electrically connecting in parallel multiple semiconductor elements in each row and connecting in series multiple semiconductor elements in each column, and a conductive inner metal case housing the multiple semiconductor elements and constituting the conductive connection mechanism, wherein each row of semiconductor elements is housed in each reflecting surface-forming groove of the inner metal case, the positive electrodes of the semiconductor electrodes are connected to the bottom plate and the negative electrodes are connected to finger leads, the bottom plate of each reflecting surface-forming grove has a cutoff slit, and the top is covered with a transparent cover member.Type: GrantFiled: July 7, 2006Date of Patent: November 8, 2011Assignees: Kyosemi Corporation, Energy Related Devices, Inc.Inventor: Josuke Nakata
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Patent number: 8030569Abstract: Multiple semiconductor elements in a semiconductor module in which multiple spherical light receiving or emitting semiconductor elements are installed can easily be retrieved, reused, or repaired. In a semiconductor module 60, two segment modules 61 are serially arranged in a storage casing 62. The segment modules 61 are each formed by molding solar battery cells 10 arranged in a matrix of multiple rows and columns, and a conductive connection mechanism serially-connecting the solar battery cells 10 in each column and parallel-connecting the solar battery cells 10 in each row in a synthetic resin with connection conductors 67 protruding at the ends. Conductive corrugated springs 70 and external terminals 76 are provided at the ends of the storage casing 62. The mechanical pressing force of the conductive corrugated springs 70 ensures that the two segment modules 61 are serially connected.Type: GrantFiled: January 11, 2006Date of Patent: October 4, 2011Assignee: Kyosemi CorporationInventor: Josuke Nakata
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Patent number: 7982308Abstract: A light-emitting diode packaging structure, a packaging module and the assembling method thereof are disclosed. The assembling method comprises the steps of: providing a light-emitting diode, wherein the light-emitting diode has two electrode leads; providing two metal plates, wherein each of the metal plates has at least a clamping portion; holding the electrode leads against the metal plates respectively; and bending the clamping portion of each of the metal plates to fix the electrode leads on the metal plates. Further, a plurality of light-emitting diodes are allowed to be mounted on the metal plates to form the light-emitting diode packaging module.Type: GrantFiled: March 19, 2008Date of Patent: July 19, 2011Assignee: Everlight Electronics Co., Ltd.Inventors: Sheng-Jia Sheu, Chien-Chang Pei
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Patent number: 7982331Abstract: A transfer switch assembly is disclosed that includes a power switch device with a number engagement landings and a printed circuit board defining an opening bordered by a number of tabs. The tabs engage the landings as the switch device extends through the openings, and can be fastened together.Type: GrantFiled: December 28, 2007Date of Patent: July 19, 2011Assignee: Cummins Power Generation IP, Inc.Inventors: Jerry Murray, Allen B. Carney, Randall L. Bax, Elias Ayana, Roger Pautzke, John McCarthy
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Patent number: RE49723Abstract: A power electronics assembly for an electric motor controller. The power electronics assembly comprises an insulated metal substrate, a composite material substrate, and a bolt having a bolt head and a bolt shaft for mechanically coupling the composite material substrate to the insulated metal substrate. The power electronics assembly also includes an electrically conductive sleeve configured to be held between a first electrical contact carried by the insulated metal substrate and a second electrical contact carried by the composite material substrate and the bolt is configured to clamp the composite material substrate to the insulated metal substrate to force the electrically conductive sleeve against the first electrical contact and the second electrical contact.Type: GrantFiled: September 21, 2021Date of Patent: November 7, 2023Assignee: Turntide Technologies, Inc.Inventors: Peter Barrass, Matt Jackson