With Electrical Isolation Means Patents (Class 257/725)
  • Patent number: 10109607
    Abstract: A device package includes a die, fan-out redistribution layers (RDLs) over the die, and an under bump metallurgy (UBM) over the fan-out RDLs. The UBM comprises a conductive pad portion and a trench encircling the conductive pad portion. The device package further includes a connector disposed on the conductive pad portion of the UBM. The fan-out RDLs electrically connect the connector and the UBM to the die.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: October 23, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Yu Chen, Hsien-Wei Chen, An-Jhih Su, Cheng-Hsien Hsieh
  • Patent number: 9793231
    Abstract: A device package includes a die, fan-out redistribution layers (RDLs) over the die, and an under bump metallurgy (UBM) over the fan-out RDLs. The UBM comprises a conductive pad portion and a trench encircling the conductive pad portion. The device package further includes a connector disposed on the conductive pad portion of the UBM. The fan-out RDLs electrically connect the connector and the UBM to the die.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: October 17, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Yu Chen, Hsien-Wei Chen, An-Jhih Su, Cheng-Hsien Hsieh
  • Patent number: 9219021
    Abstract: A semiconductor device includes a substrate serving as a base and having a surface on which electrodes are provided, a semiconductor chip mounted to the surface of the substrate, a sealing portion sealing the semiconductor chip and the surface of the substrate, first vias each penetrating the sealing portion in a thickness direction of the sealing portion to reach the electrodes on the surface of the substrate, external terminals connected to the first vias, and second vias provided near the semiconductor chip, extending to such a depth that the second vias do not penetrate the sealing portion, and insulated from the substrate and the semiconductor chip.
    Type: Grant
    Filed: December 2, 2014
    Date of Patent: December 22, 2015
    Assignee: Panasonic Corporation
    Inventors: Koichi Seko, Katsumi Otani, Katsuyoshi Matsumoto
  • Patent number: 9159892
    Abstract: An object of the invention is to provide an LED light source device and a manufacturing method for the same that can maintain high reflectance over an extended period of time notwithstanding the interaction between light and heat. More specifically, the invention provides an LED light source device that includes a substrate, an electrode formed on the substrate, a white inorganic resist layer deposited over the substrate so as to cover a surface thereof everywhere except where the electrode is formed, and an LED element connected to the electrode, wherein the white inorganic resist layer contains fine white inorganic particles dispersed or mixed into an inorganic binder, and a method for manufacturing such an LED light source device.
    Type: Grant
    Filed: July 1, 2011
    Date of Patent: October 13, 2015
    Assignees: CITIZEN HOLDINGS CO., LTD., CITIZEN ELECTRONICS CO., LTD.
    Inventors: Mizue Fukushima, Kenji Imazu, Hiroshi Tsukada, Ryo Tamura
  • Patent number: 9099567
    Abstract: An embodiment of a method of attaching a semiconductor die to a substrate includes placing a bottom surface of the die over a top surface of the substrate with an intervening die attach material. The method further includes contacting a top surface of the semiconductor die and the top surface of the substrate with a conformal structure that includes a non-solid, pressure transmissive material, and applying a pressure to the conformal structure. The pressure is transmitted by the non-solid, pressure transmissive material to the top surface of the semiconductor die. The method further includes, while applying the pressure, exposing the assembly to a temperature that is sufficient to cause the die attach material to sinter. Before placing the die over the substrate, conductive mechanical lock features may be formed on the top surface of the substrate, and/or on the bottom surface of the semiconductor die.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: August 4, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Lakshminarayan Viswanathan, L. M. Mahalingam, David F. Abdo, Jaynal A. Molla
  • Patent number: 9076664
    Abstract: A stacked semiconductor device includes a first, a second, a third, and a fourth semiconductor device. A first major surface of each of the first and second semiconductor devices which includes the active circuitry directly face each other, and a first major surface of each of the third and fourth semiconductor devices which includes the active circuitry directly face each other. A second major surface of the second semiconductor device directly faces a second major surface of the third semiconductor device. The stacked semiconductor device includes a plurality of continuous conductive vias, wherein each continuous conductive via extends from the second major surface of the first device, through the first device, second device, third device, and fourth device to the second major surface of the fourth device. Each of the semiconductor devices may include a beveled edge at the first major surface on at least one edge of the device.
    Type: Grant
    Filed: October 7, 2011
    Date of Patent: July 7, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Perry H. Pelley, Kevin J. Hess, Michael B. McShane
  • Patent number: 9026872
    Abstract: An integrated circuit (IC) structure can include a first die and a second die. The second die can include a first base unit and a second base unit. Each of the first base unit and the second base unit is self-contained and no signals pass between the first base unit and the second base unit within the second die. The IC structure can include an interposer. The interposer includes a first plurality of inter-die wires coupling the first die to the first base unit, a second plurality of inter-die wires coupling the first die to the second base unit, and a third plurality of inter-die wires coupling the first base unit to the second base unit.
    Type: Grant
    Filed: August 16, 2012
    Date of Patent: May 5, 2015
    Assignee: Xilinx, Inc.
    Inventor: Rafael C. Camarota
  • Patent number: 8987885
    Abstract: Microdevices and methods for packaging microdevices. One embodiment of a packaged microdevice includes a substrate having a mounting area, contacts in the mounting area, and external connectors electrically coupled to corresponding contacts. The microdevice also includes a die located across from the mounting area and spaced apart from the substrate by a gap. The die has an integrated circuit and pads electrically coupled to the integrated circuit. The microdevice further includes first and second conductive elements in the gap that form interconnects between the contacts of the substrate and corresponding pads of the die. The first conductive elements are electrically connected to contacts on the substrate, and the second conductive elements are electrically coupled to corresponding pads of the die.
    Type: Grant
    Filed: January 15, 2013
    Date of Patent: March 24, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Stuart L. Roberts, Tracy V. Reynolds, Rich Fogal, Matt E. Schwab
  • Patent number: 8987884
    Abstract: A device includes a first package component, and a second package component underlying the first package component. The second package component includes a first electrical connector at a top surface of the second package component, wherein the first electrical connector is bonded to the first package component. The second package component further includes a second electrical connector at the top surface of the second package component, wherein no package component is overlying and bonded to the second electrical connector.
    Type: Grant
    Filed: August 8, 2012
    Date of Patent: March 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Hsien-Wei Chen
  • Patent number: 8970046
    Abstract: A semiconductor package may include a substrate including a substrate connection terminal, at least one semiconductor chip stacked on the substrate and having a chip connection terminal, a first insulating layer covering at least portions of the substrate and the at least one semiconductor chip, and/or an interconnection penetrating the first insulating layer to connect the substrate connection terminal to the chip connection terminal. A semiconductor package may include stacked semiconductor chips, edge portions of the semiconductor chips constituting a stepped structure, and each of the semiconductor chips including a chip connection terminal; at least one insulating layer covering at least the edge portions of the semiconductor chips; and/or an interconnection penetrating the at least one insulating layer to connect to the chip connection terminal of each of the semiconductor chips.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: March 3, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young Lyong Kim, Taehoon Kim, Jongho Lee, Chul-Yong Jang
  • Patent number: 8963280
    Abstract: Semiconductor devices with reduced substrate defects and methods of manufacture are disclosed. The method includes forming a dielectric material on a substrate. The method further includes forming a shallow trench structure and deep trench structure within the dielectric material. The method further includes forming a material within the shallow trench structure and deep trench structure. The method further includes forming active areas of the material separated by shallow trench isolation structures. The shallow trench isolation structures are formed by: removing the material from within the deep trench structure and portions of the shallow trench structure to form trenches; and depositing an insulator material within the trenches.
    Type: Grant
    Filed: September 11, 2013
    Date of Patent: February 24, 2015
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 8963309
    Abstract: A semiconductor device includes a first substrate. A first semiconductor die is mounted to the first substrate. A bond wire electrically connects the first semiconductor die to the first substrate. A first encapsulant is deposited over the first semiconductor die, bond wire, and first substrate. The first encapsulant includes a penetrable, thermally conductive material. In one embodiment, the first encapsulant includes a viscous gel. A second substrate is mounted over a first surface of the first substrate. A second semiconductor die is mounted to the second substrate. The second semiconductor die is electrically connected to the first substrate. The first substrate is electrically connected to the second substrate. A second encapsulant is deposited over the first semiconductor die and second semiconductor die. An interconnect structure is formed on a second surface of the first substrate, opposite the first surface of the first substrate.
    Type: Grant
    Filed: July 13, 2011
    Date of Patent: February 24, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Byung Tai Do, Seng Guan Chow, Heap Hoe Kuan, Linda Pei Ee Chua, Rui Huang
  • Patent number: 8957497
    Abstract: Embodiments of the present invention provide an integrated circuit system including a first active layer fabricated on a front side of a semiconductor die and a second pre-fabricated layer on a back side of the semiconductor die and having electrical components embodied therein, wherein the electrical components include at least one discrete passive component. The integrated circuit system also includes at least one electrical path coupling the first active layer and the second pre-fabricated layer.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: February 17, 2015
    Assignee: Analog Devices, Inc.
    Inventors: Alan J. O'Donnell, Santiago Iriarte, Mark J. Murphy, Colin G. Lyden, Gary Casey, Eoin Edward English
  • Patent number: 8908345
    Abstract: In a stacked chip system, an IO circuit connected to a TSV pad for IO and a switch circuit constitute an IO channel in each chip, the IO channels as many as the maximum scheduled number of stacks are coupled together and connected to constitute an IO group, and the chip has one or more such IO groups. Each TSV pad for IO is connected with a through via to an IO terminal at the same position in a chip of another layer. On an interposer, if the actual number of stacks is less than the maximum scheduled number of stacks, connection pads for IO in adjacent IO groups on the interposer are connected via a conductor.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: December 9, 2014
    Assignee: Hitachi,Ltd.
    Inventors: Futoshi Furuta, Kenichi Osada
  • Patent number: 8896126
    Abstract: An integrated circuit package includes a first memory die having a first set of connections, a second memory die arranged adjacent to the first memory die, the second memory die having a second set of connections, a first substrate having a first opening and a second opening, the first substrate having a third set of connections to connect to the first set of connections of the first memory die via the first opening and a fourth set of connections to connect to the second set of connections of the second memory die via the second opening, and a second substrate having a first integrated circuit disposed thereon. The first substrate is connected to the second substrate with the first integrated circuit disposed between the first substrate and second substrate.
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: November 25, 2014
    Assignee: Marvell World Trade Ltd.
    Inventor: Sehat Setardja
  • Patent number: 8895357
    Abstract: Presented is an integrated circuit packaged at the wafer level wafer (also referred to as a wafer level chip scale package, WLCSP), and a method of manufacturing the same. The WLCSP comprises a die having an electrically conductive redistribution layer, RDL, formed above the upper surface of the die, the RDL defining a signal routing circuit. The method comprises the steps of: depositing the electrically conductive RDL so as to form an electrically conductive ring surrounding the signal routing circuit; and coating the side and lower surfaces of the die with an electrically conductive shielding material.
    Type: Grant
    Filed: April 4, 2013
    Date of Patent: November 25, 2014
    Assignee: NXP B.V.
    Inventors: Tonny Kamphuis, Leonardus Antonius Elisabeth van Gemert, Caroline Catharina Maria Beelen-Hendrikx
  • Patent number: 8890297
    Abstract: A light emitting device package according to embodiments comprises: a package body; a lead frame on the package body; a light emitting device supported by the package body and electrically connected with the lead frame; a filling material surrounding the light emitting device; and a phosphor layer comprising phosphors on the filling material.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: November 18, 2014
    Assignee: LG Innotek Co., Ltd.
    Inventors: Yu Ho Won, Geun Ho Kim
  • Patent number: 8878359
    Abstract: A plurality of semiconductor die is mounted to a temporary carrier. An encapsulant is deposited over the semiconductor die and carrier. A portion of the encapsulant is designated as a saw street between the die, and a portion of the encapsulant is designated as a substrate edge around a perimeter of the encapsulant. The carrier is removed. A first insulating layer is formed over the die, saw street, and substrate edge. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first conductive layer and first insulating layer. The encapsulant is singulated through the first insulating layer and saw street to separate the semiconductor die. A channel or net pattern can be formed in the first insulating layer on opposing sides of the saw street, or the first insulating layer covers the entire saw street and molding area around the semiconductor die.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: November 4, 2014
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Yaojian Lin, Kang Chen, Jianmin Fang, Xia Feng, Xusheng Bao
  • Patent number: 8846452
    Abstract: In one embodiment of the present invention, a method of forming a semiconductor device includes forming a device region in a first region of a semiconductor substrate, and forming an opening in a second region of the semiconductor substrate. The method further includes placing a semiconductor die within the opening, and forming a first metallization level over the semiconductor die and the device region.
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: September 30, 2014
    Assignee: Infineon Technologies AG
    Inventor: Dietrich Bonart
  • Patent number: 8836113
    Abstract: An electronic module. One embodiment includes a carrier. A first transistor is attached to the carrier. A second transistor is attached to the carrier. A first connection element includes a first planar region. The first connection element electrically connects the first transistor to the carrier. A second connection element includes a second planar region. The second connection element electrically connects the second transistor to the carrier. In one embodiment, a distance between the first planar region and the second planar region is smaller than 100 ?m.
    Type: Grant
    Filed: August 14, 2012
    Date of Patent: September 16, 2014
    Assignee: Infineon Technologies AG
    Inventors: Stefan Landau, Erwin Huber, Josef Hoeglauer, Joachim Mahler, Tino Karczeweski
  • Patent number: 8779562
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a bottom substrate; attaching a first integrated circuit die to the bottom substrate; forming an interposer including: forming an intermediate substrate; forming a shield on the intermediate substrate; and applying a wire-in-film adhesive to the shield; and attaching the interposer to the first integrated circuit die with the wire-in-film adhesive.
    Type: Grant
    Filed: March 24, 2011
    Date of Patent: July 15, 2014
    Assignee: STATS ChipPAC Ltd.
    Inventors: SeongMin Lee, Sungmin Song, SeongHun Mun
  • Patent number: 8779599
    Abstract: A device includes a bottom chip and an active top die bonded to the bottom chip. A dummy die is attached to the bottom chip. The dummy die is electrically insulated from the bottom chip.
    Type: Grant
    Filed: November 16, 2011
    Date of Patent: July 15, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Cheng-Lin Huang, Szu Wei Lu, Jui-Pin Hung, Shin-Puu Jeng, Chen-Hua Yu
  • Patent number: 8772087
    Abstract: Method and apparatus for semiconductor device fabrication using a reconstituted wafer is described. In one embodiment, diced semiconductor chips are placed within openings on a frame. A reconstituted wafer is formed by filling a mold compound into the openings. The mold compound is formed around the chips. Finished dies are formed within the reconstituted wafer. The finished dies are separated from the frame.
    Type: Grant
    Filed: October 22, 2009
    Date of Patent: July 8, 2014
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Barth, Matthias Hierlemann
  • Patent number: 8766434
    Abstract: The semiconductor module includes a plurality of memory die on a first side of a substrate and a plurality of buffer die on a second side of the substrate. Each of the memory die is disposed opposite and electrically coupled to one of the buffer die.
    Type: Grant
    Filed: January 16, 2013
    Date of Patent: July 1, 2014
    Assignee: Rambus Inc.
    Inventor: Frank Lambrecht
  • Patent number: 8759968
    Abstract: A semiconductor memory apparatus includes a first pad group located along a first edge of a plurality of banks, a second pad group located along a second edge of the plurality of banks opposite the first pad group, and a pad control section configured to provide first and second bonding signals and to implement control operation in response to a test mode signal and a bonding option signal to selectively employ signals from the first and second pad groups.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: June 24, 2014
    Assignee: SK hynix Inc.
    Inventor: Tae-Yong Lee
  • Patent number: 8749077
    Abstract: An embodiment 3DIC device includes a semiconductor chip, a die, and a polymer. The semiconductor chip includes a semiconductor substrate, wherein the semiconductor substrate comprises a first edge, and a low-k dielectric layer over the semiconductor substrate. The die is disposed over and bonded to the semiconductor chip. The polymer is molded onto the semiconductor chip and the die. The polymer includes a portion level with the low-k dielectric layer, wherein the portion of the polymer comprises a second edge vertically aligned to the first edge of the semiconductor substrate and a third edge contacting the low-k dielectric layer, wherein the second and the third edges are opposite edges of the portion of the polymer.
    Type: Grant
    Filed: July 23, 2013
    Date of Patent: June 10, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Wei Wu, Szu Wei Lu, Jing-Cheng Lin, Shin-Puu Jeng, Chen-Hua Yu
  • Patent number: 8736035
    Abstract: A semiconductor package includes a first package substrate, a first semiconductor chip disposed on the first package substrate, the semiconductor chip including first through hole vias, and a chip package disposed on the first semiconductor chip, the chip package including a second package substrate and a second semiconductor chip disposed on the second package substrate, wherein a first conductive terminal is disposed on a first surface of the semiconductor chip and a second conductive terminal is disposed on a first surface of the second package substrate, the first conductive terminal disposed on the second conductive terminal.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: May 27, 2014
    Assignee: Samsung Electronics Co. Ltd.
    Inventors: Tae-Joo Hwang, Tae-gyeong Chung, Eun-chul Ahn
  • Patent number: 8704384
    Abstract: A stacked die assembly for an IC includes a first interposer; a second interposer; a first integrated circuit die, a second integrated circuit die, and a plurality of components. The first integrated circuit die is interconnected to the first interposer and the second interposer, and the second integrated circuit die is interconnected to the second interposer. The plurality of components interconnect the first integrated circuit die to the first interposer and the second interposer. The plurality of components that interconnect the first integrated circuit die to the first interposer and the second interposer are located outside an interconnect restricted area of the first interposer and the second interposer, and signals are routed between the first integrated circuit die and the second integrated circuit die via the first integrated circuit die avoiding the interconnect restricted area of the first interposer and the second interposer.
    Type: Grant
    Filed: February 17, 2012
    Date of Patent: April 22, 2014
    Assignee: Xilinx, Inc.
    Inventors: Ephrem C. Wu, Raghunandan Chaware
  • Patent number: 8704364
    Abstract: An integrated circuit structure can include a first interposer and a second interposer. The first interposer and the second interposer can be coplanar. The integrated circuit structure further can include at least a first die that is coupled to the first interposer and the second interposer.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: April 22, 2014
    Assignee: Xilinx, Inc.
    Inventor: Bahareh Banijamali
  • Patent number: 8698304
    Abstract: A multi-chip package comprises a semiconductor chip stack structure comprising a semiconductor chip stack including a first semiconductor chip having a first power rating and a second semiconductor chip having a second power rating, the first and second semiconductor chips being stacked one on top of another; and a heat transfer blocking spacer interposed between the first semiconductor chip and the second semiconductor chip.
    Type: Grant
    Filed: May 11, 2007
    Date of Patent: April 15, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-wook Yoo, Eun-seok Cho, Heo-jung Hwang
  • Patent number: 8698283
    Abstract: A semiconductor package includes a substrate including a substrate body having a first face and a second face opposing the first face. A first through electrode passes through the substrate body between the first face and the second face. An insulation member is disposed over the first face; and a connection member having a first conductive unit disposed inside of the insulation member is electrically connected to the first through electrode, and a second conductive unit electrically connected to the first conductive unit is exposed at side faces of the insulation member. A semiconductor chip having third and fourth faces is disposed over the first face of the substrate body in a vertical direction. A second through electrode passes through the substrate body between the third and fourth faces and is electrically connected to the second conductive unit.
    Type: Grant
    Filed: September 25, 2012
    Date of Patent: April 15, 2014
    Assignee: SK Hynix Inc.
    Inventor: Min Suk Suh
  • Patent number: 8698323
    Abstract: A microelectronic assembly tolerant to misplacement of microelectronic elements therein may include a molded structure containing a plurality of microelectronic elements. Each microelectronic element has elements contacts having first and second dimensions in respective first and second directions that are transverse to each other, where the first dimension is at least twice the second dimension. In addition, the assembly may include a conductive redistribution layer including conductive vias extending through a dielectric layer to the element contacts of the respective microelectronic elements, where the conductive vias have a third dimension in a third direction and a fourth dimension in a fourth direction, and where the fourth direction is transverse to the third and first directions and the fourth dimension is greater than the third dimension.
    Type: Grant
    Filed: June 18, 2012
    Date of Patent: April 15, 2014
    Assignee: Invensas Corporation
    Inventors: Ilyas Mohammed, Belgacem Haba
  • Patent number: 8669656
    Abstract: An interconnect for transmitting an electric signal between electronic devices includes a first coupling element electromagnetically coupled to, and immediately juxtaposed to, a second coupling element. The first coupling element is mounted on and is electrically connected to a first electronic device having a first integrated circuit. The second coupling element may be mounted on and electrically connected to the first electronic device, and electrically connected to an interconnect on a second electronic device, or the second coupling element may be mounted on and electrically connected to the second electronic device.
    Type: Grant
    Filed: January 28, 2013
    Date of Patent: March 11, 2014
    Assignee: Scanimetrics Inc.
    Inventors: Steven Slupsky, Brian Moore, Christopher Sellathamby
  • Patent number: 8659149
    Abstract: Galvanic isolation between a high-voltage die and a low-voltage die in a multi-die chip is provided by a galvanic isolation die that physically supports the high-voltage die and the low-voltage die, and provides capacitive structures with high breakdown voltages that allow the high-voltage die to capacitively communicate with the low-voltage die.
    Type: Grant
    Filed: August 9, 2011
    Date of Patent: February 25, 2014
    Assignee: National Semiconductor Corporation
    Inventors: William French, Peter J. Hopper, Ann Gabrys
  • Patent number: 8643167
    Abstract: The present invention relates to a stacked semiconductor package and a method for making the same. The method includes the steps of mounting a plurality of first dice to a wafer by conducting a reflow process; and thinning the wafer from the backside surface of the wafer, thereby reducing manufacturing time and preventing warpage.
    Type: Grant
    Filed: December 5, 2011
    Date of Patent: February 4, 2014
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Chia-Lin Hung, Jen-Chuan Chen, Hui-Shan Chang, Kuo-Pin Yang
  • Patent number: 8624375
    Abstract: A semiconductor package includes: first, second, third and fourth semiconductor chips stacked while having the arrangement of chip selection vias; and a connection unit provided between a second semiconductor chip and a third semiconductor chip, and configured to mutually connect some of the chip selection vias of the second and third semiconductor chips and disconnect the others of the chip selection vias of the second and third semiconductor chips, wherein the first and second semiconductor chips and the third and fourth semiconductor chips are stacked in a flip chip type.
    Type: Grant
    Filed: December 29, 2010
    Date of Patent: January 7, 2014
    Assignee: SK Hynix Inc.
    Inventors: Bok Gyu Min, Joon Ki Hong, Tae Hoon Kim, Da Un Nah, Jae Joon Ahn, Ki Bum Kim
  • Patent number: 8618654
    Abstract: Embodiments of the present disclosure provide a method that comprises providing a first die having a surface comprising a bond pad to route electrical signals of the first die and attaching the first die to a layer of a substrate. The method further comprises forming one or more additional layers of the substrate to embed the first die in the substrate and coupling a second die to the one or more additional layers, the second die having a surface comprising a bond pad to route electrical signals of the second die. The second die is coupled to the one or more additional layers such that electrical signals are routed between the first die and the second die.
    Type: Grant
    Filed: July 15, 2011
    Date of Patent: December 31, 2013
    Assignee: Marvell World Trade Ltd.
    Inventors: Sehat Sutardja, Albert Wu, Scott Wu
  • Patent number: 8610255
    Abstract: A light emitting device package according to embodiments comprises: a package body; a lead frame on the package body; a light emitting device supported by the package body and electrically connected with the lead frame; a filling material surrounding the light emitting device; and a phosphor layer comprising phosphors on the filling material.
    Type: Grant
    Filed: July 4, 2008
    Date of Patent: December 17, 2013
    Assignee: LG Innotek Co., Ltd.
    Inventors: Yu Ho Won, Geun Ho Kim
  • Patent number: 8592973
    Abstract: A method of manufacture of an integrated circuit packaging system including: forming a top package including: providing a through silicon via interposer having a through silicon via; coupling a stacked integrated circuit die to the through silicon via, and testing a top package; forming a base package including: providing a substrate, coupling a base integrated circuit die to the substrate, and testing a base package; and coupling a stacked interconnect between the top package and the base package.
    Type: Grant
    Filed: October 16, 2009
    Date of Patent: November 26, 2013
    Assignee: STATS ChipPAC Ltd.
    Inventors: HyungSang Park, DeokKyung Yang, DaeSik Choi
  • Patent number: 8558380
    Abstract: A semiconductor package includes a first semiconductor chip having first bumps which are projectedly formed thereon; a first copper foil attachment resin covered on the first semiconductor chip to embed the first semiconductor chip, and formed such that a first copper foil layer attached on an upper surface of the first copper foil attachment resin is electrically connected with the first bumps; a second copper foil attachment resin including a second copper foil layer which is electrically connected with the first copper foil layer, and disposed on the first copper foil attachment resin; and a second semiconductor chip embedded in the second copper foil attachment resin in such a way as to face the first semiconductor chip, and having second bumps formed thereon which are electrically connected with the second copper foil layer.
    Type: Grant
    Filed: February 3, 2012
    Date of Patent: October 15, 2013
    Assignee: SK Hynix Inc.
    Inventors: Si Han Kim, Woong Sun Lee
  • Patent number: 8558374
    Abstract: An electronic package with two circuitized substrates which sandwich an interposer therebetween, the interposer electrically interconnecting the substrates while including at least one electrical component (e.g., a power module) substantially therein to provide even further operational capabilities for the resulting package.
    Type: Grant
    Filed: February 8, 2011
    Date of Patent: October 15, 2013
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Voya R. Markovich, Rabindra N. Das, Frank D. Egitto, James J. McNamara, Jr.
  • Patent number: 8546938
    Abstract: A stacked package and method of manufacture are provided. The stacked package may include a first semiconductor package, a second semiconductor package, plugs and spacers. The second semiconductor package may be stacked on the first semiconductor package. The plugs may electrically connect the first semiconductor to the second semiconductor package. The spacer may be interposed between the first semiconductor package and the second semiconductor package to form a gap between the first semiconductor package and the second semiconductor package, thereby preventing an electrical short between the plugs.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: October 1, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Geun Kim, Dong-Chul Han, Seok Goh, Jeong-Hoon Kim
  • Patent number: 8513794
    Abstract: A method is provided for fabricating a stacked microelectronic assembly by steps including stacking and joining first and second like microelectronic substrates, each including a plurality of like microelectronic elements attached together at dicing lanes. Each microelectronic element has boundaries defined by edges including a first edge and a second edge. The first and second microelectronic substrates can be joined in different orientations, such that first edges of microelectronic elements of the first microelectronic substrate are aligned with second edges of microelectronic elements of the second microelectronic substrate. After exposing traces at the first and second edges of the microelectronic elements of the stacked microelectronic substrates, first and second leads can be formed which are connected to the exposed traces of the first and second microelectronic substrates, respectively. The second leads can be electrically isolated from the first leads.
    Type: Grant
    Filed: October 17, 2011
    Date of Patent: August 20, 2013
    Assignee: Tessera, Inc.
    Inventors: Belgacem Haba, Ilyas Mohammed
  • Patent number: 8492889
    Abstract: A semiconductor package includes a substrate, a first semiconductor chip module attached to the substrate, a conductive connection member attached to the first semiconductor chip module, and a second semiconductor chip module attached to the conductive connection member. The first and second semiconductor chip modules are formed to have step like shapes to and extend laterally in opposite directions so as to define a zigzag arrangement together.
    Type: Grant
    Filed: February 1, 2013
    Date of Patent: July 23, 2013
    Assignee: SK Hynix Inc.
    Inventors: Jae Myun Kim, Seung Jee Kim, Ki Bum Kim
  • Patent number: 8436429
    Abstract: A stacked power semiconductor device includes vertical metal oxide semiconductor field-effect transistors and dual lead frames packaged with flip-chip technology. In the method of manufacturing the stacked power semiconductor device, a first semiconductor chip is flip chip mounted on the first lead frame. A mounting clips is connected to the electrode at back side of the first semiconductor chip. A second semiconductor chip is mounted on the second lead frame, which is then flipped and stacked on the mounting clip.
    Type: Grant
    Filed: May 29, 2011
    Date of Patent: May 7, 2013
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventors: Yan Xun Xue, Yueh-Se Ho, Lei Shi, Jun Lu, Liang Zhao
  • Patent number: 8432030
    Abstract: A power electronic package includes: first and second high thermal conductivity insulating non-planar substrates; and multiple semiconductor chips and electronic components between the substrates. Each substrate includes multiple electrical insulator layers and patterned electrical conductor layers connecting to the electronic components, and further includes multiple raised regions or posts, which are bonded together so that the substrates are mechanically and electrically connected. The number, arrangement, and shape of the raised regions or posts are adjusted to have mechanical separation between the substrates. The electrical conductor layers are separated and isolated one another so that multiple electric circuits are provided on at least one of the substrates.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: April 30, 2013
    Assignees: DENSO CORPORATION, University of Cambridge, The University of Sheffield
    Inventors: Rajesh Kumar Malhan, C Mark Johnson, Cyril Buttay, Jeremy Rashid, Florin Udrea
  • Patent number: 8427844
    Abstract: Disclosed herein are various embodiments of widebody coil isolators containing multiple coil transducers, where integrated circuits are not stacked vertically over the coil transducers. The disclosed coil isolators provide high voltage isolation and high voltage breakdown performance characteristics in small packages that provide a high degree of functionality at a low price.
    Type: Grant
    Filed: March 31, 2010
    Date of Patent: April 23, 2013
    Assignee: Avago Technologies ECBU IP (Singapore) Pte. Ltd.
    Inventors: Dominique Ho, Julie Fouquet
  • Patent number: 8421211
    Abstract: A wafer level semiconductor package is provided. A warpage control barrier line formed in every package of a single wafer prevents wafer from warping. The changed shape of the interface between a semiconductor chip and a molding layer at the edge of the package disperses stress applied to the outside of the package, and suppress the generation and propagation of crack. The size of the package is reduced to that of the semiconductor, and the thickness of the package is minimized.
    Type: Grant
    Filed: June 27, 2010
    Date of Patent: April 16, 2013
    Assignee: Nepes Corporation
    Inventors: In Soo Kang, Gi Jo Jung, Byoung Yool Jeon
  • Patent number: 8415783
    Abstract: A packaged integrated circuit (“IC”) has a daughter IC die stacked on a backside of a parent IC die. Backside fill material is applied to the backside of the parent IC die to provide a planarized surface.
    Type: Grant
    Filed: October 4, 2007
    Date of Patent: April 9, 2013
    Assignee: Xilinx, Inc.
    Inventors: Arifur Rahman, Raghunandan Chaware
  • Patent number: 8390114
    Abstract: A semiconductor package includes a substrate, a first semiconductor chip module attached to the substrate, a conductive connection member attached to the first semiconductor chip module, and a second semiconductor chip module attached to the conductive connection member. The first and second semiconductor chip modules are formed to have step like shapes to and extend laterally in opposite directions so as to define a zigzag arrangement together.
    Type: Grant
    Filed: July 14, 2010
    Date of Patent: March 5, 2013
    Assignee: SK Hynix Inc.
    Inventors: Jae Myun Kim, Seung Jee Kim, Ki Bum Kim