Device Held In Place By Clamping Patents (Class 257/727)
  • Patent number: 8709870
    Abstract: A method of forming an integrated circuit (IC) package is disclosed comprising: (a) removing oxides from side surfaces of terminals of the IC package; (b) substantially covering an underside of the terminals of the IC package; and (c) forming a solder coating on the side surfaces of terminals of the IC packages while covering the underside of the terminals of the IC package. The solder coating on the side surfaces of the terminals protects the terminals from oxidation due to aging and subsequent processes. Additionally, the solder coating on the side surfaces of the terminals substantially improves the solderability of the IC package to printed circuit boards (PCBs) or other mountings. This further facilitates the inspection of the solder attachment using less expensive and complicated methods.
    Type: Grant
    Filed: January 15, 2010
    Date of Patent: April 29, 2014
    Assignee: Maxim Integrated Products, Inc.
    Inventor: Kenneth J. Huening
  • Patent number: 8710644
    Abstract: A semiconductor unit of certain aspects of the invention includes electrically conductive plates in the shape of the letter L, each consisting of a horizontally disposed leg portion and a vertically disposed flat body portion that is perpendicular to a cooling plate adhered to the bottom of the semiconductor unit. A pair of the vertically disposed flat body portions sandwiches a semiconductor chip. Owing to this construction, the heat generated in the semiconductor chip can be conducted away through the both surfaces of the chip, thus improving cooling performance. Since the heat is conducted away through the leg portions of the L-shaped electrically conductive plates a projected planar area occupied by the cooling plate required for cooling the semiconductor unit is reduced. Therefore, the size of the semiconductor unit can be reduced.
    Type: Grant
    Filed: May 16, 2011
    Date of Patent: April 29, 2014
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Kenichiro Sato
  • Patent number: 8698288
    Abstract: A semiconductor device includes first and second flexible substrates each with first and second peripheral edges. First and second dies are attached on respective surfaces of the flexible substrates and are each respectively electrically connected to first and second metal traces. A first crimping structure electrically connects the first metal traces to the second metal traces and crimps together the first peripheral edges of the first and second substrates. A second crimping structure electrically connects the first metal traces to the second metal traces and crimps together the second peripheral edges of the first and second substrates.
    Type: Grant
    Filed: May 23, 2013
    Date of Patent: April 15, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Boon Yew Low, Navas Khan Oratti Kalandar, Sharon Huey Lin Tay
  • Patent number: 8659902
    Abstract: The invention relates to an electronic module (2) comprising: an electronic card (4) on which electronic components (10) are disposed, two covers (6, 8), disposed on either side of the card (4). The cover (6) facing the components (10) has a central part (22) extending at a distance from the card (4) and a flanged edge (24) turned toward the card (4), prolonging one of the two opposite sides of the central part (22). This flanged edge (24) is prolonged by a flat support (26), extending in a plane parallel to the plane of the electronic card (4), the card (4) being added onto the said support (26). The covers (6, 8) bear indexing means (34), the electronic card (4) having indexing holes (36) cooperating with the indexing means (34) during positioning of the card (4) between the covers (6, 8).
    Type: Grant
    Filed: February 18, 2011
    Date of Patent: February 25, 2014
    Assignee: Airbus Operations S.A.S.
    Inventors: Emile Colongo, Olivier Roujean
  • Patent number: 8659150
    Abstract: A semiconductor module that can be connected with simple wiring is provided. A semiconductor device of the semiconductor module is provided with a semiconductor substrate, a first electrode formed on one surface of the semiconductor substrate, and a second electrode formed on a surface of the semiconductor substrate opposite to the one surface. The semiconductor module is provided with a first electrode plate being in contact with the first electrode, a second electrode plate being in contact with the second electrode, and a first wiring member connected to the second electrode plate and penetrating the first electrode plate in a state of being insulated from the first electrode plate. The first electrode plate, the semiconductor device, and the second electrode plate are fixed with each other by an application of a pressure pressurizing the semiconductor device on the first electrode plate and the second electrode plate.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: February 25, 2014
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventor: Makoto Imai
  • Patent number: 8659130
    Abstract: A power module includes: a sealing body including a semiconductor element having a plurality of electrode surfaces, a first conductor plate connected to one electrode surface of the semiconductor element via solder, and a sealing material for sealing the semiconductor element and the first conductor plate, the sealing body having at least a first surface and a second surface on the opposite side of the first surface; and a case for housing the sealing body. The case is configured by a first heat radiation plate opposed to the first surface of the sealing body, a second heat radiation plate opposed to the second surface of the sealing body, and an intermediate member that connects the first heat radiation plate and the second heat radiation plate. The intermediate member has a first thin section having thickness smaller than the thickness of the first heat radiation plate, more easily elastically deformed than the first heat radiation plate, and formed to surround the first heat radiation plate.
    Type: Grant
    Filed: April 26, 2011
    Date of Patent: February 25, 2014
    Assignee: Hitachi Automotive Systems, Ltd.
    Inventors: Yusuke Takagi, Kaoru Uchiyama, Tokihito Suwa, Kinya Nakatsu, Takeshi Tokuyama, Shinji Hiramitsu
  • Patent number: 8637981
    Abstract: According to an exemplary embodiment, a dual compartment semiconductor package includes a conductive clip having first and second compartments. The first compartment is electrically and mechanically connected to a top surface of the first die. The second compartment electrically and mechanically connected to a top surface of a second die. The dual compartment semiconductor package also includes a groove formed between the first and second compartments, the groove preventing contact between the first and second dies. The dual compartment package electrically connects the top surface of the first die to the top surface of the second die. The first die can include an insulated-gate bipolar transistor (IGBT) and the second die can include a diode. A temperature sensor can be situated adjacent to, over, or within the groove for measuring a temperature of the dual compartment semiconductor package.
    Type: Grant
    Filed: March 30, 2011
    Date of Patent: January 28, 2014
    Assignee: International Rectifier Corporation
    Inventor: Henning M. Hauenstein
  • Patent number: 8637977
    Abstract: A method and apparatus of packaging a semiconductor device with a clip is disclosed. The clip defines a first contact region and a second contact region on a same face of the at least one clip. The chip defines a first face, and a second face opposite to the first face, the first contact region being attached to the first face of the chip and the second contact region being located within a same plane with the second face of the clip.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: January 28, 2014
    Assignee: Infineon Technologies AG
    Inventors: Boon Huat Lim, Chee Chian Lim, Yoke Chin Goh
  • Patent number: 8629555
    Abstract: A pressing portion of a fixture is put on a lid of a semiconductor package, and anchor portions on the opposite sides of the pressing portion are opposed to a baseplate. Two screw members are passed individually through opening parts formed spanning the pressing portion and anchor portions and threadedly engage with a heat sink through the baseplate. If the screw members are tightened in this state, the anchor portions are pressed by the baseplate, and the pressing portion presses the lid of the semiconductor package, whereby the baseplate is fixed to the heat sink in pressure contact with it.
    Type: Grant
    Filed: July 31, 2009
    Date of Patent: January 14, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tsuyoshi Hasegawa
  • Patent number: 8610265
    Abstract: An electrical interconnect for providing a temporary interconnect between terminals on an IC device and contact pads on a printed circuit board (PCB). The electrical interconnect includes a substrate with a first surface having a plurality of openings arranged to correspond to the terminals on the IC device. A compliant material is located in the openings. A plurality of conductive traces extend along the first surface of the substrate and onto the compliant material. The compliant material provides a biasing force that resists flexure of the conductive traces into the openings. Conductive structures are electrically coupled to the conductive traces over the openings. The conductive structures are adapted to enhance electrical coupling with the terminals on the IC device. Vias electrically extending through the substrate couple the conductive traces to PCB terminals located proximate a second surface of the substrate.
    Type: Grant
    Filed: April 17, 2012
    Date of Patent: December 17, 2013
    Assignee: Hsio Technologies, LLC
    Inventor: James Rathburn
  • Patent number: 8564117
    Abstract: The present invention is an apparatus for integrating multiple devices. The apparatus includes a substrate having a first via and a second via, a semiconductor chip positioned on a top portion of the substrate and positioned between the first via and the second via, first and second bumps positioned on the semiconductor chip, and an interposer wafer having a first interposer spring assembly and a second interposer spring assembly, the first interposer spring assembly having a first interposer spring and a first electrical connection attached to the first interposer spring, and the second interposer spring assembly having a second interposer spring and a second electrical connection attached to the second interposer spring.
    Type: Grant
    Filed: April 9, 2012
    Date of Patent: October 22, 2013
    Assignee: Toyota Motor Engineering & Manufacturing North America, Inc.
    Inventors: Sang Won Yoon, Koji Shiozaki
  • Patent number: 8519537
    Abstract: A 3D semiconductor package using an interposer is provided. In an embodiment, an interposer is provided having a first die electrically coupled to a first side of the interposer and a second die electrically coupled to a second side of the interposer. The interposer is electrically coupled to an underlying substrate, such as a packaging substrate, a high-density interconnect, a printed circuit board, or the like. The substrate has a cavity such that the second die is positioned within the cavity. The use of a cavity may allow smaller conductive bumps to be used, thereby allowing a higher number of conductive bumps to be used. A heat sink may be placed within the cavity to aid in the dissipation of the heat from the second die.
    Type: Grant
    Filed: June 10, 2010
    Date of Patent: August 27, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shin-Puu Jeng, Kim Hong Chen, Shang-Yun Hou, Chao-Wen Shih, Cheng-Chieh Hsieh, Chen-Hua Yu
  • Patent number: 8502365
    Abstract: According to one embodiment, a semiconductor device includes a casing, a semiconductor element, a terminal and a screw member. The semiconductor element is housed within the casing. The terminal is electrically connected to the semiconductor element, and has an externally projecting part extending out of the casing. The screw member is movably provided along a surface of the casing between the externally projecting part and the casing, and fixes an external terminal to the externally projecting part.
    Type: Grant
    Filed: March 18, 2011
    Date of Patent: August 6, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazuaki Onishi
  • Patent number: 8498118
    Abstract: A mounting assembly includes a circuit board, a securing member and a heat dissipating device. A retainer is located on the circuit board. The securing member includes a positioning portion and a claw connected to the positioning portion. The heat dissipating device includes a base attached to the circuit board and a number of fins perpendicularly located on the base. The number of fins defines a number of first air paths and a number of second air paths substantially perpendicular to the number of first air paths. The positioning portion is received in at least one of the number of first air paths and at least one of the number of second air paths, and the claw is engaged with the retainer.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: July 30, 2013
    Assignees: Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.
    Inventors: Tao Wang, Jian Fu, Zhi-Jiang Yao, Li-Fu Xu
  • Patent number: 8487429
    Abstract: A multi-chip module (MCM) is described. This MCM includes two substrates, having facing surfaces, which are mechanically coupled. Disposed on a surface of a first of these substrates, there is a negative feature, which is recessed below this surface. A positive feature in the MCM, which includes an assembly material other than a bulk material in the substrates, at least in part mates with the negative feature. For example, the positive feature may be disposed on the surface of the other substrate. Alternatively, prior to assembly of the MCM, the positive feature may be a separate component from the substrates (such as a micro-sphere). Note that the assembly material has a bulk modulus that is less than a bulk modulus of the material in the substrates. Furthermore, at least a portion of the positive feature may have been sacrificed when the mechanical coupling was established.
    Type: Grant
    Filed: September 22, 2009
    Date of Patent: July 16, 2013
    Assignee: Oracle America, Inc.
    Inventors: Jing Shi, David C. Douglas
  • Patent number: 8486757
    Abstract: A method and apparatus of packaging a semiconductor device with a clip is disclosed. The clip defines a first contact region and a second contact region on a same face of the at least one clip. The chip defines a first face, and a second face opposite to the first face, the first contact region being attached to the first face of the chip and the second contact region being located within a same plane with the second face of the clip.
    Type: Grant
    Filed: November 25, 2009
    Date of Patent: July 16, 2013
    Assignee: Infineon Technologies AG
    Inventors: Boon Huat Lim, Chee Chian Lim, Yoke Chin Goh
  • Patent number: 8456836
    Abstract: A lock includes an assembly of a slot engaging member insertable in a slot of a piece of equipment being locked, such as a portable or desktop computer, a laptop, notebook or other handheld electronic device, a monitor, a television/video screen, a video game, an electronic instrument such as an oscillator or a medical centrifuge or other analytical device, or the like. A rotatable locking member engages an anchor sub-assembly having a rotatable element, wherein the rotatable element communicates with a spring force urging against the rotatable locking member. The rotatable locking member is alternately movable in and out of the slot in which it is inserted, and the locking element is rotatable by finger force overcoming said spring force against the locking member, wherein the lock is locked without use of a tool.
    Type: Grant
    Filed: May 23, 2012
    Date of Patent: June 4, 2013
    Assignee: Think Products, Inc.
    Inventors: Peter Allen, Andrzej Marszalek
  • Patent number: 8379403
    Abstract: A spacer-connector and connection arrangements between daughter boards and motherboards are disclosed. Assemblies may include a daughter board one or more spacer-connectors spacing the daughter board above a motherboard and conductive elastomers providing electrical connections between the daughter board and spacer-connector and between the spacer-connector and the motherboard. The spacer-connector may include ground, power, digital and/or controlled impedance RF pathways to conduct signals between the daughter board to the mother board.
    Type: Grant
    Filed: March 30, 2010
    Date of Patent: February 19, 2013
    Assignee: QUALCOMM, Incorporated
    Inventors: David W. Waite, James L. Blair, Ashish Lohiya, Arvid G. Sammuli, Jeffrey T. Smith, Saritha Narra
  • Patent number: 8373259
    Abstract: A system includes an optical transceiver assembly, including a flip chip connection of a semiconductor die with a photonic transceiver that overhangs a substrate to which it is to be connected. The assembly further includes an alignment pin that is held to the semiconductor die at a micro-engineered structure in the semiconductor die. The alignment pin provides passive alignment of the photonic transceiver with an optical lens that interfaces the photonic transceiver to one or more optical channels.
    Type: Grant
    Filed: July 27, 2010
    Date of Patent: February 12, 2013
    Assignee: Intel Corporation
    Inventors: Brian H. Kim, Simon S. Lee
  • Patent number: 8373269
    Abstract: A device includes a lower jig and an upper jig, wherein the lower jig and the upper jig are configured to secure a package substrate. The lower jig includes a first base material and a first plurality of features attached to the first base material. The first plurality of features is disposed adjacent to a peripheral of the lower jig. The upper jig includes a second base material and a second plurality of features attached to the second base material. The second plurality of features is disposed adjacent to a peripheral of the upper jig. The first plurality of features is configured to be attracted to the second plurality of features by a magnetic force.
    Type: Grant
    Filed: September 8, 2011
    Date of Patent: February 12, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Li Hsiao, Chen-Hua Yu, Chung-Shi Liu, Chien Ling Hwang
  • Patent number: 8363405
    Abstract: A heat dissipation device is used for heat dissipating for an electronic element. The heat dissipation device includes a heat sink and a buffer arranged between the heat sink and the electronic element. The buffer is made of elastic and thermally conductive material.
    Type: Grant
    Filed: October 15, 2010
    Date of Patent: January 29, 2013
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventor: Zhi-Bin Guan
  • Patent number: 8338955
    Abstract: An integrated circuit package comprising an enclosure including a dielectric housing, a first electrical contact, and a second electrical contact. The dielectric housing, the first electrical contact, and the second electrical contact are configured to form a contact side of the enclosure. In addition, the first and second electrical contacts are sized to be substantially alignment insensitive for electro-mechanical connection to corresponding contacts of an end-use equipment. The enclosure encapsulates an integrated circuit die which is electrically coupled to the first and second electrical contacts. The alignment insensitive first and second electrical contacts may be electro-mechanically connected to corresponding contacts of an end-use equipment (e.g., a printer). Further, the integrated circuit package may be hosted by a peripheral device (e.g., a printer cartridge).
    Type: Grant
    Filed: April 5, 2007
    Date of Patent: December 25, 2012
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Jeff Alan Gordon, Steven Hass, Hal Kurkowski, Scott Jones
  • Patent number: 8338944
    Abstract: A semiconductor device includes a semiconductor module that has a joint surface, a first fitting portion and a second fitting portion provided on the joint surface of the semiconductor module, the second fitting portion having a shape different from the first fitting portion; and a radiating fin that has a joint surface, a third fitting portion and a fourth fitting portion provided on the joint surface of the radiating fin, the fourth fitting portion having a shape different from the third fitting portion. The semiconductor module is bonded to the radiating fin so that the first fitting portion is fitted into the third fitting portion or the third fitting portion is fitted into the first fitting portion, and the second fitting portion is fitted into the fourth fitting portion or the fourth fitting portion is fitted into the second fitting portion.
    Type: Grant
    Filed: November 23, 2009
    Date of Patent: December 25, 2012
    Assignee: Mitsubishi Electric Corporation
    Inventor: Takuya Shiraishi
  • Patent number: 8304867
    Abstract: An integrated circuit (IC) device includes a substrate having a top surface including active circuitry including a plurality of I/O nodes, and a plurality of die pads coupled to the plurality of I/O nodes. A first dielectric layer including first dielectric vias is over the plurality of die pads. A redirect layer (RDL) including a plurality of RDL capture pads is coupled to the plurality of die pads over the first dielectric vias. A second dielectric layer including second dielectric vias is over the plurality of RDL capture pads. At least one of the second dielectric vias is a crack arrest via that has a via shape that includes an apex that faces away from a neutral stress point of the IC die and is oriented along a line from the neutral stress point to the crack arrest via to face in a range of ±30 degrees from the line. Under bump metallization (UBM) pads are coupled to the plurality of RDL capture pads over the second dielectric vias, and metal bonding connectors are on the UBM pads.
    Type: Grant
    Filed: November 1, 2010
    Date of Patent: November 6, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Robert Fabian McCarthy, Stanley Craig Beddingfield
  • Patent number: 8283777
    Abstract: Flip chip packages having warpage control and methods for fabricating such packages are described. In one embodiment, the flip chip package comprises a package substrate; a chip coupled to the package substrate; and a ring structure coupled to the package substrate and positioned laterally around the periphery of the chip so that a surface of the chip is exposed, wherein the ring structure comprises one or more compressive members, each of the one or more compressive members compressively opposed to a surface of the package substrate to counter or absorb stresses in the package substrate.
    Type: Grant
    Filed: March 5, 2010
    Date of Patent: October 9, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Yao Lin, Wen-Yi Lin
  • Patent number: 8274798
    Abstract: A carrier substrate includes a substrate having a chip side and a PCB side, a plurality of bond pads disposed on the chip side for bonding a chip, a plurality of land grid array (LGA) pads disposed on the PCB side, and a plurality of resilient flanges installed on the PCB side in an array manner. The plurality of resilient flanges electrically connects with the LGA pads correspondingly.
    Type: Grant
    Filed: July 28, 2010
    Date of Patent: September 25, 2012
    Assignee: Unimicron Technology Corp.
    Inventors: Shih-Jung Huang, Wen-Fang Liu, Ling-Kai Su
  • Patent number: 8274793
    Abstract: A heatsink mounting system (10) is provided for containing and engaging a heatsink (16) against a heat generating component, typically an IC chip (18). The system (10) is includes a rectangular integrally formed resilient frame (12) defining a cavity (26) in which the heatsink (16) is contained. The frame (12) includes a pair of opposed lateral sides (30) and a pair of opposing gripping sides (28) with L-shaped corner blocks (32) depending from the intersections thereof. The gripping sides (28) include centrally positioned grip handles (38) with curved handle posts (39) extending upward and grip blocks (34) depending therefrom, each grip block (34) having a grip tongue (36) at the lower extent thereof extending inward into the cavity (26). Inward pressure on the grip handles (38) forces the grip tongues (36) outward to release objects captured thereby.
    Type: Grant
    Filed: August 27, 2010
    Date of Patent: September 25, 2012
    Assignee: Intricast Company, Inc.
    Inventors: Fang Wang, Thierry Sin Yan Too, Jim Moore, Mong Hu
  • Patent number: 8258622
    Abstract: Provided are a power device package coupled to a heat sink using a bolt and a semiconductor package mold for fabricating the same. The power device package includes: a substrate; at least one power device mounted on the substrate; a mold member sealing the substrate and the power device; and at least one bushing member fixed to the mold member to provide a through hole for a bolt member for coupling a heat sink to the mold member.
    Type: Grant
    Filed: January 29, 2008
    Date of Patent: September 4, 2012
    Assignee: Fairchild Korea Semiconductor, Ltd.
    Inventors: Keun-hyuk Lee, Seung-won Lim, Sung-min Park
  • Patent number: 8238103
    Abstract: An electronic component unit includes: a substrate; an electronic component mounted on the surface of the substrate; a heat dissipating member received on the electronic component; a cylinder member having one end coupled to the substrate, the cylinder member having the other end defining an opening opposed to the heat dissipating member; and a piston member having one end coupled to the heat dissipating member, the piston member having the other end inserted in the cylinder member through the opening to establish a closed decompressed space inside the cylinder member.
    Type: Grant
    Filed: May 15, 2009
    Date of Patent: August 7, 2012
    Assignee: Fujitsu Limited
    Inventor: Takashi Urai
  • Patent number: 8238110
    Abstract: The invention concerns an anti-interference advice for a housing (1) including at least two electrically conductive terminals (32, 33) distinctly positioned on an electronic card (30) and connected to processing means, a protective circuit (45) positioned relative to the two electrically conductive terminals (32, 33) in such a manner as to close the electrical circuit during the normal utilization position of the housing (1), the protective circuit (45), including means adapted for opening the electrical circuit closed in response to a deterioration in the protective circuit (45).
    Type: Grant
    Filed: May 31, 2007
    Date of Patent: August 7, 2012
    Assignee: Ingenico France
    Inventors: Eric Bonnet, Gary Didier, Lilian Vassy
  • Patent number: 8232632
    Abstract: An electrical interconnect assembly for electrically interconnecting terminals on a first circuit member with terminals on a second circuit member. The electrical interconnect assembly includes a housing having a plurality of through openings extending between a first surface and a second surface. A plurality of composite contacts are positioned in a plurality of the through openings. The composite contacts include a conductive member having a central portion and at least first and second interface portions. One or more polymeric layers extend along at least the central portion conductive member. One or more coupling features on the composite contacts engage with the housing. At least one engagement feature formed in the polymeric layers proximate the first interface portion mechanically couples with the terminals on the first circuit member.
    Type: Grant
    Filed: October 20, 2011
    Date of Patent: July 31, 2012
    Assignee: R&D Sockets, Inc.
    Inventor: James J. Rathburn
  • Patent number: 8223488
    Abstract: A locking assembly security apparatus engages with a tablet computer or similar device, which is securely locked to it via a plunger lock. A corner pocket engages one corner of the tablet computer, while another proximal lockable corner pocket engages the diagonally opposite corner of the tablet computer. The security apparatus includes a diagonally extending chassis bar between the opposite set of corner pockets. The base of a proximal pocket extends from the diagonally extending chassis bar to the flanges at the proximal end on the other side of the integral hinge pin housing of the proximal pocket, which flips up to permit a corner of the tablet computer to be inserted or disengaged.
    Type: Grant
    Filed: February 18, 2011
    Date of Patent: July 17, 2012
    Assignee: Think Products, Inc.
    Inventor: Allen Peter
  • Patent number: 8213180
    Abstract: A printed circuit board (PCB) assembly is provided that includes a PCB, an integrated circuit package, an electromagnetic interference (EMI) shield ring, and a heat sink lid. A first surface of the package is mounted to a first surface of the PCB. The EMI shield ring is mounted to the first surface of the PCB in a ring around the package. A first surface of the heat sink lid includes a recessed region and first and second supporting portions separated by the recessed region. The heat sink lid is mated with the EMI shield ring such that the package is positioned in an enclosure formed by the EMI shield ring and the recessed region of the heat sink lid. A second surface of the package may interface with a surface of the recessed region.
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: July 3, 2012
    Assignee: Broadcom Corporation
    Inventors: Sam Ziqun Zhao, Calvin Wong
  • Patent number: 8193618
    Abstract: A semiconductor die package. The semiconductor die package includes a leadframe structure comprising a first lead structure comprising a die attach pad, a second lead structure, and a third lead structure. It also includes a semiconductor die comprising a first surface and a second surface. The semiconductor die is on the die attach pad of the leadframe structure. The first surface is proximate the die attach pad. The semiconductor die package further includes a clip structure comprising a first interconnect structure and a second interconnect structure, the first interconnect structure comprising a planar portion and a protruding portion, the protruding portion including an exterior surface and side surfaces defining the exterior surface. The protruding portion extends from the planar portion of the first interconnect structure.
    Type: Grant
    Filed: December 12, 2008
    Date of Patent: June 5, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Ruben P. Madrid
  • Patent number: 8188597
    Abstract: A fixture assembly and method of forming a chip assembly is provided. The fixture assembly includes a first plate having an opening sized to accommodate a chip mounted on a laminate. The fixture assembly further includes a second plate mated to the first plate by at least one mechanical fastening mechanism. The fixture assembly further includes a space defined by facing surfaces of the first plate and the second plate and confined by a raised stepped portion of at least one of the first plate and the second plate. The space is coincident with the opening. The space is sized and shaped such that the laminate is confined within the space and directly abuts the stepped portion and the facing surfaces of the first plate and the second plate to be confined in X, Y and Z directions.
    Type: Grant
    Filed: September 22, 2010
    Date of Patent: May 29, 2012
    Assignee: International Business Machines Corporation
    Inventors: Thomas E. Lombardi, Donald Merte, Gregg B. Monjeau, David L. Questad, Son K. Tran
  • Patent number: 8154119
    Abstract: The present invention is an apparatus for integrating multiple devices. The apparatus includes a substrate having a first via and a second via, a semiconductor chip positioned on a top portion of the substrate and positioned between the first via and the second via, first and second bumps positioned on the semiconductor chip, and an interposer wafer having a first interposer spring assembly and a second interposer spring assembly, the first interposer spring assembly having a first interposer spring and a first electrical connection attached to the first interposer spring, and the second interposer spring assembly having a second interposer spring and a second electrical connection attached to the second interposer spring.
    Type: Grant
    Filed: March 31, 2010
    Date of Patent: April 10, 2012
    Assignee: Toyota Motor Engineering & Manufacturing North America, Inc.
    Inventors: Sang Won Yoon, Koji Shiozaki
  • Patent number: 8139356
    Abstract: A plunger-type security lock includes a slotted, cylindrical sliding key receptacle, a ferrule arranged on an outer cylindrical surface of the sliding key receptacle that is configured for attachment to a locking member, a cylindrical plunger, a sliding key including a hooking end and a plunger-contact end that is configured with a key definition and for slidable spring-loaded operation within the slotted, cylindrical sliding key in cooperation with the cylindrical plunger to extend and hook the flexible locking strip and to retract with and lock the locking strip in locking state and a locking mechanism that defines the locking state in cooperation with the key definition.
    Type: Grant
    Filed: January 25, 2010
    Date of Patent: March 20, 2012
    Inventor: Peter Allen
  • Patent number: 8134835
    Abstract: The present invention relates to a clamping device for compression clamping of one or more semiconductor devices and associated semiconductor components with a desired compression force equally distributed across the opposing surfaces of the devices and associated components. The semiconductor devices and components are located between opposing jaws that are joined together by at least two tie rods, which compressively load the opposing jaws to apply the desired compression force to the semiconductor devices and components. The desired compression force is first achieved in even distribution between independent clamp pressure set point assemblies and the first jaw, where each of the independent clamp pressure set point assemblies is associated with one of the tie rods.
    Type: Grant
    Filed: January 24, 2008
    Date of Patent: March 13, 2012
    Assignee: Inductotherm Corp.
    Inventors: Oleg S. Fishman, Satyen N. Prabhu
  • Patent number: 8125783
    Abstract: According to one embodiment, a printed circuit board comprises a printed wiring board, circuit component, reinforcing plate and first and second fixing portion. The printed wiring board includes first and second areas. A reinforcing plate secured to the other of the first and second surfaces in said at least one of the first and second areas. The first fixing portion is provided on a border line that defines the first and second areas. The first fixing portion can fix the reinforcing plate to both the first and second areas. The second fixing portion comprises a plurality of apertures arranged symmetrical with respect to the border line.
    Type: Grant
    Filed: September 15, 2009
    Date of Patent: February 28, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Makoto Tanaka
  • Patent number: 8067781
    Abstract: The light emitting structure disclosed includes a light emitting device, a metal frame, and a repressing fastener. The light emitting device has a plurality of first coupling terminals, and the metal frame has a plurality of second coupling portions. The light emitting device is disposed in the metal frame, and the first coupling terminals touch the second coupling portions to electrically connect the light emitting device and the metal frame. The repressing fastener is disposed on the light emitting device and fastened to the metal frame to secure the light emitting device in the metal frame. An LED securing device is also disclosed.
    Type: Grant
    Filed: November 21, 2008
    Date of Patent: November 29, 2011
    Assignee: Everlight Electronics Co., Ltd.
    Inventors: Chia-Hao Liang, Hsin-Chang Tsai, Xie-Zhi Zhong
  • Patent number: 8067273
    Abstract: A semiconductor die package. The semiconductor die package includes a semiconductor die, and a lead comprising a flat surface. It also includes a clip structure including a (i) a contact portion, where the contact portion is coupled the semiconductor die, a clip aligner structure, where the clip aligner structure is cooperatively structured with the lead with the flat surface, and an intermediate portion coupling the contact portion and the clip aligner structure.
    Type: Grant
    Filed: December 10, 2010
    Date of Patent: November 29, 2011
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Jocel P. Gomez
  • Patent number: 8063485
    Abstract: A board mounted integrated electronics package assembly is provided with one or more securing elements to attach a heat dissipating device directly to the package. The securing element(s) is located along a periphery of the package and anchors a base of the heat dissipating device to the package, thereby eliminating employment of a secondary heat dissipating material between the package and the heat dissipating device.
    Type: Grant
    Filed: June 27, 2008
    Date of Patent: November 22, 2011
    Assignee: Advanced Thermal Solutions, Inc.
    Inventor: Kaveh Azar
  • Patent number: 8044502
    Abstract: An electrical interconnect assembly for electrically interconnecting terminals on a first circuit member with terminals on a second circuit member. The electrical interconnect includes a housing having a plurality of through openings extending between a first surface and a second surface. A plurality of composite contacts are positioned in a plurality of the through openings. The composite contacts include a conductive member having a central portion and at least first and second interface portions. One or more polymeric layers extend along at least the central portion conductive member. One or more coupling features on the composite contacts engage with the housing. At least one engagement feature formed in the polymeric layers proximate the first interface portion mechanically couples with the terminals on the first circuit member.
    Type: Grant
    Filed: March 19, 2007
    Date of Patent: October 25, 2011
    Assignee: Gryphics, Inc.
    Inventor: James J. Rathburn
  • Patent number: 8026603
    Abstract: An interconnect structure of an integrated circuit and manufacturing method therefore are provided, relating to an interconnect structure of flexible packaging. The interconnect structure includes a first and a second conductive pads. A plurality of tiny and conductive first pillars is respectively formed on the first and second pads. With different densities and thicknesses of the first and second pillars, a contact strength can be generated when the pillars interconnecting with each other, such that the pillars are connected closely. Furthermore, the interconnect structure can also be used to connect with fibers made of conductive materials. Moreover, the higher the density of the pillars, the stronger the contact strength. And, electronic substrates and active or passive electronic elements can be stuck on the other side of each pad. Therefore, the interconnect structure can maintain flexibility and have high reliability without being enhanced by any thermosetting polymer.
    Type: Grant
    Filed: April 21, 2006
    Date of Patent: September 27, 2011
    Assignee: Industrial Technology Research Institute
    Inventors: Yung-Yu Hsu, Chih-Yuan Cheng, Shyi-Ching Liau, Min-Lin Lee, Ra-Min Tain, Rong-Chang Feng
  • Patent number: 8018072
    Abstract: A semiconductor device has a substrate. A die is attached to a first surface of the substrate. A heat sink is provided having an approximately planer member and support members extending from the planer member. The support members are attached to the first surface of the substrate to form a cavity over the die with the planer member positioned above the die. An encapsulant is provided for encapsulating the device, wherein an exterior surface of the planer member is exposed. A non-tapered opening is formed in the planer member. The encapsulant is injected through the opening to encapsulate the cavity and the encapsulant will partially fill the non-tapered opening.
    Type: Grant
    Filed: December 23, 2008
    Date of Patent: September 13, 2011
    Assignee: Amkor Technology, Inc.
    Inventors: Jeffrey A. Miks, Jui Min Lim
  • Publication number: 20110215463
    Abstract: Flip chip packages having warpage control and methods for fabricating such packages are described. In one embodiment, the flip chip package comprises a package substrate; a chip coupled to the package substrate; and a ring structure coupled to the package substrate and positioned laterally around the periphery of the chip so that a surface of the chip is exposed, wherein the ring structure comprises one or more compressive members, each of the one or more compressive members compressively opposed to a surface of the package substrate to counter or absorb stresses in the package substrate.
    Type: Application
    Filed: March 5, 2010
    Publication date: September 8, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Yao LIN, Wen-Yi LIN
  • Patent number: 7994637
    Abstract: An example of a high-frequency semiconductor device includes two unit semiconductor devices. Each of the two unit semiconductor devices has a ground substrate, a high-frequency semiconductor element, an input-side matching circuit, an output-side matching circuit, a side wall member, an input terminal, and an output terminal. The ground substrate has heat-radiating property. The high-frequency semiconductor element is provided on the ground substrate. The input-side matching circuit is connected to the high-frequency semiconductor element. The output-side matching circuit is connected to the high-frequency semiconductor element. The side wall member surrounds at least the high-frequency semiconductor element. The input terminal is connected to the input-side matching circuit. The output terminal is connected to the output-side matching circuit. The two unit semiconductor devices are coupled to each other at upper edges of the side wall members.
    Type: Grant
    Filed: December 31, 2009
    Date of Patent: August 9, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazutaka Takagi
  • Patent number: 7982308
    Abstract: A light-emitting diode packaging structure, a packaging module and the assembling method thereof are disclosed. The assembling method comprises the steps of: providing a light-emitting diode, wherein the light-emitting diode has two electrode leads; providing two metal plates, wherein each of the metal plates has at least a clamping portion; holding the electrode leads against the metal plates respectively; and bending the clamping portion of each of the metal plates to fix the electrode leads on the metal plates. Further, a plurality of light-emitting diodes are allowed to be mounted on the metal plates to form the light-emitting diode packaging module.
    Type: Grant
    Filed: March 19, 2008
    Date of Patent: July 19, 2011
    Assignee: Everlight Electronics Co., Ltd.
    Inventors: Sheng-Jia Sheu, Chien-Chang Pei
  • Patent number: 7977698
    Abstract: A system and method is disclosed for allowing a solid substrate, such as a printed circuit board (PCB), to act as the support structure for an electronic circuit. In one embodiment, the LEDs which form a part of a scrambler assembly are constructed on a first substrate and the electrical connections are run to the edges of the substrate and end in electrical contacts positioned thereat. The substrate is then connected to the scrambler package by a series of electrical and mechanical connections to form the LED package. The electrical contacts which are part of the LED package extend from the LED package so as to enable electrical contact with a separate controller substrate.
    Type: Grant
    Filed: March 18, 2005
    Date of Patent: July 12, 2011
    Assignee: Avago Technologies ECBU IP (Singapore) Pte. Ltd.
    Inventors: Elizabeth Fung Ching Ling, Chia Chee Wai, Ng Joh Joh, Koay Hui Peng
  • Patent number: 7961473
    Abstract: An integrated circuit is disposed on a circuit board. A heat sink retention module includes a bracket, members, and coil springs. The members extend through the coil springs and corresponding holes within the bracket to attach to the board. A heat sink is removably installed within the bracket in a toolless manner, such that the heat sink comes into contact with the integrated circuit. The heat sink and the bracket join together to become a single entity that is permitted to float along an axis perpendicular to a surface of the circuit board. The coil springs are tuned to define a predetermined force at which the heat sink is pushed against the integrated circuit. The module can include a latch having tabs bent at different angles relative to one another to balance forces applied by the tabs against the heat sink while the latter is being installed within the bracket.
    Type: Grant
    Filed: December 24, 2009
    Date of Patent: June 14, 2011
    Assignee: International Business Machines Corporation
    Inventors: Mark S. Bohannon, Derek I. Schmidt, Pat Gallarelli