Abstract: A sensor package structure includes a substrate, a sensor chip and a ring-shaped solder mask frame those are disposed on the substrate, a ring-shaped support disposed on a top side of the annular solder mask frame, and a light permeable member that is disposed on the ring-shaped support. The sensor chip is electrically coupled to the substrate. A top surface of the sensor chip has a sensing region, and the sensing region is spaced apart from an outer lateral side of the sensor chip by a distance less than 300 ?m. The ring-shaped solder mask frame surrounds and contacts the outer lateral side of the sensor chip. The light permeable member, the ring-shaped support, and the sensor chip jointly define an enclosed space.

Abstract: A semiconductor module includes: a first conductive portion; a second conductive portion spaced from the first conductive portion in a first direction; first semiconductor elements electrically bonded to the first conductive portion and mutually spaced in a second direction perpendicular to the first direction; and second semiconductor elements electrically bonded to the second conductive portion and mutually spaced in the second direction. The semiconductor module further includes: a first input terminal electrically connected to the first conductive portion; a second input terminal of opposite polarity to the first input terminal; and an output terminal opposite from the two input terminals in the first direction and electrically connected to the second conductive portion.

Abstract: An electronic power switch drive module for a power semiconductor unit, comprising a gate drive and a current transducer mounted on one or more circuit boards, the gate drive comprising at least one circuit portion for controlling at least one transistor of a power semiconductor module of said power semiconductor unit, the current transducer configured to be coupled to an output of the power semiconductor module for measuring an output current of the power semiconductor module, said at least one circuit portion connected to an output potential of the output current to be measured. The current transducer comprises at least one magnetic field sensor, the current transducer being connected to said at least one circuit portion of the gate drive at said output potential in a non-isolated manner.

Abstract: A semiconductor module includes: a first conductive portion; a second conductive portion spaced from the first conductive portion in a first direction; first semiconductor elements electrically bonded to the first conductive portion and mutually spaced in a second direction perpendicular to the first direction; and second semiconductor elements electrically bonded to the second conductive portion and mutually spaced in the second direction. The semiconductor module further includes: a first input terminal electrically connected to the first conductive portion; a second input terminal of opposite polarity to the first input terminal; and an output terminal opposite from the two input terminals in the first direction and electrically connected to the second conductive portion.

Abstract: An object is to suppress a lift of an external terminal when an external force is applied, thereby improving the reliability of a semiconductor device. A heat radiating plate 10 having on one main surface a circuit area 54 in which a semiconductor element 50 is arranged, a pair of terminals 31 and 32 connected to the semiconductor element 50, a resin housing 20 that covers the circuit area 54 of the heat radiating plate 10 to seal the semiconductor element 50, and has a terminal surface 22 formed on an upper surface, a pair of side surfaces in the longitudinal direction, and a pair of front and rear surfaces in the lateral direction, are included. The resin housing 20 has a pair of bending contact portions 22e and 23e that come into respectively contact with the pair of terminals 31 and 32 to define bending positions of the terminals 31 and 32. The pair of bending contact portions 22e and 23e are formed to have different heights.

Abstract: To provide a heat radiation member having high durability that can favorably retain the thermal conductivity under application of heat cycles, suitable for mounting a semiconductor element of a power module. The heat radiation member includes a laminated structure including metal materials 21 and 22 and a carbon material 10 having the following property (A) bonded to each other; (A) in pressurizing one principal surface of a plate specimen having a thickness of 11 mm of the carbon material with nitrogen gas of 200 kPa, the carbon material having a gas permeability of the nitrogen gas permeating to the other principal surface with a flow rate of 5 L/min or more and 30 L/min or less per 0.01 m2 in terms of area of the pressurized principal surface, the pressurized principal surface having an area of 0.005 m2 or more.

Abstract: An integrated circuit package, including a circuit board, signal pins extending orthogonally to the circuit board surface, and grouped into a plurality of differential signal pin pairs, each signal pin pair positioned at a vertex of an array of orthogonal rows and columns, wherein each signal pin pair includes a positive and a negative signal pin. The plurality of signal pin pairs includes a first subset of signal pin pairs wherein the positive and the negative signal pins are arranged in an orientation along a line parallel to rows of the array and a second subset of signal pin pairs in which the positive and the negative signal pins are arranged in an orientation along a line parallel to columns of the array. For each signal pin pair in one of the first and second subsets, each nearest signal pin pairs belong to another of the first and second subsets.

Abstract: Flat no-leads integrated circuit (IC) packages are formed with solder wettable leadframe terminals. Dies are mounted on die attach pads, bonded to adjacent leadframe terminal structures, and encapsulated in a mold compound. A laser grooving process removes mold compound from a leadframe terminal groove extending along a row of leadframe terminal structures. A saw step cut along the leadframe terminal groove extends partially through the leadframe thickness to define a saw step cut groove. Exposed leadframe surfaces, including surfaces exposed by the saw step cut, are plated with a solder-enhancing material. A singulation cut is performed along the saw step cut groove to define leadframe terminals with end surfaces plated with the solder-enhancing material. The laser grooving process may improve the results of the saw step cut, and the saw step cut may remove mold compound not removed by the laser grooving process.

Abstract: A chip-on-film (COF) package includes a film including a reinforcement area, a bending area and a chip mounting area, a conductive pattern layer disposed on the film in the reinforcement area and in the bending area, and at least partially in the chip mounting area, a chip mounted on a portion of the conductive pattern layer in the chip mounting area, a first insulating layer having a first elastic modulus and extending over the conductive pattern layer in the reinforcement area, and a second insulating layer having a second elastic modulus and extending over the conductive pattern layer in the bending area, wherein the first elastic modulus is greater than the second elastic modulus, and the film is intact in the chip mounting area.

Abstract: A multi-layer printed circuit board having a first landing pad in a first layer and along a first axis arranged to receive a positive signal and a second landing pad in the first layer and along a second axis that is spaced away from the first axis longitudinally in the first layer and where the second landing pad arranged to receive a negative signal. A first buried in a second layer and along the first axis is spaced away from the first landing pad along the first axis. A second buried in the second layer and along the second axis is spaced away from the second landing pad along the second axis. A first signal connector provides a first electrical connection between the first landing pad and the second buried via and a second signal connector provides a second electrical connection between the second landing pad and the first buried via.

Abstract: A method for manufacturing a light emitting device includes: preparing a substrate having a first region and a second region surrounding the first region; mounting a plurality of light emitting elements in the first region; mounting a reinforcement member on the second region; forming and curing a sealing member in contact with the reinforcement member and with the light emitting elements, the sealing member having a lower rigidity than the reinforcement member; and cutting the substrate, the reinforcement member, and the sealing member to separate into individual light emitting devices each including one or more of the light emitting elements.

Abstract: Described herein is a MEMS force sensor with stress concentration design. The stress concentration can be performed by providing slots, whether through or blind, and/or selective thinning of the substrate. The MEMS force sensor is in chip scale package with solder bumps or metal pillars and there are sensing elements formed on the sensor substrate at the stress concentrate area. The stress concentration can be realized through slots, selective thinning and a combination of both.

Abstract: A semiconductor device has a substrate. A conductive layer is formed over the substrate and includes a ground plane. A first tab of the conductive layer extends from the ground plane and less than half-way across a saw street of the substrate. A shape of the first tab can include elliptical, triangular, parallelogram, or rectangular portions, or any combination thereof. An encapsulant is deposited over the substrate. The encapsulant and substrate are singulated through the saw street. An electromagnetic interference (EMI) shielding layer is formed over the encapsulant. The EMI shielding layer contacts the first tab of the conductive layer.

Abstract: Representative implementations of techniques and methods include processing singulated dies in preparation for bonding. A plurality of semiconductor die components may be singulated from a wafer component, the semiconductor die components each having a substantially planar surface. Particles and shards of material may be removed from edges of the plurality of semiconductor die component. Additionally, one or more of the plurality of semiconductor die components may be bonded to a prepared bonding surface, via the substantially planar surface.

Abstract: A circuit board has an edge connector with signal traces. The signal traces are formed on a dielectric layer of the circuit board. A reference trace is formed within the dielectric layer or on another surface of the dielectric layer. Parameters of the reference trace are adjusted to set an impedance of a single-ended signal trace or a differential impedance of two adjacent signal traces.

Abstract: An Fan-out packaging system, comprising dedicated frame with associated movable metallic spring feature(s) for incoming known-good-die (KGD), is invented. The movable spring anchor(s) along with the boundaries of the frame locks the KGD in its designated position during EMC implementation and subsequent processes. In this system/approach, the position accuracy of KGDs during the wafer reconstitution process will be mostly dominated by the dicing accuracy. The proposed system is a very low cost approach as it does not need the expensive software/tool set and does not have a low throughput site-to-site lithography correction during exposure after metrology is carried out for every flash field. This system is particularly useful for chiplet consisting of component chips from different technologies and from substrate made of different material.

Abstract: A semiconductor module includes: a dual-gauge leadframe having thicker and thinner parts, part of the thinner part forming a high voltage lead; a semiconductor die attached to the thicker part; and a molding compound (MC) encapsulating the die. The thicker leadframe part is disposed at a bottom side of the MC. A side face of the MC has a stepped region between the high voltage lead and thicker leadframe part. A first generally vertical part of the stepped region extends from the high voltage lead to the generally horizontal part, a generally horizontal part of the stepped region extends to the second generally vertical part, and a second generally vertical part of the stepped region extends to the bottom side of the MC. A linear dimension of the generally horizontal part as measured from the first generally vertical part to the second generally vertical part is at least 4.5 mm.

Abstract: In examples, a semiconductor package comprises a ceramic substrate and first and second metal layers covered by the ceramic substrate. The first metal layer is configured to carry signals at least in a 20 GHz to 28 GHz frequency range. The package comprises a semiconductor die positioned above the first and second metal layers and coupled to the first metal layer. The package comprises a ground shield positioned in a horizontal plane between the semiconductor die and the first metal layer, the ground shield including an orifice above a portion of the first metal layer. The package includes a metal seal ring coupled to a top surface of the ceramic substrate, the metal seal ring having a segment that is vertically aligned with a segment of the ground shield. The segment of the ground shield is between the orifice of the ground shield and a horizontal center of the ground shield. The package comprises a metal lid coupled to a top surface of the metal seal ring.

Abstract: The present invention provides a device for testing a chip, wherein the device includes a testing board and an interposer. The testing board has a plurality of pads for providing a plurality of test signals. The interposer board includes a plurality of passive components, and at least one of the passive components is coupled between a supply voltage and a ground voltage, and the supply voltage and the ground voltage are received from a power pad and a ground pad of the plurality of pads of the testing board, respectively; wherein the chip is positioned in the device, the chip receives the test signals including the supply voltage and the ground voltage from the power pad and the ground pad of the testing board, respectively.

Abstract: Disclosed herein are cavity structures in integrated circuit (IC) package supports, as well as related methods and apparatuses. For example, in some embodiments, an IC package support may include: a cavity in a dielectric material, wherein the cavity has a bottom and sidewalls; conductive contacts at the bottom of the cavity, wherein the conductive contacts include a first material; a first peripheral material outside the cavity, wherein the first peripheral material is at the sidewalls of the cavity and proximate to the bottom of the cavity, and the first peripheral material includes the first material; and a second peripheral material outside the cavity, wherein the second peripheral material is at the sidewalls of the cavity and on the first peripheral material, and the second peripheral material is different than the first peripheral material.

Abstract: An apparatus and a method are disclosed for producing an electric terminal contact on a coated sheet, whose coating has at least one electric conductor path covered by an electrical insulation layer, in which apparatus and method a recess is produced extending through the insulation layer at least to the electrical conductor path and in this recess, an electrically conductive contact element is provided, one end of which is electrically connected to the conductor path and at the other end of which forms the electrical terminal contact. In order to increase the reproducibility, the proposal is made for the recess to be produced with the aid of a hollow needle, which is advanced in the direction toward the conductor path and which, as it is withdrawn from the recess, introduces an electrically conductive, viscous compound into this recess in order to produce the contact element.

Abstract: An IGBT module, a conductor installing structure for the IGBT module and an inverter are provided. The conductor installing structure for the IGBT module includes a substrate, a conductor and an insulation sleeve sleeved on the conductor and insulatedly isolating the conductor from the substrate. In the conductor installing structure for the IGBT module according to the present disclosure, by using the insulation sleeve sleeved on the conductor to insulatedly isolating the conductor from the substrate, the comparative tracking index of the IGBT module is improved, thereby improving the creepage distance of the IGBT module. In addition, compared with conventional technologies of spraying insulation varnish or insulation paste, the insulating property of the insulation sleeve can be better detected and guaranteed, and the bounding between the insulation sleeve and the substrate can be better enhanced, improving the insulation reliability.

Abstract: A mechanism is provided to reduce noise effects on signals traversing bond wires of a SOC by forming a bond wire ring structure that decreases mutual inductance and capacitive coupling. Bond wires form the ring structure in a daisy chain connecting isolated ground leads at a semiconductor device package surrounding the semiconductor device. This structure reduces out-of-plane electromagnetic field interference generated by signals in lead wires, as well as mutual capacitance and mutual inductance.

Abstract: A semiconductor package structure includes a semiconductor package structure includes a first supporting bar, a second supporting bar and an encapsulant. The second supporting bar is adjacent to the first supporting bar. The first supporting bar and the second supporting bar extend substantially along a first direction. The encapsulant covers the first supporting bar and the second supporting bar. The encapsulant defines a first recess and a second recess recessed from a lower surface of the encapsulant. The first recess extends substantially along a second direction different from the first direction. The second recess is located between the first recess and the second supporting bar.

Abstract: Embodiments of the invention include a microelectronic device that includes a first ultra thin substrate formed of organic dielectric material and conductive layers, a first mold material to integrate first radio frequency (RF) components with the first substrate, and a second ultra thin substrate being coupled to the first ultra thin substrate. The second ultra thin substrate formed of organic dielectric material and conductive layers. A second mold material integrates second radio frequency (RF) components with the second substrate.

Abstract: A novel 3D package configuration is provided by stacking a plurality of semiconductor package units or a folded flexible circuit board structure on a lead frame and electrically connected therewith based on the foldable characteristics of the flexible circuit board, and the high temperature resistance of the flexible circuit board which is suitable for insulating layer process, metal layer process, photolithography process, etching and development process, to make conventional semiconductor dies of various functions be bonded on one die and/or two side of a flexible circuit board and electrically connected therewith in advance.

Abstract: Discontinuous bonds for semiconductor devices are disclosed herein. A device in accordance with a particular embodiment includes a first substrate and a second substrate, with at least one of the first substrate and the second substrate having a plurality of solid-state transducers. The second substrate can include a plurality of projections and a plurality of intermediate regions and can be bonded to the first substrate with a discontinuous bond. Individual solid-state transducers can be disposed at least partially within corresponding intermediate regions and the discontinuous bond can include bonding material bonding the individual solid-state transducers to blind ends of corresponding intermediate regions. Associated methods and systems of discontinuous bonds for semiconductor devices are disclosed herein.

Abstract: A semiconductor assembly includes a semiconductor element having contacts on a first surface electrically connected with contacts of a carrier element by electrically conductive material. A second surface opposite the first surface has a convex curvature with a first radius or a concave curvature with a second radius. The second surface of the convex curvature or the second surface of the concave curvature is connected in a positive-fit manner to a cooling body surface of a concave cooling body curvature of the cooling body, and, during operation at a selected barrier layer temperature, the first radius of the convex curvature deviates by at most 10% from a third radius of the concave cooling body curvature, or the second radius of the concave curvature deviates by at most 10% from a fourth radius of the convex cooling body curvature.

Abstract: A method includes providing a semiconductor base substrate having a substantially planar growth surface and one or more preferred crystallographic cleavage planes and an epitaxial first type III-V semiconductor layer on the planar growth surface. A first trench that vertically extends from an upper surface of the first type III-V semiconductor layer is formed at least to the planar growth surface. The first trench has a first trench length direction that is antiparallel to the one or more preferred crystallographic cleavage planes.

Abstract: A light-emitting device includes a first lead having a first lateral surface, a second lead having a second lateral surface, and a resin portion. The first lateral surface of a first lead facing a second lead has a first recess that is recessed so as to be away from the second lead toward the first lead in a top view, and is continuous with an end of a first groove. The second lateral surface of the second lead facing the first lead has a second recess that is recessed so as to be away from the first lead toward the second lead in the top view, and is continuous with an end of a second groove. In the top view, a part of the resin portion is continuously disposed between the end of the first groove and the end of the second groove.

Abstract: This invention provides a nitride semiconductor light emitting device in which current concentration is suppressed without excessively increasing resistance at a low cost without increasing a manufacturing process. The planar shape of a mesa portion configuring a nitride semiconductor light emitting device is a shape containing a convex-shaped tip portion 352b formed by a curved line or a plurality of straight lines and a base portion 352a continuous to the convex-shaped tip portion 352b, in which an obtuse angle is formed by adjacent two straight lines in the convex-shaped tip portion formed by the plurality of straight lines. The first electrode layer 4 has visible outlines 411 and 412 along a visible outline 302 of the mesa portion through a gap 9 in planar view. The relationship between a gap W1 in the convex-shaped tip portion 352b and a gap W2 in the base portion 352a is W1> W2.

Abstract: In one example in accordance with the present disclosure, a fluid ejection device is described. The fluid ejection device includes a substrate and a number of nozzles formed within the substrate to eject fluid. A number of bond pads are disposed on the substrate and are electrically coupled to the number of rows of nozzles. A termination ring is disposed on the substrate and surrounds the rows of nozzles. The termination ring includes a first metallic layer that is an enclosed shape and a second metallic layer that is disposed on top of the first metallic layer. The second metallic layer includes a gap positioned adjacent the number of bond pads.

Abstract: This invention provides a nitride semiconductor light emitting device in which current concentration is suppressed without excessively increasing resistance at a low cost without increasing a manufacturing process. The planar shape of a mesa portion configuring a nitride semiconductor light emitting device is a shape containing a convex-shaped tip portion 352b formed by a curved line or a plurality of straight lines and a base portion 352a continuous to the convex-shaped tip portion 352b, in which an obtuse angle is formed by adjacent two straight lines in the convex-shaped tip portion formed by the plurality of straight lines. The first electrode layer 4 has visible outlines 411 and 412 along a visible outline 302 of the mesa portion through a gap 9 in planar view. The relationship between a gap W1 in the convex-shaped tip portion 352b and a gap W2 in the base portion 352a is W1> W2.

Abstract: A semiconductor light-emitting device 10 includes a heat sink and a semiconductor light-emitting element mounted on the heat sink. A gap is provided between a region of a part of a base bottom surface of a base of the semiconductor light-emitting element and an upper surface of the heat sink, and a lead is disposed in a region where the gap is provided so as to vertically pass through the base. A semiconductor laser chip is provided in a region where the gap is not provided so that its waveguide longitudinal direction is substantially parallel to an upper surface of the base. The lead has its lower end located within the gap and connected to a flexible substrate.

Abstract: LED tape is provided that employs a plurality of surface-mounted contact terminals. The LED tape can be severed at discrete locations adjacent to the contact terminal to create a tape segment configured to interconnect to a power source or to another tape segment by way of a wire selectively received and secured within corresponding terminal connectors. The use of the connecting wire omits the need for a mechanical connector or integration by soldering currently required to interconnect LED tape segments.

Abstract: An optoelectronic device, comprising a first semiconductor layer comprising four boundaries comprising two longer sides and two shorter sides; a second semiconductor layer formed on the first semiconductor layer; and a plurality of first conductive type electrodes formed on the first semiconductor layer, wherein one first part of the plurality of first conductive type electrodes is formed on a corner constituted by one of the two longer sides and one of the two shorter sides, and wherein one fourth part of the plurality of first conductive type electrodes is formed along the one of the two longer sides, the one fourth part of the plurality of first conductive type electrodes comprises a head portion and a tail portion, the head portion comprises a width larger than that of the tail portion.

Abstract: A method for producing a nitride semiconductor device. The method comprises providing a substrate made of a material other than a nitride semiconductor. The material has a hexagonal crystal structure. An upper face of the substrate has at least one flat section. The method further comprises growing a first nitride semiconductor layer on the upper face of the substrate. The first nitride semiconductor layer is made of monocrystalline AlN. The first nitride semiconductor layer has an upper face that is a +c plane. The first nitride semiconductor layer has a thickness in a range of 10 nm to 100 nm. The method further comprises growing a second nitride semiconductor layer on the upper face of the first nitride semiconductor layer. The second nitride semiconductor layer is made of InXAlYGa1?X?YN (0?X, 0?Y, X+Y<1).

Abstract: A flexible display panel and a manufacturing method which is capable of removing a non-display area without damaging a display element layer, the flexible display panel includes a flexible substrate which includes a display area and a peripheral area outside of the display area, a display element layer disposed on the flexible substrate, and a neutral plane balancing layer disposed on the display element layer in the peripheral area, wherein the peripheral area of the flexible substrate in which the neutral plane balancing layer is disposed is folded towards a rear side of the display area along a first bending line, and the neutral plane balancing layer overlaps the first bending line.

Abstract: A patterned substrate includes a main base and a plurality of patterned structures. The main base has at least one device-disposed region and a cutting region surrounding the device-disposed region. The patterned structures are integratedly formed with the main base, and only distributed in the cutting region of the main base. The patterned structures are separated from each other.

Abstract: LED tape is provided that employs a plurality of surface-mounted contact terminals. The LED tape can be severed at discrete locations adjacent to the contact terminal to create a tape segment configured to interconnect to a power source or to another tape segment by way of a wire selectively received and secured within corresponding terminal connectors. The use of the connecting wire omits the need for a mechanical connector or integration by soldering currently required to interconnect LED tape segments.

Abstract: A nitride semiconductor element includes a sapphire substrate including: a main surface extending in a c-plane of the sapphire substrate, and a plurality of projections disposed at the main surface, the plurality of projections including at least one projection having an elongated shape in a plan view; and a nitride semiconductor layer disposed on the main surface of the sapphire substrate. The at least one projection has an outer edge extending in a longitudinal direction of the elongated shape, the outer edge extending in a direction oriented at an angle in a range of ?10° to +10° with respect to an a-plane of the sapphire substrate in the plan view.

Abstract: A package includes a die, which includes a semiconductor substrate, a plurality of through-vias penetrating through the semiconductor substrate, a seal ring overlapping and connected to the plurality of through-vias, and a plurality of electrical connectors underlying the semiconductor substrate and connected to the seal ring. An interposer is underlying and bonded to the die. The interposer includes a substrate, and a plurality of metal lines over the substrate. The plurality of metal lines is electrically coupled to the plurality of electrical connectors. Each of the plurality metal lines has a first portion overlapped by the first die, and a second portion misaligned with the die. A heat spreader encircles the die and the interposer. A wire includes a first end bonded to one of the plurality of metal lines, and a second end bonded to the heat spreader.

Abstract: A patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers, is provided. The patterned surface can include a set of substantially flat top surfaces and a plurality of openings. Each substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the openings can have a characteristic size between approximately 0.1 micron and five microns. One or more of the substantially flat top surfaces can be patterned based on target radiation.

Abstract: A support structure located at a bottom of a ball grid array (BGA) is provided. The support structure includes a printed circuit board (PCB) having first positioning pin holes, an interface plate having second positioning pin holes which correspond to the first positioning pin holes arranged on the PCB, a support film arranged on the PCB and having support portions, and positioning components penetrating the first positioning pin holes and the second positioning pin holes corresponding to the first positioning pin holes to assemble the support film on the PCB and the interface plate.

Abstract: Embodiments of a microelectronic packaged device and methods of making are provided, where the microelectronic packaged device includes a system package comprising a first die and a second die, wherein the first die and the second die are laterally positioned to one another, and the first die and the second die are laterally separated from one another by mold compound; and a conductive trace formed between a first conductive surface on an exposed surface of the first die and a second conductive surface on an exposed surface of the second die, wherein the conductive trace is laser sintered directly on the first conductive surface, on a portion of the exposed surface of the first die, on a portion of a top surface of the mold compound, on a portion of the exposed surface of the second die, and on the second conductive surface.

Abstract: An electrical component (40) and a substrate (100) constitute at least a portion of an electrical device. At least one surface of the substrate (100) is formed of an insulator. A conductor (20) is formed on the one surface. The conductor (20) is covered with a sealing film (210). The sealing film (210) is a film having insulation properties. An opening (212) is formed in the sealing film (210). The opening (212) is located on a portion of the conductor (20) when seen in a plan view. The conductor (20) is connected to the electrical component (40) with an anisotropic conductive film (30) interposed therebetween. The anisotropic conductive film (30) overlaps the opening (212), and contains a plurality of metal particles.

Abstract: A method including bonding a process wafer having integrated circuits and a carrier wafer having at least one alignment mark to form a wafer assembly. The method further includes aligning the wafer assembly using the at least one alignment mark of the carrier wafer.

Abstract: Disclosed is an antenna assembly including a substrate, and a wireless charge antenna pattern on the substrate. The wireless charge antenna pattern has a sectional surface including a plurality of inner angles in which two inner angles are different from each other. The antenna assembly includes a wireless communication antenna pattern formed on the substrate and provided at an outside of the wireless charge antenna pattern. The wireless communication antenna pattern has a plurality of inner angles at a sectional surface thereof, and a plurality of angle values of the inner angles provided at the sectional surface of the wireless communication antenna pattern correspond to a plurality of angle values of the inner angles provided at the sectional surface of the wireless charge antenna pattern, respectively.

Abstract: A display device is driven through no wire cable such as an FPC, and a display image is continuously held for a certain period of time by storing an image signal received from a wireless communication device so that the display image can be held even when the display device is out of communication range with the wireless communication device. A display device includes at least a pixel circuit having an SRAM (static random access memory) circuit, a circuit which controls the pixel circuit, an antenna circuit, a circuit which generates a demodulation signal, a circuit which rectifies a wireless signal, a circuit which generates first voltage, a charge circuit which stores second voltage, a charge control circuit, a voltage supply control circuit, and a circuit which controls the charge control circuit and the voltage supply control circuit.

Abstract: A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board.