Outside Periphery Of Package Having Specified Shape Or Configuration Patents (Class 257/730)
  • Patent number: 10680405
    Abstract: A semiconductor light-emitting device 10 includes a heat sink and a semiconductor light-emitting element mounted on the heat sink. A gap is provided between a region of a part of a base bottom surface of a base of the semiconductor light-emitting element and an upper surface of the heat sink, and a lead is disposed in a region where the gap is provided so as to vertically pass through the base. A semiconductor laser chip is provided in a region where the gap is not provided so that its waveguide longitudinal direction is substantially parallel to an upper surface of the base. The lead has its lower end located within the gap and connected to a flexible substrate.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: June 9, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Shigetoshi Ito, Kazuaki Kaneko, Teruyuki Oomatsu
  • Patent number: 10663156
    Abstract: LED tape is provided that employs a plurality of surface-mounted contact terminals. The LED tape can be severed at discrete locations adjacent to the contact terminal to create a tape segment configured to interconnect to a power source or to another tape segment by way of a wire selectively received and secured within corresponding terminal connectors. The use of the connecting wire omits the need for a mechanical connector or integration by soldering currently required to interconnect LED tape segments.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: May 26, 2020
    Assignee: Aion LED, Inc.
    Inventor: Ryan P. Hanslip
  • Patent number: 10529893
    Abstract: An optoelectronic device, comprising a first semiconductor layer comprising four boundaries comprising two longer sides and two shorter sides; a second semiconductor layer formed on the first semiconductor layer; and a plurality of first conductive type electrodes formed on the first semiconductor layer, wherein one first part of the plurality of first conductive type electrodes is formed on a corner constituted by one of the two longer sides and one of the two shorter sides, and wherein one fourth part of the plurality of first conductive type electrodes is formed along the one of the two longer sides, the one fourth part of the plurality of first conductive type electrodes comprises a head portion and a tail portion, the head portion comprises a width larger than that of the tail portion.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: January 7, 2020
    Assignee: EPISTAR CORPORATION
    Inventors: Chao-Hsing Chen, Jia-Kuen Wang, Chien-Chih Liao, Tzu-Yao Tseng, Tsun-Kai Ko, Chien-Fu Shen
  • Patent number: 10510927
    Abstract: A method for producing a nitride semiconductor device. The method comprises providing a substrate made of a material other than a nitride semiconductor. The material has a hexagonal crystal structure. An upper face of the substrate has at least one flat section. The method further comprises growing a first nitride semiconductor layer on the upper face of the substrate. The first nitride semiconductor layer is made of monocrystalline AlN. The first nitride semiconductor layer has an upper face that is a +c plane. The first nitride semiconductor layer has a thickness in a range of 10 nm to 100 nm. The method further comprises growing a second nitride semiconductor layer on the upper face of the first nitride semiconductor layer. The second nitride semiconductor layer is made of InXAlYGa1?X?YN (0?X, 0?Y, X+Y<1).
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: December 17, 2019
    Assignee: NICHIA CORPORATION
    Inventor: Atsuo Michiue
  • Patent number: 10461267
    Abstract: A flexible display panel and a manufacturing method which is capable of removing a non-display area without damaging a display element layer, the flexible display panel includes a flexible substrate which includes a display area and a peripheral area outside of the display area, a display element layer disposed on the flexible substrate, and a neutral plane balancing layer disposed on the display element layer in the peripheral area, wherein the peripheral area of the flexible substrate in which the neutral plane balancing layer is disposed is folded towards a rear side of the display area along a first bending line, and the neutral plane balancing layer overlaps the first bending line.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: October 29, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jun Namkung, Soon Ryong Park, Chul Woo Jeong
  • Patent number: 10411159
    Abstract: A patterned substrate includes a main base and a plurality of patterned structures. The main base has at least one device-disposed region and a cutting region surrounding the device-disposed region. The patterned structures are integratedly formed with the main base, and only distributed in the cutting region of the main base. The patterned structures are separated from each other.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: September 10, 2019
    Assignee: PlayNitride Inc.
    Inventors: Yen-Lin Lai, Shen-Jie Wang, Jyun-De Wu, Chien-Chih Yen
  • Patent number: 10378747
    Abstract: LED tape is provided that employs a plurality of surface-mounted contact terminals. The LED tape can be severed at discrete locations adjacent to the contact terminal to create a tape segment configured to interconnect to a power source or to another tape segment by way of a wire selectively received and secured within corresponding terminal connectors. The use of the connecting wire omits the need for a mechanical connector or integration by soldering currently required to interconnect LED tape segments.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: August 13, 2019
    Inventor: Ryan Hanslip
  • Patent number: 10263152
    Abstract: A nitride semiconductor element includes a sapphire substrate including: a main surface extending in a c-plane of the sapphire substrate, and a plurality of projections disposed at the main surface, the plurality of projections including at least one projection having an elongated shape in a plan view; and a nitride semiconductor layer disposed on the main surface of the sapphire substrate. The at least one projection has an outer edge extending in a longitudinal direction of the elongated shape, the outer edge extending in a direction oriented at an angle in a range of ?10° to +10° with respect to an a-plane of the sapphire substrate in the plan view.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: April 16, 2019
    Assignee: NICHIA CORPORATION
    Inventors: Tomohiro Shimooka, Masahiko Sano, Naoki Azuma
  • Patent number: 10115653
    Abstract: A package includes a die, which includes a semiconductor substrate, a plurality of through-vias penetrating through the semiconductor substrate, a seal ring overlapping and connected to the plurality of through-vias, and a plurality of electrical connectors underlying the semiconductor substrate and connected to the seal ring. An interposer is underlying and bonded to the die. The interposer includes a substrate, and a plurality of metal lines over the substrate. The plurality of metal lines is electrically coupled to the plurality of electrical connectors. Each of the plurality metal lines has a first portion overlapped by the first die, and a second portion misaligned with the die. A heat spreader encircles the die and the interposer. A wire includes a first end bonded to one of the plurality of metal lines, and a second end bonded to the heat spreader.
    Type: Grant
    Filed: January 19, 2015
    Date of Patent: October 30, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jing-Cheng Lin
  • Patent number: 10032956
    Abstract: A patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers, is provided. The patterned surface can include a set of substantially flat top surfaces and a plurality of openings. Each substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the openings can have a characteristic size between approximately 0.1 micron and five microns. One or more of the substantially flat top surfaces can be patterned based on target radiation.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: July 24, 2018
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Maxim S. Shatalov, Rakesh Jain, Jinwei Yang, Michael Shur, Remigijus Gaska
  • Patent number: 10021783
    Abstract: A support structure located at a bottom of a ball grid array (BGA) is provided. The support structure includes a printed circuit board (PCB) having first positioning pin holes, an interface plate having second positioning pin holes which correspond to the first positioning pin holes arranged on the PCB, a support film arranged on the PCB and having support portions, and positioning components penetrating the first positioning pin holes and the second positioning pin holes corresponding to the first positioning pin holes to assemble the support film on the PCB and the interface plate.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: July 10, 2018
    Assignee: CHUNGHWA PRECISION TEST TECH. CO., LTD.
    Inventors: Yung-Tai Su, Ching-Fang Cheng, Ti-Chiang Chiu
  • Patent number: 9935079
    Abstract: Embodiments of a microelectronic packaged device and methods of making are provided, where the microelectronic packaged device includes a system package comprising a first die and a second die, wherein the first die and the second die are laterally positioned to one another, and the first die and the second die are laterally separated from one another by mold compound; and a conductive trace formed between a first conductive surface on an exposed surface of the first die and a second conductive surface on an exposed surface of the second die, wherein the conductive trace is laser sintered directly on the first conductive surface, on a portion of the exposed surface of the first die, on a portion of a top surface of the mold compound, on a portion of the exposed surface of the second die, and on the second conductive surface.
    Type: Grant
    Filed: December 8, 2016
    Date of Patent: April 3, 2018
    Assignee: NXP USA, Inc.
    Inventors: Chee Seng Foong, Trent Uehling, Leo M. Higgins, III
  • Patent number: 9705105
    Abstract: An electrical component (40) and a substrate (100) constitute at least a portion of an electrical device. At least one surface of the substrate (100) is formed of an insulator. A conductor (20) is formed on the one surface. The conductor (20) is covered with a sealing film (210). The sealing film (210) is a film having insulation properties. An opening (212) is formed in the sealing film (210). The opening (212) is located on a portion of the conductor (20) when seen in a plan view. The conductor (20) is connected to the electrical component (40) with an anisotropic conductive film (30) interposed therebetween. The anisotropic conductive film (30) overlaps the opening (212), and contains a plurality of metal particles.
    Type: Grant
    Filed: April 1, 2013
    Date of Patent: July 11, 2017
    Assignees: PIONEER CORPORATION, TOHOKU PIONEER CORPORATION
    Inventor: Hidetaka Ohazama
  • Patent number: 9601324
    Abstract: A method including bonding a process wafer having integrated circuits and a carrier wafer having at least one alignment mark to form a wafer assembly. The method further includes aligning the wafer assembly using the at least one alignment mark of the carrier wafer.
    Type: Grant
    Filed: July 14, 2015
    Date of Patent: March 21, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: I-Hsiung Huang, Heng-Hsin Liu, Heng-Jen Lee, Chin-Hsiang Lin
  • Patent number: 9553476
    Abstract: Disclosed is an antenna assembly including a substrate, and a wireless charge antenna pattern on the substrate. The wireless charge antenna pattern has a sectional surface including a plurality of inner angles in which two inner angles are different from each other. The antenna assembly includes a wireless communication antenna pattern formed on the substrate and provided at an outside of the wireless charge antenna pattern. The wireless communication antenna pattern has a plurality of inner angles at a sectional surface thereof, and a plurality of angle values of the inner angles provided at the sectional surface of the wireless communication antenna pattern correspond to a plurality of angle values of the inner angles provided at the sectional surface of the wireless charge antenna pattern, respectively.
    Type: Grant
    Filed: March 22, 2013
    Date of Patent: January 24, 2017
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Jeong Wook An, Jung Oh Lee, Yang Hyun Kim, Ki Min Lee, Hye Min Lee, Sung Hyun Leem, Ki Chul Chang
  • Patent number: 9548039
    Abstract: A display device is driven through no wire cable such as an FPC, and a display image is continuously held for a certain period of time by storing an image signal received from a wireless communication device so that the display image can be held even when the display device is out of communication range with the wireless communication device. A display device includes at least a pixel circuit having an SRAM (static random access memory) circuit, a circuit which controls the pixel circuit, an antenna circuit, a circuit which generates a demodulation signal, a circuit which rectifies a wireless signal, a circuit which generates first voltage, a charge circuit which stores second voltage, a charge control circuit, a voltage supply control circuit, and a circuit which controls the charge control circuit and the voltage supply control circuit.
    Type: Grant
    Filed: February 3, 2014
    Date of Patent: January 17, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Ryo Arasawa, Hiroyuki Miyake
  • Patent number: 9530457
    Abstract: A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board.
    Type: Grant
    Filed: October 21, 2014
    Date of Patent: December 27, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takafumi Betsui, Naoto Taoka, Motoo Suwa, Shigezumi Matsui, Norihiko Sugita, Yoshiharu Fukushima
  • Patent number: 9515219
    Abstract: A method for producing a nitride semiconductor device. The method comprises providing a substrate made of a material other than a nitride semiconductor. The material has a hexagonal crystal structure. An upper face of the substrate has at least one flat section. The method further comprises growing a first nitride semiconductor layer on the upper face of the substrate. The first nitride semiconductor layer is made of monocrystalline AlN. The first nitride semiconductor layer has an upper face that is a +c plane. The first nitride semiconductor layer has a thickness in a range of 10 nm to 100 nm. The method further comprises growing a second nitride semiconductor layer on the upper face of the first nitride semiconductor layer. The second nitride semiconductor layer is made of InXAlYGa1-X-YN (0?X, 0?Y, X+Y<1).
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: December 6, 2016
    Assignee: NICHIA CORPORATION
    Inventor: Atsuo Michiue
  • Patent number: 9502364
    Abstract: According to an exemplary embodiment, a semiconductor package is provided. The semiconductor package includes: a backside redistribution layer; at least one component, disposed over and connected to the backside redistribution layer; at least one chip adjacent to the at least one component; a molding compound disposed between the at least one chip and the at least one component; a via, disposed in the molding compound and connected to the backside redistribution layer; and a front redistribution layer, disposed over the chip and the via, wherein the chip and the at least one component are connected by using the backside redistribution layer, the via and the front redistribution layer.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: November 22, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Hsien-Wei Chen, An-Jhih Su
  • Patent number: 9397260
    Abstract: A device having a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions.
    Type: Grant
    Filed: October 9, 2012
    Date of Patent: July 19, 2016
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Rakesh Jain, Wenhong Sun, Jinwei Yang, Maxim S. Shatalov, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Patent number: 9362144
    Abstract: A panel with a reconfigured wafer including semiconductor chips arranged in rows and columns on semiconductor device positions includes: at least one semiconductor chip having a front, a rear and edge sides provided per semiconductor device position. The reconfigured wafer includes: a front side that forms a coplanar area with the front sides of the at least one semiconductor chip and a plastic housing composition embedding the edge sides and the rear side of the at least one semiconductor chip. The reconfigured wafer includes, on a rear side of the wafer, structures configured to stabilize the panel. The structures are composed of the plastic housing composition and are formed as thickenings of the reconfigured wafer.
    Type: Grant
    Filed: June 26, 2012
    Date of Patent: June 7, 2016
    Assignee: INTEL DEUTSCHLAND GMBH
    Inventors: Thorsten Meyer, Markus Brunnbauer
  • Patent number: 9331235
    Abstract: According to one embodiment, a semiconductor device includes a first semiconductor layer of an n type including a nitride semiconductor, a first metal layer of an alloy containing Al and Au, and a second metal layer. The first metal layer is in contact with the first semiconductor layer. The second metal layer is in contact with the first metal layer. The second metal layer includes a metal different from Al. The first metal layer is disposed between the second metal layer and the first semiconductor layer.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: May 3, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshihide Ito, Hiroshi Katsuno, Shinya Nunoue
  • Patent number: 9326387
    Abstract: An electrical connector for electrically connecting a first electronic element having protruding conductive portions in the bottom thereof to a second electronic element, includes an insulating body located below the first and above the second electronic element, a conductor, a solder pad disposed on the lower surface of the insulating body, and a conducting line disposed in the insulating body and conducting the conductor and the solder pad. Upper surface of the insulating body has accommodation holes. Aperture of the accommodation hole is greater than outer diameter of the conductive portion. Wall and bottom of the accommodation holes form the conductor. The accommodation hole has low-melting point liquid metal conductor. When the conductive portion enters the accommodation hole, the liquid metal adheres to the conductive portion, and forms a conductive path between the conductive portion and the conductor. A manufacturing method of the electrical connector.
    Type: Grant
    Filed: December 2, 2013
    Date of Patent: April 26, 2016
    Assignee: LOTES CO., LTD
    Inventor: Ted Ju
  • Patent number: 9252075
    Abstract: A semiconductor device is made from a semiconductor wafer containing semiconductor die separated by a peripheral region. A conductive via-in-via structure is formed in the peripheral region or through an active region of the device to provide additional tensile strength. The conductive via-in-via structure includes an inner conductive via and outer conductive via separated by insulating material. A middle conductive via can be formed between the inner and outer conductive vias. The inner conductive via has a first cross-sectional area adjacent to a first surface of the semiconductor device and a second cross-sectional area adjacent to a second surface of the semiconductor device. The outer conductive via has a first cross-sectional area adjacent to the first surface of the semiconductor device and a second cross-sectional area adjacent to the second surface of the semiconductor device. The first cross-sectional area is different from the second cross-sectional area.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: February 2, 2016
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Lionel Chien Hui Tay, Jianmin Fang, Zigmund R. Camacho
  • Patent number: 9247682
    Abstract: An electronic circuit module includes a circuit board on which electronic components are mounted, and a metal cover covering the circuit board. The metal cover includes a top plate disposed so as to face the circuit board, side plates, and mounting legs. The circuit board has lands to which the mounting legs are joined. The mounting legs each have a bent portion located on the outer periphery of the top plate of the metal cover, and a mounting leg fixing portion in contact with the lands of the circuit board. When seen from the upper surface of the circuit board, the position of the bent portion is on the inner side of the position of the mounting leg fixing portion, and the width of the bent portion is greater than the width of the mounting leg fixing portion.
    Type: Grant
    Filed: July 17, 2013
    Date of Patent: January 26, 2016
    Assignee: Alps Electric Co., Ltd.
    Inventor: Yoshikiyo Watanabe
  • Patent number: 9236412
    Abstract: A method of manufacturing a semiconductor device includes bonding a first semiconductor wafer including a first substrate and a first insulating layer formed to contact one surface of the first substrate, and a second semiconductor wafer including a second substrate and a second insulating layer, forming a third insulating layer, performing etching so that the second insulating layer remains on a second wiring layer, forming a first connection hole, forming an insulating film on the first connection hole, performing etching of the second insulating layer and the insulating film, forming a second connection hole, and forming a first via formed in inner portions of the connection holes and connected to the second wiring layer, wherein a diameter of the first connection hole formed on the other surface of the first substrate is greater than a diameter of the first connection hole formed on the third insulating layer.
    Type: Grant
    Filed: April 11, 2012
    Date of Patent: January 12, 2016
    Assignee: SONY CORPORATION
    Inventor: Masaki Okamoto
  • Patent number: 9215811
    Abstract: A method for manufacturing a multi-piece substrate includes preparing a first frame having a connecting portion to which a first piece substrate is to be connected, forming on a portion of the first piece substrate connected to a second frame a conductive pattern having a contour corresponding to the periphery of the connecting portion of the first frame, irradiating laser along the boundary between the second frame and the conductive pattern on the first piece substrate such that the first piece substrate having a joint portion which engages with the connecting portion of the first frame is detached from the second frame, and fitting the joint portion of the first piece substrate into the connecting portion of the first frame such that the first piece substrate is connected to the first frame.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: December 15, 2015
    Assignee: IBIDEN CO., LTD.
    Inventors: Michimasa Takahashi, Nobuyuki Naganuma, Toshinobu Asai, Teruyuki Ishihara
  • Patent number: 9190368
    Abstract: According to embodiments, a semiconductor device includes an insulating substrate, a first electrode plate disposed on the insulating substrate, a second electrode plate disposed on the insulating substrate, a third electrode plate disposed on the insulating substrate, a first semiconductor element disposed on the first electrode plate, a first electrode of the first semiconductor element being electrically connected to the first electrode plate, a second semiconductor element disposed on the second electrode plate, a first electrode of the second semiconductor element being electrically connected to the second electrode plate, a first bonding wire electrically connecting a second electrode of the first semiconductor element to the third electrode plate, and a second bonding wire electrically connecting a second electrode of the second semiconductor element to the third electrode plate.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: November 17, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoko Sakiyama
  • Patent number: 9147654
    Abstract: An integrated circuit system that includes: providing a substrate including front-end-of-line circuitry; forming a first conductive level including a first conductive trace over the substrate; forming a second conductive level spaced apart from the first conductive level and including a second conductive trace; and connecting the first conductive level to a third conductive level with a viabar that passes through the second conductive level without contacting the second conductive trace.
    Type: Grant
    Filed: July 7, 2008
    Date of Patent: September 29, 2015
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Haifeng Sheng, Fan Zhang, Juan Boon Tan, Bei Chao Zhang, Dong Kyun Sohn
  • Patent number: 9142490
    Abstract: Provided is an integrated circuit device including a through-silicon-via (TSV) structure and a method of manufacturing the integrated circuit device. The integrated circuit device includes a semiconductor structure including a substrate and an interlayer insulating film, a TSV structure passing through the substrate and the interlayer insulating film, a via insulating film substantially surrounding the TSV structure, and an insulating spacer disposed between the interlayer insulating film and the via insulating film.
    Type: Grant
    Filed: July 7, 2014
    Date of Patent: September 22, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-hwa Park, Kwang-jin Moon, Byung-lyul Park, Suk-chul Bang
  • Patent number: 9041205
    Abstract: A semiconductor apparatus includes a semiconductor die having a surface with an integrated circuit thereon coupled to contact pads of an uppermost metallization layer of a semiconductor package substrate by a plurality of conductive contacts. A plurality of discrete metal planes is disposed at the uppermost metallization layer of the semiconductor package substrate, each metal plane located, from a plan view perspective, at a corner of a perimeter of the semiconductor die. Microstrip routing is disposed at the uppermost metallization layer of the semiconductor package substrate, from the plan view perspective, outside of the perimeter of the semiconductor die.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: May 26, 2015
    Assignee: Intel Corporation
    Inventors: Omkar G. Karhade, Nevin Altunyurt, Kyu Oh Lee, Krishna Bharath
  • Patent number: 9030032
    Abstract: Provided is a technology capable of inhibiting a shield film formed over a surface of a sealing body from peeling from the surface of the sealing body, and inhibiting a part of the shield film from bulging from the surface of the sealing body. The present invention is characterized in that a peeling-prevention-mark formation region is provided so as to surround a product-identification-mark formation region, and a plurality of peeling prevention marks are formed in the peeling-prevention-mark formation region. That is, the present invention is characterized in that the region of the surface region of the sealing body which is different from the product-identification-mark formation region is defined as the peeling-prevention-mark formation region, and the peeling prevention marks are formed in the peeling-prevention-mark formation region.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: May 12, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Takashi Kitahara, Hiroshi Koguma
  • Patent number: 9024437
    Abstract: An embodiment of the invention provides a chip package which includes: a substrate having a plurality of sides and a plurality of corner regions, wherein each of the corner regions is located at an intersection of at least two of the sides of the substrate; a device region formed in the substrate; a conducting layer disposed on the substrate and electrically connected to the device region; an insulating layer disposed between the substrate and the conducting layer; and a carrier substrate, wherein the substrate is disposed on the carrier substrate, and the substrate has a recess extending towards the carrier substrate in at least one of the corner regions.
    Type: Grant
    Filed: June 15, 2012
    Date of Patent: May 5, 2015
    Inventors: Yu-Lin Yen, Chien-Hui Chen, Tsang-Yu Liu, Yen-Shih Ho
  • Patent number: 9018755
    Abstract: A joint structure includes: a ceramic member; a metallized layer formed on a surface of the ceramic member; and a metal member joined to the metallized layer via a brazing material. The metal member includes a base part erected on the metallized layer, and an extended part extended from the base part to define a predetermined gap with respect to the metallized layer. The base part includes an end joined to the metallized layer by a brazing material layer including the brazing material, and a side joined to the metallized layer around the base part by a fillet including the brazing material formed on the metallized layer around the base part. The extended part defines a recess at a position facing the metallized layer on which the fillet is formed.
    Type: Grant
    Filed: April 8, 2014
    Date of Patent: April 28, 2015
    Assignee: NGK Spark Plug Co., Ltd.
    Inventors: Sadahiro Nishimura, Naoki Tsuda
  • Patent number: 9013036
    Abstract: A sealing member is disclosed, which includes a first structure and a second structure. The first structure includes a groove with an opening towards the outside of the sealing member, wherein the second structure is disposed in the groove. The first structure includes a first material, and the second structure includes a second material, wherein the water absorption rate of the second material is greater than the water absorption rate of the first material. Also, an electronic device using the sealing member is disclosed.
    Type: Grant
    Filed: September 11, 2013
    Date of Patent: April 21, 2015
    Assignee: Wistron Corp.
    Inventor: Chih-Feng Yeh
  • Patent number: 9006881
    Abstract: An aspect of the present embodiment, there is provided a semiconductor device, including an insulating substrate, at least one semiconductor chip provided above the insulating substrate, a wiring terminal including a connection portion electrically connected to the semiconductor chip, a surrounding frame surrounding the semiconductor chip and the connection portion, an embedded material provided in the surrounding frame covering the semiconductor chip and the connection portion, and a pressing unit provided on a surface of the embedded material.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: April 14, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Fukuyoshi, Junichi Nakao, Yoshiki Endo, Eitaro Miyake
  • Patent number: 9003637
    Abstract: A method of manufacturing a microphone assembly having an ear set function includes assembling a mike cell unit; obtaining a region for connection with the mike cell unit on a PCB, mounting only a conductive member in the region, and mounting other remaining components outside the region; adhering the mike cell unit to a corresponding region of the PCB; and sealing an adhering portion between the mike cell unit and the PCB. Assembling the mike cell unit includes inserting a mike cell case having a sound hole and a curing portion into a diaphragm assembly; stacking a spacer on the diaphragm assembly; inserting a back electrode plate into an insulating ring base; mounting the insulating ring base on the spacer; mounting a metal ring base on the insulating ring base; and curing or clamping a curing portion of the mike cell case.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: April 14, 2015
    Assignee: BSE Co., Ltd.
    Inventors: Dong Sun Lee, Hyoung Joo Kim
  • Patent number: 9000595
    Abstract: To provide a semiconductor device having a reduced size and thickness while suppressing deterioration in reliability. After a semiconductor wafer is ground at a back surface thereof with a grinding material into a predetermined thickness, the resulting semiconductor wafer is diced along a cutting region to obtain a plurality of semiconductor chips. While leaving grinding grooves on the back surface of each of the semiconductor chips, the semiconductor chip is placed on the upper surface of a die island via a conductive resin paste so as to face the back surface of the semiconductor chip and the upper surface of the die island each other. The die island has, on the upper surface thereof, a concave having a depth of from 3 ?m to 10 ?m from the edge of the concave to the bottom of the concave.
    Type: Grant
    Filed: April 3, 2014
    Date of Patent: April 7, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Eiji Ono, Eiji Osugi
  • Patent number: 9000571
    Abstract: An SMT LED device includes an LED and a circuit board carrying the LED. The circuit board has two copper pads thereon, each being provided with a solder on an inner later side thereof which faces the other copper pad. The LED includes two pins and each pin includes a horizontal protrusion and a vertical portion. The LED is mounted on the circuit board between the two copper pads. The solders securely and electrically connect the two pins of the LED with the circuit board.
    Type: Grant
    Filed: June 18, 2012
    Date of Patent: April 7, 2015
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventor: Chih-Chen Lai
  • Patent number: 8994133
    Abstract: Some embodiments of the disclosed subject matter include an integrated circuit. The integrated circuit includes a solid state device controller configured to control a plurality of flash memory devices, a first set of input output IO pads, coupled to the solid state device controller, arranged as a first pad ring around a perimeter of the integrated circuit, and a second set of IO pads arranged adjacent to at least one side of the first pad ring, wherein one of the second set of IO pads includes a power source node configured to receive a power supply voltage for the solid state device controller, a ground node, and a bond pad configured to receive an external signal.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: March 31, 2015
    Assignee: STEC, Inc.
    Inventor: Tsan Lin Chen
  • Patent number: 8981403
    Abstract: A patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers, is provided. The patterned surface can include a set of substantially flat top surfaces and a plurality of openings. Each substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the openings can have a characteristic size between approximately 0.1 micron and five microns.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: March 17, 2015
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Maxim S Shatalov, Rakesh Jain, Jinwei Yang, Michael Shur, Remigijus Gaska
  • Patent number: 8975754
    Abstract: A chip package is described. This chip package includes a substrate having a side at an angle relative to the top and bottom surfaces of the substrate that is between that of a direction parallel to the top and bottom surfaces and that of a direction perpendicular to the top and bottom surfaces (i.e., between 0° and 90°). This side may be configured to couple to a stack of semiconductor dies in which the semiconductor dies are offset from each other in a direction parallel to the top and bottom surfaces so that one side of the stack defines a stepped terrace. For example, the side may include electrical pads. These electrical pads may be coupled to electrical pads on the top surface by through-substrate vias (TSVs) in the substrate. Moreover, the electrical pads on the top surface may be configured to couple to an integrated circuit.
    Type: Grant
    Filed: February 11, 2013
    Date of Patent: March 10, 2015
    Assignee: Oracle International Corporation
    Inventors: Hiren D. Thacker, John E. Cunningham, Ashok V. Krishnamoorthy
  • Patent number: 8963307
    Abstract: Various embodiments related to a compact device package are disclosed herein. In some arrangements, a flexible substrate can be coupled to a carrier having walls angled relative to one another. The substrate can be shaped to include two bends. First and second integrated device dies can be mounted on opposite sides of the substrate between the two bends in various arrangements.
    Type: Grant
    Filed: January 11, 2013
    Date of Patent: February 24, 2015
    Assignee: Analog Devices, Inc.
    Inventor: David Bolognia
  • Patent number: 8952527
    Abstract: Of three chips (2A), (2B), and (2C) mounted on a main surface of a package substrate (1) in a multi-chip module (MCM), a chip (2A) with a DRAM formed thereon and a chip (2B) with a flash memory formed thereon are electrically connected to wiring lines (5) of the package substrate (1) through Au bumps (4), and a gap formed between main surfaces (lower surfaces) of the chips (2A), (2B) and a main surface of the package substrate (1) is filled with an under-fill resin (6). A chip (2C) with a high-speed microprocessor formed thereon is mounted over the two chips (2A) and (2B) and is electrically connected to bonding pads (9) of the package substrate (1) through Au wires (8).
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: February 10, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshiyuki Kado, Takahiro Naito, Toshihiko Sato, Hikaru Ikegami, Takafumi Kikuchi
  • Patent number: 8946875
    Abstract: A packaged semiconductor device includes at least first and second lead-fingers. A molded structure forms a cavity and is molded around portions of each of the first and second lead-fingers to thereby mechanically attach each of the first and second lead-fingers to the molded structure. A semiconductor structure (e.g., a IC, chip or die) is attached within the cavity. First and second bond wires respectively providing electrical connections between the semiconductor structure and the first and second lead-fingers. A further portion of each of the first and second lead-fingers is mechanically attached to a bottom surface of the semiconductor structure to inhibit relative mechanical motion between the semiconductor structure, the molded structure and the first and second lead-fingers.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: February 3, 2015
    Assignee: Intersil Americas LLC
    Inventors: Nikhil Vishwanath Kelkar, Lynn Wiese, Viraj Ajit Patwardhan
  • Patent number: 8941230
    Abstract: A metal plate covers an opening on the upper surface of a core substrate and exposes an outer edge of the upper surface of the core substrate. A conductive layer covers the lower surface of the core substrate. A semiconductor chip bonded to a first surface of the metal plate is exposed through the opening. A first insulating layer covers the upper and side surface of the metal plate and the outer edge of the upper surface of the core substrate. A second insulating layer fills the openings of the metal plate and the conductive layer and covers the outer edge of the lower surface of the core substrate, the conductive layer, and the semiconductor chip. The metal plate is thinner than the semiconductor chip. Total thickness of the conductive layer and the core substrate is equal to or larger than the thickness of the semiconductor chip.
    Type: Grant
    Filed: August 26, 2013
    Date of Patent: January 27, 2015
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Masahiro Kyozuka, Akihiko Tateiwa, Yuji Kunimoto, Jun Furuichi
  • Patent number: 8937382
    Abstract: The present disclosure relates to the field of fabricating microelectronic device packages and, more particularly, to microelectronic device packages having bumpless build-up layer (BBUL) designs, wherein at least one secondary device is disposed within the thickness (i.e. the z-direction or z-height) of the microelectronic device of the microelectronic device package.
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: January 20, 2015
    Assignee: Intel Corporation
    Inventors: Weng Hong Teh, John S. Guzek
  • Patent number: 8912648
    Abstract: A semiconductor device has a stress relief buffer mounted to a temporary substrate in locations designated for bump formation. The stress relief buffer can be a multi-layer composite material such as a first compliant layer, a silicon layer formed over the first compliant layer, and a second compliant layer formed over the silicon layer. A semiconductor die is also mounted to the temporary substrate. The stress relief buffer can be thinner than the semiconductor die. An encapsulant is deposited between the semiconductor die and stress relief buffer. The temporary substrate is removed. An interconnect structure is formed over the semiconductor die, encapsulant, and stress relief buffer. The interconnect structure is electrically connected to the semiconductor die. A stiffener layer can be formed over the stress relief buffer and encapsulant. A circuit layer containing active devices, passive devices, conductive layers, and dielectric layers can be formed within the stress relief buffer.
    Type: Grant
    Filed: September 13, 2011
    Date of Patent: December 16, 2014
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Yaojian Lin, Il Kwon Shim, Seng Guan Chow
  • Patent number: 8907467
    Abstract: A semiconductor package includes a baseplate having a die attach region and a peripheral region, a transistor die having a first terminal attached to the die attach region, and a second terminal and a third terminal facing away from the baseplate, and a frame including an electrically insulative member having a first side attached to the peripheral region of the baseplate, a second side facing away from the baseplate, a first metallization at the first side of the insulative member and a second metallization at the second side of the insulative member. The insulative member extends outward beyond a lateral sidewall of the baseplate. The first metallization is attached to the part of the first side which extends outward beyond the lateral sidewall of the baseplate. The first and second metallizations are electrically connected at a region of the insulative member spaced apart from the lateral sidewall of the baseplate.
    Type: Grant
    Filed: March 28, 2012
    Date of Patent: December 9, 2014
    Assignee: Infineon Technologies AG
    Inventors: Alexander Komposch, Soon Ing Chew, Brian Condie
  • Patent number: 8901728
    Abstract: A three-dimensional structure in which a wiring and a pad part are provided on a surface is provided. A recessed gutter for wiring and a hole for the pad part having a depth that is greater than a thickness of the recessed gutter for wiring are provided on the surface of the three-dimensional structure. The hole for the pad part is provided in succession with the recessed gutter for wiring. At least a part of a wiring conductor is embedded in the recessed gutter for wiring and in the hole for the pad part.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: December 2, 2014
    Assignee: Panasonic Corporation
    Inventors: Shingo Yoshioka, Hiroaki Fujiwara