Abstract: In a CSP type semiconductor device, the invention prevents a second wiring from forming a narrowed portion on a lower surface of a step portion at the time of forming the second wiring that is connected to the back surface of a first wiring formed near a side surface portion of a semiconductor die on the front surface and extends onto the back surface of the semiconductor die over the step portion of a window that is formed from the back surface side of the semiconductor die so as to expose the back surface of the first wiring. A glass substrate is bonded on a semiconductor substrate on which a first wiring is formed on the front surface near a dicing line with an adhesive resin being interposed therebetween. The semiconductor substrate is then etched from the back surface to form a window having step portions with inclined sidewalls around the dicing line as a center.

Abstract: A semiconductor device includes: a package; an input matching circuit and an output matching circuit in the package; and transistor chips between the input matching circuit and the output matching circuit in the package. Each transistor chip includes a semiconductor substrate having long sides and short sides that are shorter than the long sides, and a gate electrode, a drain electrode and a source electrode on the semiconductor substrate. The gate electrode has gate fingers arranged along the long sides of the semiconductor substrate and a gate pad commonly connected to the gate fingers and connected to the input matching circuit via a first wire. The drain electrode is connected to the output matching circuit via a second wire. The long sides of the semiconductor substrates of the transistor chips are oblique with respect to an input/output direction extending from the input matching circuit to the output matching circuit.

Abstract: A support substrate includes a first surface and a second surface located above the level of the first surface. Chips are mounted on the first surface. A first insulating film is disposed over each chip. First conductive plugs are connected to the chip extending through each first insulating film. Filler material made of resin filling a space between chips. Wirings are disposed over the first insulating film and the filler material for interconnecting different chips. The second surface, an upper surface of the first insulating film and an upper surface of the filler material are located at the same level.

Abstract: Disclosed is a semiconductor light emitting element (1) which is provided with: a laminated semiconductor layer which is formed on a substrate, and in which a first semiconductor layer having a first conductivity type, a light emitting layer, and a second semiconductor layer having a second conductivity type different from the first conductivity type; a first electrode (first electrode (170)) which is formed on a surface of the first semiconductor layer in the laminated semiconductor layer, and has a first opening (170a) used for electrical connection with an outside; and a second electrode (second electrode (180)) which is formed on a surface of the second semiconductor layer, and has a second opening (180a) used for electrical connection with the outside. The surface of the second semiconductor layer is exposed by cutting off a part of the laminated semiconductor layer.

Abstract: Semiconductor chips are placed in recesses of a support carrier with electrode surfaces facing upward in a state where the semiconductor chips are arranged separately from each other. A seal resin part is formed by encapsulating the semiconductor chips by an insulating resin on said support carrier. Rewiring patterns are formed on a top surface of the seal resin part. External connection terminals are formed on the rewiring patterns. Bottom parts of the recesses of the support carrier are removed from the seal resin part while maintaining reinforcing members of the support carrier to be remained. The semiconductor packages are individualized by cutting the seal resin part along an outside of each reinforcing member.

Abstract: In various embodiments, an integrated circuit die is provided. The integrated circuit die may include a circuit on a surface of a semiconductor substrate that has a peripheral sidewall extending substantially perpendicular to and away from the surface. A first protective layer may cover the sidewall of the semiconductor substrate and peripheral edges of the circuit to provide protection from contaminant diffusion. In some embodiments, a semiconductor substrate is provided that has a plurality of dice contained thereon. Each of the dice may have an integrated circuit region and a peripheral sidewall etched into the semiconductor substrate. A first protective layer may be used to cover the peripheral sidewall of the semiconductor substrate to provide protection from contaminant diffusion. Additional apparatuses, systems, and methods are disclosed.

Abstract: An electronic package with improved warpage compensation. The electronic package includes a mold cap having a variable thickness. The variable thickness can have a mound or dimple design. In another embodiment, a method is provided for reducing unit warpage of an electronic package by designing the topography of a mold cap to compensate for warpage.

Abstract: According to one embodiment, a package for housing semiconductor element includes: a base plate including a top surface and a recessed portion formed as a downwardly-recessed portion of the top surface; a peripheral wall provided on the top surface of the base plate; a lid provided on an upper side of the peripheral wall and forming a semiconductor element housing space in cooperation with the base plate and the peripheral wall; and a feed-through terminal including a bottom end and fixed to the recessed portion so that the bottom end is located at a lower position than the top surface of the base plate except the recessed portion.

Abstract: A packaged semiconductor device includes a package substrate, a semiconductor die on the package substrate, an encapsulant over the semiconductor die and package substrate, and a heat spreader having a pedestal portion and an outer portion surrounding the pedestal portion. The encapsulant includes an opening within a perimeter of the semiconductor die. The bottom surface of the pedestal portion of the heat spreader faces the top surface of the semiconductor die, wherein a first portion of the opening and at least a portion of the encapsulant is between the bottom surface of the pedestal portion and the semiconductor die.

Abstract: An electronic component includes: a substrate; a functional portion provided on the substrate; an interconnection line provided on the substrate and electrically connected to the functional portion; a metal wall provided on the substrate so as to surround the functional portion and the interconnection line; and a seal portion that contacts the metal wall and covers the functional portion and the interconnection line so as to define a cavity above the functional portion, the seal portion being made of liquid crystal polymer.

Abstract: A sensor arrangement is provided, the sensor arrangement including a chip including a sensor circuit configured to detect a bending of the chip; and a package structure configured to protect the chip; wherein the package structure includes a first region and a second region, and wherein the package structure is configured such that it is easier to be deformed in the first region than in the second region.

Abstract: A method of forming an integrated circuit (IC) package is disclosed comprising: (a) removing oxides from side surfaces of terminals of the IC package; (b) substantially covering an underside of the terminals of the IC package; and (c) forming a solder coating on the side surfaces of terminals of the IC packages while covering the underside of the terminals of the IC package. The solder coating on the side surfaces of the terminals protects the terminals from oxidation due to aging and subsequent processes. Additionally, the solder coating on the side surfaces of the terminals substantially improves the solderability of the IC package to printed circuit boards (PCBs) or other mountings. This further facilitates the inspection of the solder attachment using less expensive and complicated methods.

Abstract: A method of manufacture of an integrated circuit packaging system includes: mounting an integrated circuit over a package carrier; mounting a conductive connector over the package carrier; forming an encapsulation over the integrated circuit, the encapsulation having a recess exposing the conductive connector; and mounting a heat slug over the encapsulation, the heat slug having an opening with an opening width greater than a recess width of the recess, the opening exposing a portion of a top surface of the encapsulation.

Abstract: Microelectronic devices having intermediate contacts, and associated methods of packaging microelectronic devices with intermediate contacts, are disclosed herein. A packaged microelectronic device configured in accordance with one embodiment of the invention includes a microelectronic die attached to an interconnecting substrate. The microelectronic die includes an integrated circuit electrically coupled to a plurality of terminals. Each of the terminals is electrically coupled to a corresponding first contact on the die with an individual wire-bond. Each of the first contacts on the die is electrically coupled to a corresponding second contact on the interconnecting substrate by a conductive coupler such as a solder ball.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a package substrate having a warpage-compensation zone with a substrate-interior layer exposed from a top substrate-cover, and the warpage-compensation zone having contiguous exposed portion of the substrate-interior layer over corner portions of the package substrate; connecting an integrated circuit die to the package substrate with an internal interconnect; and forming an encapsulation over the integrated circuit die, with the encapsulation directly on the substrate-interior layer in the warpage-compensation zone.

Abstract: A package structure and a package process are provided. In the package process, firstly, a first electronic component having a plurality of first conductive bumps at a bottom thereof is provided. Then, a first insulation paste is coated on the first conductive bumps. The first electronic component is disposed on a circuit substrate having a plurality of substrate pads, and the first conductive bumps are respectively situated on the substrate pads. Next, a heating process is performed to both of the first conductive bumps and the first insulation paste, wherein the first conductive bumps is reflowed to bond the first electronic component and the substrate pads, and the first insulation paste is cured.

Abstract: A MEMS package includes a substrate having an L-shaped cross-section. The substrate includes a vertical portion having a front surface and a back surface, and a horizontal portion protruding from a lower part of the front surface of the vertical portion, wherein the front surface of the vertical portion includes a mounting region. A MEMS die is mounted on the mounting region such that the MEMS die is oriented substantially parallel to the front surface; a lid attached to the front surface of the substrate while covering the MEMS die; and a plurality of leads formed on a bottom surface of the substrate. The leads can extend substantially parallel to one another, and substantially perpendicular to the front surface. The MEMS die can be oriented substantially perpendicular to a PCB substrate on which the package is mounted.

Abstract: A device including two mounting surfaces. One embodiment provides a power semiconductor chip and having a first electrode on a first surface and a second electrode on a second surface opposite to the first surface. A first external contact element and a second external contact element, are both electrically coupled to the first electrode of the semiconductor chip. A third external contact element and a fourth external contact element, both electrically coupled to the second electrode of the semiconductor chip. A first mounting surface is provided on which the first and third external contact elements are disposed. A second mounting surface is provided on which the second and fourth external contact elements are disposed.

Abstract: A fabrication method of a semiconductor package includes the steps of: providing a carrier having a concave portion and a releasing layer formed on a surface thereof; disposing a chip on the releasing layer in the concave portion; forming an encapsulant on the chip and the releasing layer; removing the releasing layer and the carrier; and forming a circuit structure on the encapsulant and the chip. The design of the concave portion facilitates alignment of the chip to prevent it from displacement, thereby improving the product reliability. A semiconductor package fabricated by the fabrication method is also provided.

Abstract: There is provided a thin film transistor having improved reliability. A gate electrode includes a first gate electrode having a taper portion and a second gate electrode with a width narrower than the first gate electrode. A semiconductor layer is doped with phosphorus of a low concentration through the first gate electrode. In the semiconductor layer, two kinds of n?-type impurity regions are formed between a channel formation region and n+-type impurity regions. Some of the n?-type impurity regions overlap with a gate electrode, and the other n?-type impurity regions do not overlap with the gate electrode. Since the two kinds of n?-type impurity regions are formed, an off current can be reduced, and deterioration of characteristics can be suppressed.

Abstract: Stacked semiconductor devices and assemblies including attached lead frames are disclosed herein. One embodiment of a method of manufacturing a semiconductor assembly includes forming a plurality of first side trenches to a first intermediate depth in a molded portion of a molded wafer having a plurality of dies arranged in rows and columns. The method also includes forming a plurality of lateral contacts at sidewall portions of the trenches and electrically connecting first side bond-sites of the dies with corresponding lateral contacts of the trenches. The method further includes forming a plurality of second side channels to a second intermediate depth in the molded portion such that the channels intersect the trenches. The method also includes singulating and stacking the first and second dies with the channels associated with the first die aligned with channels associated with the second die.

Abstract: One or more integrated circuit chips are flip-chip bonded to a first surface of a substrate. A contact array is fabricated on a second surface of the substrate. Corner structures attached to the integrated circuit chip cover at least two corners of the IC chip.

Abstract: Of three chips (2A), (2B), and (2C) mounted on a main surface of a package substrate (1) in a multi-chip module (MCM), a chip (2A) with a DRAM formed thereon and a chip (2B) with a flash memory formed thereon are electrically connected to wiring lines (5) of the package substrate (1) through Au bumps (4), and a gap formed between main surfaces (lower surfaces) of the chips (2A), (2B) and a main surface of the package substrate (1) is filled with an under-fill resin (6). A chip (2C) with a high-speed microprocessor formed thereon is mounted over the two chips (2A) and (2B) and is electrically connected to bonding pads (9) of the package substrate (1) through Au wires (8).

Abstract: A semiconductor device includes a wiring substrate, a semiconductor element mounted on the wiring substrate, a first radiator member arranged on and thermally coupled to the semiconductor element, and a second radiator member arranged on and thermally coupled to the first radiator member. The second radiator member includes projections which project out toward the first radiator member. The projections are formed on a circumference of a concentric circle with respect to a center point of the second radiator member. The first radiator member includes grooves in which the projections are movable. The grooves are formed on a circumference of a concentric circle with respect to a center point of the first radiator member. The projections are fitted to terminating ends of the grooves with the center point of the first radiator member and the center point of the second radiator member coincided.

Abstract: A seek-scan probe (SSP) memory involves multiple-wafer bonding needing precision small gaps in between. Solder reflow bonding is typically used to join the wafers due to its reliability and ability to hermetically seal. However, solder reflow bonding may not provide a consistently controllable gap due to flowing solder during the bonding process. Thus, a bond stop technique and process is used to provide accurate cantilever to media gap control.

Abstract: A micromechanical assembly for bonding semiconductor substrates includes a semiconductor substrate having a chip pattern having a plurality of semiconductor chips, each having a functional region and an edge region surrounding the functional region. There is a bonding frame made of a bonding alloy made from at least two alloy components in the edge region, spaced apart from the functional region. Within the part of the edge region surrounding the bonding frame between the bonding frame and the functional region, there is at least one stop frame made of at least one of the alloy components, which is configured such that when a melt of the bond alloy contacts the stop frame during bonding, the bonding alloy solidifies.

Abstract: A silicon device has a flat panel shape which is a polygon in a plan view, and at least one corner of the polygon includes two sides adjacent to each other out of plural sides of the polygon and a corner curve portion connected to the two sides so as to connect the two sides.

Abstract: A semiconductor substrate having a semiconductor device formable area, wherein a reinforcing part, which is thicker than the semiconductor device formable area and has a top part of which surface is flat, is formed on an outer circumference part of the semiconductor substrate, and an inner side surface connecting the top part of the reinforcing part and the semiconductor device formable area has a cross-sectional shape of which inner diameter becomes smaller as being closer to the semiconductor device formable area.

Abstract: A layered substrate includes a first substrate including an upper surface, a lower surface, a peripheral surface between peripheral edges of the upper surface and the lower surface, and a cut portion cut into the peripheral surface and passing through the upper surface and the lower surface, and a second substrate including an upper surface, a lower surface, and a peripheral surface between peripheral edges of the upper surface and the lower surface, and the lower surface of the second substrate layered on the upper surface of the first substrate and closing the cut portion of the first substrate from above. The second substrate includes a heat conductor that is thermally connected to an element to be mounted on the upper surface of the second substrate, the heat conductor configured to thermally extend to the cut portion of the first substrate.

Abstract: A resin sealing method of a semiconductor device includes: positioning semiconductor devices at predetermined positions of an adhesive layer formed on a support body and adhering the semiconductor devices thereto, sealing a part of each of the semiconductor devices with resin by curing a first seal resin in a fluidization state so as to fix the semiconductor devices adhered to the predetermined positions of the adhesive layer formed on the support body, setting the semiconductor devices fixed to the predetermined positions of the adhesive layer formed on the support body in a mold and sealing the exposure parts of the semiconductor devices exposed from the first seal resin with a second seal resin, and removing the support body and the adhesive layer from the semiconductor devices sealed with the resin.

Abstract: Embodiments include a light emitting device package. The light emitting device package comprises a housing including a cavity; a light emitting device positioned in the cavity; a lead frame including a first section electrically connected to the light emitting device in the cavity, a second section, which penetrates the housing, extending from the first section and a third section, which is exposed to outside air, extending from the second section; and a metal layer positioned on an area defined by a distance which is distant from the housing in the second section of the lead frame.

Abstract: An assembly of microelectronic devices and method for forming an assembly of microelectronic devices. In one embodiment, an assembly comprises a support member having support member circuitry and a first microelectronic die attached to the support member and coupled to the support member circuitry with first conductive members. The assembly further comprises a second microelectronic die positioned at least proximate to the first microelectronic die and coupled directly to the support member circuitry with second conductive members that are not in direct contact with the first conductive members. One of the first or second microelectronic dies is positioned between the support member and the other of the first and second microelectronic dies.

Abstract: An embodiment of the invention provides a chip package, which includes: a semiconductor substrate having a device region and a non-device region neighboring the device region; a package layer disposed on the semiconductor substrate; a spacing layer disposed between the semiconductor substrate and the package layer and surrounding the device region and the non-device region; a ring structure disposed between the semiconductor substrate and the package layer, and between the spacing layer and the device region, and surrounding a portion of the non-device region; and an auxiliary pattern including a hollow pattern formed in the spacing layer or the ring structure, a material pattern located between the spacing layer and the device region, or combinations thereof.

Abstract: A storage battery control device detects an overhead wire supply current value showing a sum of a current value output from a storage battery and a current value output from a transformer substation, and charging or discharging of the storage battery is controlled so that a charging rate of the storage battery becomes a charging rate target value when the detected overhead wire supply current value is less than a first threshold. In addition, charging or discharging of the storage battery is controlled so that the output voltage of the storage battery control device is maintained at a constant voltage control mode when the detected overhead wire supply current value is greater than or equal to the first threshold.

Abstract: In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package.

Abstract: A semiconductor device or semiconductor package (e.g., a QFP package) including a uniquely configured leadframe sized and configured to maximize the available number of exposed leads in the semiconductor package, and further to provide one or more power bars in the semiconductor package. More particularly, the semiconductor package of the present invention includes a generally planar die paddle or die pad defining multiple peripheral edge segments. In addition, the semiconductor package includes a plurality of leads. Some of these leads include exposed bottom surface portions which are provided in at least two concentric rows or rings which at least partially circumvent the die pad, with other leads including portions which protrude from respective side surfaces of a package body of the semiconductor package. Connected to the top surface of the die pad is at least one semiconductor die which is electrically connected to at least some of the leads.

Abstract: A semiconductor device includes a substrate having a first surface and an opposite second surface. An electrode extends within the substrate towards the first surface and has a protruding portion extending from the first surface. A supporting portion extends from the first surface of the substrate to a sidewall of the protruding portion and supports the protruding portion.

Abstract: A chip stack structure includes a logic chip having an active device surface, and memory slices of a memory unit vertically aligned such that a surface of the memory slices is oriented perpendicular to the active device surface of the logic chip. The chip stack structure also includes wiring patterned on an upper surface of the memory slices, the wiring electrically connecting memory leads of the memory slices to logic grids corresponding to logic grid connections of the logic chip.

Abstract: An encapsulated micro-electro-mechanical device, wherein a MEMS chip is encapsulated by a package formed by a first, a second, and a third substrates that are bonded together. The first substrate has a main surface bearing the MEMS chip, the second substrate is bonded to the first substrate and defines a chamber surrounding the MEMS chip, and the third substrate is bonded to the second substrate and upwardly closes the chamber. A grid or mesh structure of electrically conductive material is formed in or on the third substrate and overlies the MEMS chip; the second substrate has a conductive connection structure coating the walls of the chamber, and the first substrate incorporates an electrically conductive region, which forms, together with the conductive layer and the grid or mesh structure, a Faraday cage.

Abstract: A semiconductor device having a structure that can reduce stress due to difference in coefficients of thermal expansion and prevent or suppress generation of cracks, and a semiconductor device manufacturing method, are provided. The semiconductor device includes a single crystal silicon substrate having a main face on which semiconductor elements are formed and a side face intersecting with the main face, and a sealing resin provided covering at least a portion of the side face. The side face covered by the sealing resin is equipped with a first face with a plane direction forming an angle of ?5° to +5° to the plane direction of the main face.

Abstract: A backside illuminated image sensor includes a substrate layer having a frontside and a backside. An array of photosensitive pixels is disposed within the substrate layer and is sensitive to light incident through the backside of the substrate layer. A metal grid is disposed over the backside of the substrate layer. The metal grid surrounds each of the photosensitive pixels and defines optical apertures for receiving the light into the photosensitive pixels through the backside. The metal grid includes intersecting wires each having a triangular cross-section. A material layer surrounds the metal grid.

Abstract: A semiconductor package and a package on package are provided. The semiconductor package includes a substrate; a semiconductor chip attached to a surface of the substrate; connecting conductors disposed on the surface of the substrate; a mold formed on the substrate and in which the connecting conductors and the semiconductor chip are provided; and connecting via holes extending through the mold and exposing the connecting conductors. With respect to a first connecting via hole of the connecting via holes, a planar distance between a first connecting conductor exposed by the first connecting via hole and an entrance of the first connecting via hole is not uniform.

Abstract: Of three chips (2A), (2B), and (2C) mounted on a main surface of a package substrate (1) in a multi-chip module (MCM), a chip (2A) with a DRAM formed thereon and a chip (2B) with a flash memory formed thereon are electrically connected to wiring lines (5) of the package substrate (1) through Au bumps (4), and a gap formed between main surfaces (lower surfaces) of the chips (2A), (2B) and a main surface of the package substrate (1) is filled with an under-fill resin (6). A chip (2C) with a high-speed microprocessor formed thereon is mounted over the two chips (2A) and (2B) and is electrically connected to bonding pads (9) of the package substrate (1) through Au wires (8).

Abstract: A chip arrangement includes semiconductor chips coupled to opposing sides of an insulating layer. The arrangement includes a first semiconductor chip having a first chip surface presenting a first chip conductive region. An electrically insulating layer includes a first layer surface presenting a first layer conductive region, and a second, opposing surface presenting a second layer conductive region. The electrically insulating layer is coupled to the first semiconductor chip by applying the first layer conductive region to the first chip conductive region. The electrically insulating layer is then coupled to the second chip conductive region by applying the second layer conductive region to the second chip conductive region.

Abstract: A package-base structure of a luminescent diode and its fabricating process. The package-base structure includes a substrate having thereon a holding space; an insulating layer extending from a bottom surface of the holding space to the bottom of the substrate; an through hole defined in the insulating layer; and a conductive layer disposed over the insulating layer. The insulating layer decouples the current flow and heat flow to increase the lifetime of the package-base structure together with the luminescent diode. In the fabricating process, the insulating layer is formed by anodic etching to allow the insulating layer have a porous structure.

Abstract: A back-illuminated type MOS (metal-oxide semiconductor) solid-state image pickup device 32 in which micro pads 34, 37 are formed on the wiring layer side and a signal processing chip 33 having micro pads 35, 38 formed on the wiring layer at the positions corresponding to the micro pads 34, 37 of the MOS solid-state image pickup device 32 are connected by micro bumps 36, 39. In a semiconductor module including the MOS type solid-state image pickup device, at the same time an image processing speed can be increased, simultaneity within the picture can be realized and image quality can be improved, a manufacturing process can be facilitated, and a yield can be improved. Also, it becomes possible to decrease a power consumption required when all pixels or a large number of pixels is driven at the same time.

Abstract: A semiconductor package includes a conductive base, a die disposed adjacent to an upper surface of the conductive base, a patterned conductive layer, and a dielectric layer encapsulating the die. The dielectric layer defines an opening through which the patterned conductive layer is electrically connected to the upper surface of the conductive base. The conductive base has a lateral surface including a first portion adjacent to the upper surface of the conductive base and a second portion adjacent to a lower surface of the conductive base, where the second portion is sloped inwardly with respect to the lower surface of the conductive base.

Abstract: A power module includes at least one semiconductor die holding structure. Each die holding structure has a substantially cylindrical outer profile and a central axis. Each die holding structure is disposed within a common cylindrical EMI shield. A plurality of semiconductor devices are mounted to each die holding structure to form a substantially symmetric die mounting pattern respect to the central axis of the die holding structure.

Abstract: A method for manufacturing an integrated circuit package system includes: providing a base device; attaching a base interconnect to the base device; applying an encapsulant over the base device and the base interconnect; and forming a re-routing film over the encapsulant, the base device, and the base interconnect for connectivity without a substrate.

Abstract: A no-lead type semiconductor package is formed by attaching a die to a top surface of a flag of a lead frame and then taping a bottom surface of the flag and leads of the lead frame. Die bonding pads are connected to the leads with wires and then the assembly is put in a mold chase and encapsulated with a plastic material. The mold chase has protrusions between the flag and the leads of a lead frame, and between the leads themselves, which causes indentations to be formed between the leads and between the flag and the leads. The method is particularly useful for making quad flat no lead (QFN) devices and power-QFN type devices.