Abstract: A cryogenic under bump metallization (UBM) stack includes an adhesion and barrier layer and a conductive pillar on the adhesion and barrier layer. The conductive pillar functions as a solder wetting layer of the UBM stack and has a thickness. An indium superconducting solder bump is on the conductive pillar. The thickness of the conductive pillar is sufficient to prevent intermetallic regions, which form in the conductive pillar at room temperature due to interdiffusion, from extending through the entire thickness of the conductive pillar to maintain the structural integrity of the UBM stack. The indium (In) solder bump may be formed through electroplating, with the conductive pillar being copper (Cu) and the adhesion and barrier layer being titanium tungsten (TiW) and a thin seed layer of copper (Cu), or a layer of titanium (Ti).

Abstract: A redistribution layer with a landing pad is formed over a substrate with one or more mesh holes extending through the landing pad. The mesh holes may be arranged in a circular shape, and a passivation layer may be formed over the landing pad and the mesh holes. An opening is formed through the passivation layer and an underbump metallization is formed in contact with an exposed portion of the landing pad and extends over the mesh holes. By utilizing the mesh holes, sidewall delamination and peeling that might otherwise occur may be reduced or eliminated.

Abstract: A method includes forming a first dielectric layer, forming a first redistribution line comprising a first via extending into the first dielectric layer, and a first trace over the first dielectric layer, forming a second dielectric layer covering the first redistribution line, and patterning the second dielectric layer to form a via opening. The first redistribution line is revealed through the via opening. The method further includes forming a second via in the second dielectric layer, and a conductive pad over and contacting the second via, and forming a conductive bump over the conductive pad. The conductive pad is larger than the conductive bump, with a first center of conductive pad being offsetting from a second center of the conductive bump. The second via is further offset from the second center of the conductive bump.

Abstract: A semiconductor package includes a semiconductor substrate forming a cavity and a redistribution layer on a first side of the semiconductor substrate, the redistribution layer forming die contacts within the cavity and a set of terminals for the semiconductor package opposite the semiconductor substrate. The redistribution layer electrically connects one or more of the die contacts to the set of terminals. The semiconductor package further includes a semiconductor die including die terminals within the cavity with the die terminals electrically coupled to the die contacts within the cavity.

Abstract: A package structure and methods of forming a package structure are provided. The package structure includes a first die, a second die, a wall structure and an encapsulant. The second die is electrically bonded to the first die. The wall structure is located aside the second die and on the first die. The wall structure is in contact with the first die and a hole is defined within the wall structure for accommodating an optical element. The encapsulant laterally encapsulates the second die and the wall structure.

Abstract: A Cu3Sn electrical interconnect and method of making same in an electrical device, such as for hybrid bond 3D-integration of the electrical device with one or more other electrical devices. The method of forming the Cu3Sn electrical interconnect includes: depositing a Sn layer in the via hole; depositing a Cu layer atop and in contact with the Sn layer; and heating the Sn layer and the Cu layer such that the Sn and Cu layers diffuse together to form a Cu3Sn interconnect in the via hole. During the heating, a diffusion front between the Sn and Cu layers moves in a direction toward the Cu layer as initially deposited, such that any remaining Cu layer or any voids formed during the diffusion are at an upper region of the formed Cu3Sn interconnect in the via hole, thereby allowing such voids or remaining material to be easily removed.

Abstract: A semiconductor device includes a conductive pad having a first width. The semiconductor device includes a passivation layer over the conductive pad, wherein the passivation layer directly contacts the conductive pad. The semiconductor device includes a protective layer over the passivation layer, wherein the protective layer directly contacts the conductive pad. The semiconductor device includes an under-bump metallization (UBM) layer directly contacting the conductive pad, wherein the UBM layer has a second width greater than the first width. The semiconductor device includes a conductive pillar on the UBM layer.

Abstract: Embodiments provide a method for packaging a semiconductor, a semiconductor package structure, and a package. The method includes: providing a substrate wafer having a first surface and a second surface arranged opposite to each other, the first surface having a plurality of grooves, a plurality of electrically conductive pillars being provided at a bottom of the groove, and the electrically conductive pillar penetrating through the bottom of the groove to the second surface; providing a plurality of semiconductor die stacks; placing the semiconductor die stack in the groove; and covering a cover plate wafer on the first surface of the substrate wafer to seal up the groove so as to form a semiconductor package structure, a gap between the substrate wafer, the semiconductor die stack and the cover plate wafer being not filled with a filler.

Abstract: A method of forming a package includes bonding a device die to an interposer wafer, with the interposer wafer including metal lines and vias, forming a dielectric region to encircle the device die, and forming a through-via to penetrate through the dielectric region. The through-via is electrically connected to the device die through the metal lines and the vias in the interposer wafer. The method further includes forming a polymer layer over the dielectric region, and forming an electrical connector. The electrical connector is electrically coupled to the through-via through a conductive feature in the polymer layer. The interposer wafer is sawed to separate the package from other packages.

Abstract: Semiconductor device packages and method are provided. A semiconductor device package according to the present disclosure includes a substrate including a first region, a passive device disposed over the first region of the substrate, a contact pad disposed over the passive device, a passivation layer disposed over the contact pad, a recess through the passivation layer, and an under-bump metallization (UBM) layer. The recess exposes the contact pad and the UBM layer includes an upper portion disposed over the passivation layer and a lower portion disposed over a sidewall of the recess. A projection of the upper portion of the UBM layer along a direction perpendicular to the substrate falls within an area of the contact pad.

Abstract: An electronic device structure having a shielding structure includes a substrate with an electronic component electrically connected to the substrate. The shielding structure includes conductive spaced-apart pillar structures that have proximate ends connected to the substrate and distal ends spaced apart from the substrate, and that are laterally spaced apart from the first electronic component. In one embodiment, the conductive pillar structures are conductive wires attached at one end to the substrate with an opposing end extending away from the substrate so that the conductive wires are provided generally perpendicular to the substrate. A package body encapsulates the electronic component and the conductive spaced-apart pillar structures. In one embodiment, the shielding structure further includes a shielding layer disposed adjacent the package body, which is electrically connected to the conductive spaced-apart pillar structures. In one embodiment, the electrical connection is made through the package.

Abstract: A semiconductor device includes a first Chip-On-Wafer (CoW) device having a first interposer and a first die attached to a first side of the first interposer; a second CoW device having a second interposer and a second die attached to a first side of the second interposer, the second interposer being laterally spaced apart from the first interposer; and a redistribution structure extending along a second side of the first interposer opposing the first side of the first interposer and extending along a second side of the second interposer opposing the first side of the second interposer, the redistribution structure extending continuously from the first CoW device to the second CoW device.

Abstract: A semiconductor structure includes a semiconductor wafer, a first surface mount component, a second surface mount component and a first barrier structure. The first surface mount component is disposed on the semiconductor wafer, and electrically connected to the semiconductor wafer through a plurality of first electrical connectors. The second surface mount component is disposed on the semiconductor wafer, and electrically connected to the semiconductor wafer through a plurality of second electrical connectors, wherein an edge of the second surface mount component is overhanging a periphery of the semiconductor wafer. The first barrier structure is disposed on the semiconductor wafer in between the second electrical connectors and the edge of the second surface mount component, wherein a first surface of the first barrier structure is facing the second electrical connectors, and a second surface of the first barrier structure is facing away from the second electrical connectors.

Abstract: A circuit formation method includes: a protruding portion formation step of forming a protruding portion by applying a curable viscous fluid onto a base and curing the curable viscous fluid; a wiring formation step of forming a wiring extending toward the protruding portion by applying a metal-containing liquid containing nanometer-sized metal fine particles onto a base and making the metal-containing liquid conductive; a paste application step of applying a resin paste containing micrometer-sized metal particles different from the metal-containing liquid on the protruding portion and the wiring, such that the protruding portion and the wiring are connected to each other; and a component placement step of placing a component having an electrode on the base, such that the electrode is in contact with the resin paste applied on the protruding portion.

Abstract: A semiconductor light-emitting device includes: a board including a front surface, a back surface facing an opposite side of the front surface, a first wiring pattern formed on the front surface, and a second wiring pattern formed on the side of the back surface with respect to the first wiring pattern; and a light-emitting element, a switching element, and a capacitor, which are electrically connected to one another by both the first wiring pattern and the second wiring pattern. Among the light-emitting element, the switching element, and the capacitor, a first predetermined element and a second predetermined element are arranged in a first direction and the second predetermined element and a third predetermined element are arranged in a second direction. The second wiring pattern forms a second current path opposite to a direction of a first current path. The second current path overlaps the first current path.

Abstract: A chip structure is provided. The chip structure includes a substrate. The chip structure includes a redistribution layer over the substrate. The chip structure includes a bonding pad over the redistribution layer. The chip structure includes a shielding pad over the redistribution layer and surrounding the bonding pad. The chip structure includes an insulating layer over the redistribution layer and the shielding pad. The chip structure includes a bump over the bonding pad and the insulating layer. A sidewall of the bump is over the shielding pad.

Abstract: A semiconductor device assembly can include a substrate including a plurality of external connections. The assembly can include a first individual module and a first bond pad. The first individual module can be disposed on the substrate such that the first side of the first individual module faces the substrate. In some embodiments, the first individual module electrically is coupled to an external connection of the substrate via the first bond pad. The assembly can include a second individual module comprising a plurality of lateral sides. The second individual module can be disposed over the first individual module. In some embodiments, a first lateral side of the second individual module includes a first step forming a first overhang portion and a first recess. In some embodiments, the first bond pad is vertically aligned with the first recess of the second individual module.

Abstract: A semiconductor device package comprises a semiconductor device, a first encapsulant surrounding the semiconductor device, a second encapsulant covering the semiconductor device and the first encapsulant, and a redistribution layer extending through the second encapsulant and electrically connected to the semiconductor device.

Abstract: A device includes a semiconductor chip including an electrical contact arranged on a main surface of the semiconductor chip. The device includes an external connection element configured to provide a first coax-like electrical connection between the device and a printed circuit board, wherein the first coax-like electrical connection includes a section extending in a direction vertical to the main surface of the semiconductor chip. The device further includes an electrical redistribution layer arranged over the main surface of the semiconductor chip and configured to provide a second coax-like electrical connection between the electrical contact of the semiconductor chip and the external connection element, wherein the second coax-like electrical connection includes a section extending in a direction parallel to the main surface of the semiconductor chip.

Abstract: An example of a cavity structure comprises a cavity substrate comprising a substrate surface, a cavity extending into the cavity substrate, the cavity having a cavity bottom and cavity walls, and a cap disposed on a side of the cavity opposite the cavity bottom. The cavity substrate, the cap, and the one or more cavity walls form a cavity enclosing a volume. A component can be disposed in the cavity and can extend above the substrate surface. The component can be a piezoelectric or a MEMS device. The cap can have a tophat configuration. The cavity structure can be micro-transfer printed from a source wafer to a destination substrate.

Abstract: A semiconductor package structure includes a substrate, a redistribution layer, a first semiconductor component, a conductive pillar, and a second semiconductor component. The redistribution layer is over the substrate. The first semiconductor component is over the redistribution layer. The conductive pillar is adjacent to the first semiconductor component, wherein the first semiconductor component and the conductive pillar are surrounded by a molding material. The second semiconductor component is over the molding material, wherein the second semiconductor component is electrically coupled to the redistribution layer through the conductive pillar.

Abstract: An exemplary semiconductor device can comprise (a) a substrate comprising a substrate dielectric structure between the substrate top side and the substrate bottom side, conductive pads at the substrate bottom side, and a substrate cavity through the substrate dielectric structure, (b) a base electronic component comprising inner short bumps; outer short bumps bounding a perimeter around the inner short bumps, and tall bumps between the outer short bumps and an edge of the base component top side, and (c) a mounted electronic component coupled to the inner short bumps of the base electronic component. The tall bumps of the base component can be coupled to the conductive pads of the substrate. The mounted electronic component can be located in the substrate cavity. The substrate bottom side can cover at least a portion of the outer short bumps of the base electronic component. Other examples and related methods are disclosed herein.

Abstract: A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).

Abstract: The present disclosure provides a semiconductor package including a semiconductor chip and a package substrate. The semiconductor chip includes a substrate, a plurality of conductive pads in the substrate, and a plurality of conductive bumps. Each of the conductive bumps is over corresponding conductive pad. At least one of the conductive bumps proximity to an edge of the semiconductor chip is in contact with at least two discrete regions of the corresponding conductive pad. The package substrate has a concave surface facing the semiconductor chip and joining the semiconductor chip through the plurality of conductive bumps.

Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing a Pad on Solder Mask (PoSM) semiconductor substrate package.

Abstract: A semiconductor device package having a thermal dissipation feature is provided. The semiconductor device package includes a package substrate. A semiconductor die is mounted on a first surface of the package substrate. A first conductive connector is affixed to a first connector pad of the package substrate. A conformal thermal conductive layer is applied on the semiconductor die and a portion of the first surface of the package substrate. The conformal thermal conductive layer is configured and arranged as a thermal conduction path between the semiconductor die and the first conductive connector.

Abstract: A semiconductor package includes a semiconductor chip comprising a first surface and a second surface, a redistribution layer on the first surface of the semiconductor chip, an under bump metal (UBM) layer on the redistribution layer, and a solder bump on the UBM layer, and the solder bump covers both outer side surfaces of the UBM layer.

Abstract: A computing device of an information handling system includes a hardware component. The hardware component is also connected to a trace. The computing device also includes a corrosion management component that is physically connected to the trace. The corrosion management component reduces a rate of corrosion of the trace due to an ambient environment in which the trace resides. The corrosion management component reduces the rate of corrosion by applying an electrical potential to the trace.

Abstract: A method includes forming a dielectric layer over a carrier, forming a plurality of bond pads in the dielectric layer, and performing a planarization to level top surfaces of the dielectric layer and the plurality of bond pads with each other. A device die is bonded to the dielectric layer and portions of the plurality of bond pads through hybrid bonding. The device die is encapsulated in an encapsulating material. The carrier is then demounted from the device die and the dielectric layer.

Abstract: A method for evaluation of thin film non-uniform stress using high order wafer warpage, the steps including measuring a net wafer warpage across a wafer area due to thin film deposition, fitting a two dimensional low-order polynomial to the wafer warpage measurements and subtracting the low-order polynomial from the net wafer warpage across the wafer area.

Abstract: A method of making a display structure comprises providing a display substrate having a display surface, disposing components on and in contact with the display surface, uniformly blanket coating the display surface with a curable layer of uncured light-absorbing material, and curing the curable layer of uncured light-absorbing material to provide a layer of cured light-absorbing material so that the components project from the layer of cured light-absorbing material without having pattern-wise etched the layer of cured light-absorbing material after the light-absorbing material has been cured. The uniform blanket coating has a thickness greater than a thickness of the component, disposing the components comprises printing the components through the uniform blanket coating such that the components protrude from the uniform blanket coating, or the component is coated with a de-wetting material.

Abstract: A semiconductor package includes: a first semiconductor device including a first pad and a first metal bump structure on the first pad; and a second semiconductor device on the first semiconductor device, and including a third pad and a second metal bump structure on the third pad, wherein the first and second metal bump structures are bonded to each other to electrically connect the first and second semiconductor devices to each other. Each of the first and second metal bumps structures includes first to third metal patterns. The first to third metal patterns of the first metal bump structure are on the first pad. The first to third metal patterns of the second metal bump structure are on the third pad. The first and third metal patterns include a first metal having a first coefficient of thermal expansion less than that of a second metal of the second metal pattern.

Abstract: An adhesive composition contains a resin component, a thermal crosslinking agent, and a curing agent, in which the resin component contains a resin having a maleimide group. In a method for producing a semiconductor device having a plurality of connection units for connecting a semiconductor chip and a wiring circuit substrate to each other, or for connecting a plurality of semiconductor chips to each other, a first connection unit is electrically connected to a second connection unit, and at least a portion of the first and second connection units is sealed using the adhesive composition.

Abstract: Implementations of semiconductor packages may include: a semiconductor die having a first side and a second side; one or more bumps included on the first side of the wafer, the bumps comprising a first layer having a first metal and a second layer including a second metal. The first layer may have a first thickness and the second layer may have a second thickness. The semiconductor package may also have a mold compound encapsulating all the semiconductor die except for a face of the one or more bumps.

Abstract: A package substrate includes a substrate, an interposer and an insulating protective layer. The substrate has a first surface and a second surface opposing to the first surface. The first surface includes a plurality of first conductive pads. The interposer is disposed on the first surface of the substrate such that the first conductive pads are partially covered by the interposer. The interposer includes a plurality of penetrating conductive vias electrically connected to the substrate. The insulating protective layer is disposed on the first surface of the substrate and surrounding the interposer. The insulating protective layer includes at least one penetrating conductive column, wherein a first width of the respective penetrating conductive column is greater than a second width of each of the penetrating conductive vias of the interposer.

Abstract: A semiconductor device, includes: a substrate having a first surface on which a plurality of devices are disposed and a second surface, opposite to the first surface; an interlayer insulating film on the first surface of the substrate; an etching delay layer disposed in a region between the substrate and the interlayer insulating film; first and second landing pads on the interlayer insulating film; a first through electrode penetrating through the substrate and the interlayer insulating film; and a second through electrode penetrating the substrate, the etching delay layer, and the interlayer insulating film, the second through electrode having a width, greater than that of the first through electrode, wherein each of the first and second through electrodes includes first and second tapered end portions in the interlayer insulating film, each of first and second tapered end portions having a cross-sectional shape narrowing closer to the landing pads.

Abstract: Edge-connected semiconductor systems are described along with methods of making and using the same. First and second integrated circuit packages are obtained, each including a substrate assembly having top and bottom sides and an edge that extends between the top and the bottom sides. Edge contacts are disposed on the edges of the substrate assemblies. A ganged assembly is formed by establishing conductive paths between the edge contacts of the substrate assemblies. The ganged assembly is coupled to a printed circuit board (“PCB”) by coupling host contacts on one or more of the substrate assemblies to corresponding contacts on the PCB.

Abstract: The present disclosure relates to a semiconductor package including a first semiconductor chip having a first surface on which first connection pads are disposed, and a second surface on which second connection pads are disposed, and including through-vias connected to the second connection pads; a connection structure disposed on the first surface and including a first redistribution layer; a first redistribution disposed on the second surface; and a second semiconductor chip disposed on the connection structure. The first connection pads are connected to a signal pattern of the first redistribution layer, and the second connection pads are connected to at least one of a power pattern and a ground pattern of the second redistribution layer.

Abstract: An integrated circuit package substrate (ICPS) system includes a die including a first array of connectors and a substrate including a second array of connectors that is configured to be thermocompression bonded to the first array of connectors at a bonding temperature that is above a solder melting temperature. The first die is bonded to the substrate such that the first die is asymmetric with respect to a substrate center, and the second array of connectors is adjusted, at an alignment temperature that is below the solder melting temperature, for thermal expansion to the bonding temperature with respect to a reference point that is not a first die center.

Abstract: A package comprising a first integrated device comprising a plurality of first pillar interconnects; an encapsulation layer at least partially encapsulating the first integrated device; a metallization portion located over the first integrated device and the encapsulation layer, wherein the metallization portion includes at least one passivation layer and a plurality of metallization layer interconnects, wherein the plurality of first pillar interconnects is coupled to the plurality of metallization layer interconnects; and a second integrated device comprising a plurality of second pillar interconnects, wherein the second integrated device is coupled to the plurality of metallization layer interconnects through a plurality of second pillar interconnects and a plurality of solder interconnects.

Abstract: Provided a package substrate including an insulation substrate, a conductive layer provided in the insulation substrate, upper pads provided on an upper surface of the insulation substrate and electrically connected to the conductive layer, lower pads provided on a lower surface of the insulation substrate and electrically connected to the conductive layer, and at least one trench provided at a portion of the insulation substrate adjacent to at least one of the upper pads and configured to block stress, which is generated by an expansion of the insulation substrate, from spreading to the at least one of the upper pads.

Abstract: A semiconductor package includes at least one semiconductor chip disposed in such a way that an active surface with chip pads faces a redistribution layer, vertical interconnectors extending in a vertical direction from the chip pads toward the redistribution layer, wherein each of the vertical connectors has a first end portion that is connected to a corresponding chip pad and a second end portion that is disposed on an opposite end of each vertical interconnector in relation to the first end portion, and a molding layer covering the semiconductor chip and the vertical interconnectors while exposing a surface of each of the second end portions of the vertical interconnectors, wherein the redistribution layer is formed over the molding layer, the redistribution layer having a redistribution land that is in contact with the surface of the second end portion, and wherein a width of the surface of the second end portion is greater than a width of an extension portion between the first end portion and the second

Abstract: A method is provided that includes inspecting a layer of a printed circuit board through an inspection window comprising an opening formed in one or more other layers of the printed circuit board and identifying a location of a trace aligned with the inspection window, relative to a marker in a fiber bundle of a fiber weave to assess fiber weave skew.

Abstract: A light-emitting device includes a pair of light-transmissive insulator sheets disposed opposite to each other and two types of light-transmissive electroconductive layers disposed on a common one of or separately on one and the other of the pair of light-transmissive insulator sheets, and at least one light-emitting semiconductor each provided with a cathode and an anode which are individually and electrically connected to the two types of the light-transmissive electroconductive layers. The electrical connection and mechanical bonding between the members are improved by a light-transmissive elastomer which is between the pair of light-transmissive insulator sheets. A method in which a light-emitting semiconductor element and a light-transmissive electroconductive member are subjected to vacuum hot-pressing.

Abstract: A redistribution structure includes a first dielectric layer, a pad pattern, and a second dielectric layer. The pad pattern is disposed on the first dielectric layer and includes a pad portion and a peripheral portion. The pad portion is embedded in the first dielectric layer, wherein a lower surface of the pad portion is substantially coplanar with a lower surface of the first dielectric layer. The peripheral portion surrounds the pad portion. The second dielectric layer is disposed on the pad pattern and includes a plurality of extending portions extending through the peripheral portion.

Abstract: A signal transmission circuit packaging structure is disclosed. The signal transmission circuit packaging structure includes a body, a main circuit unit, power pins, input pins, output pins, control pins, and ground pins. The main circuit unit is arranged in the center of the body. The power pins supply power signal to the main circuit unit. The input pins and the output pins are arranged on a first and a second side of the body separately for electrically connecting to the main circuit unit. The control pins are arranged on the second side of the body and electrically connected to the main circuit unit. The ground pins are arranged at corners of the body to separate the input pins, the output pins, and the control pins.

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment an electronic package comprises a package substrate, and a first level interconnect (FLI) bump region on the package substrate. In an embodiment, the FLI bump region comprises a plurality of pads, and a plurality of bumps, where each bump is over a different one of the plurality of pads. In an embodiment, the electronic package further comprises a guard feature adjacent to the FLI bump region. In an embodiment, the guard feature comprises, a guard pad, and a guard bump over the guard pad, wherein the guard feature is electrically isolated from circuitry of the electronic package.

Abstract: A semiconductor substrate including an upper surface and a lower surface may include a bump pad unit disposed on the upper surface. The semiconductor substrate may also include test pads disposed on the upper surface or the lower surface. The semiconductor substrate may also include traces configured to connect the bump pad unit and the test pads. The bump pad unit includes a main bump pad disposed on the upper surface, and a plurality of side bump pads disposed on the upper surface to be spaced apart from the main bump pad. The traces may connect the main bump pad and the plurality of side bump pads to the test pads in a one-to-one manner.

Abstract: Embodiments of the invention include device packages and methods of forming such packages. In an embodiment, the method of forming a device package may comprise forming a reinforcement layer over a substrate. One or more openings may be formed through the reinforcement layer. In an embodiment, a device die may be placed into one of the openings. The device die may be bonded to the substrate by reflowing one or more solder bumps positioned between the device die and the substrate. Embodiments of the invention may include a molded reinforcement layer. Alternative embodiments include a reinforcement layer that is adhered to the surface of the substrate with an adhesive layer.

Abstract: An integrated circuit with mixed poly pitch cells with a plurality of different pitch sizes is disclosed. The integrated circuit includes: at least a minimum unit each with at least a first number of first poly pitch cells with a first pitch size, and a second number of second poly pitch cells with a second pitch size, the first pitch size PP is different from the second pitch size PP1, the greatest common divisor of the first pitch size PP and the second pitch size PP1 is GCD, wherein GCD is an integer greater than 1; a gate length of the first pitch size is Lg; a gate length of the second pitch size is Lg1; Lg and Lg1 are capable of being extended to achieve G-bias for power and speed optimization of the minimum unit and the integrated circuit.