Abstract: Aspects for reducing or avoiding mechanical stress in static random access memory (SRAM) strap cells are disclosed herein. An exemplary SRAM strap cell includes a P-type doped well (Pwell) tap electrically coupled to a first supply rail to distribute a first supply voltage to a Pwell region of corresponding SRAM bit cell rows. The SRAM strap cell also includes an N-type doped well (Nwell) tap electrically coupled to a second supply rail to distribute a second supply voltage to an Nwell region of corresponding SRAM bit cell rows. In one exemplary aspect, the Nwell tap can include multiple supply contacts used to couple the second supply rail to the SRAM strap cell to reduce mechanical stress in the Nwell tap. In another exemplary aspect, the Pwell tap can include non-active gates disposed across multiple Fins to stabilize the Fins and reduce or avoid mechanical stress in the Pwell tap.

Abstract: A semiconductor device is provided with: a semiconductor substrate; a first electrode disposed on a surface of the semiconductor device and configured to be soldered to a conductive member; and a second electrode disposed on the surface of the semiconductor device and configured to be wire-bonded to a conductive member. The first electrode includes first, second and third metal layers. The second metal layer is located between the first and third metal layers. A metallic material of the second metal layer is greater in tensile strength than a metallic material of each one of the first metal layer and the third metal layer. The second electrode includes a layer made of a same metallic material as one of the first metal layer and the third metal layer, and does not include any layers made of a same metallic material as the second metal layer.

Abstract: Various embodiments process semiconductor devices. In one embodiment, a release layer is applied to a handler. The release layer comprises at least one additive that adjusts a frequency of electro-magnetic radiation absorption property of the release layer. The additive comprises, for example, a 355 nm chemical absorber and/or chemical absorber for one of more wavelengths in a range comprising 600 nm to 740 nm. The at least one singulated semiconductor device is bonded to the handler. The at least one singulated semiconductor device is packaged while it is bonded to the handler. The release layer is ablated by irradiating the release layer through the handler with a laser. The at least one singulated semiconductor device is removed from the transparent handler after the release layer has been ablated.

Abstract: A technique of suppressing leak current in a semiconductor device is provided. A semiconductor device, comprises: a semiconductor layer made of a semiconductor; an insulating layer configured to have electric insulation property and formed to cover part of the semiconductor layer; a first electrode layer formed on the semiconductor layer, configured to have a work function of not less than 0.5 eV relative to electron affinity of the semiconductor layer and extended to surface of the insulating layer to form a field plate structure; and a second electrode layer configured to have electrical conductivity and formed to cover at least part of the first electrode layer. A distance between an edge of a part of the first electrode layer that is in contact with the semiconductor layer and the second electrode layer is equal to or greater than 0.2 ?m.

Abstract: Disclosed are a structure for improving electrical signal isolation in a semiconductor substrate and an associated method for the structure's fabrication. The structure includes a deep trench having sidewalls disposed in the semiconductor substrate. An isolation region may be formed along at least an upper portion of the sidewalls of the deep trench, and a metallic filler may be disposed in the deep trench. The isolation region may include a PN junction formed by one or more of ion implantation and annealing, deposition of highly doped polysilicon and out diffusion, and gas phase doping and annealing. In the alternative, the isolation region may be a dielectric isolation region formed by one or more of uniform dielectric deposition, partial dieletric deposition, and dielectric deposition by ionic reaction.

Abstract: A power substrate utilizing silver conductors on ceramic, and the process for making said device. The insulating portion of the substrate is fabricated from a ceramic by placing trenches into the ceramic which can be filled with silver conductors. These conductors can serve the purpose of traces for electrical interconnection, pads for die attachment, as well as thermal conductors for heat pipes and heat spreaders. The conductors can be made on both the top and the bottom of the ceramic. Such substrates may be used for a multitude of applications requiring power substrates for conducting large currents, and are suitable for high efficiency, high temperature, and/or high reliability applications.

Abstract: A through-substrate via (TSV) structure includes at least two electrically conductive via segments embedded in a substrate and separated from each other by an electrically conductive barrier layer therebetween. The length of each individual conductive via segment is typically equal to, or less than, the Blech length of the conductive material so that the stress-induced back flow force, generated by each conductive barrier layer, cancels the electromigration force in each conductive via segment. Consequently, the TSV structures are immune to electromigration, and provide reliable electrical connections among a chips stacked in 3 dimensions.

Abstract: Methods for electrodepositing germanium on various semiconductor substrates such as Si, Ge, SiGe, and GaAs are provided. The electrodeposited germanium can be formed as a blanket or patterned film, and may be crystallized by solid phase epitaxy to the orientation of the underlying semiconductor substrate by subsequent annealing. These plated germanium layers may be used as the channel regions of high-mobility channel field effect transistors (FETs) in complementary metal oxide semiconductor (CMOS) circuits.

Abstract: The invention relates to a contact structure of a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a trench below the major surface; a strained material filling the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; an inter-layer dielectric (ILD) layer having an opening over the strained material, wherein the opening comprises dielectric sidewalls and a strained material bottom; a semiconductor layer on the sidewalls and bottom of the opening; a dielectric layer on the semiconductor layer; and a metal layer filling an opening of the dielectric layer.

Abstract: A semiconductor device comprises a substrate, a dielectric layer, an undoped silicon layer, and a silicon material. The substrate comprises a doped region. The dielectric layer is formed on the substrate and comprises a contact hole, and the contact hole corresponds to the doped region. The undoped silicon layer is formed on the doped region. The silicon material fills the contact hole from the undoped silicon layer.

Abstract: A germanium semiconductor radiation detector contact made of yttrium metal. A thin (˜1000 ?) deposited layer of yttrium metal forms a thin hole-barrier and/or electron-barrier contact on both p- and n-type germanium semiconductor radiation detectors. Yttrium contacts provide a sufficiently high hole barrier to prevent measurable contact leakage current below ˜120 K. The yttrium contacts can be conveniently segmented into multiple electrically independent electrodes having inter-electrode resistances greater than 10 G?. Germanium semiconductor radiation detector diodes fabricated with yttrium contacts provide good gamma-ray spectroscopy data.

Abstract: In accordance with one aspect of the invention, a method is provided for fabricating a semiconductor element having a contact via. In such method, a hole can be formed in a dielectric layer to at least partially expose a region including at least one of semiconductor or conductive material. A seed layer can be deposited over a major surface of the dielectric layer and over a surface within the hole. In one embodiment, the seed layer can include a metal selected from the group consisting of iridium, osmium, palladium, platinum, rhodium, and ruthenium. A layer consisting essentially of cobalt can be electroplated over the seed layer within the hole to form a contact via in electrically conductive communication with the region.

Abstract: A method patterns at least one pair of openings through a protective layer and into a substrate. The openings are positioned on opposite sides of a channel region of the substrate. The method forms sidewall spacers along the sidewalls of the openings and removes additional substrate material from the bottom of the openings. The material removal process creates an extended bottom within the openings. The method forms a first strain producing material within the extended bottom of the openings. The method removes the sidewall spacers and forms a second material within the remainder of the openings between the first strain producing material and the top of the openings. The method removes the protective layer and forms a gate dielectric and a gate conductor on the horizontal surface on the substrate adjacent the channel region. The second material comprises source and drain regions.

Abstract: A power semiconductor module is provided in which power semiconductor chips with an aluminum-based chip metallization and power semiconductor chips with a copper-based chip metallization are included in the same module, and operated at different barrier-layer temperatures during use.

Abstract: To form a semiconductor device, a through electrode is formed in a semiconductor die, and a dielectric layer is then formed to cover the through electrode. The dielectric layer has an opening by being partially etched to allow the through electrode to protrude to the outside, or has a thickness thinner overall so as to allow the through electrode to protrude to the outside. Subsequently, a conductive pad is formed on the through electrode protruding to the outside through the dielectric layer by using an electroless plating method.

Abstract: The semiconductor device includes: a transistor having a gate electrode formed on a semiconductor substrate and first and second source/drain regions formed in portions of the semiconductor substrate on both sides of the gate electrode; a gate interconnect formed at a position opposite to the gate electrode with respect to the first source/drain region; and a first silicon-germanium layer formed on the first source/drain region to protrude above the top surface of the semiconductor substrate. The gate interconnect and the first source/drain region are connected via a local interconnect structure that includes the first silicon-germanium layer.

Abstract: A semiconductor device including a first memory die having a first memory type, a second memory die having a second memory type different from the first memory type, and a logic die such as a microprocessor. The first memory die can be electrically connected to the logic die using a first type of electrical connection preferred for the first memory type. The second memory die can be electrically connected to the logic die using a second type of electrical connection different from the first type of electrical connection which is preferred for the second memory type. Other devices can include dies all of the same type, or two or more dies of a first type and two or more dies of a second type different from the first type.

Abstract: A semiconductor arrangement includes first and second integrated circuits (dies), an electrically conductive intermediate element, and one or more bond conductors. The first and the second integrated circuits are arranged in a package. The first integrated circuit has a first contact pad. The second integrated circuit has a second contact pad. The intermediate element is disposed on the second contact pad. The conductors electrically connect the first and the second integrated circuits. At least one of the bond conductors has a first end electrically connected to the first contact pad, and a second wedge shaped end electrically connected to the intermediate element. The bond conductor is made of a first material and the intermediate element is made of a second material which is softer than the first material.

Abstract: A method that solves the increased nucleation temperature that is exhibited during the formation of cobalt disilicides in the presence of Ge atoms is provided. The reduction in silicide formation temperature is achieved by first providing a structure including a Co layer including at least Ni, as an additive element, on top of a SiGe containing substrate. Next, the structure is subjected to a self-aligned silicide process which includes a first anneal, a selective etching step and a second anneal to form a solid solution of (Co, Ni) disilicide on the SiGe containing substrate. The Co layer including at least Ni can comprise an alloy layer of Co and Ni, a stack of Ni/Co or a stack of Co/Ni. A semiconductor structure including the solid solution of (Co, Ni) disilicide on the SiGe containing substrate is also provided.

Abstract: In a semiconductor apparatus having a plurality of wiring layers, the semiconductor apparatus includes a bonding pad formed by an uppermost wiring layer, a first-layer plug wire formed by a first lower wiring layer in a region under the bonding pad, and a first conductive plug connecting the bonding pad and the first-layer plug wire. The first-layer plug wire may include a plurality of first-layer plug wires arranged in parallel to one another in a stripe pattern.

Abstract: A contact structure is disclosed in which a continuous metal semiconductor alloy is located within a via contained within a dielectric material. The continuous semiconductor metal alloy is in direct contact with an upper metal line of a first metal level located atop the continuous semiconductor metal alloy and at least a surface of each source and drain diffusion region located beneath the continuous metal semiconductor alloy. The continuous metal semiconductor alloy can be derived from either a semiconductor nanowire or an epitaxial grown semiconductor material. The continuous metal semiconductor alloy includes a lower portion that is contained within an upper surface of each source and drain region, and a vertical pillar portion extending upward from the lower portion. The lower portion of the continuous metal semiconductor alloy and the vertical pillar portion are not separated by a material interface. Instead, the two portions of the continuous metal semiconductor alloy are of unitary construction, i.e.

Abstract: A method of forming an integrated circuit structure, the method includes providing a semiconductor substrate; forming a dielectric layer over the semiconductor substrate; forming an opening in the dielectric layer; forming a seed layer in the opening; forming a copper line on the seed layer, wherein at least one of the seed layer and the copper line comprises an alloying material; and forming an etch stop layer on the copper line.

Abstract: A semiconductor structure includes a first silicon-containing layer comprising an element selected from the group consisting essentially of carbon and germanium wherein the silicon-containing layer has a first atomic percentage of the element to the element and silicon, a second silicon-containing layer comprising the element over the first silicon-containing layer, and a silicide layer on the second silicon-containing layer. The element in the second silicon-containing layer has a second atomic percentage of the element to the element and silicon, wherein the second atomic percentage is substantially lower than the first atomic percentage.

Abstract: The present invention provides an ohmic contact for a copper metallization whose heat diffusion is improved and cost is reduced. Therein, the ohmic contact is formed through a depositing and an annealing of three metal layers of Pd, Ge and Cu; and, the contact resistance of the ohmic contact is adjusted by the thicknesses of the three layers.

Abstract: A process for forming a junction-isolated, electrically conductive via in a silicon substrate and a conductive apparatus to carry electrical signal from one side of a silicon wafer to the other side are provided. The conductive via is junction-isolated from the bulk of the silicon substrate by diffusing the via with a dopant that is different than the material of the silicon substrate. Several of the junction-isolated vias can be formed in a silicon substrate and the silicon wafer coupled to a second silicon substrate of a device that requires electrical connection. This process for forming junction-isolated, conductive vias is simpler than methods of forming metallized vias, especially for electrical devices more tolerant of both resistance and capacitance.

Abstract: A semiconductor device suitable for the miniaturization and comprising properly controlled Si/SiGe gate electrode comprises an insulator formed on a semiconductor substrate, a first gate electrode formed on the insulator and including silicon-germanium, wherein a germanium concentration is higher near an interface to the insulator and lower in a surface side opposite to the insulator, and a second gate electrode formed on the insulator and including silicon-germanium, wherein a germanium concentration is substantially uniform and an n-type dopant of a concentration of above 6×1020 atoms/cm3 is contained.

Abstract: An integrated circuit (IC) is formed on a substrate. The IC has a first well having a first dopant concentration that includes a second conductivity low-voltage transistor. The IC also has a second well having a dopant concentration equal to the first dopant concentration that includes a first conductivity high-voltage transistor. In addition, the IC has a third well having a second dopant concentration of an opposite type than the first well that includes a first conductivity low-voltage transistor. The first conductivity low-voltage transistor and the second conductivity low-voltage transistor are created without a threshold voltage (Vt) implant.

Abstract: A typical integrated-circuit fabrication requires interconnecting millions of microscopic transistors and resistors with metal wires. Making the metal wires flush, or coplanar, with underlying insulation requires digging trenches in the insulation, and then filling the trenches with metal to form the wires. The invention provides a new “trench-less” or “self-planarizing” method of making coplanar metal wires. Specifically, one embodiment forms a first layer that includes silicon and germanium; oxidizes a region of the first layer to define an oxidized region and a non-oxidized region; and reacts aluminum or an aluminum alloy with the non-oxidized region. The reaction substitutes, or replaces, the non-oxidized region with aluminum to form a metallic wire coplanar with the first layer. Another step removes germanium oxide from the oxidized region to form a porous insulation having a very low dielectric constant, thereby reducing capacitance.

Abstract: A new method and structure for an improved contact using doped silicon is provided. The structures are integrated into several higher level embodiments. The improved contact has low contact resistivity. Improved junctions are thus provided between an IGFET device and subsequent metallization layers. The improvements are obtained through the use of a silicon-germanium (Si—Ge) alloy. The alloy can be formed from depositing germanium onto the substrate and subsequently annealing the contact or by selectively depositing the preformed alloy into a contact opening. The above advantages are incorporated with relatively few process steps.

Abstract: A thermal processing method is described which improves integrated circuit metal polishing and increases conductivity following polish. A method of fabricating a metal layer in an integrated circuit is described which comprises the steps of depositing a layer of metal alloy which contains alloy dopant precipitates, and performing a first anneal of the integrated circuit to drive the alloy dopants into solid solution. The metal is quenched to prevent the alloy dopants from coming out of solution prior to removing excess metal alloy with a polish process. To improve conductivity after polishing, the dopants are allowed to come out of solution. The metal alloy is described as aluminum with alloy dopants of silicon and copper where the first anneal is performed at 400 to 500° C. This process is particularly applicable to fabrication of interconnects formed using a dual damascene process. The integrated circuit is described as any circuit, but can be a memory device such as a DRAM.

Abstract: A semiconductor device wherein Si—Ge is the base of a bipolar transistor and a Silicon layer is the emitter. A method of making such a semiconductor device including steps of forming a Silicon dioxide layer on a Silicon substrate, using a photo resist application and exposure to define where a HBT device will be placed. Plasma etching the Silicon dioxide layer to define an undercut, epitaxially growing an Si—Ge layer and a Silicon layer, and continuing manufacture to form one or more bipolar and CMOS devices and define interconnect and passivation.

Abstract: A semiconductor light receiving element having a light receiving layer (1) formed from a GaN group semiconductor, and an electrode (2) formed on one surface of the light receiving layer as a light receiving surface (1a) in such a way that the light (L) can enter the light receiving layer is provided. When the light receiving element is of a Schottky barrier type, the aforementioned electrode (2) contains at least a Schottky electrode, which is formed in such a way that, on the light receiving surface (1a), the total length of the boundary lines between areas covered with the Schottky electrode and exposed areas is longer than the length of the outer periphery of the light receiving surface (1a).

Abstract: An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has an opening formed therein. A barrier layer lines the channel opening. A conductor core fills the opening over the barrier layer. A cerium-conductor interconnect cap is disposed over the conductor core with a capping layer over the dielectric layer and the cerium-conductor interconnect cap.

Abstract: A typical integrated-circuit fabrication requires interconnecting millions of microscopic transistors and resistors with aluminum wires. Making the aluminum wires flush, or coplanar, with underlying insulation requires digging trenches in the insulation, and then filling the trenches with aluminum to form the aluminum wires. Trench digging is time consuming and costly. Moreover, aluminum has higher electrical resistance than other metals, such as silver. Accordingly, the invention provides a new “self-trenching” or “self-planarizing” method of making coplanar silver wires. Specifically, one embodiment forms a first layer that includes silicon and germanium; oxidizes a region of the first layer to define an oxidized region and a non-oxidized region; and reacts silver with the non-oxidized region. The reaction substitutes, or replaces, the non-oxidized region with silver to form silver wires coplanar with the first layer.

Abstract: A process for forming an interlayer dielectric layer is disclosed. The method comprises first forming a carbon-doped oxide (CDO) layer with a first concentration of carbon dopants therein. Next, the CDO layer is further formed with a second concentration of carbon dopants therein, wherein the first concentration is different than the second concentration.

Abstract: Copper interconnects are formed by depositing substantially pure copper into the lower portion of an interconnect opening. The upper portion of the interconnect opening is then filled with doped copper followed by a planarization process. The resulting copper interconnect exhibits reduced electromigration while maintaining low overall resistivity.

Abstract: A nanostructure based material is capable of accepting-and reacting with an alkali metal such as lithium. The material exhibits a reversible capacity ranging from at least approximately 900 mAh/g-1,500 mAh/g. The high capacity of the material makes it attractive for a number of applications, such as a battery electrode material.

Abstract: A vertical type power MOSFET made of silicon carbide includes a surface channel layer doped with nitrogen as dopant with a concentration equal to or less than 1×1015 cm−3. Accordingly, when a gate oxide film is formed on the surface channel layer, an amount of silicon nitride produced in the gate oxide film and at the interface between the gate oxide film and the surface channel layer becomes extremely small. As a result, carrier traps are prevented from being produced by silicon nitride, resulting in stable FET characteristics and high reliability to the gate oxide film.

Abstract: A die incorporating vertical conductors, or vias, extending from active and passive devices on the active die side to the back side thereof. The vias are preferably formed in the die material matrix by introduction of a conductive material as known in the art. Such dice may be employed in singulated fashion on a carrier substrate as an alternative to so-called “flip chip” dice, or in vertically-stacked fashion to form a sealed multi-chip module the same size as the die from which it is formed. Certain vias of the various dice in the stack may be vertically aligned or superimposed to provide common access from each die level to a terminal such as a bond pad or C4 or other connection on the back side of the lowermost die contacting the carrier substrate, while other stacked vias are employed for individual access from each die level to the carrier substrate through the back side of the lowermost die.

Abstract: A thermal processing method is described which improves integrated circuit metal polishing and increases conductivity following polish. A method of fabricating a metal layer in an integrated circuit is described which comprises the steps of depositing a layer of metal alloy which contains alloy dopant precipitates, and performing a first anneal of the integrated circuit to drive the alloy dopants into solid solution. The metal is quenched to prevent the alloy dopants from coming out of solution prior to removing excess metal alloy with a polish process. To improve conductivity after polishing, the dopants are allowed to come out of solution. The metal alloy is described as aluminum with alloy dopants of silicon and copper where the first anneal is performed at 400 to 500° C. This process is particularly applicable to fabrication of interconnects formed using a dual damascene process. The integrated circuit is described as any circuit, but can be a memory device such as a DRAM.

Abstract: A nanostructure based material is capable of accepting and reacting with an alkali metal such as lithium. The material exhibits a reversible capacity ranging from at least approximately 900 mAh/g-1,500 mAh/g. The high capacity of the material makes it attractive for a number of applications, such as a battery electrode material.

Abstract: A novel transistor with a low resistance ultra shallow tip region and its method of fabrication. The novel transistor of the present invention has a source/drain extension or tip comprising an ultra shallow region which extends beneath the gate electrode and a raised region.

Abstract: A thin film multilayered structure comprises a single crystal Si substrate; a MgO buffer layer epitaxially grown on said single crystal Si substrate; and a metallic thin film made of Ir or Rh epitaxially grown on said MgO buffer layer.

Abstract: A typical integrated-circuit fabrication requires interconnecting millions of microscopic transistors and resistors with aluminum wires. Making the aluminum wires flush, or coplanar, with underlying insulation requires digging trenches in the insulation, and then filling the trenches with aluminum to form the aluminum wires. Trench digging is time consuming and costly. Moreover, aluminum has higher electrical resistance than other metals, such as silver. Accordingly, the invention provides a new "self-trenching" or "self-planarizing" method of making coplanar silver wires. Specifically, one embodiment forms a first layer that includes silicon and germanium; oxidizes a region of the first layer to define an oxidized region and a non-oxidized region; and reacts silver with the non-oxidized region. The reaction substitutes, or replaces, the non-oxidized region with silver to form silver wires coplanar with the first layer.

Abstract: A typical integrated-circuit fabrication requires interconnecting millions of microscopic transistors and resistors with aluminum wires. Making the aluminum wires flush, or coplanar, with underlying insulation requires digging trenches in the insulation, and then filling the trenches with aluminum to form the aluminum wires. Trench digging is time consuming and costly. Moreover, aluminum has higher electrical resistance than other metals, such as gold. Accordingly, the invention provides a new "self-trenching" or "self-planarizing" method of making coplanar gold wires. Specifically, one embodiment forms a first layer that includes silicon and germanium; oxidizes a region of the first layer to define an oxidized region and a non-oxidized region; and reacts gold with the non-oxidized region. The reaction substitutes, or replaces, the non-oxidized region with gold to form gold wires coplanar with the first layer.

Abstract: An integrated circuit arrangement contains an MOS transistor surrounded by an insulation structure, the source and drain thereof being arranged laterally and in different depths. A channel thereof proceeds essentially perpendicular to the surface of the circuit arrangement. Since the channel length is determined by etching or by growing a layer, channel lengths as short as less than 50 nm can be realized. For the manufacture, most of the masks of the traditional circuit arrangements in which planar transistors are integrated are employed, this significantly facilitating incorporation into the semiconductor manufacture.

Abstract: On a main surface of a silicon substrate of one conductivity type, a diffusion layer of the opposite conductivity type is formed, and the main surface of the silicon substrate is covered by an insulator film. The insulator film is formed with a contact hole which extends to reach the diffusion layer of the opposite conductivity type. A contact plug is provided in the contact hole. The contact plug fills the contact hole and comprises a first silicon layer of the opposite conductivity type directly connected to the diffusion layer of the opposite conductivity type, a silicon-germanium alloy layer of the opposite conductivity type directly contact to the first silicon layer, and a second silicon layer of the opposite conductivity type directly contact to the silicon-germanium alloy layer. Wiring is provided on the surface of the insulator film in direct contact to the contact plug.

Abstract: A die incorporating vertical conductors, or vias, extending from active and passive devices on the active die side to the back side thereof. The vias are preferably formed in the die material matrix by introduction of a conductive material as known in the art. Such die may be employed in singulated fashion on a carrier substrate as an alternative to so-called "flip chip" die, or in vertically-stacked fashion to form a sealed multi-chip module the same size as the die from which it is formed. Certain vias of the various dice in the stack may be vertically aligned or superimposed to provide common access from each die level to a terminal such as a bond pad or C4 or other connection on the back side of the lowermost die contacting the carrier, while other stacked vias are employed for individual access from each die level to the carrier through the back side of the lowermost die.

Abstract: A typical integrated-circuit fabrication requires interconnecting millions of microscopic transistors and resistors with aluminum wires. Making the aluminum wires flush, or coplanar, with underlying insulation requires digging trenches in the insulation, and then filling the trenches with aluminum to form the aluminum wires. Trench digging is time consuming and costly. Moreover, aluminum has higher electrical resistance than other metals, such as gold. Accordingly, the invention provides a new "self-trenching" or "self-planarizing" method of making coplanar gold wires. Specifically, one embodiment forms a first layer that includes silicon and germanium; oxidizes a region of the first layer to define an oxidized region and a non-oxidized region; and reacts gold with the non-oxidized region. The reaction substitutes, or replaces, the non-oxidized region with gold to form gold wires coplanar with the first layer.

Abstract: A semiconductor device includes a first diffusion layer, an insulating film, and an electrode. The first diffusion layer is formed on the surface of a first-conductivity-type semiconductor substrate and has an opposite conductivity type. The insulating film is formed on the first diffusion layer. The electrode is made of a conductor layer formed on the insulating film. The width of the electrode is smaller than a value twice the length by which an impurity doped into the surface of the semiconductor substrate, using the electrode as a mask, laterally diffuses during annealing to a position immediately below the electrode.